From 7798690cb936d49e6e05b599afe79f047c172e43 Mon Sep 17 00:00:00 2001
From: DanielMartinBuckley <daniel.m.buckley@intel.com>
Date: Wed, 16 Jan 2019 16:45:56 +0000
Subject: Support NSB NFVi buffering and Load Balance on 2 and 4 ports

JIRA: YARDSTICK-1582

Most use cases support 4 ports.
Buffering support only 1 core.
Request is about supporting buffering & Load balance
for 2 and 4 ports

Change-Id: I734f9d6702825b31253a21092c86fc72e367586b
Signed-off-by: Daniel Martin Buckley <daniel.m.buckley@intel.com>
---
 .../nsut/prox/configs/gen_buffering-4.cfg          | 122 +++++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 samples/vnf_samples/nsut/prox/configs/gen_buffering-4.cfg

(limited to 'samples/vnf_samples/nsut/prox/configs/gen_buffering-4.cfg')

diff --git a/samples/vnf_samples/nsut/prox/configs/gen_buffering-4.cfg b/samples/vnf_samples/nsut/prox/configs/gen_buffering-4.cfg
new file mode 100644
index 000000000..9be6297a8
--- /dev/null
+++ b/samples/vnf_samples/nsut/prox/configs/gen_buffering-4.cfg
@@ -0,0 +1,122 @@
+# Copyright (c) 2016-2019 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#;
+
+[eal options]
+-n=4 ; number of memory channels
+no-output=no ; disable DPDK debug output
+
+[port 0]
+name=p0
+mac=hardware
+
+[port 1]
+name=p1
+mac=hardware
+
+[port 2]
+name=p2
+mac=hardware
+
+[port 3]
+name=p3
+mac=hardware
+
+
+[defaults]
+mempool size=4K
+
+[variables]
+$sut_mac0=@@dst_mac0
+$sut_mac1=@@dst_mac1
+$sut_mac2=@@dst_mac2
+$sut_mac3=@@dst_mac3
+
+[global]
+start time=5
+name=Buffering gen
+
+[core 0]
+mode=master
+
+[core 1-4]
+name=p0
+task=0
+mode=gen
+tx port=p0
+bps=1250000000
+; Ethernet + IP + UDP
+pkt inline=${sut_mac0} 70 00 00 00 00 01 08 00 45 00 00 20 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 0c 55 7b 42 43 44 45
+lat pos=42
+
+[core 5-8]
+name=p1
+task=0
+mode=gen
+tx port=p1
+bps=1250000000
+; Ethernet + IP + UDP
+pkt inline=${sut_mac1} 70 00 00 00 00 01 08 00 45 00 00 20 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 0c 55 7b 42 43 44 45
+lat pos=42
+
+
+[core 9-12]
+name=p2
+task=0
+mode=gen
+tx port=p2
+bps=1250000000
+; Ethernet + IP + UDP
+pkt inline=${sut_mac2} 70 00 00 00 00 01 08 00 45 00 00 20 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 0c 55 7b 42 43 44 45
+lat pos=42
+
+
+[core 13-16]
+name=p3
+task=0
+mode=gen
+tx port=p3
+bps=1250000000
+; Ethernet + IP + UDP
+pkt inline=${sut_mac3} 70 00 00 00 00 01 08 00 45 00 00 20 00 01 00 00 40 11 f7 7d c0 a8 01 01 c0 a8 01 01 13 88 13 88 00 0c 55 7b 42 43 44 45
+lat pos=42
+
+[core 28]
+name=P0
+task=0
+mode=lat
+rx port=p0
+lat pos=42
+
+[core 29]
+name=P1
+task=0
+mode=lat
+rx port=p1
+lat pos=42
+
+[core 30]
+name=P2
+task=0
+mode=lat
+rx port=p2
+lat pos=42
+
+[core 31]
+name=P3
+task=0
+mode=lat
+rx port=p3
+lat pos=42
-- 
cgit 1.2.3-korg