/* * Simple LatticeMico32 disassembler. * * Copyright (c) 2012 Michael Walle * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . * */ #include "qemu/osdep.h" #include "disas/bfd.h" typedef enum { LM32_OP_SRUI = 0, LM32_OP_NORI, LM32_OP_MULI, LM32_OP_SH, LM32_OP_LB, LM32_OP_SRI, LM32_OP_XORI, LM32_OP_LH, LM32_OP_ANDI, LM32_OP_XNORI, LM32_OP_LW, LM32_OP_LHU, LM32_OP_SB, LM32_OP_ADDI, LM32_OP_ORI, LM32_OP_SLI, LM32_OP_LBU, LM32_OP_BE, LM32_OP_BG, LM32_OP_BGE, LM32_OP_BGEU, LM32_OP_BGU, LM32_OP_SW, LM32_OP_BNE, LM32_OP_ANDHI, LM32_OP_CMPEI, LM32_OP_CMPGI, LM32_OP_CMPGEI, LM32_OP_CMPGEUI, LM32_OP_CMPGUI, LM32_OP_ORHI, LM32_OP_CMPNEI, LM32_OP_SRU, LM32_OP_NOR, LM32_OP_MUL, LM32_OP_DIVU, LM32_OP_RCSR, LM32_OP_SR, LM32_OP_XOR, LM32_OP_ILL0, LM32_OP_AND, LM32_OP_XNOR, LM32_OP_ILL1, LM32_OP_SCALL, LM32_OP_SEXTB, LM32_OP_ADD, LM32_OP_OR, LM32_OP_SL, LM32_OP_B, LM32_OP_MODU, LM32_OP_SUB, LM32_OP_ILL2, LM32_OP_WCSR, LM32_OP_ILL3, LM32_OP_CALL, LM32_OP_SEXTH, LM32_OP_BI, LM32_OP_CMPE, LM32_OP_CMPG, LM32_OP_CMPGE, LM32_OP_CMPGEU, LM32_OP_CMPGU, LM32_OP_CALLI, LM32_OP_CMPNE, } Lm32Opcode; typedef enum { FMT_INVALID = 0, FMT_RRI5, FMT_RRI16, FMT_IMM26, FMT_LOAD, FMT_STORE, FMT_RRR, FMT_R, FMT_RNR, FMT_CRN, FMT_CNR, FMT_BREAK, } Lm32OpcodeFmt; typedef enum { LM32_CSR_IE = 0, LM32_CSR_IM, LM32_CSR_IP, LM32_CSR_ICC, LM32_CSR_DCC, LM32_CSR_CC, LM32_CSR_CFG, LM32_CSR_EBA, LM32_CSR_DC, LM32_CSR_DEBA, LM32_CSR_CFG2, LM32_CSR_JTX = 0xe, LM32_CSR_JRX, LM32_CSR_BP0, LM32_CSR_BP1, LM32_CSR_BP2, LM32_CSR_BP3, LM32_CSR_WP0 = 0x18, LM32_CSR_WP1, LM32_CSR_WP2, LM32_CSR_WP3, } Lm32CsrNum; typedef struct { int csr; const char *name; } Lm32CsrInfo; static const Lm32CsrInfo lm32_csr_info[] = { {LM32_CSR_IE, "ie", }, {LM32_CSR_IM, "im", }, {LM32_CSR_IP, "ip", }, {LM32_CSR_ICC, "icc", }, {LM32_CSR_DCC, "dcc", }, {LM32_CSR_CC, "cc", }, {LM32_CSR_CFG, "cfg", }, {LM32_CSR_EBA, "eba", }, {LM32_CSR_DC, "dc", }, {LM32_CSR_DEBA, "deba", }, {LM32_CSR_CFG2, "cfg2", }, {LM32_CSR_JTX, "jtx", }, {LM32_CSR_JRX, "jrx", }, {LM32_CSR_BP0, "bp0", }, {LM32_CSR_BP1, "bp1", }, {LM32_CSR_BP2, "bp2", }, {LM32_CSR_BP3, "bp3", }, {LM32_CSR_WP0, "wp0", }, {LM32_CSR_WP1, "wp1", }, {LM32_CSR_WP2, "wp2", }, {LM32_CSR_WP3, "wp3", }, }; static const Lm32CsrInfo *find_csr_info(int csr) { const Lm32CsrInfo *info; int i; for (i = 0; i < ARRAY_SIZE(lm32_csr_info); i++) { info = &lm32_csr_info[i]; if (csr == info->csr) { return info; } } return NULL; } typedef struct { int reg; const char *name; } Lm32RegInfo; typedef enum { LM32_REG_R0 = 0, LM32_REG_R1, LM32_REG_R2, LM32_REG_R3, LM32_REG_R4, LM32_REG_R5, LM32_REG_R6, LM32_REG_R7, LM32_REG_R8, LM32_REG_R9, LM32_REG_R10, LM32_REG_R11, LM32_REG_R12, LM32_REG_R13, LM32_REG_R14, LM32_REG_R15, LM32_REG_R16, LM32_REG_R17, LM32_REG_R18, LM32_REG_R19, LM32_REG_R20, LM32_REG_R21, LM32_REG_R22, LM32_REG_R23, LM32_REG_R24, LM32_REG_R25, LM32_REG_GP, LM32_REG_FP, LM32_REG_SP, LM32_REG_RA, LM32_REG_EA, LM32_REG_BA, } Lm32RegNum; static const Lm32RegInfo lm32_reg_info[] = { {LM32_REG_R0, "r0", }, {LM32_REG_R1, "r1", }, {LM32_REG_R2, "r2", }, {LM32_REG_R3, "r3", }, {LM32_REG_R4, "r4", }, {LM32_REG_R5, "r5", }, {LM32_REG_R6, "r6", }, {LM32_REG_R7, "r7", }, {LM32_REG_R8, "r8", }, {LM32_REG_R9, "r9", }, {LM32_REG_R10, "r10", }, {LM32_REG_R11, "r11", }, {LM32_REG_R12, "r12", }, {LM32_REG_R13, "r13", }, {LM32_REG_R14, "r14", }, {LM32_REG_R15, "r15", }, {LM32_REG_R16, "r16", }, {LM32_REG_R17, "r17", }, {LM32_REG_R18, "r18", }, {LM32_REG_R19, "r19", }, {LM32_REG_R20, "r20", }, {LM32_REG_R21, "r21", }, {LM32_REG_R22, "r22", }, {LM32_REG_R23, "r23", }, {