/* * Topcliff PCH DMA controller driver * Copyright (c) 2010 Intel Corporation * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include #include #include #include #include #include #include #include "dmaengine.h" #define DRV_NAME "pch-dma" #define DMA_CTL0_DISABLE 0x0 #define DMA_CTL0_SG 0x1 #define DMA_CTL0_ONESHOT 0x2 #define DMA_CTL0_MODE_MASK_BITS 0x3 #define DMA_CTL0_DIR_SHIFT_BITS 2 #define DMA_CTL0_BITS_PER_CH 4 #define DMA_CTL2_START_SHIFT_BITS 8 #define DMA_CTL2_IRQ_ENABLE_MASK ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1) #define DMA_STATUS_IDLE 0x0 #define DMA_STATUS_DESC_READ 0x1 #define DMA_STATUS_WAIT 0x2 #define DMA_STATUS_ACCESS 0x3 #define DMA_STATUS_BITS_PER_CH 2 #define DMA_STATUS_MASK_BITS 0x3 #define DMA_STATUS_SHIFT_BITS 16 #define DMA_STATUS_IRQ(x) (0x1 << (x)) #define DMA_STATUS0_ERR(x) (0x1 << ((x) + 8)) #define DMA_STATUS2_ERR(x) (0x1 << (x)) #define DMA_DESC_WIDTH_SHIFT_BITS 12 #define DMA_DESC_WIDTH_1_BYTE (0x3 << DMA_DESC_WIDTH_SHIFT_BITS) #define DMA_DESC_WIDTH_2_BYTES (0x2 << DMA_DESC_WIDTH_SHIFT_BITS) #define DMA_DESC_WIDTH_4_BYTES (0x0 << DMA_DESC_WIDTH_SHIFT_BITS) #define DMA_DESC_MAX_COUNT_1_BYTE 0x3FF #define DMA_DESC_MAX_COUNT_2_BYTES 0x3FF #define DMA_DESC_MAX_COUNT_4_BYTES 0x7FF #define DMA_DESC_END_WITHOUT_IRQ 0x0 #define DMA_DESC_END_WITH_IRQ 0x1 #define DMA_DESC_FOLLOW_WITHOUT_IRQ 0x2 #define DMA_DESC_FOLLOW_WITH_IRQ 0x3 #define MAX_CHAN_NR 12 #define DMA_MASK_CTL0_MODE 0x33333333 #define DMA_MASK_CTL2_MODE 0x00003333 static unsigned int init_nr_desc_per_channel = 64; module_param(init_nr_desc_per_channel, uint, 0644); MODULE_PARM_DESC(init_nr_desc_per_channel, "initial descriptors per channel (default: 64)"); struct pch_dma_desc_regs { u32 dev_addr; u32 mem_addr; u32 size; u32 next; }; struct pch_dma_regs { u32 dma_ctl0; u32 dma_ctl1; u32 dma_ctl2; u32 dma_ctl3; u32 dma_sts0; u32 dma_sts1; u32 dma_sts2; u32 reserved3; struct pch_dma_desc_regs desc[MAX_CHAN_NR]; }; struct pch_dma_desc { struct pch_dma_desc_regs regs; struct dma_async_tx_descriptor txd; struct list_head desc_node; struct list_head tx_list; }; struct pch_dma_chan { struct dma_chan chan; void __iomem *membase; enum dma_transfer_direction dir; struct tasklet_struct tasklet; unsigned long err_status; spinlock_t lock; struct list_head active_list; struct list_head queue; struct list_head free_list; unsigned int descs_allocated; }; #define PDC_DEV_ADDR 0x00 #define PDC_MEM_ADDR 0x04 #define PDC_SIZE 0x08 #define PDC_NEXT 0x0C #define channel_readl(pdc, name) \ readl((pdc)->membase + PDC_##name) #define channel_writel(pdc, name, val) \ writel((val), (pdc)->membase + PDC_##name) struct pch_dma { struct dma_device dma; void __iomem *membase; struct pci_pool *pool; struct pch_dma_regs regs; struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR]; struct pch_dma_chan channels[MAX_CHAN_NR]; }; #define PCH_DMA_CTL0 0x00 #define PCH_DMA_CTL1 0x04 #define PCH_DMA_CTL2 0x08 #define PCH_DMA_CTL3 0x0C #define PCH_DMA_STS0 0x10 #define PCH_DMA_STS1 0x14 #define PCH_DMA_STS2 0x18 #define dma_readl(pd, name) \ readl((pd)->membase + PCH_DMA_##name) #define dma_writel(pd, name, val) \ writel((val), (pd)->membase + PCH_DMA_##name) static inline struct pch_dma_desc *to_pd_desc(struct dma_async_tx_descriptor *txd) { return container_of(txd, struct pch_dma_desc, txd); } static inline struct pch_dma_chan *to_pd_chan(struct dma_chan *chan) { return container_of(chan, struct pch_dma_chan, chan); } static inline struct pch_dma *to_pd(struct dma_device *ddev) { return container_of(ddev, struct pch_dma, dma); } static inline struct device *chan2dev(struct dma_chan *chan) { return &chan->dev->device; } static inline struct device *chan2parent(struct dma_chan *chan) { return chan->dev->device.parent; } static inline struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan) { return list_first_entry(&pd_chan->active_list, struct pch_dma_desc, desc_node); } static inline struct pch_dma_desc *pdc_first_queued(struct pch_dma_chan *pd_chan) { return list_first_entry(&pd_chan->queue, struct pch_dma_desc, desc_node); } static void pdc_enable_irq(struct dma_chan *chan, int enable) { struct pch_dma *pd = to_pd(chan->device); u32 val; int pos; if (chan->chan_id < 8) pos = chan->chan_id; else pos = chan->chan_id + 8; val = dma_readl(pd, CTL2); if (enable) val |= 0x1 << pos; else val &= ~(0x1 << pos); dma_writel(pd, CTL2, val); dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x\n", chan->chan_id, val); } static void pdc_set_dir(struct dma_chan *chan) { struct pch_dma
#!/bin/bash
##############################################################################
# Copyright (c) 2016 EMC and others.
#
# All rights reserved. This program and the accompanying materials
# are made available under the terms of the Apache License, Version 2.0
# which accompanies this distribution, and is available at
# http://www.apache.org/licenses/LICENSE-2.0
##############################################################################

cd `dirname $0`

storperf_container=`docker ps -a -q -f name=storperf`

if [ ! -z $storperf_container ]
then
    echo "Stopping any existing StorPerf container"
    docker rm -fv $storperf_container
fi

if [ ! -f job/admin.rc ]
then
    ./generate-admin-rc.sh
fi

if [ ! -d job/carbon ]
then
    mkdir job/carbon
    sudo chown 33:33 job/carbon
fi

if [ -z $DOCKER_TAG ]
then
    DOCKER_TAG=latest
fi

docker pull opnfv/storperf:$DOCKER_TAG

docker run -d --env-file `pwd`/job/admin.rc \
    -p 5000:5000 \
    -p 8000:8000 \
    -v `pwd`/job/carbon:/opt/graphite/storage/whisper \
    --name storperf opnfv/storperf
#    -v `pwd`/../../storperf:/home/opnfv/repos/storperf \

echo "Waiting for StorPerf to become active"
while [ $(curl -X GET 'http://127.0.0.1:5000/api/v1.0/configurations' > /dev/null 2>&1;echo $?) -ne 0 ]
do
    sleep 1
done
ret0 = IRQ_HANDLED; } } else { if (sts2 & DMA_STATUS_IRQ(i - 8)) { if (sts2 & DMA_STATUS2_ERR(i)) set_bit(0, &pd_chan->err_status); tasklet_schedule(&pd_chan->tasklet); ret2 = IRQ_HANDLED; } } } /* clear interrupt bits in status register */ if (ret0) dma_writel(pd, STS0, sts0); if (ret2) dma_writel(pd, STS2, sts2); return ret0 | ret2; } #ifdef CONFIG_PM static void pch_dma_save_regs(struct pch_dma *pd) { struct pch_dma_chan *pd_chan; struct dma_chan *chan, *_c; int i = 0; pd->regs.dma_ctl0 = dma_readl(pd, CTL0); pd->regs.dma_ctl1 = dma_readl(pd, CTL1); pd->regs.dma_ctl2 = dma_readl(pd, CTL2); pd->regs.dma_ctl3 = dma_readl(pd, CTL3); list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { pd_chan = to_pd_chan(chan); pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR); pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR); pd->ch_regs[i].size = channel_readl(pd_chan, SIZE); pd->ch_regs[i].next = channel_readl(pd_chan, NEXT); i++; } } static void pch_dma_restore_regs(struct pch_dma *pd) { struct pch_dma_chan *pd_chan; struct dma_chan *chan, *_c; int i = 0; dma_writel(pd, CTL0, pd->regs.dma_ctl0); dma_writel(pd, CTL1, pd->regs.dma_ctl1); dma_writel(pd, CTL2, pd->regs.dma_ctl2); dma_writel(pd, CTL3, pd->regs.dma_ctl3); list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { pd_chan = to_pd_chan(chan); channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr); channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr); channel_writel(pd_chan, SIZE, pd->ch_regs[i].size); channel_writel(pd_chan, NEXT, pd->ch_regs[i].next); i++; } } static int pch_dma_suspend(struct pci_dev *pdev, pm_message_t state) { struct pch_dma *pd = pci_get_drvdata(pdev); if (pd) pch_dma_save_regs(pd); pci_save_state(pdev); pci_disable_device(pdev); pci_set_power_state(pdev, pci_choose_state(pdev, state)); return 0; } static int pch_dma_resume(struct pci_dev *pdev) { struct pch_dma *pd = pci_get_drvdata(pdev); int err; pci_set_power_state(pdev, PCI_D0); pci_restore_state(pdev); err = pci_enable_device(pdev); if (err) { dev_dbg(&pdev->dev, "failed to enable device\n"); return err; } if (pd) pch_dma_restore_regs(pd); return 0; } #endif static int pch_dma_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pch_dma *pd; struct pch_dma_regs *regs; unsigned int nr_channels; int err; int i; nr_channels = id->driver_data; pd = kzalloc(sizeof(*pd), GFP_KERNEL); if (!pd) return -ENOMEM; pci_set_drvdata(pdev, pd); err = pci_enable_device(pdev); if (err) { dev_err(&pdev->dev, "Cannot enable PCI device\n"); goto err_free_mem; } if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { dev_err(&pdev->dev, "Cannot find proper base address\n"); err = -ENODEV; goto err_disable_pdev; } err = pci_request_regions(pdev, DRV_NAME); if (err) { dev_err(&pdev->dev, "Cannot obtain PCI resources\n"); goto err_disable_pdev; } err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (err) { dev_err(&pdev->dev, "Cannot set proper DMA config\n"); goto err_free_res; } regs = pd->membase = pci_iomap(pdev, 1, 0); if (!pd->membase) { dev_err(&pdev->dev, "Cannot map MMIO registers\n"); err = -ENOMEM; goto err_free_res; } pci_set_master(pdev); err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd); if (err) { dev_err(&pdev->dev, "Failed to request IRQ\n"); goto err_iounmap; } pd->pool = pci_pool_create("pch_dma_desc_pool", pdev, sizeof(struct pch_dma_desc), 4, 0); if (!pd->pool) { dev_err(&pdev->dev, "Failed to alloc DMA descriptors\n"); err = -ENOMEM; goto err_free_irq; } pd->dma.dev = &pdev->dev; INIT_LIST_HEAD(&pd->dma.channels); for (i = 0; i < nr_channels; i++) { struct pch_dma_chan *pd_chan = &pd->channels[i]; pd_chan->chan.device = &pd->dma; dma_cookie_init(&pd_chan->chan); pd_chan->membase = ®s->desc[i]; spin_lock_init(&pd_chan->lock); INIT_LIST_HEAD(&pd_chan->active_list); INIT_LIST_HEAD(&pd_chan->queue); INIT_LIST_HEAD(&pd_chan->free_list); tasklet_init(&pd_chan->tasklet, pdc_tasklet, (unsigned long)pd_chan); list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels); } dma_cap_zero(pd->dma.cap_mask); dma_cap_set(DMA_PRIVATE, pd->dma.cap_mask); dma_cap_set(DMA_SLAVE, pd->dma.cap_mask); pd->dma.device_alloc_chan_resources = pd_alloc_chan_resources; pd->dma.device_free_chan_resources = pd_free_chan_resources; pd->dma.device_tx_status = pd_tx_status; pd->dma.device_issue_pending = pd_issue_pending; pd->dma.device_prep_slave_sg = pd_prep_slave_sg; pd->dma.device_terminate_all = pd_device_terminate_all; err = dma_async_device_register(&pd->dma); if (err) { dev_err(&pdev->dev, "Failed to register DMA device\n"); goto err_free_pool; } return 0; err_free_pool: pci_pool_destroy(pd->pool); err_free_irq: free_irq(pdev->irq, pd); err_iounmap: pci_iounmap(pdev, pd->membase); err_free_res: pci_release_regions(pdev); err_disable_pdev: pci_disable_device(pdev); err_free_mem: kfree(pd); return err; } static void pch_dma_remove(struct pci_dev *pdev) { struct pch_dma *pd = pci_get_drvdata(pdev); struct pch_dma_chan *pd_chan; struct dma_chan *chan, *_c; if (pd) { dma_async_device_unregister(&pd->dma); free_irq(pdev->irq, pd); list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { pd_chan = to_pd_chan(chan); tasklet_kill(&pd_chan->tasklet); } pci_pool_destroy(pd->pool); pci_iounmap(pdev, pd->membase); pci_release_regions(pdev); pci_disable_device(pdev); kfree(pd); } } /* PCI Device ID of DMA device */ #define PCI_VENDOR_ID_ROHM 0x10DB #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810 #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815 #define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026 #define PCI_DEVICE_ID_ML7213_DMA2_8CH 0x802B #define PCI_DEVICE_ID_ML7213_DMA3_4CH 0x8034 #define PCI_DEVICE_ID_ML7213_DMA4_12CH 0x8032 #define PCI_DEVICE_ID_ML7223_DMA1_4CH 0x800B #define PCI_DEVICE_ID_ML7223_DMA2_4CH 0x800E #define PCI_DEVICE_ID_ML7223_DMA3_4CH 0x8017 #define PCI_DEVICE_ID_ML7223_DMA4_4CH 0x803B #define PCI_DEVICE_ID_ML7831_DMA1_8CH 0x8810 #define PCI_DEVICE_ID_ML7831_DMA2_4CH 0x8815 static const struct pci_device_id pch_dma_id_table[] = { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_4CH), 4 }, { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA4_12CH), 12}, /* I2S */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA1_4CH), 4}, /* UART */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA2_4CH), 4}, /* Video SPI */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA3_4CH), 4}, /* Security */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA1_8CH), 8}, /* UART */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA2_4CH), 4}, /* SPI */ { 0, }, }; static struct pci_driver pch_dma_driver = { .name = DRV_NAME, .id_table = pch_dma_id_table, .probe = pch_dma_probe, .remove = pch_dma_remove, #ifdef CONFIG_PM .suspend = pch_dma_suspend, .resume = pch_dma_resume, #endif }; module_pci_driver(pch_dma_driver); MODULE_DESCRIPTION("Intel EG20T PCH / LAPIS Semicon ML7213/ML7223/ML7831 IOH " "DMA controller driver"); MODULE_AUTHOR("Yong Wang "); MODULE_LICENSE("GPL v2"); MODULE_DEVICE_TABLE(pci, pch_dma_id_table);