;;
;; Copyright (c) 2010-2017 Intel Corporation
;;
;; Licensed under the Apache License, Version 2.0 (the "License");
;; you may not use this file except in compliance with the License.
;; You may obtain a copy of the License at
;;
;;     http://www.apache.org/licenses/LICENSE-2.0
;;
;; Unless required by applicable law or agreed to in writing, software
;; distributed under the License is distributed on an "AS IS" BASIS,
;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;; See the License for the specific language governing permissions and
;; limitations under the License.
;;

[eal options]
-n=4 ; force number of memory channels
no-output=no ; disable DPDK debug output

[port 0]
name=p0
mac=00:00:00:00:00:01
[port 1]
name=p1
mac=00:00:00:00:00:02
[port 2]
name=p2
mac=00:00:00:00:00:03
[port 3]
name=p3
mac=00:00:00:00:00:04

[defaults]
mempool size=4K

[global]
start time=5
name=Basic Gen

[core 0s1]
mode=master

[core 1s1]
name=p0
task=0
mode=gen
tx port=p0
bps=1250000000
pkt inline=68 05 ca 30 6b d0 68 05 ca 30 6c b0 08 00 45 00 04 20 00 00 40 00 40 11 a5 fd c8 02 00 65 c8 02 00 66 9c c4 12 b6 04 0c 00 00 0c 40 00 04 00 00 00 00 40 06 01 03 00 03 e9 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 07 00 00 00 01 00 06 00 08 00 45 00 03 d6 00 00 00 00 40 06 48 15 0a 00 00 01 c0 a8 64 64 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 00 d9 b0 00 00 00 01 02 03 04 05 06 07 08 09 0a