;;
;; Copyright (c) 2010-2017 Intel Corporation
;;
;; Licensed under the Apache License, Version 2.0 (the "License");
;; you may not use this file except in compliance with the License.
;; You may obtain a copy of the License at
;;
;;     http://www.apache.org/licenses/LICENSE-2.0
;;
;; Unless required by applicable law or agreed to in writing, software
;; distributed under the License is distributed on an "AS IS" BASIS,
;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;; See the License for the specific language governing permissions and
;; limitations under the License.
;;

;;
; This is one of the most basic configurations. Note that this configuration
; does not perform any real work as opposed to configurations like BNG/BRAS
; or lwAFTR. This configuration sets up four interfaces and five cores (one
; master core and four worker cores). Packets are passed (i.e. without being
; touched) as follows:
; - interface 0 to interface 1 (handled by core 1)
; - interface 1 to interface 0 (handled by core 2)
; - interface 2 to interface 3 (handled by core 3)
; - interface 3 to interface 2 (handled by core 4)
;;

[eal options]
-n=4 ; force number of memory channels
no-output=no ; disable DPDK debug output

[port 0]
name=if0
mac=hardware
[port 1]
name=if1
mac=hardware
[port 2]
name=if2
mac=hardware
[port 3]
name=if3
mac=hardware

[defaults]
mempool size=8K

[global]
start time=5
name=NOP forwarding (4x)

[core 0s0]
mode=master

[core 1s0]
name=nop
task=0
mode=nop
rx port=if0
tx port=if1
drop=no

[core 2s0]
name=nop
task=0
mode=nop
rx port=if1
tx port=if0
drop=no

[core 3s0]
name=nop
task=0
mode=nop
rx port=if2
tx port=if3
drop=no

[core 4s0]
name=nop
task=0
mode=nop
rx port=if3
tx port=if2
drop=no