#CHARACTERIZE VSWITCH PERFORMANCE FOR TELCO NFV USE CASES LEVEL TEST DESIGN
##Table of Contents
- [1. Introduction](#Introduction)
- [1.1. Document identifier](#DocId)
- [1.2. Scope](#Scope)
- [1.3. References](#References)
- [2. Details of the Level Test Design](#DetailsOfTheLevelTestDesign)
- [2.1. Features to be tested](#FeaturesToBeTested)
- [2.2. Approach](#Approach)
- [2.3. Test identification](#TestIdentification)
- [2.3.1 Throughput tests](#ThroughputTests)
- [2.3.2 Packet Delay Tests](#PacketDelayTests)
- [2.3.3 Scalability Tests](#ScalabilityTests)
- [2.3.4 CPU and Memory Consumption Tests](#CPUTests)
- [2.3.5 Coupling Between the Control Path and The Datapath Tests](#CPDPTests)
- [2.3.6 Time to Establish Flows Tests](#FlowLatencyTests)
- [2.3.7 Noisy Neighbour Tests](#NoisyNeighbourTests)
- [2.3.8 Overlay Tests](#OverlayTests)
- [2.3.9 Summary Test List](#SummaryList)
- [2.4. Feature pass/fail criteria](#PassFail)
- [2.5. Test deliverables](#TestDeliverables)
- [3. General](#General)
- [3.1. Glossary](#Glossary)
- [3.2. Document change procedures and history](#History)
- [3.3. Contributors](#Contributors)
---
##1. Introduction
The objective of the OPNFV project titled **“Characterize vSwitch Performance for Telco NFV Use Cases”**, is to evaluate a virtual switch to identify its suitability for a Telco Network Function Virtualization (NFV) environment. The intention of this Level Test Design (LTD) document is to specify the set of tests to carry out in order to objectively measure the current characteristics of a virtual switch in the Network Function Virtualization Infrastructure (NFVI) as well as the test pass criteria. The detailed test cases will be defined in [Section 2](#DetailsOfTheLevelTestDesign), preceded by the [Document identifier](#DocId) and the [Scope](#Scope).
This document is currently in draft form.
###1.1. Document identifier
The document id will be used to uniquely identify versions of the LTD. The format for the document id will be: OPNFV\_vswitchperf\_LTD\_ver\_NUM\_MONTH\_YEAR\_STATUS, where by the status is one of: draft, reviewed, corrected or final. The document id for this version of the LTD is: OPNFV\_vswitchperf\_LTD\_ver\_1.6\_Jan\_15\_DRAFT.
###1.2. Scope
The main purpose of this project is to specify a suite of performance tests in order to objectively measure the current packet transfer characteristics of a virtual switch in the NFVI. The intent of the project is to facilitate testing of any virtual switch. Thus, a generic suite of tests shall be developed, with no hard dependencies to a single implementation. In addition, the test case suite shall be architecture independent.
The test cases developed in this project shall not form part of a separate test framework, all of these tests may be inserted into the Continuous Integration Test Framework and/or the Platform Functionality Test Framework - if a vSwitch becomes a standard component of an OPNFV release.
###1.3. References
- [RFC 1242 Benchmarking Terminology for Network Interconnection Devices](http://www.ietf.org/rfc/rfc1242.txt)
- [RFC 2544 Benchmarking Methodology for Network Interconnect Devices](http://www.ietf.org/rfc/rfc2544.txt)
- [RFC 2285 Benchmarking Terminology for LAN Switching Devices](http://www.ietf.org/rfc/rfc2285.txt)
- [RFC 2889 Benchmarking Methodology for LAN Switching Devices](http://www.ietf.org/rfc/rfc2889.txt)
- [RFC 3918 Methodology for IP Multicast Benchmarking](http://www.ietf.org/rfc/rfc3918.txt)
- [RFC 4737 Packet Reordering Metrics](http://www.ietf.org/rfc/rfc4737.txt)
- [RFC 5481 Packet Delay Variation Applicability Statement](http://www.ietf.org/rfc/rfc5481.txt)
- [RFC 6201 Device Reset Characterization](http://tools.ietf.org/html/rfc6201)
##2. Details of the Level Test Design
This section describes the features to be tested ([cf. 2.1](#FeaturesToBeTested)), the test approach ([cf. 2.2](#Approach)); it also identifies the sets of test cases or scenarios ([cf. 2.3](#TestIdentification)) along with the pass/fail criteria ([cf. 2.4](#PassFail)) and the test deliverables ([cf. 2.5](#TestDeliverables)).
###2.1. Features to be tested
Characterizing virtual switches (i.e. Device Under Test (DUT) in this document) includes measuring the following performance metrics:
- **Throughput** as defined by [RFC1242]: The maximum rate at which **none** of the offered frames are dropped by the DUT. The maximum frame rate and bit rate that can be transmitted by the DUT without any error should be recorded. Note there is an equivalent bit rate and a specific layer at which the payloads contribute to the bits. Errors and improperly formed frames or packets are dropped.
- **Packet delay** introduced by the DUT and its cumulative effect on E2E networks. Frame delay can be measured equivalently.
- **Packet delay variation**: measured from the perspective of the VNF/application. Packet delay variation is sometimes called "jitter". However, we will avoid the term "jitter" as the term holds different meaning to different groups of people. In this document we will simply use the term packet delay variation. The preferred form for this metric is the PDV form of delay variation defined in [RFC5481].
- **Packet loss** (within a configured waiting time at the receiver): All packets sent to the DUT should be accounted for.
- **Burst behaviour**: measures the ability of the DUT to buffer packets.
- **Packet re-ordering**: measures the ability of the device under test to maintain sending order throughout transfer to the destination.
- **Packet correctness**: packets or Frames must be well-formed, in that they include all required fields, conform to length requirements, pass integrity checks, etc.
- **Availability and capacity** of the DUT i.e. when the DUT is fully “up” and connected:
- Includes power consumption of the CPU (in various power states) and system.
- Includes CPU utilization.
- Includes the number of NIC interfaces supported.
- Includes headroom of VM workload processing cores (i.e. available for applications).
###2.2. Approach
In order to determine the packet transfer characteristics of a virtual switch, the tests will be broken down into the following categories:
- **Throughput Tests** to measure the maximum forwarding rate (in frames per second or fps) and bit rate (in Mbps) for a constant load (as defined by [RFC1242]) without traffic loss.
- **Packet and Frame Delay Tests** to measure average, min and max packet and frame delay for constant loads.
- **Stream Performance Tests** (TCP, UDP) to measure bulk data transfer performance, i.e. how fast systems can send and receive data through the switch.
- **Request/Response Performance** Tests (TCP, UDP) the measure the transaction rate through the switch.
- **Packet Delay Tests** to understand latency distribution for different packet sizes and over an extended test run to uncover outliers.
- **Scalability Tests** to understand how the virtual switch performs as the number of flows, active ports, complexity of the forwarding logic's configuration... it has to deal with increases.
- **Control Path and Datapath Coupling** Tests, to understand how closely coupled the datapath and the control path are as well as the effect of this coupling on the performance of the DUT.
- **CPU and Memory Consumption Tests** to understand the virtual switch’s footprint on the system, this includes:
- CPU utilization
- Cache utilization
- Memory footprint
- Time To Establish Flows Tests.
- **Noisy Neighbour Tests**, to understand the effects of resource sharing on the performance of a virtual switch.
**Note:** some of the tests above can be conducted simultaneously where the combined results would be insightful, for example Packet/Frame Delay and Scalability.
The following represents possible deployments which can help to determine the performance of both the virtual switch and the datapath into the VNF:
- Physical port → virtual switch → physical port.
__
+--------------------------------------------------+ |
| +--------------------+ | |
| | | | |
| | v | | Host
| +--------------+ +--------------+ | |
| | phy port | vSwitch | phy port | | |
+---+--------------+------------+--------------+---+ __|
^ :
| |
: v
+--------------------------------------------------+
| |
| traffic generator |
| |
+--------------------------------------------------+
- Physical port → virtual switch → VNF → virtual switch → physical port.
__
+---------------------------------------------------+ |
| | |
| +-------------------------------------------+ | |
| | Application | | |
| +-------------------------------------------+ | |
| ^ : | |
| | | | | Guest
| : v | |
| +---------------+ +---------------+ | |
| | logical port 0| | logical port 1| | |
+---+---------------+-----------+---------------+---+ __|
^ :
| |
: v __
+---+---------------+----------+---------------+---+ |
| | logical port 0| | logical port 1| | |
| +---------------+ +---------------+ | |
| ^ : | |
| | | | | Host
| : v | |
| +--------------+ +--------------+ | |
| | phy port | vSwitch | phy port | | |
+---+--------------+------------+--------------+---+ __|
^ :
| |
: v
+--------------------------------------------------+
| |
| traffic generator |
| |
+--------------------------------------------------+
- Physical port → virtual switch → VNF → virtual switch → VNF → virtual switch → physical port.
__
+----------------------+ +----------------------+ |
| Guest 1 | | Guest 2 | |
| +---------------+ | | +---------------+ | |
| | Application | | | | Application | | |
| +---------------+ | | +---------------+ | |
| ^ | | | ^ | | |
| | v | | | v | | Guests
| +---------------+ | | +---------------+ | |
| | logical ports | | | | logical ports | | |
| | 0 1 | | | | 0 1 | | |
+---+---------------+--+ +---+---------------+--+__|
^ : ^ :
| | | |
: v : v _
+---+---------------+---------+---------------+--+ |
| | 0 1 | | 3 4 | | |
| | logical ports | | logical ports | | |
| +---------------+ +---------------+ | |
| ^ | ^ | | | Host
| | L-----------------+ v | |
| +--------------+ +--------------+ | |
| | phy ports | vSwitch | phy ports | | |
+---+--------------+----------+--------------+---+_|
^ : ^ :
| | | |
: v : v
+--------------------------------------------------+
| |
| traffic generator |
| |
+--------------------------------------------------+
- Physical port → virtual switch → VNF.
__
+---------------------------------------------------+ |
| | |
| +-------------------------------------------+ | |
| | Application | | |
| +-------------------------------------------+ | |
| ^ | |
| | | | Guest
| : | |
| +---------------+ | |
| | logical port 0| | |
+---+---------------+-------------------------------+ __|
^
|
: __
+---+---------------+------------------------------+ |
| | logical port 0| | |
| +---------------+ | |
| ^ | |
| | | | Host
| : | |
| +--------------+ | |
| | phy port | vSwitch | |
+---+--------------+------------ -------------- ---+ __|
^
|
:
+--------------------------------------------------+
| |
| traffic generator |
| |
+--------------------------------------------------+
- VNF → virtual switch → physical port.
__
+---------------------------------------------------+ |
| | |
| +-------------------------------------------+ | |
| | Application | | |
| +-------------------------------------------+ | |
| : | |
| | | | Guest
| v | |
| +---------------+ | |
| | logical port | | |
+-------------------------------+---------------+---+ __|
:
|
v __
+------------------------------+---------------+---+ |
| | logical port | | |
| +---------------+ | |
| : | |
| | | | Host
| v | |
| +--------------+ | |
| vSwitch | phy port | | |
+-------------------------------+--------------+---+ __|
:
|
v
+--------------------------------------------------+
| |
| traffic generator |
| |
+--------------------------------------------------+
- virtual switch → VNF → virtual switch.
__
+---------------------------------------------------+ +---------------------------------------------------+ |
| Guest 1 | | Guest 2 | |
| +-------------------------------------------+ | | +-------------------------------------------+ | |
| | Application | | | | Application | | |
| +-------------------------------------------+ | | +-------------------------------------------+ | |
| : | | ^ | |
| | | | | | | Guest
| v | | : | |
| +---------------+ | | +---------------+ | |
| | logical port 0| | | | logical port 0| | |
+-------------------------------+---------------+---+ +---+---------------+-------------------------------+__|
: ^
| |
v : __
+------------------------------+---------------+------------+---------------+-------------------------------+ |
| | port 0 | | port 1 | | |
| +---------------+ +---------------+ | |
| : ^ | |
| | | | | Host
| +--------------------+ | |
| | |
| vswitch | |
+-----------------------------------------------------------------------------------------------------------+__|
**Note:** For tests where the traffic generator and/or measurement receiver are implemented on VM and connected to the virtual switch through vNIC, the issues of shared resources and interactions between the measurement devices and the device under test must be considered.
####General Methodology:
To establish the baseline performance of the virtual switch, tests would initially be run with a simple workload in the VNF (the recommended simple workload VNF would be [DPDK]'s testpmd application forwarding packets in a VM or vloop_vnf a simple kernel module that forwards traffic between two network interfaces inside the virtualized environment while bypassing the networking stack). Subsequently, the tests would also be executed with a real Telco workload running in the VNF, which would exercise the virtual switch in the context of higher level Telco NFV use cases, and prove that its underlying characteristics and behaviour can be measured and validated. Suitable real Telco workload VNFs are yet to be identified.
#####Default Test Parameters:
The following list identifies the default parameters for suite of tests:
- Reference application: Simple forwarding or Open Source VNF.
- Frame size (bytes): 64, 128, 256, 512, 1024, 1280, 1518, 2K, 4k OR Packet size based on use-case (e.g. RTP 64B, 256B).
- Reordering check: Tests should confirm that packets within a flow are not reordered.
- Duplex: Unidirectional / Bidirectional. Default: Full duplex with traffic transmitting in both directions, as network traffic generally does not flow in a single direction. By default the data rate of transmitted traffic should be the same in both directions, please note that asymmetric traffic (e.g. downlink-heavy) tests will be mentioned explicitly for the relevant test cases.
- Number of Flows: Default for non scalability tests is a single flow. For scalability tests the goal is to test with maximum supported flows but where possible will test up to 10 Million flows. Start with a single flow and scale up. By default flows should be added sequentially, tests that add flows simultaneously will explicitly call out their flow addition behaviour. Packets are generated across the flows uniformly with no burstiness.
- Traffic Types: UDP, SCTP, RTP, GTP and UDP traffic.
- Deployment scenarios are:
- Physical → virtual switch → physical.
- Physical → virtual switch → VNF → virtual switch → physical.
- Physical → virtual switch → VNF → virtual switch → VNF → virtual switch → physical.
- Physical → virtual switch → VNF.
- VNF → virtual switch → Physical.
- VNF → virtual switch → VNF.
Tests MUST have these parameters unless otherwise stated. **Test cases with non default parameters will be stated explicitly**.
**Note**: For throughput tests unless stated otherwise, test configurations should ensure that traffic traverses the installed flows through the switch, i.e. flows are installed and have an appropriate time out that doesn't expire before packet transmission starts.
#####Test Priority
Tests will be assigned a priority in order to determine which tests should be implemented immediately and which tests implementations can be deferred.
Priority can be of following types:
- Urgent: Must be implemented immediately.
- High: Must be implemented in the next release.
- Medium: May be implemented after the release.
- Low: May or may not be implemented at all.
#####DUT Setup
The DUT should be configured to its "default" state. The DUT's configuration or set-up must not change between tests in any way other than what is required to do the test. All supported protocols must be configured and enabled for each test set up.
#####Port Configuration
The DUT should be configured with n ports where n is a multiple of 2. Half of the ports on the DUT should be used as ingress ports and the other half of the ports on the DUT should be used as egress ports. Where a DUT has more than 2 /*
* Copyright (C) ST-Ericsson SA 2012
*
* Author: Ola Lilja <ola.o.lilja@stericsson.com>,
* Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
* Roger Nilsson <roger.xr.nilsson@stericsson.com>,
* for ST-Ericsson.
*
* Based on the early work done by:
* Mikko J. Lehto <mikko.lehto@symbio.com>,
* Mikko Sarmanne <mikko.sarmanne@symbio.com>,
* for ST-Ericsson.
*
* License terms:
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef AB8500_CODEC_REGISTERS_H
#define AB8500_CODEC_REGISTERS_H
#define AB8500_SUPPORTED_RATE (SNDRV_PCM_RATE_48000)
#define AB8500_SUPPORTED_FMT (SNDRV_PCM_FMTBIT_S16_LE)
/* AB8500 interface slot offset definitions */
#define AB8500_AD_DATA0_OFFSET 0
#define AB8500_DA_DATA0_OFFSET 8
#define AB8500_AD_DATA1_OFFSET 16
#define AB8500_DA_DATA1_OFFSET 24
/* AB8500 audio bank (0x0d) register definitions */
#define AB8500_POWERUP 0x00
#define AB8500_AUDSWRESET 0x01
#define AB8500_ADPATHENA 0x02
#define AB8500_DAPATHENA 0x03
#define AB8500_ANACONF1 0x04
#define AB8500_ANACONF2 0x05
#define AB8500_DIGMICCONF 0x06
#define AB8500_ANACONF3 0x07
#define AB8500_ANACONF4 0x08
#define AB8500_DAPATHCONF 0x09
#define AB8500_MUTECONF 0x0A
#define AB8500_SHORTCIRCONF 0x0B
#define AB8500_ANACONF5 0x0C
#define AB8500_ENVCPCONF 0x0D
#define AB8500_SIGENVCONF 0x0E
#define AB8500_PWMGENCONF1 0x0F
#define AB8500_PWMGENCONF2 0x10
#define AB8500_PWMGENCONF3 0x11
#define AB8500_PWMGENCONF4 0x12
#define AB8500_PWMGENCONF5 0x13
#define AB8500_ANAGAIN1 0x14
#define AB8500_ANAGAIN2 0x15
#define AB8500_ANAGAIN3 0x16
#define AB8500_ANAGAIN4 0x17
#define AB8500_DIGLINHSLGAIN 0x18
#define AB8500_DIGLINHSRGAIN 0x19
#define AB8500_ADFILTCONF 0x1A
#define AB8500_DIGIFCONF1 0x1B
#define AB8500_DIGIFCONF2 0x1C
#define AB8500_DIGIFCONF3 0x1D
#define AB8500_DIGIFCONF4 0x1E
#define AB8500_ADSLOTSEL1 0x1F
#define AB8500_ADSLOTSEL2 0x20
#define AB8500_ADSLOTSEL3 0x21
#define AB8500_ADSLOTSEL4 0x22
#define AB8500_ADSLOTSEL5 0x23
#define AB8500_ADSLOTSEL6 0x24
#define AB8500_ADSLOTSEL7 0x25
#define AB8500_ADSLOTSEL8 0x26
#define AB8500_ADSLOTSEL9 0x27
#define AB8500_ADSLOTSEL10 0x28
#define AB8500_ADSLOTSEL11 0x29
#define AB8500_ADSLOTSEL12 0x2A
#define AB8500_ADSLOTSEL13 0x2B
#define AB8500_ADSLOTSEL14 0x2C
#define AB8500_ADSLOTSEL15 0x2D
#define AB8500_ADSLOTSEL16 0x2E
#define AB8500_ADSLOTSEL(slot) (AB8500_ADSLOTSEL1 + (slot >> 1))
#define AB8500_ADSLOTHIZCTRL1 0x2F
#define AB8500_ADSLOTHIZCTRL2 0x30
#define AB8500_ADSLOTHIZCTRL3 0x31
#define AB8500_ADSLOTHIZCTRL4 0x32
#define AB8500_DASLOTCONF1 0x33
#define AB8500_DASLOTCONF2 0x34
#define AB8500_DASLOTCONF3 0x35
#define AB8500_DASLOTCONF4 0x36
#define AB8500_DASLOTCONF5 0x37
#define AB8500_DASLOTCONF6 0x38
#define AB8500_DASLOTCONF7 0x39
#define AB8500_DASLOTCONF8 0x3A
#define AB8500_CLASSDCONF1 0x3B
#define AB8500_CLASSDCONF2 0x3C
#define AB8500_CLASSDCONF3 0x3D
#define AB8500_DMICFILTCONF 0x3E
#define AB8500_DIGMULTCONF1 0x3F
#define AB8500_DIGMULTCONF2 0x40
#define AB8500_ADDIGGAIN1 0x41
#define AB8500_ADDIGGAIN2 0x42
#define AB8500_ADDIGGAIN3 0x43
#define AB8500_ADDIGGAIN4 0x44
#define AB8500_ADDIGGAIN5 0x45
#define AB8500_ADDIGGAIN6 0x46
#define AB8500_DADIGGAIN1 0x47
#define AB8500_DADIGGAIN2 0x48
#define AB8500_DADIGGAIN3 0x49
#define AB8500_DADIGGAIN4 0x4A
#define AB8500_DADIGGAIN5 0x4B
#define AB8500_DADIGGAIN6 0x4C
#define AB8500_ADDIGLOOPGAIN1 0x4D
#define AB8500_ADDIGLOOPGAIN2 0x4E
#define AB8500_HSLEARDIGGAIN 0x4F
#define AB8500_HSRDIGGAIN 0x50
#define AB8500_SIDFIRGAIN1 0x51
#define AB8500_SIDFIRGAIN2 0x52
#define AB8500_ANCCONF1 0x53
#define AB8500_ANCCONF2 0x54
#define AB8500_ANCCONF3 0x55
#define AB8500_ANCCONF4 0x56
#define AB8500_ANCCONF5 0x57
#define AB8500_ANCCONF6 0x58
#define AB8500_ANCCONF7 0x59
#define AB8500_ANCCONF8 0x5A
#define AB8500_ANCCONF9 0x5B
#define AB8500_ANCCONF10 0x5C
#define AB8500_ANCCONF11 0x5D
#define AB8500_ANCCONF12 0x5E
#define AB8500_ANCCONF13 0x5F
#define AB8500_ANCCONF14 0x60
#define AB8500_SIDFIRADR 0x61
#define AB8500_SIDFIRCOEF1 0x62
#define AB8500_SIDFIRCOEF2 0x63
#define AB8500_SIDFIRCONF 0x64
#define AB8500_AUDINTMASK1 0x65
#define AB8500_AUDINTSOURCE1 0x66
#define AB8500_AUDINTMASK2 0x67
#define AB8500_AUDINTSOURCE2 0x68
#define AB8500_FIFOCONF1 0x69
#define AB8500_FIFOCONF2 0x6A
#define AB8500_FIFOCONF3 0x6B
#define AB8500_FIFOCONF4 0x6C
#define AB8500_FIFOCONF5 0x6D
#define AB8500_FIFOCONF6 0x6E
#define AB8500_AUDREV 0x6F
#define AB8500_FIRST_REG AB8500_POWERUP
#define AB8500_LAST_REG AB8500_AUDREV
#define AB8500_CACHEREGNUM (AB8500_LAST_REG + 1)
#define AB8500_MASK_ALL 0xFF
#define AB8500_MASK_SLOT(slot) ((slot & 1) ? 0xF0 : 0x0F)
#define AB8500_MASK_NONE 0x00
/* AB8500_POWERUP */
#define AB8500_POWERUP_POWERUP 7
#define AB8500_POWERUP_ENANA 3
/* AB8500_AUDSWRESET */
#define AB8500_AUDSWRESET_SWRESET 7
/* AB8500_ADPATHENA */
#define AB8500_ADPATHENA_ENAD12 7
#define AB8500_ADPATHENA_ENAD34 5
#define AB8500_ADPATHENA_ENAD5768 3
/* AB8500_DAPATHENA */
#define AB8500_DAPATHENA_ENDA1 7
#define AB8500_DAPATHENA_ENDA2 6
#define AB8500_DAPATHENA_ENDA3 5
#define AB8500_DAPATHENA_ENDA4 4
#define AB8500_DAPATHENA_ENDA5 3
#define AB8500_DAPATHENA_ENDA6 2
/* AB8500_ANACONF1 */
#define AB8500_ANACONF1_HSLOWPOW 7
#define AB8500_ANACONF1_DACLOWPOW1 6
#define AB8500_ANACONF1_DACLOWPOW0 5
#define AB8500_ANACONF1_EARDACLOWPOW 4
#define AB8500_ANACONF1_EARSELCM 2
#define AB8500_ANACONF1_HSHPEN 1
#define AB8500_ANACONF1_EARDRVLOWPOW 0
/* AB8500_ANACONF2 */
#define AB8500_ANACONF2_ENMIC1 7
#define AB8500_ANACONF2_ENMIC2 6
#define AB8500_ANACONF2_ENLINL 5
#define AB8500_ANACONF2_ENLINR 4
#define AB8500_ANACONF2_MUTMIC1 3
#define AB8500_ANACONF2_MUTMIC2 2
#define AB8500_ANACONF2_MUTLINL 1
#define AB8500_ANACONF2_MUTLINR 0
/* AB8500_DIGMICCONF */
#define AB8500_DIGMICCONF_ENDMIC1 7
#define AB8500_DIGMICCONF_ENDMIC2 6
#define AB8500_DIGMICCONF_ENDMIC3 5
#define AB8500_DIGMICCONF_ENDMIC4 4
#define AB8500_DIGMICCONF_ENDMIC5 3
#define AB8500_DIGMICCONF_ENDMIC6 2
#define AB8500_DIGMICCONF_HSFADSPEED 0
/* AB8500_ANACONF3 */
#define AB8500_ANACONF3_MIC1SEL 7
#define AB8500_ANACONF3_LINRSEL 6
#define AB8500_ANACONF3_ENDRVHSL 5
#define AB8500_ANACONF3_ENDRVHSR 4
#define AB8500_ANACONF3_ENADCMIC 2
#define AB8500_ANACONF3_ENADCLINL 1
#define AB8500_ANACONF3_ENADCLINR 0
/* AB8500_ANACONF4 */
#define AB8500_ANACONF4_DISPDVSS 7
#define AB8500_ANACONF4_ENEAR 6
#define AB8500_ANACONF4_ENHSL 5
#define AB8500_ANACONF4_ENHSR 4
#define AB8500_ANACONF4_ENHFL 3
#define AB8500_ANACONF4_ENHFR 2
#define AB8500_ANACONF4_ENVIB1 1
#define AB8500_ANACONF4_ENVIB2 0
/* AB8500_DAPATHCONF */
#define AB8500_DAPATHCONF_ENDACEAR 6
#define AB8500_DAPATHCONF_ENDACHSL 5
#define AB8500_DAPATHCONF_ENDACHSR 4
#define AB8500_DAPATHCONF_ENDACHFL 3
#define AB8500_DAPATHCONF_ENDACHFR 2
#define AB8500_DAPATHCONF_ENDACVIB1 1
#define AB8500_DAPATHCONF_ENDACVIB2 0
/* AB8500_MUTECONF */
#define AB8500_MUTECONF_MUTEAR 6
#define AB8500_MUTECONF_MUTHSL 5
#define AB8500_MUTECONF_MUTHSR 4
#define AB8500_MUTECONF_MUTDACEAR 2
#define AB8500_MUTECONF_MUTDACHSL 1
#define AB8500_MUTECONF_MUTDACHSR 0
/* AB8500_SHORTCIRCONF */
#define AB8500_SHORTCIRCONF_ENSHORTPWD 7
#define AB8500_SHORTCIRCONF_EARSHORTDIS 6
#define AB8500_SHORTCIRCONF_HSSHORTDIS 5
#define AB8500_SHORTCIRCONF_HSPULLDEN 4
#define AB8500_SHORTCIRCONF_HSOSCEN 2
#define AB8500_SHORTCIRCONF_HSFADDIS 1
#define AB8500_SHORTCIRCONF_HSZCDDIS 0
/* Zero cross should be disabled */
/* AB8500_ANACONF5 */
#define AB8500_ANACONF5_ENCPHS 7
#define AB8500_ANACONF5_HSLDACTOLOL 5
#define AB8500_ANACONF5_HSRDACTOLOR 4
#define AB8500_ANACONF5_ENLOL 3
#define AB8500_ANACONF5_ENLOR 2
#define AB8500_ANACONF5_HSAUTOEN 0
/* AB8500_ENVCPCONF */
#define AB8500_ENVCPCONF_ENVDETHTHRE 4
#define AB8500_ENVCPCONF_ENVDETLTHRE 0
#define AB8500_ENVCPCONF_ENVDETHTHRE_MAX 0x0F
#define AB8500_ENVCPCONF_ENVDETLTHRE_MAX 0x0F
/* AB8500_SIGENVCONF */
#define AB8500_SIGENVCONF_CPLVEN 5
#define AB8500_SIGENVCONF_ENVDETCPEN 4
#define AB8500_SIGENVCONF_ENVDETTIME 0
#define AB8500_SIGENVCONF_ENVDETTIME_MAX 0x0F
/* AB8500_PWMGENCONF1 */
#define AB8500_PWMGENCONF1_PWMTOVIB1 7
#define AB8500_PWMGENCONF1_PWMTOVIB2 6
#define AB8500_PWMGENCONF1_PWM1CTRL 5
#define AB8500_PWMGENCONF1_PWM2CTRL 4
#define AB8500_PWMGENCONF1_PWM1NCTRL 3
#define AB8500_PWMGENCONF1_PWM1PCTRL 2
#define AB8500_PWMGENCONF1_PWM2NCTRL 1
#define AB8500_PWMGENCONF1_PWM2PCTRL 0
/* AB8500_PWMGENCONF2 */
/* AB8500_PWMGENCONF3 */
/* AB8500_PWMGENCONF4 */
/* AB8500_PWMGENCONF5 */
#define AB8500_PWMGENCONFX_PWMVIBXPOL 7
#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC 0
#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX 0x64
/* AB8500_ANAGAIN1 */
/* AB8500_ANAGAIN2 */
#define AB8500_ANAGAINX_ENSEMICX 7
#define AB8500_ANAGAINX_LOWPOWMICX 6
#define AB8500_ANAGAINX_MICXGAIN 0
#define AB8500_ANAGAINX_MICXGAIN_MAX 0x1F
/* AB8500_ANAGAIN3 */
#define AB8500_ANAGAIN3_HSLGAIN 4
#define AB8500_ANAGAIN3_HSRGAIN 0
#define AB8500_ANAGAIN3_HSXGAIN_MAX 0x0F
/* AB8500_ANAGAIN4 */
#define AB8500_ANAGAIN4_LINLGAIN 4
#define AB8500_ANAGAIN4_LINRGAIN 0
#define AB8500_ANAGAIN4_LINXGAIN_MAX 0x0F
/* AB8500_DIGLINHSLGAIN */
/* AB8500_DIGLINHSRGAIN */
#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN 0
#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX 0x13
/* AB8500_ADFILTCONF */
#define AB8500_ADFILTCONF_AD1NH 7
#define AB8500_ADFILTCONF_AD2NH 6
#define AB8500_ADFILTCONF_AD3NH 5
#define AB8500_ADFILTCONF_AD4NH 4
#define AB8500_ADFILTCONF_AD1VOICE 3
#define AB8500_ADFILTCONF_AD2VOICE 2
#define AB8500_ADFILTCONF_AD3VOICE 1
#define AB8500_ADFILTCONF_AD4VOICE 0
/* AB8500_DIGIFCONF1 */
#define AB8500_DIGIFCONF1_ENMASTGEN 7
#define AB8500_DIGIFCONF1_IF1BITCLKOS1 6
#define AB8500_DIGIFCONF1_IF1BITCLKOS0 5
#define AB8500_DIGIFCONF1_ENFSBITCLK1 4
#define AB8500_DIGIFCONF1_IF0BITCLKOS1 2
#define AB8500_DIGIFCONF1_IF0BITCLKOS0 1
#define AB8500_DIGIFCONF1_ENFSBITCLK0 0
/* AB8500_DIGIFCONF2 */
#define AB8500_DIGIFCONF2_FSYNC0P 6
#define AB8500_DIGIFCONF2_BITCLK0P 5
#define AB8500_DIGIFCONF2_IF0DEL 4
#define AB8500_DIGIFCONF2_IF0FORMAT1 3
#define AB8500_DIGIFCONF2_IF0FORMAT0 2
#define AB8500_DIGIFCONF2_IF0WL1 1
#define AB8500_DIGIFCONF2_IF0WL0 0
/* AB8500_DIGIFCONF3 */
#define AB8500_DIGIFCONF3_IF0DATOIF1AD 7
#define AB8500_DIGIFCONF3_IF0CLKTOIF1CLK 6
#define AB8500_DIGIFCONF3_IF1MASTER 5
#define AB8500_DIGIFCONF3_IF1DATOIF0AD 3
#define AB8500_DIGIFCONF3_IF1CLKTOIF0CLK 2
#define AB8500_DIGIFCONF3_IF0MASTER 1
#define AB8500_DIGIFCONF3_IF0BFIFOEN 0
/* AB8500_DIGIFCONF4 */
#define AB8500_DIGIFCONF4_FSYNC1P 6
#define AB8500_DIGIFCONF4_BITCLK1P 5
#define AB8500_DIGIFCONF4_IF1DEL 4
#define AB8500_DIGIFCONF4_IF1FORMAT1 3
#define AB8500_DIGIFCONF4_IF1FORMAT0 2
#define AB8500_DIGIFCONF4_IF1WL1 1
#define AB8500_DIGIFCONF4_IF1WL0 0
/* AB8500_ADSLOTSELX */
#define AB8500_AD_OUT1 0x0
#define AB8500_AD_OUT2 0x1
#define AB8500_AD_OUT3 0x2
#define AB8500_AD_OUT4 0x3
#define AB8500_AD_OUT5 0x4
#define AB8500_AD_OUT6 0x5
#define AB8500_AD_OUT7 0x6
#define AB8500_AD_OUT8 0x7
#define AB8500_ZEROES 0x8
#define AB8500_TRISTATE 0xF
#define AB8500_ADSLOTSELX_EVEN_SHIFT 0
#define AB8500_ADSLOTSELX_ODD_SHIFT 4
#define AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(out, slot) \
((out) << (((slot) & 1) ? \
AB8500_ADSLOTSELX_ODD_SHIFT : AB8500_ADSLOTSELX_EVEN_SHIFT))
/* AB8500_ADSLOTHIZCTRL1 */
/* AB8500_ADSLOTHIZCTRL2 */
/* AB8500_ADSLOTHIZCTRL3 */
/* AB8500_ADSLOTHIZCTRL4 */
/* AB8500_DASLOTCONF1 */
#define AB8500_DASLOTCONF1_DA12VOICE 7
#define AB8500_DASLOTCONF1_SWAPDA12_34 6
#define AB8500_DASLOTCONF1_DAI7TOADO1 5
/* AB8500_DASLOTCONF2 */
#define AB8500_DASLOTCONF2_DAI8TOADO2 5
/* AB8500_DASLOTCONF3 */
#define AB8500_DASLOTCONF3_DA34VOICE 7
#define AB8500_DASLOTCONF3_DAI7TOADO3 5
/* AB8500_DASLOTCONF4 */
#define AB8500_DASLOTCONF4_DAI8TOADO4 5
/* AB8500_DASLOTCONF5 */
#define AB8500_DASLOTCONF5_DA56VOICE 7
#define AB8500_DASLOTCONF5_DAI7TOADO5 5
/* AB8500_DASLOTCONF6 */
#define AB8500_DASLOTCONF6_DAI8TOADO6 5
/* AB8500_DASLOTCONF7 */
#define AB8500_DASLOTCONF7_DAI8TOADO7 5
/* AB8500_DASLOTCONF8 */
#define AB8500_DASLOTCONF8_DAI7TOADO8 5
#define AB8500_DASLOTCONFX_SLTODAX_SHIFT 0
#define AB8500_DASLOTCONFX_SLTODAX_MASK 0x1F
/* AB8500_CLASSDCONF1 */
#define AB8500_CLASSDCONF1_PARLHF 7
#define AB8500_CLASSDCONF1_PARLVIB 6
#define AB8500_CLASSDCONF1_VIB1SWAPEN 3
#define AB8500_CLASSDCONF1_VIB2SWAPEN 2
#define AB8500_CLASSDCONF1_HFLSWAPEN 1
#define AB8500_CLASSDCONF1_HFRSWAPEN 0
/* AB8500_CLASSDCONF2 */
#define AB8500_CLASSDCONF2_FIRBYP3 7
#define AB8500_CLASSDCONF2_FIRBYP2 6
#define AB8500_CLASSDCONF2_FIRBYP1 5
#define AB8500_CLASSDCONF2_FIRBYP0 4
#define AB8500_CLASSDCONF2_HIGHVOLEN3 3
#define AB8500_CLASSDCONF2_HIGHVOLEN2 2
#define AB8500_CLASSDCONF2_HIGHVOLEN1 1
#define AB8500_CLASSDCONF2_HIGHVOLEN0 0
/* AB8500_CLASSDCONF3 */
#define AB8500_CLASSDCONF3_DITHHPGAIN 4
#define AB8500_CLASSDCONF3_DITHHPGAIN_MAX 0x0A
#define AB8500_CLASSDCONF3_DITHWGAIN 0
#define AB8500_CLASSDCONF3_DITHWGAIN_MAX 0x0A
/* AB8500_DMICFILTCONF */
#define AB8500_DMICFILTCONF_ANCINSEL 7
#define AB8500_DMICFILTCONF_DA3TOEAR 6
#define AB8500_DMICFILTCONF_DMIC1SINC3 5
#define AB8500_DMICFILTCONF_DMIC2SINC3 4
#define AB8500_DMICFILTCONF_DMIC3SINC3 3
#define AB8500_DMICFILTCONF_DMIC4SINC3 2
#define AB8500_DMICFILTCONF_DMIC5SINC3 1
#define AB8500_DMICFILTCONF_DMIC6SINC3 0
/* AB8500_DIGMULTCONF1 */
#define AB8500_DIGMULTCONF1_DATOHSLEN 7
#define AB8500_DIGMULTCONF1_DATOHSREN 6
#define AB8500_DIGMULTCONF1_AD1SEL 5
#define AB8500_DIGMULTCONF1_AD2SEL 4
#define AB8500_DIGMULTCONF1_AD3SEL 3
#define AB8500_DIGMULTCONF1_AD5SEL 2
#define AB8500_DIGMULTCONF1_AD6SEL 1
#define AB8500_DIGMULTCONF1_ANCSEL 0
/* AB8500_DIGMULTCONF2 */
#define AB8500_DIGMULTCONF2_DATOHFREN 7
#define AB8500_DIGMULTCONF2_DATOHFLEN 6
#define AB8500_DIGMULTCONF2_HFRSEL 5
#define AB8500_DIGMULTCONF2_HFLSEL 4
#define AB8500_DIGMULTCONF2_FIRSID1SEL 2
#define AB8500_DIGMULTCONF2_FIRSID2SEL 0
/* AB8500_ADDIGGAIN1 */
/* AB8500_ADDIGGAIN2 */
/* AB8500_ADDIGGAIN3 */
/* AB8500_ADDIGGAIN4 */
/* AB8500_ADDIGGAIN5 */
/* AB8500_ADDIGGAIN6 */
#define AB8500_ADDIGGAINX_FADEDISADX 6
#define AB8500_ADDIGGAINX_ADXGAIN_MAX 0x3F
/* AB8500_DADIGGAIN1 */
/* AB8500_DADIGGAIN2 */
/* AB8500_DADIGGAIN3 */
/* AB8500_DADIGGAIN4 */
/* AB8500_DADIGGAIN5 */
/* AB8500_DADIGGAIN6 */
#define AB8500_DADIGGAINX_FADEDISDAX 6
#define AB8500_DADIGGAINX_DAXGAIN_MAX 0x3F
/* AB8500_ADDIGLOOPGAIN1 */
/* AB8500_ADDIGLOOPGAIN2 */
#define AB8500_ADDIGLOOPGAINX_FADEDISADXL 6
#define AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX 0x3F
/* AB8500_HSLEARDIGGAIN */
#define AB8500_HSLEARDIGGAIN_HSSINC1 7
#define AB8500_HSLEARDIGGAIN_FADEDISHSL 4
#define AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX 0x09
/* AB8500_HSRDIGGAIN */
#define AB8500_HSRDIGGAIN_FADESPEED 6
#define AB8500_HSRDIGGAIN_FADEDISHSR 4
#define AB8500_HSRDIGGAIN_HSRDGAIN_MAX 0x09
/* AB8500_SIDFIRGAIN1 */
/* AB8500_SIDFIRGAIN2 */
#define AB8500_SIDFIRGAINX_FIRSIDXGAIN_MAX 0x1F
/* AB8500_ANCCONF1 */
#define AB8500_ANCCONF1_ANCIIRUPDATE 3
#def