/* * Copyright (C) 2011 OMICRON electronics GmbH * * Based on da850evm.h. Original Copyrights follow: * * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ * Copyright (C) 2007 Sergey Kubushyn * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H /* * Board */ #define CONFIG_DRIVER_TI_EMAC #define MACH_TYPE_CALIMAIN 3528 #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN /* * SoC Configuration */ #define CONFIG_MACH_DAVINCI_CALIMAIN #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_TEXT_BASE 0x60000000 #define CONFIG_DA850_LOWLEVEL #define CONFIG_SYS_DA850_PLL_INIT #define CONFIG_SYS_DA850_DDR_INIT #define CONFIG_ARCH_CPU_INIT #define CONFIG_DA8XX_GPIO #define CONFIG_HW_WATCHDOG #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE #define CONFIG_SYS_WDT_PERIOD_LOW \ (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) /* * PLL configuration */ #define CONFIG_SYS_DV_CLKMODE 0 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 #define CONFIG_SYS_DA850_PLL0_PLLM \ ((calimain_get_osc_freq() == 25000000) ? 23 : 24) #define CONFIG_SYS_DA850_PLL1_PLLM \ ((calimain_get_osc_freq() == 25000000) ? 20 : 21) /* * DDR2 memory configuration */ #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (1 << DV_DDR_SDTMR1_WTR_SHIFT)) #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (2 << DV_DDR_SDTMR2_CKE_SHIFT)) #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 /* * Flash memory timing */ #define CONFIG_SYS_DA850_CS2CFG ( \ DAVINCI_ABCR_WSETUP(2) | \ DAVINCI_ABCR_WSTROBE(5) | \ DAVINCI_ABCR_WHOLD(3) | \ DAVINCI_ABCR_RSETUP(1) | \ DAVINCI_ABCR_RSTROBE(14) | \ DAVINCI_ABCR_RHOLD(0) | \ DAVINCI_ABCR_TA(3) | \ DAVINCI_ABCR_ASIZE_16BIT) /* single 64 MB NOR flash device connected to CS2 and CS3 */ #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG /* * Memory Info */ #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ DAVINCI_SYSCFG_SUSPSRC_EMAC | \ DAVINCI_SYSCFG_SUSPSRC_I2C) /* memtest start addr */ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) /* memtest will be run on 16MB */ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ /* * Serial Driver info */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ #define CONFIG_ENV_ADDR \ (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SEC