/* * wm8400.c -- WM8400 ALSA Soc Audio driver * * Copyright 2008-11 Wolfson Microelectronics PLC. * Author: Mark Brown * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "wm8400.h" static struct regulator_bulk_data power[] = { { .supply = "I2S1VDD", }, { .supply = "I2S2VDD", }, { .supply = "DCVDD", }, { .supply = "AVDD", }, { .supply = "FLLVDD", }, { .supply = "HPVDD", }, { .supply = "SPKVDD", }, }; /* codec private data */ struct wm8400_priv { struct wm8400 *wm8400; u16 fake_register; unsigned int sysclk; unsigned int pcmclk; int fll_in, fll_out; }; static void wm8400_codec_reset(struct snd_soc_codec *codec) { struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); wm8400_reset_codec_reg_cache(wm8400->wm8400); } static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0); static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; int reg = mc->reg; int ret; u16 val; ret = snd_soc_put_volsw(kcontrol, ucontrol); if (ret < 0) return ret; /* now hit the volume update bits (always bit 8) */ val = snd_soc_read(codec, reg); return snd_soc_write(codec, reg, val | 0x0100); } #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \ SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \ snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array) static const char *wm8400_digital_sidetone[] = {"None", "Left ADC", "Right ADC", "Reserved"}; static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum, WM8400_DIGITAL_SIDE_TONE, WM8400_ADC_TO_DACL_SHIFT, wm8400_digital_sidetone); static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum, WM8400_DIGITAL_SIDE_TONE, WM8400_ADC_TO_DACR_SHIFT, wm8400_digital_sidetone); static const char *wm8400_adcmode[] = {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum, WM8400_ADC_CTRL, WM8400_ADC_HPF_CUT_SHIFT, wm8400_adcmode); static const struct snd_kcontrol_new wm8400_snd_controls[] = { /* INMIXL */ SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT, 1, 0), SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT, 1, 0), /* INMIXR */ SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT, 1, 0), SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT, 1, 0), /* LOMIX */ SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3, WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5, WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5, WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5, WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), /* ROMIX */ SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4, WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6, WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6, WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv), SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6, WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv), /* LOUT */ WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv), SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0), /* ROUT */ WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv), SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0), /* LOPGA */ WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME, WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv), SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME, WM8400_LOPGAZC_SHIFT, 1, 0), /* ROPGA */ WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME, WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv), SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME, WM8400_ROPGAZC_SHIFT, 1, 0), SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, WM8400_LONMUTE_SHIFT, 1, 0), SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, WM8400_LOPMUTE_SHIFT, 1, 0), SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, WM8400_LOATTN_SHIFT, 1, 0), SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, WM8400_RONMUTE_SHIFT, 1, 0), SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, WM8400_ROPMUTE_SHIFT, 1, 0), SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, WM8400_ROATTN_SHIFT, 1, 0), SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME, WM8400_OUT3MUTE_SHIFT, 1, 0), SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME, WM8400_OUT3ATTN_SHIFT, 1, 0), SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME, WM8400_OUT4MUTE_SHIFT, 1, 0), SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME, WM8400_OUT4ATTN_SHIFT, 1, 0), SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1, WM8400_CDMODE_SHIFT, 1, 0), SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME, WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0), SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3, WM8400_DCGAIN_SHIFT, 6, 0), SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3, WM8400_ACGAIN_SHIFT, 6, 0), WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT, 127, 0, out_dac_tlv), WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT, 127, 0, out_dac_tlv), SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum), SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum), SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL, WM8400_ADC_HPF_ENA_SHIFT, 1, 0), SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum), WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", WM8400_LEFT_ADC_DIGITAL_VOLUME, WM8400_ADCL_VOL_SHIFT, WM8400_ADCL_VOL_MASK, 0, in_adc_tlv), WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", WM8400_RIGHT_ADC_DIGITAL_VOLUME, WM8400_ADCR_VOL_SHIFT, WM8400_ADCR_VOL_MASK, 0, in_adc_tlv), WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, WM8400_LIN12VOL_SHIFT, WM8400_LIN12VOL_MASK, 0, in_pga_tlv), SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, WM8400_LI12ZC_SHIFT, 1, 0), SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, WM8400_LI12MUTE_SHIFT, 1, 0), WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, WM8400_LIN34VOL_SHIFT, WM8400_LIN34VOL_MASK, 0, in_pga_tlv), SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, WM8400_LI34ZC_SHIFT, 1, 0), SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, WM8400_LI34MUTE_SHIFT, 1, 0), WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, WM8400_RIN12VOL_SHIFT, WM8400_RIN12VOL_MASK, 0, in_pga_tlv), SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, WM8400_RI12ZC_SHIFT, 1, 0), SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, WM8400_RI12MUTE_SHIFT, 1, 0), WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, WM8400_RIN34VOL_SHIFT, WM8400_RIN34VOL_MASK, 0, in_pga_tlv), SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, WM8400_RI34ZC_SHIFT, 1, 0), SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, WM8400_RI34MUTE_SHIFT, 1, 0), }; /* * _DAPM_ Controls */ static int outmixer_event (struct snd_soc_dapm_widget *w, struct snd_kcontrol * kcontrol, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; u32 reg_shift = mc->shift; int ret = 0; u16 reg; switch (reg_shift) { case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) : reg = snd_soc_read(codec, WM8400_OUTPUT_MIXER1); if (reg & WM8400_LDLO) { printk(KERN_WARNING "Cannot set as Output Mixer 1 LDLO Set\n"); ret = -1; } break; case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8): reg = snd_soc_read(codec, WM8400_OUTPUT_MIXER2); if (reg & WM8400_RDRO) { printk(KERN_WARNING "Cannot set as Output Mixer 2 RDRO Set\n"); ret = -1; } break; case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8): reg = snd_soc_read(codec, WM8400_SPEAKER_MIXER); if (reg & WM8400_LDSPK) { printk(KERN_WARNING "Cannot set as Speaker Mixer LDSPK Set\n"); ret = -1; } break; case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8): reg = snd_soc_read(codec, WM8400_SPEAKER_MIXER); if (reg & WM8400_RDSPK) { printk(KERN_WARNING "Cannot set as Speaker Mixer RDSPK Set\n"); ret = -1; } break; } return ret; } /* INMIX dB values */ static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0); /* Left In PGA Connections */ static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = { SOC_DAPM_SINGLE("LIN1 Switch", WM84
/*
  drbd_limits.h
  This file is part of DRBD by Philipp Reisner and Lars Ellenberg.
*/

/*
 * Our current limitations.
 * Some of them are hard limits,
 * some of them are arbitrary range limits, that make it easier to provide
 * feedback about nonsense settings for certain configurable values.
 */

#ifndef DRBD_LIMITS_H
#define DRBD_LIMITS_H 1

#define DEBUG_RANGE_CHECK 0

#define DRBD_MINOR_COUNT_MIN 1
#define DRBD_MINOR_COUNT_MAX 255
#define DRBD_MINOR_COUNT_DEF 32
#define DRBD_MINOR_COUNT_SCALE '1'

#define DRBD_VOLUME_MAX 65535

#define DRBD_DIALOG_REFRESH_MIN 0
#define DRBD_DIALOG_REFRESH_MAX 600
#define DRBD_DIALOG_REFRESH_SCALE '1'

/* valid port number */
#define DRBD_PORT_MIN 1
#define DRBD_PORT_MAX 0xffff
#define DRBD_PORT_SCALE '1'

/* startup { */
  /* if you want more than 3.4 days, disable */
#define DRBD_WFC_TIMEOUT_MIN 0
#define DRBD_WFC_TIMEOUT_MAX 300000
#define DRBD_WFC_TIMEOUT_DEF 0
#define DRBD_WFC_TIMEOUT_SCALE '1'

#define DRBD_DEGR_WFC_TIMEOUT_MIN 0
#define DRBD_DEGR_WFC_TIMEOUT_MAX 300000
#define DRBD_DEGR_WFC_TIMEOUT_DEF 0
#define DRBD_DEGR_WFC_TIMEOUT_SCALE '1'

#define DRBD_OUTDATED_WFC_TIMEOUT_MIN 0
#define DRBD_OUTDATED_WFC_TIMEOUT_MAX 300000
#define DRBD_OUTDATED_WFC_TIMEOUT_DEF 0
#define DRBD_OUTDATED_WFC_TIMEOUT_SCALE '1'
/* }*/

/* net { */
  /* timeout, unit centi seconds
   * more than one minute timeout is not useful */
#define DRBD_TIMEOUT_MIN 1
#define DRBD_TIMEOUT_MAX 600
#define DRBD_TIMEOUT_DEF 60       /* 6 seconds */
#define DRBD_TIMEOUT_SCALE '1'

 /* If backing disk takes longer than disk_timeout, mark the disk as failed */
#define DRBD_DISK_TIMEOUT_MIN 0    /* 0 = disabled */
#define DRBD_DISK_TIMEOUT_MAX 6000 /* 10 Minutes */
#define DRBD_DISK_TIMEOUT_DEF 0    /* disabled */
#define DRBD_DISK_TIMEOUT_SCALE '1'

  /* active connection retries when C_WF_CONNECTION */
#define DRBD_CONNECT_INT_MIN 1
#define DRBD_CONNECT_INT_MAX 120
#define DRBD_CONNECT_INT_DEF 10   /* seconds */
#define DRBD_CONNECT_INT_SCALE '1'

  /* keep-alive probes when idle */
#define DRBD_PING_INT_MIN 1
#define DRBD_PING_INT_MAX 120
#define DRBD_PING_INT_DEF 10
#define DRBD_PING_INT_SCALE '1'

 /* timeout for the ping packets.*/
#define DRBD_PING_TIMEO_MIN  1
#define DRBD_PING_TIMEO_MAX  300
#define DRBD_PING_TIMEO_DEF  5
#define DRBD_PING_TIMEO_SCALE '1'

  /* max number of write requests between write barriers */
#define DRBD_MAX_EPOCH_SIZE_MIN 1
#define DRBD_MAX_EPOCH_SIZE_MAX 20000
#define DRBD_MAX_EPOCH_SIZE_DEF 2048
#define DRBD_MAX_EPOCH_SIZE_SCALE '1'

  /* I don't think that a tcp send buffer of more than 10M is useful */
#define DRBD_SNDBUF_SIZE_MIN  0
#define DRBD_SNDBUF_SIZE_MAX  (10<<20)
#define DRBD_SNDBUF_SIZE_DEF  0
#define DRBD_SNDBUF_SIZE_SCALE '1'

#define DRBD_RCVBUF_SIZE_MIN  0
#define DRBD_RCVBUF_SIZE_MAX  (10<<20)
#define DRBD_RCVBUF_SIZE_DEF  0
#define DRBD_RCVBUF_SIZE_SCALE '1'

  /* @4k PageSize -> 128kB - 512MB */
#define DRBD_MAX_BUFFERS_MIN  32
#define DRBD_MAX_BUFFERS_MAX  131072
#define DRBD_MAX_BUFFERS_DEF  2048
#define DRBD_MAX_BUFFERS_SCALE '1'

  /* @4k PageSize -> 4kB - 512MB */
#define DRBD_UNPLUG_WATERMARK_MIN  1
#define DRBD_UNPLUG_WATERMARK_MAX  131072
#define DRBD_UNPLUG_WATERMARK_DEF (DRBD_MAX_BUFFERS_DEF/16)
#define DRBD_UNPLUG_WATERMARK_SCALE '1'

  /* 0 is disabled.
   * 200 should be more than enough even for very short timeouts */
#define DRBD_KO_COUNT_MIN  0
#define DRBD_KO_COUNT_MAX  200
#define DRBD_KO_COUNT_DEF  7
#define DRBD_KO_COUNT_SCALE '1'
/* } */

/* syncer { */
  /* FIXME allow rate to be zero? */
#define DRBD_RESYNC_RATE_MIN 1
/* channel bonding 10 GbE, or other hardware */
#define DRBD_RESYNC_RATE_MAX (4 << 20)
#define DRBD_RESYNC_RATE_DEF 250
#define DRBD_RESYNC_RATE_SCALE 'k'  /* kilobytes */

  /* less than 7 would hit performance unnecessarily. */
#define DRBD_AL_EXTENTS_MIN  7
  /* we use u16 as "slot number", (u16)~0 is "FREE".
   * If you use >= 292 kB on-disk ring buffer,
   * this is the maximum you can use: */
#define DRBD_AL_EXTENTS_MAX  0xfffe
#define DRBD_AL_EXTENTS_DEF  1237
#define DRBD_AL_EXTENTS_SCALE '1'

#define DRBD_MINOR_NUMBER_MIN  -1
#define DRBD_MINOR_NUMBER_MAX  ((1 << 20) - 1)
#define DRBD_MINOR_NUMBER_DEF  -1
#define DRBD_MINOR_NUMBER_SCALE '1'

/* } */

/* drbdsetup XY resize -d Z
 * you are free to reduce the device size to nothing, if you want to.
 * the upper limit with 64bit kernel, enough ram and flexible meta data
 * is 1 PiB, currently. */
/* DRBD_MAX_SECTORS */
#define DRBD_DISK_SIZE_MIN  0
#define DRBD_DISK_SIZE_MAX  (1 * (2LLU << 40))
#define DRBD_DISK_SIZE_DEF  0 /* = disabled = no user size... */
#define DRBD_DISK_SIZE_SCALE 's'  /* sectors */

#define DRBD_ON_IO_ERROR_DEF EP_DETACH
#define DRBD_FENCING_DEF FP_DONT_CARE
#define DRBD_AFTER_SB_0P_DEF ASB_DISCONNECT
#define DRBD_AFTER_SB_1P_DEF ASB_DISCONNECT
#define DRBD_AFTER_SB_2P_DEF ASB_DISCONNECT
#define DRBD_RR_CONFLICT_DEF ASB_DISCONNECT
#define DRBD_ON_NO_DATA_DEF OND_IO_ERROR
#define DRBD_ON_CONGESTION_DEF OC_BLOCK
#define DRBD_READ_BALANCING_DEF RB_PREFER_LOCAL

#define DRBD_MAX_BIO_BVECS_MIN 0
#define DRBD_MAX_BIO_BVECS_MAX 128
#define DRBD_MAX_BIO_BVECS_DEF 0
#define DRBD_MAX_BIO_BVECS_SCALE '1'

#define DRBD_C_PLAN_AHEAD_MIN  0
#define DRBD_C_PLAN_AHEAD_MAX  300
#define DRBD_C_PLAN_AHEAD_DEF  20
#define DRBD_C_PLAN_AHEAD_SCALE '1'

#define DRBD_C_DELAY_TARGET_MIN 1
#define DRBD_C_DELAY_TARGET_MAX 100
#define DRBD_C_DELAY_TARGET_DEF 10
#define DRBD_C_DELAY_TARGET_SCALE '1'

#define DRBD_C_FILL_TARGET_MIN 0
#define DRBD_C_FILL_TARGET_MAX (1<<20) /* 500MByte in sec */
#define DRBD_C_FILL_TARGET_DEF 100 /* Try to place 50KiB in socket send buffer during resync */
#define DRBD_C_FILL_TARGET_SCALE 's'  /* sectors */

#define DRBD_C_MAX_RATE_MIN     250
#define DRBD_C_MAX_RATE_MAX     (4 << 20)
#define DRBD_C_MAX_RATE_DEF     102400
#define DRBD_C_MAX_RATE_SCALE	'k'  /* kilobytes */

#define DRBD_C_MIN_RATE_MIN     0
#define DRBD_C_MIN_RATE_MAX     (4 << 20)
#define DRBD_C_MIN_RATE_DEF     250
#define DRBD_C_MIN_RATE_SCALE	'k'  /* kilobytes */

#define DRBD_CONG_FILL_MIN	0
#define DRBD_CONG_FILL_MAX	(10<<21) /* 10GByte in sectors */
#define DRBD_CONG_FILL_DEF	0
#define DRBD_CONG_FILL_SCALE	's'  /* sectors */

#define DRBD_CONG_EXTENTS_MIN	DRBD_AL_EXTENTS_MIN
#define DRBD_CONG_EXTENTS_MAX	DRBD_AL_EXTENTS_MAX
#define DRBD_CONG_EXTENTS_DEF	DRBD_AL_EXTENTS_DEF
#define DRBD_CONG_EXTENTS_SCALE DRBD_AL_EXTENTS_SCALE

#define DRBD_PROTOCOL_DEF DRBD_PROT_C

#define DRBD_DISK_BARRIER_DEF	0
#define DRBD_DISK_FLUSHES_DEF	1
#define DRBD_DISK_DRAIN_DEF	1
#define DRBD_MD_FLUSHES_DEF	1
#define DRBD_TCP_CORK_DEF	1
#define DRBD_AL_UPDATES_DEF     1

#define DRBD_ALLOW_TWO_PRIMARIES_DEF	0
#define DRBD_ALWAYS_ASBP_DEF	0
#define DRBD_USE_RLE_DEF	1
#define DRBD_CSUMS_AFTER_CRASH_ONLY_DEF 0

#define DRBD_AL_STRIPES_MIN     1
#define DRBD_AL_STRIPES_MAX     1024
#define DRBD_AL_STRIPES_DEF     1
#define DRBD_AL_STRIPES_SCALE   '1'

#define DRBD_AL_STRIPE_SIZE_MIN   4
#define DRBD_AL_STRIPE_SIZE_MAX   16777216
#define DRBD_AL_STRIPE_SIZE_DEF   32
#define DRBD_AL_STRIPE_SIZE_SCALE 'k' /* kilobytes */

#define DRBD_SOCKET_CHECK_TIMEO_MIN 0
#define DRBD_SOCKET_CHECK_TIMEO_MAX DRBD_PING_TIMEO_MAX
#define DRBD_SOCKET_CHECK_TIMEO_DEF 0
#define DRBD_SOCKET_CHECK_TIMEO_SCALE '1'
#endif
te) { struct snd_soc_codec *codec = dai->codec; u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE; if (mute) snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); else snd_soc_write(codec, WM8400_DAC_CTRL, val); return 0; } /* TODO: set bias for best performance at standby */ static int wm8400_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); u16 val; int ret; switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: /* VMID=2*50k */ val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) & ~WM8400_VMID_MODE_MASK; snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2); break; case SND_SOC_BIAS_STANDBY: if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { ret = regulator_bulk_enable(ARRAY_SIZE(power), &power[0]); if (ret != 0) { dev_err(wm8400->wm8400->dev, "Failed to enable regulators: %d\n", ret); return ret; } snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, WM8400_CODEC_ENA | WM8400_SYSCLK_ENA); /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | WM8400_BUFDCOPEN | WM8400_POBCTRL); msleep(50); /* Enable VREF & VMID at 2x50k */ val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); val |= 0x2 | WM8400_VREF_ENA; snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); /* Enable BUFIOEN */ snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | WM8400_BUFDCOPEN | WM8400_POBCTRL | WM8400_BUFIOEN); /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN); } /* VMID=2*300k */ val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) & ~WM8400_VMID_MODE_MASK; snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4); break; case SND_SOC_BIAS_OFF: /* Enable POBCTRL and SOFT_ST */ snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | WM8400_POBCTRL | WM8400_BUFIOEN); /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | WM8400_BUFDCOPEN | WM8400_POBCTRL | WM8400_BUFIOEN); /* mute DAC */ val = snd_soc_read(codec, WM8400_DAC_CTRL); snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); /* Enable any disabled outputs */ val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); val |= WM8400_SPK_ENA | WM8400_OUT3_ENA | WM8400_OUT4_ENA | WM8400_LOUT_ENA | WM8400_ROUT_ENA; snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); /* Disable VMID */ val &= ~WM8400_VMID_MODE_MASK; snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); msleep(300); /* Enable all output discharge bits */ snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE | WM8400_DIS_RLINE | WM8400_DIS_OUT3 | WM8400_DIS_OUT4 | WM8400_DIS_LOUT | WM8400_DIS_ROUT); /* Disable VREF */ val &= ~WM8400_VREF_ENA; snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ snd_soc_write(codec, WM8400_ANTIPOP2, 0x0); ret = regulator_bulk_disable(ARRAY_SIZE(power), &power[0]); if (ret != 0) return ret; break; } return 0; } #define WM8400_RATES SNDRV_PCM_RATE_8000_96000 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE) static const struct snd_soc_dai_ops wm8400_dai_ops = { .hw_params = wm8400_hw_params, .digital_mute = wm8400_mute, .set_fmt = wm8400_set_dai_fmt, .set_clkdiv = wm8400_set_dai_clkdiv, .set_sysclk = wm8400_set_dai_sysclk, .set_pll = wm8400_set_dai_pll, }; /* * The WM8400 supports 2 different and mutually exclusive DAI * configurations. * * 1. ADC/DAC on Primary Interface * 2. ADC on Primary Interface/DAC on secondary */ static struct snd_soc_dai_driver wm8400_dai = { /* ADC/DAC on primary */ .name = "wm8400-hifi", .playback = { .stream_name = "Playback", .channels_min = 1, .channels_max = 2, .rates = WM8400_RATES, .formats = WM8400_FORMATS, }, .capture = { .stream_name = "Capture", .channels_min = 1, .channels_max = 2, .rates = WM8400_RATES, .formats = WM8400_FORMATS, }, .ops = &wm8400_dai_ops, }; static int wm8400_codec_probe(struct snd_soc_codec *codec) { struct wm8400 *wm8400 = dev_get_platdata(codec->dev); struct wm8400_priv *priv; int ret; u16 reg; priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv), GFP_KERNEL); if (priv == NULL) return -ENOMEM; snd_soc_codec_set_drvdata(codec, priv); priv->wm8400 = wm8400; ret = devm_regulator_bulk_get(wm8400->dev, ARRAY_SIZE(power), &power[0]); if (ret != 0) { dev_err(codec->dev, "Failed to get regulators: %d\n", ret); return ret; } wm8400_codec_reset(codec); reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA); /* Latch volume update bits */ reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME); snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME, reg & WM8400_IPVU); reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME); snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, reg & WM8400_IPVU); snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); return 0; } static int wm8400_codec_remove(struct snd_soc_codec *codec) { u16 reg; reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg & (~WM8400_CODEC_ENA)); return 0; } static struct regmap *wm8400_get_regmap(struct device *dev) { struct wm8400 *wm8400 = dev_get_platdata(dev); return wm8400->regmap; } static struct snd_soc_codec_driver soc_codec_dev_wm8400 = { .probe = wm8400_codec_probe, .remove = wm8400_codec_remove, .get_regmap = wm8400_get_regmap, .set_bias_level = wm8400_set_bias_level, .suspend_bias_off = true, .controls = wm8400_snd_controls, .num_controls = ARRAY_SIZE(wm8400_snd_controls), .dapm_widgets = wm8400_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets), .dapm_routes = wm8400_dapm_routes, .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes), }; static int wm8400_probe(struct platform_device *pdev) { return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400, &wm8400_dai, 1); } static int wm8400_remove(struct platform_device *pdev) { snd_soc_unregister_codec(&pdev->dev); return 0; } static struct platform_driver wm8400_codec_driver = { .driver = { .name = "wm8400-codec", }, .probe = wm8400_probe, .remove = wm8400_remove, }; module_platform_driver(wm8400_codec_driver); MODULE_DESCRIPTION("ASoC WM8400 driver"); MODULE_AUTHOR("Mark Brown"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:wm8400-codec");