/* * NXP LPC32XX NAND SLC driver * * Authors: * Kevin Wells * Roland Stigge * * Copyright © 2011 NXP Semiconductors * Copyright © 2012 Roland Stigge * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define LPC32XX_MODNAME "lpc32xx-nand" /********************************************************************** * SLC NAND controller register offsets **********************************************************************/ #define SLC_DATA(x) (x + 0x000) #define SLC_ADDR(x) (x + 0x004) #define SLC_CMD(x) (x + 0x008) #define SLC_STOP(x) (x + 0x00C) #define SLC_CTRL(x) (x + 0x010) #define SLC_CFG(x) (x + 0x014) #define SLC_STAT(x) (x + 0x018) #define SLC_INT_STAT(x) (x + 0x01C) #define SLC_IEN(x) (x + 0x020) #define SLC_ISR(x) (x + 0x024) #define SLC_ICR(x) (x + 0x028) #define SLC_TAC(x) (x + 0x02C) #define SLC_TC(x) (x + 0x030) #define SLC_ECC(x) (x + 0x034) #define SLC_DMA_DATA(x) (x + 0x038) /********************************************************************** * slc_ctrl register definitions **********************************************************************/ #define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */ #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ #define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */ /********************************************************************** * slc_cfg register definitions **********************************************************************/ #define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */ #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */ #define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */ #define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ #define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */ /********************************************************************** * slc_stat register definitions **********************************************************************/ #define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */ #define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */ /********************************************************************** * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions **********************************************************************/ #define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */ #define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */ /********************************************************************** * slc_tac register definitions **********************************************************************/ /* Computation of clock cycles on basis of controller and device clock rates */ #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s) /* Clock setting for RDY write sample wait time in 2*n clocks */ #define SLCTAC_WDR(n) (((n) & 0xF) << 28) /* Write pulse width in clock cycles, 1 to 16 clocks */ #define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24)) /* Write hold time of control and data signals, 1 to 16 clocks */ #define SLCTAC_WHOLD(c, n) (SLCTAC_CLOCKS(c, n, 20)) /* Write setup time of control and data signals, 1 to 16 clocks */ #define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16)) /* Clock setting for RDY read sample wait time in 2*n clocks */ #define SLCTAC_RDR(n) (((n) & 0xF) << 12) /* Read pulse width in clock cycles, 1 to 16 clocks */ #define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8)) /* Read hold time of control and data signals, 1 to 16 clocks */ #define SLCTAC_RHOLD(c, n) (SLCTAC_CLOCKS(c, n, 4)) /* Read setup time of control and data signals, 1 to 16 clocks */ #define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0)) /********************************************************************** * slc_ecc register definitions **********************************************************************/ /* ECC line party fetch macro */ #define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF) #define SLCECC_TO_COLPAR(n) ((n) & 0x3F) /* * DMA requires storage space for the DMA local buffer and the hardware ECC * storage area. The DMA local buffer is only used if DMA mapping fails * during runtime. */ #define LPC32XX_DMA_DATA_SIZE 4096 #define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4) /* Number of bytes used for ECC stored in NAND per 256 bytes */ #define LPC32XX_SLC_DEV_ECC_BYTES 3 /* * If the NAND base clock frequency can't be fetched, this frequency will be * used instead as the base. This rate is used to setup the timing registers * used for NAND accesses. */ #define LPC32XX_DEF_BUS_RATE 133250000 /* Milliseconds for DMA FIFO timeout (unlikely anyway) */ #define LPC32XX_DMA_TIMEOUT 100 /* * NAND ECC Layout for small page NAND devices * Note: For large and huge page devices, the default layouts are used */ static struct nand_ecclayout lpc32xx_nand_oob_16 = { .eccbytes = 6, .eccpos = {10, 11, 12, 13, 14, 15}, .oobfree = { { .offset = 0, .length = 4 }, { .offset = 6, .length = 4 }, }, }; static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; /* * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6 * Note: Large page devices used the default layout */ static struct nand_bbt_descr bbt_smallpage_main_descr = { .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, .offs = 0, .len = 4, .veroffs = 6, .maxblocks = 4, .pattern = bbt_pattern }; static struct nand_bbt_descr bbt_smallpage_mirror_descr = { .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, .offs = 0, .len = 4, .veroffs = 6, .maxblocks = 4, .pattern = mirror_pattern }; /* * NAND platform configuration structure */ struct lpc32xx_nand_cfg_slc { uint32_t wdr_clks; uint32_t wwidth; uint32_t whold; uint32_t wsetup; uint32_t rdr_clks; uint32_t rwidth; uint32_t rhold; uint32_t rsetup; bool use_bbt; int wp_gpio; struct mtd_partition *parts; unsigned num_parts; }; struct lpc32xx_nand_host { struct nand_chip nand_chip; struct lpc32xx_slc_platform_data *pdata; struct clk *clk; struct mtd_info mtd; void __iomem *io_base; struct lpc32xx_nand_cfg_slc *ncfg; struct completion comp; struct dma_chan *dma_chan; uint32_t dma_buf_len; struct dma_slave_config dma_slave_config; struct scatterlist sgl; /* * DMA and CPU addresses of ECC work area and data buffer */ uint32_t *ecc_buf; uint8_t *data_buf; dma_addr_t io_base_dma; }; static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) { uint32_t clkrate, tmp; /* Reset SLC controller */ writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); udelay(1000); /* Basic setup */ writel(0, SLC_CFG(host->io_base)); writel(0, SLC_IEN(host->io_base)); writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN), SLC_ICR(host->io_base)); /* Get base clock for SLC block */ clkrate = clk_get_rate(host->clk); if (clkrate == 0) clkrate = LPC32XX_DEF_BUS_RATE; /* Compute clock setup values */ tmp = SLCTAC_WDR(host->ncfg->wdr_clks) | SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) | SLCTAC_WHOLD(clkrate, host->ncfg->whold) | SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) | SLCTAC_RDR(host->ncfg->rdr_clks) | SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) | SLCTAC_RHOLD(clkrate, host->ncfg->rhold) | SLCTAC_RSETUP(clkrate, host->ncfg->rsetup); writel(tmp, SLC_TAC(host->io_base)); } /* * Hardware specific access to control lines */ static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { uint32_t tmp; struct nand_chip *chip = mtd->priv; struct lpc32xx_nand_host *host = chip->priv; /* Does CE state need to be changed? */ tmp = readl(SLC_CFG(host->io_base)); if (ctrl & NAND_NCE) tmp |= SLCCFG_CE_LOW; else tmp &= ~SLCCFG_CE_LOW; writel(tmp, SLC_CFG(host->io_base)); if (cmd != NAND_CMD_NONE) { if (ctrl & NAND_CLE) writel(cmd, SLC_CMD(host->io_base)); else writel(cmd, SLC_ADDR(host->io_base)); } } /* * Read the Device Ready pin */ static int lpc32xx_nand_device_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; struct lpc32xx_nand_host *host = chip->priv; int rdy = 0; if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0) rdy = 1; return rdy; } /* * Enable NAND write protect */ static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) { if (gpio_is_valid(host->ncfg->wp_gpio)) gpio_set_value(host->ncfg->wp_gpio, 0); } /* * Disable NAND write protect */ static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) { if (gpio_is_valid(host->ncfg->wp_gpio)) gpio_set_value(host->ncfg->wp_gpio, 1); } /* * Prepares SLC for transfers with H/W ECC enabled */ static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode) { /* Hardware ECC is enabled automatically in hardware as needed */ } /* * Calculates the ECC for the data */ static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd, const unsigned char *buf, unsigned char *code) { /* * ECC is calculated automatically in hardware during syndrome read * and write operations, so it doesn't need to be calculated here. */ return 0; } /* * Read a single byte from NAND device */ static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; struct lpc32xx_nand_host *host = chip->priv; return (uint8_t)readl(SLC_DATA(host->io_base)); } /* * Simple device read without ECC */ static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { struct nand_chip *chip = mtd->priv; struct lpc32xx_nand_host *host = chip->priv; /* Direct device read with no ECC */ while (len-- > 0) *buf++ = (uint8_t)readl(SLC_DATA(host->io_base)); } /* * Simple device write without ECC */ static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { struct nand_chip *chip = mtd->priv; struct lpc32xx_nand_host *host = chip->priv; /* Direct device write with no ECC */ while (len-- > 0) writel((uint32_t)*buf++, SLC_DATA(host->io_base)); } /* * Read the OOB data from the device without ECC using FIFO method */ static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page) { chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); return 0; } /* * Write the OOB data to the device without ECC using FIFO method */ static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page) { int status; chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); /* Send command to program the OOB data */ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); status = chip->waitfunc(mtd, chip); return status & NAND_STATUS_FAIL ? -EIO : 0; } /* * Fills in the ECC fields in the OOB buffer with the hardware generated ECC */ static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) { int i; for (i = 0; i < (count * 3); i += 3) { uint32_t ce = ecc[i / 3]; ce = ~(ce << 2) & 0xFFFFFF; spare[i + 2] = (uint8_t)(ce & 0xFF); ce >>= 8; spare[i + 1] = (uint8_t)(ce & 0xFF); ce >>= 8; spare[i] = (uint8_t)(ce & 0xFF); } } static void lpc32xx_dma_complete_func(void *completion) { complete(completion); } static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma, void *mem, int len, enum dma_transfer_direction dir) { struct nand_chip *chip = mtd->priv; struct lpc32xx_nand_host *host = chip->priv; struct dma_async_tx_descriptor *desc; int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; int res; host->dma_slave_config.direction = dir; host->dma_slave_config.src_addr = dma; host->dma_slave_config.dst_addr = dma; host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; host->dma_slave_config.src_maxburst = 4; host->dma_slave_config.dst_maxburst = 4; /* DMA controller does flow control: */ host->dma_slave_config.device_fc = false; if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); return -ENXIO; } sg_init_one(&host->sgl, mem, len); res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, DMA_BIDIRECTIONAL); if (res != 1) { dev_err(mtd->dev.parent, "Failed to map sg list\n"); return -ENXIO; } desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, flags); if (!desc) { dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); goto out1; } init_completion(&host->comp); desc->callback = lpc32xx_dma_complete_func; desc->callback_param = &host->comp; dmaengine_submit(desc); dma_async_issue_pending(host->dma_chan); wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000)); dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, DMA_BIDIRECTIONAL); return 0; out1: dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, DMA_BIDIRECTIONAL); return -ENXIO; } /* * DMA read/write transfers with ECC support */ static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages, int read) { struct nand_chip *chip = mtd->priv; struct lpc32xx_nand_host *host = chip->priv; int i, status = 0; unsigned long timeout; int res; enum dma_transfer_direction dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; uint8_t *dma_buf; bool dma_mapped; if ((void *)buf <= high_memory) { dma_buf = buf; dma_mapped = true; } else { dma_buf = host->data_buf; dma_mapped = false; if (!read) memcpy(host->data_buf, buf, mtd->writesize); } if (read) { writel(readl(SLC_CFG(host->io_base)) | SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCF
/*
 * rtc-tps65910.c -- TPS65910 Real Time Clock interface
 *
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 * Author: Venu Byravarasu <vbyravarasu@nvidia.com>
 *
 * Based on original TI driver rtc-twl.c
 *   Copyright (C) 2007 MontaVista Software, Inc
 *   Author: Alexandre Rusev <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/mfd/tps65910.h>

struct tps65910_rtc {
	struct rtc_device	*rtc;
	int irq;
};

/* Total number of RTC registers needed to set time*/
#define NUM_TIME_REGS	(TPS65910_YEARS - TPS65910_SECONDS + 1)

static int tps65910_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
	struct tps65910 *tps = dev_get_drvdata(dev->parent);
	u8 val = 0;

	if (enabled)
		val = TPS65910_RTC_INTERRUPTS_IT_ALARM;

	return regmap_write(tps->regmap, TPS65910_RTC_INTERRUPTS, val);
}

/*
 * Gets current tps65910 RTC time and date parameters.
 *
 * The RTC's time/alarm representation is not what gmtime(3) requires
 * Linux to use:
 *
 *  - Months are 1..12 vs Linux 0-11
 *  - Years are 0..99 vs Linux 1900..N (we assume 21st century)
 */
static int tps65910_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	unsigned char rtc_