/*****************************************************************************/ /* * moxa.c -- MOXA Intellio family multiport serial driver. * * Copyright (C) 1999-2000 Moxa Technologies (support@moxa.com). * Copyright (c) 2007 Jiri Slaby * * This code is loosely based on the Linux serial driver, written by * Linus Torvalds, Theodore T'so and others. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ /* * MOXA Intellio Series Driver * for : LINUX * date : 1999/1/7 * version : 5.1 */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "moxa.h" #define MOXA_VERSION "6.0k" #define MOXA_FW_HDRLEN 32 #define MOXAMAJOR 172 #define MAX_BOARDS 4 /* Don't change this value */ #define MAX_PORTS_PER_BOARD 32 /* Don't change this value */ #define MAX_PORTS (MAX_BOARDS * MAX_PORTS_PER_BOARD) #define MOXA_IS_320(brd) ((brd)->boardType == MOXA_BOARD_C320_ISA || \ (brd)->boardType == MOXA_BOARD_C320_PCI) /* * Define the Moxa PCI vendor and device IDs. */ #define MOXA_BUS_TYPE_ISA 0 #define MOXA_BUS_TYPE_PCI 1 enum { MOXA_BOARD_C218_PCI = 1, MOXA_BOARD_C218_ISA, MOXA_BOARD_C320_PCI, MOXA_BOARD_C320_ISA, MOXA_BOARD_CP204J, }; static char *moxa_brdname[] = { "C218 Turbo PCI series", "C218 Turbo ISA series", "C320 Turbo PCI series", "C320 Turbo ISA series", "CP-204J series", }; #ifdef CONFIG_PCI static struct pci_device_id moxa_pcibrds[] = { { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C218), .driver_data = MOXA_BOARD_C218_PCI }, { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C320), .driver_data = MOXA_BOARD_C320_PCI }, { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP204J), .driver_data = MOXA_BOARD_CP204J }, { 0 } }; MODULE_DEVICE_TABLE(pci, moxa_pcibrds); #endif /* CONFIG_PCI */ struct moxa_port; static struct moxa_board_conf { int boardType; int numPorts; int busType; unsigned int ready; struct moxa_port *ports; void __iomem *basemem; void __iomem *intNdx; void __iomem *intPend; void __iomem *intTable; } moxa_boards[MAX_BOARDS]; struct mxser_mstatus { tcflag_t cflag; int cts; int dsr; int ri; int dcd; }; struct moxaq_str { int inq; int outq; }; struct moxa_port { struct tty_port port; struct moxa_board_conf *board; void __iomem *tableAddr; int type; int cflag; unsigned long statusflags; u8 DCDState; /* Protected by the port lock */ u8 lineCtrl; u8 lowChkFlag; }; struct mon_str { int tick; int rxcnt[MAX_PORTS]; int txcnt[MAX_PORTS]; }; /* statusflags */ #define TXSTOPPED 1 #define LOWWAIT 2 #define EMPTYWAIT 3 #define SERIAL_DO_RESTART #define WAKEUP_CHARS 256 static int ttymajor = MOXAMAJOR; static struct mon_str moxaLog; static unsigned int moxaFuncTout = HZ / 2; static unsigned int moxaLowWaterChk; static DEFINE_MUTEX(moxa_openlock); static DEFINE_SPINLOCK(moxa_lock); static unsigned long baseaddr[MAX_BOARDS]; static unsigned int type[MAX_BOARDS]; static unsigned int numports[MAX_BOARDS]; static struct tty_port moxa_service_port; MODULE_AUTHOR("William Chen"); MODULE_DESCRIPTION("MOXA Intellio Family Multiport Board Device Driver"); MODULE_LICENSE("GPL"); MODULE_FIRMWARE("c218tunx.cod"); MODULE_FIRMWARE("cp204unx.cod"); MODULE_FIRMWARE("c320tunx.cod"); module_param_array(type, uint, NULL, 0); MODULE_PARM_DESC(type, "card type: C218=2, C320=4"); module_param_array(baseaddr, ulong, NULL, 0); MODULE_PARM_DESC(baseaddr, "base address"); module_param_array(numports, uint, NULL, 0); MODULE_PARM_DESC(numports, "numports (ignored for C218)"); module_param(ttymajor, int, 0); /* * static functions: */ static int moxa_open(struct tty_struct *, struct file *); static void moxa_close(struct tty_struct *, struct file *); static int moxa_write(struct tty_struct *, const unsigned char *, int); static int moxa_write_room(struct tty_struct *); static void moxa_flush_buffer(struct tty_struct *); static int moxa_chars_in_buffer(struct tty_struct *); static void moxa_set_termios(struct tty_struct *, struct ktermios *); static void moxa_stop(struct tty_struct *); static void moxa_start(struct tty_struct *); static void moxa_hangup(struct tty_struct *); static int moxa_tiocmget(struct tty_struct *tty); static int moxa_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear); static void moxa_poll(unsigned long); static void moxa_set_tty_param(struct tty_struct *, struct ktermios *); static void moxa_shutdown(struct tty_port *); static int moxa_carrier_raised(struct tty_port *); static void moxa_dtr_rts(struct tty_port *, int); /* * moxa board interface functions: */ static void MoxaPortEnable(struct moxa_port *); static void MoxaPortDisable(struct moxa_port *); static int MoxaPortSetTermio(struct moxa_port *, struct ktermios *, speed_t); static int MoxaPortGetLineOut(struct moxa_port *, int *, int *); static void MoxaPortLineCtrl(struct moxa_port *, int, int); static void MoxaPortFlowCtrl(struct moxa_port *, int, int, int, int, int); static int MoxaPortLineStatus(struct moxa_port *); static void MoxaPortFlushData(struct moxa_port *, int); static int MoxaPortWriteData(struct tty_struct *, const unsigned char *, int); static int MoxaPortReadData(struct moxa_port *); static int MoxaPortTxQueue(struct moxa_port *); static int MoxaPortRxQueue(struct moxa_port *); static int MoxaPortTxFree(struct moxa_port *); static void MoxaPortTxDisable(struct moxa_port *); static void MoxaPortTxEnable(struct moxa_port *); static int moxa_get_serial_info(struct moxa_port *, struct serial_struct __user *); static int moxa_set_serial_info(struct moxa_port *, struct serial_struct __user *); static void MoxaSetFifo(struct moxa_port *port, int enable); /* * I/O functions */ static DEFINE_SPINLOCK(moxafunc_lock); static void moxa_wait_finish(void __iomem *ofsAddr) { unsigned long end = jiffies + moxaFuncTout; while (readw(ofsAddr + FuncCode) != 0) if (time_after(jiffies, end)) return; if (readw(ofsAddr + FuncCode) != 0) printk_ratelimited(KERN_WARNING "moxa function expired\n"); } static void moxafunc(void __iomem *ofsAddr, u16 cmd, u16 arg) { unsigned long flags; spin_lock_irqsave(&moxafunc_lock, flags); writew(arg, ofsAddr + FuncArg); writew(cmd, ofsAddr + FuncCode); moxa_wait_finish(ofsAddr); spin_unlock_irqrestore(&moxafunc_lock, flags); } static int moxafuncret(void __iomem *ofsAddr, u16 cmd, u16 arg) { unsigned long flags; u16 ret; spin_lock_irqsave(&moxafunc_lock, flags); writew(arg, ofsAddr + FuncArg); writew(cmd, ofsAddr + FuncCode); moxa_wait_finish(ofsAddr); ret = readw(ofsAddr + FuncArg); spin_unlock_irqrestore(&moxafunc_lock, flags); return ret; } static void moxa_low_water_check(void __iomem *ofsAddr) { u16 rptr, wptr, mask, len; if (readb(ofsAddr + FlagStat) & Xoff_state) { rptr = readw(ofsAddr + RXrptr); wptr = readw(ofsAddr + RXwptr); mask = readw(ofsAddr + RX_mask); len = (wptr - rptr) & mask; if (len <= Low_water) moxafunc(ofsAddr, FC_SendXon, 0); } } /* * TTY operations */ static int moxa_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg) { struct moxa_port *ch = tty->driver_data; void __user *argp = (void __user *)arg; int status, ret = 0; if (tty->index == MAX_PORTS) { if (cmd != MOXA_GETDATACOUNT && cmd != MOXA_GET_IOQUEUE && cmd != MOXA_GETMSTATUS) return -EINVAL; } else if (!ch) return -ENODEV; switch (cmd) { case MOXA_GETDATACOUNT: moxaLog.tick = jiffies; if (copy_to_user(argp, &moxaLog, sizeof(moxaLog))) ret = -EFAULT; break; case MOXA_FLUSH_QUEUE: MoxaPortFlushData(ch, arg); break; case MOXA_GET_IOQUEUE: { struct moxaq_str __user *argm = argp; struct moxaq_str tmp; struct moxa_port *p; unsigned int i, j; for (i = 0; i < MAX_BOARDS; i++) { p = moxa_boards[i].ports; for (j = 0; j < MAX_PORTS_PER_BOARD; j++, p++, argm++) { memset(&tmp, 0, sizeof(tmp)); spin_lock_bh(&moxa_lock); if (moxa_boards[i].ready) { tmp.inq = MoxaPortRxQueue(p); tmp.outq = MoxaPortTxQueue(p); } spin_unlock_bh(&moxa_lock); if (copy_to_user(argm, &tmp, sizeof(tmp))) return -EFAULT; } } break; } case MOXA_GET_OQUEUE: status = MoxaPortTxQueue(ch); ret = put_user(status, (unsigned long __user *)argp); break; case MOXA_GET_IQUEUE: status = MoxaPortRxQueue(ch); ret = put_user(status, (unsigned long __user *)argp); break; case MOXA_GETMSTATUS: { struct mxser_mstatus __user *argm = argp; struct mxser_mstatus tmp; struct moxa_port *p; unsigned int i, j; for (i = 0; i < MAX_BOARDS; i++) { p = moxa_boards[i].ports; for (j = 0; j < MAX_PORTS_PER_BOARD; j++, p++, argm++) { struct tty_struct *ttyp; memset(&tmp, 0, sizeof(tmp)); spin_lock_bh(&moxa_lock); if (!moxa_boards[i].ready) { spin_unlock_bh(&moxa_lock); goto copy; } status = MoxaPortLineStatus(p); spin_unlock_bh(&moxa_lock); if (status & 1) tmp.cts = 1; if (status & 2) tmp.dsr = 1; if (status & 4) tmp.dcd = 1; ttyp = tty_port_tty_get(&p->port); if (!ttyp) tmp.cflag = p->cflag; else tmp.cflag = ttyp->termios.c_cflag; tty_kref_put(ttyp); copy: if (copy_to_user(argm, &tmp, sizeof(tmp))) return -EFAULT; } } break; } case TIOCGSERIAL: mutex_lock(&ch->port.mutex); ret = moxa_get_serial_info(ch, argp); mutex_unlock(&ch->port.mutex); break; case TIOCSSERIAL: mutex_lock(&ch->port.mutex); ret = moxa_set_serial_info(ch, argp); mutex_unlock(&ch->port.mutex); break; default: ret = -ENOIOCTLCMD; } return ret; } static int moxa_break_ctl(struct tty_struct *tty, int state) { struct moxa_port *port = tty->driver_data; moxafunc(port->tableAddr, state ? FC_SendBreak : FC_StopBreak, Magic_code); return 0; } static const struct tty_operations moxa_ops = { .open = moxa_open, .close = moxa_close, .write = moxa_write, .write_room = moxa_write_room, .flush_buffer = moxa_flush_buffer, .chars_in_buffer = moxa_chars_in_buffer, .ioctl = moxa_ioctl, .set_termios = moxa_set_termios, .stop = moxa_stop, .start = moxa_start, .hangup = moxa_hangup, .break_ctl = moxa_break_ctl, .tiocmget = moxa_tiocmget, .tiocmset = moxa_tiocmset, }; static const struct tty_port_operations moxa_port_ops = { .carrier_raised = moxa_carrier_raised, .dtr_rts = moxa_dtr_rts, .shutdown = moxa_shutdown, }; static struct tty_driver *moxaDriver; static DEFINE_TIMER(moxaTimer, moxa_poll, 0, 0); /* * HW init */ static int moxa_check_fw_model(struct moxa_board_conf *brd, u8 model) { switch (brd->boardType) { case MOXA_BOARD_C218_ISA: case MOXA_BOARD_C218_PCI: if (model != 1) goto err; break; case MOXA_BOARD_CP204J: if (model != 3) goto err; break; default: if (model != 2) goto err; break; } return 0; err: return -EINVAL; } static int moxa_check_fw(const void *ptr) { const __le16 *lptr = ptr; if (*lptr != cpu_to_le16(0x7980)) return -EINVAL; return 0; } static int moxa_load_bios(struct moxa_board_conf *brd, const u8 *buf, size_t len) { void __iomem *baseAddr = brd->basemem; u16 tmp; writeb(HW_reset, baseAddr + Control_reg); /* reset */ msleep(10); memset_io(baseAddr, 0, 4096); memcpy_toio(baseAddr, buf, len); /* download BIOS */ writeb(0, baseAddr + Control_reg); /* restart */ msleep(2000); switch (brd->boardType) { case MOXA_BOARD_C218_ISA: case MOXA_BOARD_C218_PCI: tmp = readw(baseAddr + C218_key); if (tmp != C218_KeyCode) goto err; break; case MOXA_BOARD_CP204J: tmp = readw(baseAddr + C218_key); if (tmp != CP204J_KeyCode) goto err; break; default: tmp = readw(baseAddr + C320_key); if (tmp != C320_KeyCode) goto err; tmp = readw(baseAddr + C320_status); if (tmp != STS_init) { printk(KERN_ERR "MOXA: bios upload failed -- CPU/Basic " "module not found\n"); return -EIO; } break; } return 0; err: printk(KERN_ERR "MOXA: bios upload failed -- board not found\n"); return -EIO; } static int moxa_load_320b(struct moxa_board_conf *brd, const u8 *ptr, size_t len) { void __iomem *baseAddr = brd->basemem; if (len < 7168) { printk(KERN_ERR "MOXA: invalid 320 bios -- too short\n"); return -EINVAL; } writew(len - 7168 - 2, baseAddr + C320bapi_len); writeb(1, baseAddr + Control_reg); /* Select Page 1 */ memcpy_toio(baseAddr + DynPage_addr, ptr, 7168); writeb(2, baseAddr + Control_reg); /* Select Page 2 */ memcpy_toio(baseAddr + DynPage_addr, ptr + 7168, len - 7168); return 0; } static int moxa_real_load_code(struct moxa_board_conf *brd, const void *ptr, size_t len) { void __iomem *baseAddr = brd->basemem; const __le16 *uptr = ptr; size_t wlen, len2, j; unsigned long key, loadbuf, loadlen, checksum, checksum_ok; unsigned int i, retry; u16 usum, keycode; keycode = (brd->boardType == MOXA_BOARD_CP204J) ? CP204J_KeyCode : C218_KeyCode; switch (brd->boardType) { case MOXA_BOARD_CP204J: case MOXA_BOARD_C218_ISA: case MOXA_BOARD_C218_PCI: key = C218_key; loadbuf = C218_LoadBuf; loadlen = C218DLoad_len; checksum = C218check_sum; checksum_ok = C218chksum_ok; break; default: key = C320_key; keycode = C320_KeyCode; loadbuf = C320_LoadBuf; loadlen = C320DLoad_len; checksum = C320check_sum; checksum_ok = C320chksum_ok; break; } usum = 0; wlen = len >> 1; for (i = 0; i < wlen; i++) usum += le16_to_cpu(uptr[i]); retry = 0; do { wlen = len >> 1; j = 0; while (wlen) { len2 = (wlen > 2048) ? 2048 : wlen; wlen -= len2; memcpy_toio(baseAddr + loadbuf, ptr + j, len2 << 1); j += len2 << 1; writew(len2, baseAddr + loadlen); writew(0, baseAddr + key); for (i = 0; i < 100; i++) { if (readw(baseAddr + key) == keycode) break; msleep(10); } if (readw(baseAddr + key) != keycode) return -EIO; } writew(0, baseAddr + loadlen); writew(usum, baseAddr + checksum); writew(0, baseAddr + key); for (i = 0; i < 100; i++) { if (readw(baseAddr + key) == keycode) break; msleep(10); } retry++; } while ((readb(baseAddr + checksum_ok) != 1) && (retry < 3)); if (readb(baseAddr + checksum_ok) != 1) return -EIO; writew(0, baseAddr + key); for (i = 0; i < 600; i++) { if (readw(baseAddr + Magic_no) == Magic_code) break; msleep(10); } if (readw(baseAddr + Magic_no) != Magic_code) return -EIO; if (MOXA_IS_320(brd)) { if (brd->busType == MOXA_BUS_TYPE_PCI) { /* ASIC board */ writew(0x3800, baseAddr + TMS320_PORT1); writew(0x3900, baseAddr + TMS320_PORT2); writew(28499, baseAddr + TMS320_CLOCK); } else { writew(0x3200, baseAddr + TMS320_PORT1); writew(0x3400, baseAddr + TMS320_PORT2); writew(19999, baseAddr + TMS320_CLOCK); } } writew(1, baseAddr + Disable_IRQ); writew(0, baseAddr + Magic_no); for (i = 0; i < 500; i++) { if (readw(baseAddr + Magic_no) == Magic_code) break; msleep(10); } if (readw(baseAddr + Magic_no) != Magic_code) return -EIO; if (MOXA_IS_320(brd)) { j = readw(baseAddr + Module_cnt); if (j <= 0) return -EIO; brd->numPorts = j * 8; writew(j, baseAddr + Module_no); writew(0, baseAddr + Magic_no); for (i = 0; i < 600; i++) { if (readw(baseAddr + Magic_no) == Magic_code) break; msleep(10); } if (readw(baseAddr + Magic_no) != Magic_code) return -EIO; } brd->intNdx = baseAddr + IRQindex; brd->intPend = baseAddr + IRQpending; brd->intTable = baseAddr + IRQtable; return 0; } static int moxa_load_code(struct moxa_board_conf *brd, const void *ptr, size_t len) { void __iomem *ofsAddr, *baseAddr = brd->basemem; struct moxa_port *port; int retval, i; if (len % 2) { printk(KERN_ERR "MOXA: bios length is not even\n"); return -EINVAL; } retval = moxa_real_load_code(brd, ptr, len); /* may change numPorts */ if (retval) return retval; switch (brd->boardType) { case MOXA_BOARD_C218_ISA: case MOXA_BOARD_C218_PCI: case MOXA_BOARD_CP204J: port = brd->ports; for (i = 0; i < brd->numPorts; i++, port++) { port->board = brd; port->DCDState = 0; port->tableAddr = baseAddr + Extern_table + Extern_size * i; ofsAddr = port->tableAddr; writew(C218rx_mask, ofsAddr + RX_mask); writew(C218tx_mask, ofsAddr + TX_mask); writew(C218rx_spage + i * C218buf_pageno, ofsAddr + Page_rxb); writew(readw(ofsAddr + Page_rxb) + C218rx_pageno, ofsAddr + EndPage_rxb); writew(C218tx_spage + i * C218buf_pageno, ofsAddr + Page_txb); writew(readw(ofsAddr + Page_txb) + C218tx_pageno, ofsAddr + EndPage_txb); } break; default: port = brd->ports; for (i = 0; i < brd->numPorts; i++, port++) { port->board = brd; port->DCDState = 0; port->tableAddr = baseAddr + Extern_table + Extern_size * i; ofsAddr = port->tableAddr; switch (brd->numPorts) { case 8: writew(C320p8rx_mask, ofsAddr + RX_mask); writew(C320p8tx_mask, ofsAddr + TX_mask); writew(C320p8rx_spage + i * C320p8buf_pgno, ofsAddr + Page_rxb); writew(readw(ofsAddr + Page_rxb) + C320p8rx_pgno, ofsAddr + EndPage_rxb); writew(C320p8tx_spage + i * C320p8buf_pgno, ofsAddr + Page_txb); writew(readw(ofsAddr + Page_txb) + C320p8tx_pgno, ofsAddr + EndPage_txb); break; case 16: writew(C320p16rx_mask, ofsAddr + RX_mask); writew(C320p16tx_mask, ofsAddr + TX_mask); writew(C320p16rx_spage + i * C320p16buf_pgno, ofsAddr + Page_rxb); writew(readw(ofsAddr + Page_rxb) + C320p16rx_pgno, ofsAddr + EndPage_rxb); writew(C320p16tx_spage + i * C320p16buf_pgno, ofsAddr + Page_txb); writew(readw(ofsAddr + Page_txb) + C320p16tx_pgno, ofsAddr + EndPage_txb); break; case 24: writew(C320p24rx_mask, ofsAddr + RX_mask); writew(C320p24tx_mask, ofsAddr + TX_mask); writew(C320p24rx_spage + i * C320p24buf_pgno, ofsAddr + Page_rxb); writew(readw(ofsAddr + Page_rxb) + C320p24rx_pgno, ofsAddr + EndPage_rxb); writew(C320p24tx_spage + i * C320p24buf_pgno, ofsAddr + Page_txb); writew(readw(ofsAddr + Page_txb), ofsAddr + EndPage_txb); break; case 32: writew(C320p32rx_mask, ofsAddr + RX_mask); writew(C320p32tx_mask, ofsAddr + TX_mask); writew(C320p32tx_ofs, ofsAddr + Ofs_txb); writew(C320p32rx_spage + i * C320p32buf_pgno, ofsAddr + Page_rxb); writew(readb(ofsAddr + Page_rxb), ofsAddr + EndPage_rxb); writew(C320p32tx_spage + i * C320p32buf_pgno, ofsAddr + Page_txb); writew(readw(ofsAddr + Page_txb), ofsAddr + EndPage_txb); break; } } break; } return 0; } static int moxa_load_fw(struct moxa_board_conf *brd, const struct firmware *fw) { const void *ptr = fw->data; char rsn[64]; u16 lens[5]; size_t len; unsigned int a, lenp, lencnt; int ret = -EINVAL; struct { __le32 magic; /* 0x34303430 */ u8 reserved1[2]; u8 type; /* UNIX = 3 */ u8 model; /* C218T=1, C320T=2, CP204=3 */ u8 reserved2[8]; __le16 len[5]; } const *hdr = ptr; BUILD_BUG_ON(ARRAY_SIZE(hdr->len) != ARRAY_SIZE(lens)); if (fw->size < MOXA_FW_HDRLEN) { strcpy(rsn, "too short (even header won't fit)"); goto err; } if (hdr->magic != cpu_to_le32(0x30343034)) { sprintf(rsn, "bad magic: %.8x", le32_to_cpu(hdr->magic)); goto err; } if (hdr->type != 3) { sprintf(rsn, "not for linux, type is %u", hdr->type); goto err; } if (moxa_check_fw_model(brd, hdr->model)) { sprintf(rsn, "not for this card, model is %u", hdr->model); goto err; } len = MOXA_FW_HDRLEN; lencnt = hdr->model == 2 ? 5 : 3; for (a = 0; a < ARRAY_SIZE(lens); a++) { lens[a] = le16_to_cpu(hdr->len[a]); if (lens[a] && len + lens[a] <= fw->size && moxa_check_fw(&fw->data[len])) printk(KERN_WARNING "MOXA firmware: unexpected input " "at offset %u, but going on\n", (u32)len); if (!lens[a] && a < lencnt) { sprintf(rsn, "too few entries in fw file"); goto err; } len += lens[a]; } if (len != fw->size) { sprintf(rsn, "bad length: %u (should be %u)", (u32)fw->size, (u32)len); goto err; } ptr += MOXA_FW_HDRLEN; lenp = 0; /* bios */ strcpy(rsn, "read above"); 
/*
 * Designware application register space functions for Keystone PCI controller
 *
 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
 *		http://www.ti.com
 *
 * Author: Murali Karicheri <m-karicheri2@ti.com>
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>

#include "pcie-designware.h"
#include "pci-keystone.h"

/* Application register defines */
#define LTSSM_EN_VAL		        1
#define LTSSM_STATE_MASK		0x1f
#define LTSSM_STATE_L0			0x11
#define DBI_CS2_EN_VAL			0x20
#define OB_XLAT_EN_VAL		        2

/* Application registers */
#define CMD_STATUS			0x004
#define CFG_SETUP			0x008
#define OB_SIZE				0x030
#define CFG_PCIM_WIN_SZ_IDX		3
#define CFG_PCIM_WIN_CNT		32
#define SPACE0_REMOTE_CFG_OFFSET	0x1000
#define OB_OFFSET_INDEX(n)		(0x200 + (8 * n))
#define OB_OFFSET_HI(n)			(0x204 + (8 * n))

/* IRQ register defines */
#define IRQ_EOI				0x050
#define IRQ_STATUS			0x184
#define IRQ_ENABLE_SET			0x188
#define IRQ_ENABLE_CLR			0x18c

#define MSI_IRQ				0x054
#define MSI0_IRQ_STATUS			0x104
#define MSI0_IRQ_ENABLE_SET		0x108
#define MSI0_IRQ_ENABLE_CLR		0x10c
#define IRQ_STATUS			0x184
#define MSI_IRQ_OFFSET			4

/* Config space registers */
#define DEBUG0				0x728

#define to_keystone_pcie(x)	container_of(x, struct keystone_pcie, pp)

static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
{
	return sys->private_data;
}

static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
					     u32 *bit_pos)
{
	*reg_offset = offset % 8;
	*bit_pos = offset >> 3;
}

u32 ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
{
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

	return ks_pcie->app.start + MSI_IRQ;
}

void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
{
	struct pcie_port *pp = &ks_pcie->pp;
	u32 pending, vector;
	int src, virq;

	pending = readl(ks_pcie->va_app_base + MSI0_IRQ_STATUS + (offset << 4));

	/*
	 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
	 * shows 1, 9, 17, 25 and so forth
	 */
	for (src = 0; src < 4; src++) {
		if (BIT(src) & pending) {
			vector = offset + (src << 3);
			virq = irq_linear_revmap(pp->irq_domain, vector);
			dev_dbg(pp->dev, "irq: bit %d, vector %d, virq %d\n",
				src, vector, virq);
			generic_handle_irq(virq);
		}
	}
}

static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
{
	u32 offset, reg_offset, bit_pos;
	struct keystone_pcie *ks_pcie;
	unsigned int irq = d->irq;
	struct msi_desc *msi;
	struct pcie_port *pp;

	msi = irq_get_msi_desc(irq);
	pp = sys_to_pcie(msi->dev->bus->sysdata);
	ks_pcie = to_keystone_pcie(pp);
	offset = irq - irq_linear_revmap(pp->irq_domain, 0);
	update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);

	writel(BIT(bit_pos),
	       ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4));
	writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI);
}

void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
{
	u32 reg_offset, bit_pos;
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
	writel(BIT(bit_pos),
	       ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4));
}

void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
{
	u32 reg_offset, bit_pos;
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);

	update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
	writel(BIT(bit_pos),
	       ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4));
}

static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
{
	struct keystone_pcie *ks_pcie;
	unsigned int irq = d->irq;
	struct msi_desc *msi;
	struct pcie_port *pp;
	u32 offset;

	msi = irq_get_msi_desc(irq);
	pp = sys_to_pcie(msi->dev->bus->sysdata);
	ks_pcie = to_keystone_pcie(pp);
	offset = irq - irq_linear_revmap(pp->irq_domain, 0);

	/* Mask the end point if PVM implemented */
	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		if (msi->msi_attrib.maskbit)
			pci_msi_mask_irq(d);
	}

	ks_dw_pcie_msi_clear_irq(pp, offset);
}

static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
{
	struct keystone_pcie *ks_pcie;
	unsigned int irq = d->irq;
	struct msi_desc *msi;
	struct pcie_port *pp;
	u32 offset;

	msi = irq_get_msi_desc(irq);
	pp = sys_to_pcie(msi->dev->bus->sysdata);
	ks_pcie = to_keystone_pcie(pp);
	offset = irq - irq_linear_revmap(pp->irq_domain, 0);

	/* Mask the end point if PVM implemented */
	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		if (msi->msi_attrib.maskbit)
			pci_msi_unmask_irq(d);
	}

	ks_dw_pcie_msi_set_irq(pp, offset);
}

static struct irq_chip ks_dw_pcie_msi_irq_chip = {
	.name = "Keystone-PCIe-MSI-IRQ",
	.irq_ack = ks_dw_pcie_msi_irq_ack,
	.irq_mask = ks_dw_pcie_msi_irq_mask,
	.irq_unmask = ks_dw_pcie_msi_irq_unmask,
};

static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
			      irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
				 handle_level_irq);
	irq_set_chip_data(irq, domain->host_data);
	set_irq_flags(irq, IRQF_VALID);

	return 0;
}

static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
	.map = ks_dw_pcie_msi_map,
};

int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip