/* * omap_wdt.c * * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog * * Author: MontaVista Software, Inc. * or * * 2003 (c) MontaVista Software, Inc. This file is licensed under the * terms of the GNU General Public License version 2. This program is * licensed "as is" without any warranty of any kind, whether express * or implied. * * History: * * 20030527: George G. Davis * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c * (c) Copyright 2000 Oleg Drokin * Based on SoftDog driver by Alan Cox * * Copyright (c) 2004 Texas Instruments. * 1. Modified to support OMAP1610 32-KHz watchdog timer * 2. Ported to 2.6 kernel * * Copyright (c) 2005 David Brownell * Use the driver model and standard identifiers; handle bigger timeouts. */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include #include #include #include #include #include #include #include #include #include #include #include #include #include "omap_wdt.h" static bool nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); static unsigned timer_margin; module_param(timer_margin, uint, 0); MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); struct omap_wdt_dev { void __iomem *base; /* physical */ struct device *dev; bool omap_wdt_users; int wdt_trgr_pattern; struct mutex lock; /* to avoid races with PM */ }; static void omap_wdt_reload(struct omap_wdt_dev *wdev) { void __iomem *base = wdev->base; /* wait for posted write to complete */ while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) cpu_relax(); wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern; writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); /* wait for posted write to complete */ while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) cpu_relax(); /* reloaded WCRR from WLDR */ } static void omap_wdt_enable(struct omap_wdt_dev *wdev) { void __iomem *base = wdev->base; /* Sequence to enable the watchdog */ writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR); while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) cpu_relax(); writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR); while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) cpu_relax(); } static void omap_wdt_disable(struct omap_wdt_dev *wdev) { void __iomem *base = wdev->base; /* sequence required to disable watchdog */ writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) cpu_relax(); writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) cpu_relax(); } static void omap_wdt_set_timer(struct omap_wdt_dev *wdev, unsigned int timeout) { u32 pre_margin = GET_WLDR_VAL(timeout); void __iomem *base = wdev->base; /* just count up at 32 KHz */ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) cpu_relax(); writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR); while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) cpu_relax(); } static int omap_wdt_start(struct watchdog_device *wdog) { struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog); void __iomem *base = wdev->base; mutex_lock(&wdev->lock); wdev->omap_wdt_users = true; pm_runtime_get_sync(wdev->dev); /* * Make sure the watchdog is disabled. This is unfortunately required * because writing to various registers with the watchdog running has no * effect. */ omap_wdt_disable(wdev); /* initialize prescaler */ while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) cpu_relax(); writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); while (readl_relaxed(base + OMAP_W
#ifndef _ASM_X86_MISC_H
#define _ASM_X86_MISC_H

int num_digits(int val);

#endif /* _ASM_X86_MISC_H */