/*
* TriCore emulation for qemu: main translation routines.
*
* Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see .
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "disas/disas.h"
#include "tcg-op.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "tricore-opcodes.h"
#include "exec/log.h"
/*
* TCG registers
*/
static TCGv cpu_PC;
static TCGv cpu_PCXI;
static TCGv cpu_PSW;
static TCGv cpu_ICR;
/* GPR registers */
static TCGv cpu_gpr_a[16];
static TCGv cpu_gpr_d[16];
/* PSW Flag cache */
static TCGv cpu_PSW_C;
static TCGv cpu_PSW_V;
static TCGv cpu_PSW_SV;
static TCGv cpu_PSW_AV;
static TCGv cpu_PSW_SAV;
/* CPU env */
static TCGv_env cpu_env;
#include "exec/gen-icount.h"
static const char *regnames_a[] = {
"a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
"a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
"a12" , "a13" , "a14" , "a15",
};
static const char *regnames_d[] = {
"d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
"d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
"d12" , "d13" , "d14" , "d15",
};
typedef struct DisasContext {
struct TranslationBlock *tb;
target_ulong pc, saved_pc, next_pc;
uint32_t opcode;
int singlestep_enabled;
/* Routine used to access memory */
int mem_idx;
uint32_t hflags, saved_hflags;
int bstate;
} DisasContext;
enum {
BS_NONE = 0,
BS_STOP = 1,
BS_BRANCH = 2,
BS_EXCP = 3,
};
enum {
MODE_LL = 0,
MODE_LU = 1,
MODE_UL = 2,
MODE_UU = 3,
};
void tricore_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;
uint32_t psw;
int i;
psw = psw_read(env);
cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
for (i = 0; i < 16; ++i) {
if ((i & 3) == 0) {
cpu_fprintf(f, "\nGPR A%02d:", i);
}
cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
}
for (i = 0; i < 16; ++i) {
if ((i & 3) == 0) {
cpu_fprintf(f, "\nGPR D%02d:", i);
}
cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
}
cpu_fprintf(f, "\n");
}
/*
* Functions to generate micro-ops
*/
/* Makros for generating helpers */
#define gen_helper_1arg(name, arg) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg); \
gen_helper_##name(cpu_env, helper_tmp); \
tcg_temp_free_i32(helper_tmp); \
} while (0)
#define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
tcg_gen_sari_tl(arg00, arg0, 16); \
tcg_gen_ext16s_tl(arg01, arg0); \
tcg_gen_ext16s_tl(arg11, arg1); \
gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
tcg_temp_free(arg00); \
tcg_temp_free(arg01); \
tcg_temp_free(arg11); \
} while (0)
#define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg10 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
tcg_gen_sari_tl(arg00, arg0, 16); \
tcg_gen_ext16s_tl(arg01, arg0); \
tcg_gen_sari_tl(arg11, arg1, 16); \
tcg_gen_ext16s_tl(arg10, arg1); \
gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
tcg_temp_free(arg00); \
tcg_temp_free(arg01); \
tcg_temp_free(arg10); \
tcg_temp_free(arg11); \
} while (0)
#define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg10 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
tcg_gen_sari_tl(arg00, arg0, 16); \
tcg_gen_ext16s_tl(arg01, arg0); \
tcg_gen_sari_tl(arg10, arg1, 16); \
tcg_gen_ext16s_tl(arg11, arg1); \
gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
tcg_temp_free(arg00); \
tcg_temp_free(arg01); \
tcg_temp_free(arg10); \
tcg_temp_free(arg11); \
} while (0)
#define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
TCGv arg00 = tcg_temp_new(); \
TCGv arg01 = tcg_temp_new(); \
TCGv arg11 = tcg_temp_new(); \
tcg_gen_sari_tl(arg01, arg0, 16); \
tcg_gen_ext16s_tl(arg00, arg0); \
tcg_gen_sari_tl(arg11, arg1, 16); \
gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
tcg_temp_free(arg00); \
tcg_temp_free(arg01); \
tcg_temp_free(arg11); \
} while (0)
#define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
TCGv_i64 ret = tcg_temp_new_i64(); \
TCGv_i64 arg1 = tcg_temp_new_i64(); \
\
tcg_gen_concat_i32_i64(arg1, al1, ah1); \
gen_helper_##name(ret, arg1, arg2); \
tcg_gen_extr_i64_i32(rl, rh, ret); \
\
tcg_temp_free_i64(ret); \
tcg_temp_free_i64(arg1); \
} while (0)
#define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
TCGv_i64 ret = tcg_temp_new_i64(); \
\
gen_helper_##name(ret, cpu_env, arg1, arg2); \
tcg_gen_extr_i64_i32(rl, rh, ret); \
\
tcg_temp_free_i64(ret); \
} while (0)
#define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
#define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
((offset & 0x0fffff) << 1))
/* For two 32-bit registers used a 64-bit register, the first
registernumber needs to be even. Otherwise we trap. */
static inline void generate_trap(DisasContext *ctx, int class, int tin);
#define CHECK_REG_PAIR(reg) do { \
if (reg & 0x1) { \
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
} \
} while (0)
/* Functions for load/save to/from memory */
static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
int16_t con, TCGMemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, con);
tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
tcg_temp_free(temp);
}
static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
int16_t con, TCGMemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, con);
tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
tcg_temp_free(temp);
}
static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
{
TCGv_i64 temp = tcg_temp_new_i64();
tcg_gen_concat_i32_i64(temp, rl, rh);
tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
tcg_temp_free_i64(temp);
}
static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, base, con);
gen_st_2regs_64(rh, rl, temp, ctx);
tcg_temp_free(temp);
}
static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
{
TCGv_i64 temp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
/* write back to two 32 bit regs */
tcg_gen_extr_i64_i32(rl, rh, temp);
tcg_temp_free_i64(temp);
}
static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
DisasContext *ctx)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, base, con);
gen_ld_2regs_64(rh, rl, temp, ctx);
tcg_temp_free(temp);
}
static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
TCGMemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, off);
tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
tcg_gen_mov_tl(r2, temp);
tcg_temp_free(temp);
}
static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
TCGMemOp mop)
{
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, r2, off);
tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
tcg_gen_mov_tl(r2, temp);
tcg_temp_free(temp);
}
/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63
/*
* Renesas Technology Corp. SH7786 Urquell Support.
*
* Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
* Copyright (C) 2009, 2010 Paul Mundt
*
* Based on board-sh7785lcr.c
* Copyright (C) 2008 Yoshihiro Shimoda
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/smc91x.h>
#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/sh_intc.h>
#include <mach/urquell.h>
#include <cpu/sh7786.h>
#include <asm/heartbeat.h>
#include <asm/sizes.h>
#include <asm/smp-ops.h>
/*
* bit 1234 5678
*----------------------------
* SW1 0101 0010 -> Pck 33MHz version
* (1101 0010) Pck 66MHz version
* SW2 0x1x xxxx -> little endian
* 29bit mode
* SW47 0001 1000 -> CS0 : on-board flash
* CS1 : SRAM, registers, LAN, PCMCIA
* 38400 bps for SCIF1
*
* Address
* 0x00000000 - 0x04000000 (CS0) Nor Flash
* 0x04000000 - 0x04200000 (CS1) SRAM
* 0x05000000 - 0x05800000 (CS1) on board register
* 0x05800000 - 0x06000000 (CS1) LAN91C111
* 0x06000000 - 0x06400000 (CS1) PCMCIA
* 0x08000000 - 0x10000000 (CS2-CS3) DDR3
* 0x10000000 - 0x14000000 (CS4) PCIe
* 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
* 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
* 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash
* 0x1C000000 - (CS7) SH7786 Control register
*/
/* HeartBeat */
static struct resource heartbeat_resource = {
.start = BOARDREG(SLEDR),
.end = BOARDREG(SLEDR),
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = 1,
.resource = &heartbeat_resource,
};
/* LAN91C111 */
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "SMC91C111" ,
.start = 0x05800300,
.end = 0x0580030f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x360),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
.dev = {
.platform_data = &smc91x_info,
},
};
/* Nor Flash */
static struct mtd_partition nor_flash_partitions[] = {
{
.name = "loader",
.offset = 0x00000000,
.size = SZ_512K,
.mask_flags = MTD_WRITEABLE, /* Read-only */
},
{
.name = "bootenv",
.offset = MTDPART_OFS_APPEND,
.size = SZ_512K,
.mask_flags = MTD_WRITEABLE, /* Read-only */
},
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
},
{
.name = "data",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct physmap_flash_data nor_flash_data = {
.width = 2,
.parts = nor_flash_partitions,
.nr_parts = ARRAY_SIZE(nor_flash_partitions),
};
static struct resource nor_flash_resources[] = {
[0] = {
.start = NOR_FLASH_ADDR,
.end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device nor_flash_device = {
.name = "physmap-flash",
.dev = {
.platform_data = &nor_flash_data,
},
.num_resources = ARRAY_SIZE(nor_flash_resources),
.resource = nor_flash_resources,
};
static struct platform_device *urquell_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
&nor_flash_device,
};
static int __init urquell_devices_setup(void)
{
/* USB */
gpio_request(GPIO_FN_USB_OVC0, NULL);
gpio_request(GPIO_FN_USB_PENC0, NULL);
/* enable LAN */
__raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001,
UBOARDREG(IRL2MSKR));
return platform_add_devices(urquell_devices,
ARRAY_SIZE(urquell_devices));
}
device_initcall(urquell_devices_setup);
static void urquell_power_off(void)
{
__raw_writew(0xa5a5, UBOARDREG(SRSTR));
}
static void __init urquell_init_irq(void)
{
plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
}
static int urquell_mode_pins(void)
{
return __raw_readw(UBOARDREG(MDSWMR));
}
static int urquell_clk_init(void)
{
struct clk *clk;
int ret;
/*
* Only handle the EXTAL case, anyone interfacing a crystal
* resonator will need to provide their own input clock.
*/
if (test_mode_pin(MODE_PIN9))
return -EINVAL;
clk = clk_get(NULL, "extal");
if (IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_set_rate(clk, 33333333);
clk_put(clk);
return ret;
}
/* Initialize the board */
static void __init urquell_setup(char **cmdline_p)
{
printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
pm_power_off = urquell_power_off;
register_smp_ops(&shx3_smp_ops);
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_urquell __initmv = {
.mv_name = "Urquell",
.mv_setup = urquell_setup,
.mv_init_irq = urquell_init_irq,
.mv_mode_pins = urquell_mode_pins,
.mv_clk_init = urquell_clk_init,
};