/* linux/drivers/usb/gadget/s3c-hsudc.c * * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * * S3C24XX USB 2.0 High-speed USB controller gadget driver * * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints. * Each endpoint can be configured as either in or out endpoint. Endpoints * can be configured for Bulk or Interrupt transfer mode. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define S3C_HSUDC_REG(x) (x) /* Non-Indexed Registers */ #define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */ #define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */ #define S3C_EIR_EP0 (1<<0) #define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */ #define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */ #define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */ #define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */ #define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */ #define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */ #define S3C_SSR_DTZIEN_EN (0xff8f) #define S3C_SSR_ERR (0xff80) #define S3C_SSR_VBUSON (1 << 8) #define S3C_SSR_HSP (1 << 4) #define S3C_SSR_SDE (1 << 3) #define S3C_SSR_RESUME (1 << 2) #define S3C_SSR_SUSPEND (1 << 1) #define S3C_SSR_RESET (1 << 0) #define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */ #define S3C_SCR_DTZIEN_EN (1 << 14) #define S3C_SCR_RRD_EN (1 << 5) #define S3C_SCR_SUS_EN (1 << 1) #define S3C_SCR_RST_EN (1 << 0) #define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */ #define S3C_EP0SR_EP0_LWO (1 << 6) #define S3C_EP0SR_STALL (1 << 4) #define S3C_EP0SR_TX_SUCCESS (1 << 1) #define S3C_EP0SR_RX_SUCCESS (1 << 0) #define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */ #define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4)) /* Indexed Registers */ #define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */ #define S3C_ESR_FLUSH (1 << 6) #define S3C_ESR_STALL (1 << 5) #define S3C_ESR_LWO (1 << 4) #define S3C_ESR_PSIF_ONE (1 << 2) #define S3C_ESR_PSIF_TWO (2 << 2) #define S3C_ESR_TX_SUCCESS (1 << 1) #define S3C_ESR_RX_SUCCESS (1 << 0) #define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */ #define S3C_ECR_DUEN (1 << 7) #define S3C_ECR_FLUSH (1 << 6) #define S3C_ECR_STALL (1 << 1) #define S3C_ECR_IEMS (1 << 0) #define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */ #define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */ #define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */ #define WAIT_FOR_SETUP (0) #define DATA_STATE_XMIT (1) #define DATA_STATE_RECV (2) static const char * const s3c_hsudc_supply_names[] = { "vdda", /* analog phy supply, 3.3V */ "vddi", /* digital phy supply, 1.2V */ "vddosc", /* oscillator supply, 1.8V - 3.3V */ }; /** * struct s3c_hsudc_ep - Endpoint representation used by driver. * @ep: USB gadget layer representation of device endpoint. * @name: Endpoint name (as required by ep autoconfiguration). * @dev: Reference to the device controller to which this EP belongs. * @desc: Endpoint descriptor obtained from the gadget driver. * @queue: Transfer request queue for the endpoint. * @stopped: Maintains state of endpoint, set if EP is halted. * @bEndpointAddress: EP address (including direction bit). * @fifo: Base address of EP FIFO. */ struct s3c_hsudc_ep { struct usb_ep ep; char name[20]; struct s3c_hsudc *dev; struct list_head queue; u8 stopped; u8 wedge; u8 bEndpointAddress; void __iomem *fifo; }; /** * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request. * @req: Reference to USB gadget transfer request. * @queue: Used for inserting this request to the endpoint request queue. */ struct s3c_hsudc_req { struct usb_request req; struct list_head queue; }; /** * struct s3c_hsudc - Driver's abstraction of the device controller. * @gadget: Instance of usb_gadget which is referenced by gadget driver. * @driver: Reference to currenty active gadget driver. * @dev: The device reference used by probe function. * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed). * @regs: Remapped base address of controller's register space. * irq: IRQ number used by the controller. * uclk: Reference to the controller clock. * ep0state: Current state of EP0. * ep: List of endpoints supported by the controller. */ struct s3c_hsudc { struct usb_gadget gadget; struct usb_gadget_driver *driver; struct device *dev; struct s3c24xx_hsudc_platdata *pd; struct usb_phy *transceiver; struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)]; spinlock_t lock; void __iomem *regs; int irq; struct clk *uclk; int ep0state; struct s3c_hsudc_ep ep[]; }; #define ep_maxpacket(_ep) ((_ep)->ep.maxpacket) #define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN) #define ep_index(_ep) ((_ep)->bEndpointAddress & \ USB_ENDPOINT_NUMBER_MASK) static const char driver_name[] = "s3c-udc"; static const char ep0name[] = "ep0-control"; static inline struct s3c_hsudc_req *our_req(struct usb_request *req) { return container_of(req, struct s3c_hsudc_req, req); } static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep) { return container_of(ep, struct s3c_hsudc_ep, ep); } static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget) { return container_of(gadget, struct s3c_hsudc, gadget); } static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr) { ep_addr &= USB_ENDPOINT_NUMBER_MASK; writel(ep_addr, hsudc->regs + S3C_IR); } static inline void __orr32(void __iomem *ptr, u32 val) { writel(readl(ptr) | val, ptr); } static void s3c_hsudc_init_phy(void) { u32 cfg; cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY; writel(cfg, S3C2443_PWRCFG); cfg = readl(S3C2443_URSTCON); cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); writel(cfg, S3C2443_URSTCON); mdelay(1); cfg = readl(S3C2443_URSTCON); cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); writel(cfg, S3C2443_URSTCON); cfg = readl(S3C2443_PHYC
/*
 * OMAP3 Voltage Processor (VP) data
 *
 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 * Lesly A M <x0080970@ti.com>
 * Thara Gopinath <thara@ti.com>
 *
 * Copyright (C) 2008, 2011 Nokia Corporation
 * Kalle Jokiniemi
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>
#include <linux/err.h>
#include <linux/init.h>

#include "common.h"

#include "prm-regbits-34xx.h"
#include "voltage.h"

#include "vp.h"
#include "prm2xxx_3xxx.h"

static const struct omap_vp_ops omap3_vp_ops = {
	.check_txdone = omap_prm_vp_check_txdone,
	.clear_txdone = omap_prm_vp_clear_txdone,
};

/*
 * VP data common to 34xx/36xx chips
 * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
 */
static const struct omap_vp_common omap3_vp_common = {
	.vpconfig_erroroffset_mask = OMAP3430_ERROROFFSET_MASK,
	.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
	.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK,
	.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK,
	.vpconfig_initvdd = OMAP3430_INITVDD_MASK,
	.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK,
	.vpconfig_vpenable = OMAP3430_VPENABLE_MASK,
	.vstepmin_smpswaittimemin_shift = OMAP3430_SMPSWAITTIMEMIN_SHIFT,
	.vstepmax_smpswaittimemax_shift = OMAP3430_SMPSWAITTIMEMAX_SHIFT,
	.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT,
	.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT,
	.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
	.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
	.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
	.vpvoltage_mask = OMAP3430_VPVOLTAGE_MASK,

	.ops = &omap3_vp_ops,
};

struct omap_vp_instance omap3_vp_mpu = {
	.id = OMAP3_VP_VDD_MPU_ID,
	.common = &omap3_vp_common,
	.vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
	.vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
	.vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
	.vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
	.vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
	.voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
};

struct omap_vp_instance omap3_vp_core = {
	.id = OMAP3_VP_VDD_CORE_ID,
	.common = &omap3_vp_common,
	.vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
	.vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
	.vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
	.vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
	.vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
	.voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
};

struct omap_vp_param omap3_mpu_vp_data = {
	.vddmin			= OMAP3430_VP1_VLIMITTO_VDDMIN,
	.vddmax			= OMAP3430_VP1_VLIMITTO_VDDMAX,
};

struct omap_vp_param omap3_core_vp_data = {
	.vddmin			= OMAP3430_VP2_VLIMITTO_VDDMIN,
	.vddmax			= OMAP3430_VP2_VLIMITTO_VDDMAX,
};
>ep.name == ep0name) return -EINVAL; spin_lock_irqsave(&hsudc->lock, flags); list_for_each_entry(hsreq, &hsep->queue, queue) { if (&hsreq->req == _req) break; } if (&hsreq->req != _req) { spin_unlock_irqrestore(&hsudc->lock, flags); return -EINVAL; } set_index(hsudc, hsep->bEndpointAddress); s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET); spin_unlock_irqrestore(&hsudc->lock, flags); return 0; } static struct usb_ep_ops s3c_hsudc_ep_ops = { .enable = s3c_hsudc_ep_enable, .disable = s3c_hsudc_ep_disable, .alloc_request = s3c_hsudc_alloc_request, .free_request = s3c_hsudc_free_request, .queue = s3c_hsudc_queue, .dequeue = s3c_hsudc_dequeue, .set_halt = s3c_hsudc_set_halt, .set_wedge = s3c_hsudc_set_wedge, }; /** * s3c_hsudc_initep - Initialize a endpoint to default state. * @hsudc - Reference to the device controller. * @hsep - Endpoint to be initialized. * @epnum - Address to be assigned to the endpoint. * * Initialize a endpoint with default configuration. */ static void s3c_hsudc_initep(struct s3c_hsudc *hsudc, struct s3c_hsudc_ep *hsep, int epnum) { char *dir; if ((epnum % 2) == 0) { dir = "out"; } else { dir = "in"; hsep->bEndpointAddress = USB_DIR_IN; } hsep->bEndpointAddress |= epnum; if (epnum) snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir); else snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name); INIT_LIST_HEAD(&hsep->queue); INIT_LIST_HEAD(&hsep->ep.ep_list); if (epnum) list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list); hsep->dev = hsudc; hsep->ep.name = hsep->name; usb_ep_set_maxpacket_limit(&hsep->ep, epnum ? 512 : 64); hsep->ep.ops = &s3c_hsudc_ep_ops; hsep->fifo = hsudc->regs + S3C_BR(epnum); hsep->ep.desc = NULL; hsep->stopped = 0; hsep->wedge = 0; set_index(hsudc, epnum); writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR); } /** * s3c_hsudc_setup_ep - Configure all endpoints to default state. * @hsudc: Reference to device controller. * * Configures all endpoints to default state. */ static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc) { int epnum; hsudc->ep0state = WAIT_FOR_SETUP; INIT_LIST_HEAD(&hsudc->gadget.ep_list); for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum); } /** * s3c_hsudc_reconfig - Reconfigure the device controller to default state. * @hsudc: Reference to device controller. * * Reconfigures the device controller registers to a default state. */ static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc) { writel(0xAA, hsudc->regs + S3C_EDR); writel(1, hsudc->regs + S3C_EIER); writel(0, hsudc->regs + S3C_TR); writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN | S3C_SCR_RST_EN, hsudc->regs + S3C_SCR); writel(0, hsudc->regs + S3C_EP0CR); s3c_hsudc_setup_ep(hsudc); } /** * s3c_hsudc_irq - Interrupt handler for device controller. * @irq: Not used. * @_dev: Reference to the device controller. * * Interrupt handler for the device controller. This handler handles controller * interrupts and endpoint interrupts. */ static irqreturn_t s3c_hsudc_irq(int irq, void *_dev) { struct s3c_hsudc *hsudc = _dev; struct s3c_hsudc_ep *hsep; u32 ep_intr; u32 sys_status; u32 ep_idx; spin_lock(&hsudc->lock); sys_status = readl(hsudc->regs + S3C_SSR); ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF; if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) { spin_unlock(&hsudc->lock); return IRQ_HANDLED; } if (sys_status) { if (sys_status & S3C_SSR_VBUSON) writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR); if (sys_status & S3C_SSR_ERR) writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR); if (sys_status & S3C_SSR_SDE) { writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR); hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ? USB_SPEED_HIGH : USB_SPEED_FULL; } if (sys_status & S3C_SSR_SUSPEND) { writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR); if (hsudc->gadget.speed != USB_SPEED_UNKNOWN && hsudc->driver && hsudc->driver->suspend) hsudc->driver->suspend(&hsudc->gadget); } if (sys_status & S3C_SSR_RESUME) { writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR); if (hsudc->gadget.speed != USB_SPEED_UNKNOWN && hsudc->driver && hsudc->driver->resume) hsudc->driver->resume(&hsudc->gadget); } if (sys_status & S3C_SSR_RESET) { writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR); for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) { hsep = &hsudc->ep[ep_idx]; hsep->stopped = 1; s3c_hsudc_nuke_ep(hsep, -ECONNRESET); } s3c_hsudc_reconfig(hsudc); hsudc->ep0state = WAIT_FOR_SETUP; } } if (ep_intr & S3C_EIR_EP0) { writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR); set_index(hsudc, 0); s3c_hsudc_handle_ep0_intr(hsudc); } ep_intr >>= 1; ep_idx = 1; while (ep_intr) { if (ep_intr & 1) { hsep = &hsudc->ep[ep_idx]; set_index(hsudc, ep_idx); writel(1 << ep_idx, hsudc->regs + S3C_EIR); if (ep_is_in(hsep)) s3c_hsudc_epin_intr(hsudc, ep_idx); else s3c_hsudc_epout_intr(hsudc, ep_idx); } ep_intr >>= 1; ep_idx++; } spin_unlock(&hsudc->lock); return IRQ_HANDLED; } static int s3c_hsudc_start(struct usb_gadget *gadget, struct usb_gadget_driver *driver) { struct s3c_hsudc *hsudc = to_hsudc(gadget); int ret; if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) return -EINVAL; if (!hsudc) return -ENODEV; if (hsudc->driver) return -EBUSY; hsudc->driver = driver; ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies); if (ret != 0) { dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret); goto err_supplies; } /* connect to bus through transceiver */ if (!IS_ERR_OR_NULL(hsudc->transceiver)) { ret = otg_set_peripheral(hsudc->transceiver->otg, &hsudc->gadget); if (ret) { dev_err(hsudc->dev, "%s: can't bind to transceiver\n", hsudc->gadget.name); goto err_otg; } } enable_irq(hsudc->irq); s3c_hsudc_reconfig(hsudc); pm_runtime_get_sync(hsudc->dev); s3c_hsudc_init_phy(); if (hsudc->pd->gpio_init) hsudc->pd->gpio_init(); return 0; err_otg: regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies); err_supplies: hsudc->driver = NULL; return ret; } static int s3c_hsudc_stop(struct usb_gadget *gadget) { struct s3c_hsudc *hsudc = to_hsudc(gadget); unsigned long flags; if (!hsudc) return -ENODEV; spin_lock_irqsave(&hsudc->lock, flags); hsudc->gadget.speed = USB_SPEED_UNKNOWN; s3c_hsudc_uninit_phy(); pm_runtime_put(hsudc->dev); if (hsudc->pd->gpio_uninit) hsudc->pd->gpio_uninit(); s3c_hsudc_stop_activity(hsudc); spin_unlock_irqrestore(&hsudc->lock, flags); if (!IS_ERR_OR_NULL(hsudc->transceiver)) (void) otg_set_peripheral(hsudc->transceiver->otg, NULL); disable_irq(hsudc->irq); regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies); hsudc->driver = NULL; return 0; } static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc) { return readl(hsudc->regs + S3C_FNR) & 0x3FF; } static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget) { return s3c_hsudc_read_frameno(to_hsudc(gadget)); } static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA) { struct s3c_hsudc *hsudc = to_hsudc(gadget); if (!hsudc) return -ENODEV; if (!IS_ERR_OR_NULL(hsudc->transceiver)) return usb_phy_set_power(hsudc->transceiver, mA); return -EOPNOTSUPP; } static const struct usb_gadget_ops s3c_hsudc_gadget_ops = { .get_frame = s3c_hsudc_gadget_getframe, .udc_start = s3c_hsudc_start, .udc_stop = s3c_hsudc_stop, .vbus_draw = s3c_hsudc_vbus_draw, }; static int s3c_hsudc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *res; struct s3c_hsudc *hsudc; struct s3c24xx_hsudc_platdata *pd = dev_get_platdata(&pdev->dev); int ret, i; hsudc = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsudc) + sizeof(struct s3c_hsudc_ep) * pd->epnum, GFP_KERNEL); if (!hsudc) return -ENOMEM; platform_set_drvdata(pdev, dev); hsudc->dev = dev; hsudc->pd = dev_get_platdata(&pdev->dev); hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++) hsudc->supplies[i].supply = s3c_hsudc_supply_names[i]; ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies), hsudc->supplies); if (ret != 0) { dev_err(dev, "failed to request supplies: %d\n", ret); goto err_supplies; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); hsudc->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(hsudc->regs)) { ret = PTR_ERR(hsudc->regs); goto err_res; } spin_lock_init(&hsudc->lock); hsudc->gadget.max_speed = USB_SPEED_HIGH; hsudc->gadget.ops = &s3c_hsudc_gadget_ops; hsudc->gadget.name = dev_name(dev); hsudc->gadget.ep0 = &hsudc->ep[0].ep; hsudc->gadget.is_otg = 0; hsudc->gadget.is_a_peripheral = 0; hsudc->gadget.speed = USB_SPEED_UNKNOWN; s3c_hsudc_setup_ep(hsudc); ret = platform_get_irq(pdev, 0); if (ret < 0) { dev_err(dev, "unable to obtain IRQ number\n"); goto err_res; } hsudc->irq = ret; ret = devm_request_irq(&pdev->dev, hsudc->irq, s3c_hsudc_irq, 0, driver_name, hsudc); if (ret < 0) { dev_err(dev, "irq request failed\n"); goto err_res; } hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device"); if (IS_ERR(hsudc->uclk)) { dev_err(dev, "failed to find usb-device clock source\n"); ret = PTR_ERR(hsudc->uclk); goto err_res; } clk_enable(hsudc->uclk); local_irq_disable(); disable_irq(hsudc->irq); local_irq_enable(); ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget); if (ret) goto err_add_udc; pm_runtime_enable(dev); return 0; err_add_udc: clk_disable(hsudc->uclk); err_res: if (!IS_ERR_OR_NULL(hsudc->transceiver)) usb_put_phy(hsudc->transceiver); err_supplies: return ret; } static struct platform_driver s3c_hsudc_driver = { .driver = { .name = "s3c-hsudc", }, .probe = s3c_hsudc_probe, }; module_platform_driver(s3c_hsudc_driver); MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver"); MODULE_AUTHOR("Thomas Abraham "); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:s3c-hsudc");