/*====================================================================== A PCMCIA ethernet driver for NS8390-based cards This driver supports the D-Link DE-650 and Linksys EthernetCard cards, the newer D-Link and Linksys combo cards, Accton EN2212 cards, the RPTI EP400, and the PreMax PE-200 in non-shared-memory mode, and the IBM Credit Card Adapter, the NE4100, the Thomas Conrad ethernet card, and the Kingston KNE-PCM/x in shared-memory mode. It will also handle the Socket EA card in either mode. Copyright (C) 1999 David A. Hinds -- dahinds@users.sourceforge.net pcnet_cs.c 1.153 2003/11/09 18:53:09 The network driver code is based on Donald Becker's NE2000 code: Written 1992,1993 by Donald Becker. Copyright 1993 United States Government as represented by the Director, National Security Agency. This software may be used and distributed according to the terms of the GNU General Public License, incorporated herein by reference. Donald Becker may be reached at becker@scyld.com Based also on Keith Moore's changes to Don Becker's code, for IBM CCAE support. Drivers merged back together, and shared-memory Socket EA support added, by Ken Raeburn, September 1995. ======================================================================*/ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include #include #include #include #include #include #include #include #include #include #include "8390.h" #include #include #include #include #include #include #include #define PCNET_CMD 0x00 #define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */ #define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */ #define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */ #define PCNET_START_PG 0x40 /* First page of TX buffer */ #define PCNET_STOP_PG 0x80 /* Last page +1 of RX ring */ /* Socket EA cards have a larger packet buffer */ #define SOCKET_START_PG 0x01 #define SOCKET_STOP_PG 0xff #define PCNET_RDC_TIMEOUT (2*HZ/100) /* Max wait in jiffies for Tx RDC */ static const char *if_names[] = { "auto", "10baseT", "10base2"}; static u32 pcnet_msg_enable; /*====================================================================*/ /* Module parameters */ MODULE_AUTHOR("David Hinds "); MODULE_DESCRIPTION("NE2000 compatible PCMCIA ethernet driver"); MODULE_LICENSE("GPL"); #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) INT_MODULE_PARM(if_port, 1); /* Transceiver type */ INT_MODULE_PARM(use_big_buf, 1); /* use 64K packet buffer? */ INT_MODULE_PARM(mem_speed, 0); /* shared mem speed, in ns */ INT_MODULE_PARM(delay_output, 0); /* pause after xmit? */ INT_MODULE_PARM(delay_time, 4); /* in usec */ INT_MODULE_PARM(use_shmem, -1); /* use shared memory? */ INT_MODULE_PARM(full_duplex, 0); /* full duplex? */ /* Ugh! Let the user hardwire the hardware address for queer cards */ static int hw_addr[6] = { 0, /* ... */ }; module_param_array(hw_addr, int, NULL, 0); /*====================================================================*/ static void mii_phy_probe(struct net_device *dev); static int pcnet_config(struct pcmcia_device *link); static void pcnet_release(struct pcmcia_device *link); static int pcnet_open(struct net_device *dev); static int pcnet_close(struct net_device *dev); static int ei_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); static irqreturn_t ei_irq_wrapper(int irq, void *dev_id); static void ei_watchdog(u_long arg); static void pcnet_reset_8390(struct net_device *dev); static int set_config(struct net_device *dev, struct ifmap *map); static int setup_shmem_window(struct pcmcia_device *link, int start_pg, int stop_pg, int cm_offset); static int setup_dma_config(struct pcmcia_device *link, int start_pg, int stop_pg); static void pcnet_detach(struct pcmcia_device *p_dev); /*====================================================================*/ struct hw_info { u_int offset; u_char a0, a1, a2; u_int flags; }; #define DELAY_OUTPUT 0x01 #define HAS_MISC_REG 0x02 #define USE_BIG_BUF 0x04 #define HAS_IBM_MISC 0x08 #define IS_DL10019 0x10 #define IS_DL10022 0x20 #define HAS_MII 0x40 #define USE_SHMEM 0x80 /* autodetected */ #define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */ #define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */ #define MII_PHYID_REV_MASK 0xfffffff0 #define MII_PHYID_REG1 0x02 #define MII_PHYID_REG2 0x03 static struct hw_info hw_info[] = { { /* Accton EN2212 */ 0x0ff0, 0x00, 0x00, 0xe8, DELAY_OUTPUT }, { /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 }, { /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 }, { /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94, DELAY_OUTPUT | HAS_IBM_MISC }, { /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 }, { /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 }, { /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 }, { /* D-Link DE-650 */ 0x0040, 0x00, 0x80, 0xc8, 0 }, { /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 }, { /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 }, { /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48, HAS_MISC_REG | HAS_IBM_MISC }, { /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 }, { /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 }, { /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a, HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac, HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29, HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a, HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM FME */ 0x0374, 0x00, 0x04, 0xac, HAS_MISC_REG | HAS_IBM_MISC }, { /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87, HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17, HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8, HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0, HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0, HAS_MISC_REG | HAS_IBM_MISC }, { /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 }, { /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 }, { /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0, HAS_MISC_REG | HAS_IBM_MISC }, { /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f, HAS_MISC_REG | HAS_IBM_MISC }, { /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 }, { /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 }, { /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 }, { /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 }, { /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65, HAS_MISC_REG | HAS_IBM_MISC }, { /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45, HAS_MISC_REG | HAS_IBM_MISC }, { /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 }, { /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 }, { /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 }, { /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b, DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF }, { /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 }, { /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 }, { /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 }, { /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 }, { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 } }; #define NR_INFO ARRAY_SIZE(hw_info) static struct hw_info default_info = { 0, 0, 0, 0, 0 }; static struct hw_info dl10019_info = { 0, 0, 0, 0, IS_DL10019|HAS_MII }; static struct hw_info dl10022_info = { 0, 0, 0, 0, IS_DL10022|HAS_MII }; struct pcnet_dev { struct pcmcia_device *p_dev; u_int flags; void __iomem *base; struct timer_list watchdog; int stale, fast_poll; u_char phy_id; u_char eth_phy, pna_phy; u_short link_status; u_long mii_reset; }; static inline struct pcnet_dev *PRIV(struct net_device *dev) { char *p = netdev_priv(dev); return (struct pcnet_dev *)(p + sizeof(struct ei_device)); } static const struct net_device_ops pcnet_netdev_ops = { .ndo_open = pcnet_open, .ndo_stop = pcnet_close, .ndo_set_config = set_config, .ndo_start_xmit = ei_start_xmit, .ndo_get_stats = ei_get_stats, .ndo_do_ioctl = ei_ioctl, .ndo_set_rx_mode = ei_set_multicast_list, .ndo_tx_timeout = ei_tx_timeout, .ndo_change_mtu = eth_change_mtu, .ndo_set_mac_address = eth_mac_addr, .ndo_validate_addr = eth_validate_addr, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = ei_poll, #endif }; static int pcnet_probe(struct pcmcia_device *link) { struct pcnet_dev *info; struct net_device *dev; dev_dbg(&link->dev, "pcnet_attach()\n"); /* Create new ethernet device */ dev = __alloc_ei_netdev(sizeof(struct pcnet_dev)); if (!dev) return -ENOMEM; info = PRIV(dev); info->p_dev = link; link->priv = dev; link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO; dev->netdev_ops = &pcnet_netdev_ops; return pcnet_config(link); } /* pcnet_attach */ static void pcnet_detach(struct pcmcia_device *link) { struct net_device *dev = link->priv; dev_dbg(&link->dev, "pcnet_detach\n"); unregister_netdev(dev); pcnet_release(link); free_netdev(dev); } /* pcnet_detach */ /*====================================================================== This probes for a card's hardware address, for card types that encode this information in their CIS. ======================================================================*/ static struct hw_info *get_hwinfo(struct pcmcia_device *link) { struct net_device *dev = link->priv; u_char __iomem *base, *virt; int i, j; /* Allocate a small memory window */ link->resource[2]->flags |= WIN_DATA_WIDTH_8|WIN_MEMORY_TYPE_AM|WIN_ENABLE; link->resource[2]->start = 0; link->resource[2]->end = 0; i = pcmcia_request_window(link, link->resource[2], 0); if (i != 0) return NULL; virt = ioremap(link->resource[2]->start, resource_size(link->resource[2])); for (i = 0; i < NR_INFO; i++) { pcmcia_map_mem_page(link, link->resource[2], hw_info[i].offset & ~(resource_size(link->resource[2])-1)); base = &virt[hw_info[i].offset & (resource_size(link->resource[2])-1)]; if ((readb(base+0) == hw_info[i].a0) && (readb(base+2) == hw_info[i].a1) && (readb(base+4) == hw_info[i].a2)) { for (j = 0; j < 6; j++) dev->dev_addr[j] = readb(base + (j<<1)); break; } } iounmap(virt); j = pcmcia_release_window(link, link->resource[2]); return (i < NR_INFO) ? hw_info+i : NULL; } /* get_hwinfo */ /*====================================================================== This probes for a card's hardware address by reading the PROM. It checks the address against a list of known types, then falls back to a simple NE2000 clone signature check. ======================================================================*/ static struct hw_info *get_prom(struct pcmcia_device *link) { struct net_device *dev = link->priv; unsigned int ioaddr = dev->base_addr; u_char prom[32]; int i, j; /* This is lifted straight from drivers/net/ethernet/8390/ne.c */ struct { u_char value, offset; } program_seq[] = { {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/ {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */ {0x00, EN0_RCNTLO}, /* Clear the count regs. */ {0x00, EN0_RCNTHI}, {0x00, EN0_IMR}, /* Mask completion irq. */ {0xFF, EN0_ISR}, {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */ {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */ {32, EN0_RCNTLO}, {0x00, EN0_RCNTHI}, {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */ {0x00, EN0_RSARHI}, {E8390_RREAD+E8390_START, E8390_CMD}, }; pcnet_reset_8390(dev); mdelay(10); for (i = 0; i < ARRAY_SIZE(program_seq); i++) outb_p(program_seq[i].value, ioaddr + program_seq[i].offset); for (i = 0; i < 32; i++) prom[i] = inb(ioaddr + PCNET_DATAPORT); for (i = 0; i < NR_INFO; i++) { if ((prom[0] == hw_info[i].a0) && (prom[2] == hw_info[i].a1) && (prom[4] == hw_info[i].a2)) break; } if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) { for (j = 0; j < 6; j++) dev->dev_addr[j] = prom[j<<1]; return (i < NR_INFO) ? hw_info+i : &default_info; } return NULL; } /* get_prom */ /*====================================================================== For DL10019 based cards, like the Linksys EtherFast ======================================================================*/ static struct hw_info *get_dl10019(struct pcmcia_device *link) { struct net_device *dev = link->priv; int i; u_char sum; for (sum = 0, i = 0x14; i < 0x1c; i++) sum += inb_p(dev->base_addr + i); if (sum != 0xff) return NULL; for (i = 0; i < 6; i++) dev->dev_addr[i] = inb_p(dev->base_addr + 0x14 + i); i = inb(dev->base_addr + 0x1f); return ((i == 0x91)||(i == 0x99)) ? &dl10022_info : &dl10019_info; } /*====================================================================== For Asix AX88190 based cards ======================================================================*/ static struct hw_info *get_ax88190(struct pcmcia_device *link) { struct net_device *dev = link->priv; unsigned int ioaddr = dev->base_addr; int i, j; /* Not much of a test, but the alternatives are messy */ if (link->config_base != 0x03c0) return NULL; outb_p(0x01, ioaddr + EN0_DCFG); /* Set word-wide access. */ outb_p(0x00, ioaddr + EN0_RSARLO); /* DMA starting at 0x0400. */ outb_p(0x04, ioaddr + EN0_RSARHI); outb_p(E8390_RREAD+E8390_START, ioaddr + E8390_CMD); for (i = 0; i < 6; i += 2) { j = inw(ioaddr + PCNET_DATAPORT); dev->dev_addr[i] = j & 0xff; dev->dev_addr[i+1] = j >> 8; } return NULL; } /*====================================================================== This should be totally unnecessary... but when we can't figure out the hardware address any other way, we'll let the user hard wire it when the module is initialized. ======================================================================*/ static struct hw_info *get_hwired(struct pcmcia_device *link) { struct net_device *dev = link->priv; int i; for (i = 0; i < 6; i++) if (hw_addr[i] != 0) break; if (i == 6) return NULL; for (i = 0; i < 6; i++) dev->dev_addr[i] = hw_addr[i]; return &default_info; } /* get_hwired */ static int try_io_port(struct pcmcia_device *link) { int j, ret; link->resource[0]->flags &= ~IO_DATA_PATH_WIDTH; link->resource[1]->flags &= ~IO_DATA_PATH_WIDTH; if (link->resource[0]->end == 32) { link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO; if (link->resource[1]->end > 0) { /* for master/slave multifunction cards */ link->resource[1]->flags |= IO_DATA_PATH_WIDTH_8; } } else { /* This should be two 16-port windows */ link->resource[0]->flags |= IO_DATA_PATH_WIDTH_8; link->resource[1]->flags |= IO_DATA_PATH_WIDTH_16; } if (link->resource[0]->start == 0) { for (j = 0; j < 0x400; j += 0x20) { link->resource[0]->start = j ^ 0x300; link->resource[1]->start = (j ^ 0x300) + 0x10; link->io_lines = 16; ret = pcmcia_request_io(link); if (ret == 0) return ret; } return ret; } else { return pcmcia_request_io(link); } } static int pcnet_confcheck(struct pcmcia_device *p_dev, void *priv_data) { int *priv = priv_data; int try = (*priv & 0x1); *priv &= (p_dev->resource[2]->end >= 0x4000) ? 0x10 : ~0x10; if (p_dev->config_index == 0) return -EINVAL; if (p_dev->resource[0]->end + p_dev->resource[1]->end < 32) return -EINVAL; if (try) p_dev->io_lines = 16; return try_io_port(p_dev); } static struct hw_info *pcnet_try_config(struct pcmcia_device *link, int *has_shmem, int try) { struct net_device *dev = link->priv; struct hw_info *local_hw_info; struct pcnet_dev *info = PRIV(dev); int priv = try; int ret; ret = pcmcia_loop_config(link, pcnet_confcheck, &priv); if (ret) { dev_warn(&link->dev, "no useable port range found\n"); return NULL; } *has_shmem = (priv & 0x10); if (!link->irq) return NULL; if (resource_size(link->resource[1]) == 8) link->config_flags |= CONF_ENABLE_SPKR; if ((link->manf_id == MANFID_IBM) && (link->card_id == PRODID_IBM_HOME_AND_AWAY)) link->config_index |= 0x10; ret = pcmcia_enable_device(link); if (ret) return NULL; dev->irq = link->irq; dev->base_addr = link->resource[0]->start; if (info->flags & HAS_MISC_REG) { if ((if_port == 1) || (if_port == 2)) dev->if_port = if_port; else dev_notice(&link->dev, "invalid if_port requested\n"); } else dev->if_port = 0; if ((link->config_base == 0x03c0) && (link->manf_id == 0x149) && (link->card_id == 0xc1ab)) { dev_info(&link->dev, "this is an AX88190 card - use axnet_cs instead.\n"); return NULL; } local_hw_info = get_hwinfo(link); if (!local_hw_info) local_hw_info = get_prom(link); if (!local_hw_info) local_hw_info = get_dl10019(link); if (!local_hw_info) local_hw_info = get_ax88190(link); if (!local_hw_info) local_hw_info = get_hwired(link); return local_hw_info; } static int pcnet_config(struct pcmcia_device *link) { struct net_device *dev = link->priv; struct pcnet_dev *info = PRIV(dev); int start_pg, stop_pg, cm_offset; int has_shmem = 0; struct hw_info *local_hw_info; struct ei_device *ei_local; dev_dbg(&link->dev, "pcnet_config\n"); local_hw_info = pcnet_try_config(link, &has_shmem, 0); if (!local_hw_info) { /* check whether forcing io_lines to 16 helps... */ pcmcia_disable_device(link); local_hw_info = pcnet_try_config(link, &has_shmem, 1); if (local_hw_info == NULL) { dev_notice(&link->dev, "unable to read hardware net" " address for io base %#3lx\n", dev->base_addr); goto failed; } } info->flags = local_hw_info->flags; /* Check for user overrides */ info->flags |= (delay_output) ? DELAY_OUTPUT : 0; if ((link->manf_id == MANFID_SOCKET) && ((link->card_id == PRODID_SOCKET_LPE) || (link->card_id == PRODID_SOCKET_LPE_CF) || (link->card_id == PRODID_SOCKET_EIO))) info->flags &= ~USE_BIG_BUF; if (!use_big_buf) info->flags &= ~USE_BIG_BUF; if (info->flags & USE_BIG_BUF) { start_pg = SOCKET_START_PG; stop_pg = SOCKET_STOP_PG; cm_offset = 0x10000; } else { start_pg = PCNET_START_PG; stop_pg = PCNET_STOP_PG; cm_offset = 0; } /* has_shmem is ignored if use_shmem != -1 */ if ((use_shmem == 0) || (!has_shmem && (use_shmem == -1)) || (setup_shmem_window(link, start_pg, stop_pg, cm_offset) != 0)) setup_dma_config(link, start_pg, stop_pg); ei_status.name = "NE2000"; ei_status.word16 = 1; ei_status.reset_8390 = pcnet_reset_8390; if (info->flags & (IS_DL10019|IS_DL10022)) mii_phy_probe(dev); SET_NETDEV_DEV(dev, &link->dev); ei_local = netdev_priv(dev); ei_local->msg_enable = pcnet_msg_enable; if (register_netdev(dev) != 0) { pr_notice("register_netdev() failed\n"); goto failed; } if (info->flags & (IS_DL10019|IS_DL10022)) { u_char id = inb(dev->base_addr + 0x1a); netdev_info(dev, "NE2000 (DL100%d rev %02x): ", (info->flags & IS_DL10022) ? 22 : 19, id); if (info->pna_phy) pr_cont("PNA, "); } else { netdev_info(dev, "NE2000 Compatible: "); } pr_cont("io %#3lx, irq %d,", dev->base_addr, dev->irq); if (info->flags & USE_SHMEM) pr_cont(" mem %#5lx,", dev->mem_start); if (info->flags & HAS_MISC_REG) pr_cont(" %s xcvr,", if_names[dev->if_port]); pr_cont(" hw_addr %pM\n", dev->dev_addr); return 0; failed: pcnet_release(link); return -ENODEV; } /* pcnet_config */ static void pcnet_release(struct pcmcia_device *link) { struct pcnet_dev *info = PRIV(link->priv); dev_dbg(&link->dev, "pcnet_release\n"); if (info->flags & USE_SHMEM) iounmap(info->base); pcmcia_disable_device(link); } static int pcnet_suspend(struct pcmcia_device *link) { struct net_device *dev = link->priv; if (link->open) netif_device_detach(dev); return 0; } static int pcnet_resume(struct pcmcia_device *link) { struct net_device *dev = link->priv; if (link->open) { pcnet_reset_8390(dev); NS8390_init(dev, 1); netif_device_attach(dev); } return 0; } /*====================================================================== MII interface support for DL10019 and DL10022 based cards On the DL10019, the MII IO direction bit is 0x10; on the DL10022 it is 0x20. Setting both bits seems to work on both card types. ======================================================================*/ #define DLINK_GPIO 0x1c #define DLINK_DIAG 0x1d #define DLINK_EEPROM 0x1e #define MDIO_SHIFT_CLK 0x80 #define MDIO_DATA_OUT 0x40 #define MDIO_DIR_WRITE 0x30 #define MDIO_DATA_WRITE0 (MDIO_DIR_WRITE) #define MDIO_DATA_WRITE1 (MDIO_DIR_WRITE | MDIO_DATA_OUT) #define MDIO_DATA_READ 0x10 #define MDIO_MASK 0x0f static void mdio_sync(u
/*
 * OMAP4 CM instance functions
 *
 * Copyright (C) 2009 Nokia Corporation
 * Copyright (C) 2008-2011 Texas Instruments, Inc.
 * Paul Walmsley
 * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1,
 * or CM2 hardware modules.  For example, the EMU_CM CM instance is in
 * the PRM hardware module.  What a mess...
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include "clockdomain.h"
#include "cm.h"
#include "cm1_44xx.h"
#include "cm2_44xx.h"
#include "cm44xx.h"
#include "cm-regbits-34xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
#include "prcm_mpu44xx.h"
#include "prcm-common.h"

#define OMAP4430_IDLEST_SHIFT		16
#define OMAP4430_IDLEST_MASK		(0x3 << 16)
#define OMAP4430_CLKTRCTRL_SHIFT	0
#define OMAP4430_CLKTRCTRL_MASK		(0x3 << 0)
#define OMAP4430_MODULEMODE_SHIFT	0
#define OMAP4430_MODULEMODE_MASK	(0x3 << 0)

/*
 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
 *
 *   0x0 func:     Module is fully functional, including OCP
 *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
 *                 abortion
 *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
 *                 using separate functional clock
 *   0x3 disabled: Module is disabled and cannot be accessed
 *
 */
#define CLKCTRL_IDLEST_FUNCTIONAL		0x0
#define CLKCTRL_IDLEST_INTRANSITION		0x1
#define CLKCTRL_IDLEST_INTERFACE_IDLE		0x2
#define CLKCTRL_IDLEST_DISABLED			0x3

static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];

/**
 * omap_cm_base_init - Populates the cm partitions
 *
 * Populates the base addresses of the _cm_bases
 * array used for read/write of cm module registers.
 */
static void omap_cm_base_init(void)
{
	_cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
	_cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
	_cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
	_cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
}

/* Private functions */

static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);

/**
 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
 * bit 0.
 */
static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs)
{
	u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
	v &= OMAP4430_IDLEST_MASK;
	v >>= OMAP4430_IDLEST_SHIFT;
	return v;
}

/**
 * _is_module_ready - can module registers be accessed without causing an abort?
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
 */
static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs)
{
	u32 v;

	v = _clkctrl_idlest(part, inst, clkctrl_offs);

	return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
		v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
}

/* Read a register in a CM instance */
static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
{
	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
	       part == OMAP4430_INVALID_PRCM_PARTITION ||
	       !_cm_bases[part]);
	return readl_relaxed(_cm_bases[part] + inst + idx);
}

/* Write into a register in a CM instance */
static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
{
	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
	       part == OMAP4430_INVALID_PRCM_PARTITION ||
	       !_cm_bases[part]);
	writel_relaxed(val, _cm_bases[part] + inst + idx);
}

/* Read-modify-write a register in CM1. Caller must lock */
static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
					  s16 idx)
{
	u32 v;

	v = omap4_cminst_read_inst_reg(part, inst, idx);
	v &= ~mask;
	v |= bits;
	omap4_cminst_write_inst_reg(v, part, inst, idx);

	return v;
}

static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
{
	return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
}

static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
					    s16 idx)
{
	return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
}

static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
{
	u32 v;

	v = omap4_cminst_read_inst_reg(part, inst, idx);
	v &= mask;
	v >>= __ffs(mask);

	return v;
}

/*
 *
 */

/**
 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
 * will handle the shift itself.
 */
static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
{
	u32 v;

	v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
	v &= ~OMAP4430_CLKTRCTRL_MASK;
	v |= c << OMAP4430_CLKTRCTRL_SHIFT;
	omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
}

/**
 * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
 * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
 * is in hardware-supervised idle mode, or 0 otherwise.
 */
static bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
{
	u32 v;

	v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
	v &= OMAP4430_CLKTRCTRL_MASK;
	v >>= OMAP4430_CLKTRCTRL_SHIFT;

	return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
}

/**
 * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
 * @part: PRCM partition ID that the clockdomain registers exist in
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
 * hardware-supervised idle mode.  No return value.
 */
static void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
{
	_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
}

/**
 * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
 * @part: PRCM partition ID that the clockdomain registers exist in
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
 * software-supervised idle mode, i.e., controlled manually by the
 * Linux OMAP clockdomain code.  No return value.
 */
static void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
{
	_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
}

/**
 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
 * @part: PRCM partition ID that the clockdomain registers exist in
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
 * waking it up.  No return value.
 */
static void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
{
	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
}

/*
 *
 */

static void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
{
	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
}

/**
 * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 * @bit_shift: bit shift for the register, ignored for OMAP4+
 *
 * Wait for the module IDLEST to be functional. If the idle state is in any
 * the non functional state (trans, idle or disabled), module and thus the
 * sysconfig cannot be accessed and will probably lead to an "imprecise
 * external abort"
 */
static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
					  u8 bit_shift)
{
	int i = 0;

	if (!clkctrl_offs)
		return 0;

	omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
			  MAX_MODULE_READY_TIME, i);

	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}

/**
 * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
 * state
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 * @bit_shift: Bit shift for the register, ignored for OMAP4+
 *
 * Wait for the module IDLEST to be disabled. Some PRCM transition,
 * like reset assertion or parent clock de-activation must wait the
 * module to be fully disabled.
 */
static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
					 u8 bit_shift)
{
	int i = 0;

	if (!clkctrl_offs)
		return 0;

	omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) ==
			   CLKCTRL_IDLEST_DISABLED),
			  MAX_MODULE_DISABLE_TIME, i);

	return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY;
}

/**
 * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
 * @mode: Module mode (SW or HW)
 * @part: PRCM partition ID that the CM_CLKCTRL register exists in
 * @inst: CM instance register offset (*_INST macro)