/* * Device Tree Include file for Marvell Armada 38x family of SoCs. * * Copyright (C) 2014 Marvell * * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" #include #include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { model = "Marvell Armada 38x family SoC"; compatible = "marvell,armada380"; aliases { gpio0 = &gpio0; gpio1 = &gpio1; serial0 = &uart0; serial1 = &uart1; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts-extended = <&mpic 3>; }; soc { compatible = "marvell,armada380-mbus", "simple-bus"; #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; interrupt-parent = <&gic>; pcie-mem-aperture = <0xe0000000 0x8000000>; pcie-io-aperture = <0xe8000000 0x100000>; bootrom { compatible = "marvell,bootrom"; reg = ; }; devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; #address-cells = <1>; #size-cells = <1>; clocks = <&coreclk 0>; status = "disabled"; }; internal-regs { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; L2: cache-controller@8000 { compatible = "arm,pl310-cache"; reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; }; scu@c000 { compatible = "arm,cortex-a9-scu"; reg = <0xc000 0x58>; }; timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; interrupts = ; clocks = <&coreclk 2>; }; gic: interrupt-controller@d000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #size-cells = <0>; interrupt-controller; reg = <0xd000 0x1000>, <0xc100 0x100>; }; spi0: spi@10600 { compatible = "marvell,orion-spi"; reg = <0x10600 0x50>; #address-cells = <1>; #size-cells = <0>; cell-index = <0>; interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; spi1: spi@10680 { compatible = "marvell,orion-spi"; reg = <0x10680 0x50>; #address-cells = <1>; #size-cells = <0>; cell-index = <1>; interrupts = ; clocks = <&coreclk 0>; status = "disabled"; }; i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; interrupts = ; timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; i2c1: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; interrup
#include "qcom-apq8064-v2.0.dtsi"

/ {
	model = "CompuLab CM-QS600";
	compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064";

	soc {
		pinctrl@800000 {
			i2c1_pins: i2c1 {
				mux {
					pins = "gpio20", "gpio21";
					function = "gsbi1";
				};
			};
		};

		gsbi@12440000 {
			status = "okay";
			qcom,mode = <GSBI_PROT_I2C>;

			i2c@12460000 {
				status = "okay";
				clock-frequency = <200000>;
				pinctrl-0 = <&i2c1_pins>;
				pinctrl-names = "default";