/* * Device Tree Source for the r8a7794 SoC * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright (C) 2014 Ulrich Hecht * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include #include / { compatible = "renesas,r8a7794"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; }; }; gic: interrupt-controller@f1001000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; cmt0: timer@ffca0000 { compatible = "renesas,cmt-48-gen2"; reg = <0 0xffca0000 0 0x1004>; interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, <0 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7794_CLK_CMT0>; clock-names = "fck"; renesas,channels-mask = <0x60>; status = "disabled"; }; cmt1: timer@e6130000 { compatible = "renesas,cmt-48-gen2"; reg = <0 0xe6130000 0 0x1004>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, <0 121 IRQ_TYPE_LEVEL_HIGH>, <0 122 IRQ_TYPE_LEVEL_HIGH>, <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 124 IRQ_TYPE_LEVEL_HIGH>, <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_CMT1>; clock-names = "fck"; renesas,channels-mask = <0xff>; status = "disabled"; }; timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7794", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, <0 3 IRQ_TYPE_LEVEL_HIGH>, <0 12 IRQ_TYPE_LEVEL_HIGH>, <0 13 IRQ_TYPE_LEVEL_HIGH>, <0 14 IRQ_TYPE_LEVEL_HIGH>, <0 15 IRQ_TYPE_LEVEL_HIGH>, <0 16 IRQ_TYPE_LEVEL_HIGH>, <0 17 IRQ_TYPE_LEVEL_HIGH>; }; dmac0: dma-controller@e6700000 { compatible = "renesas,rcar-dmac"; reg = <0 0xe6700000 0 0x20000>; interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH 0 200 IRQ_TYPE_LEVEL_HIGH 0 201 IRQ_TYPE_LEVEL_HIGH 0 202 IRQ_TYPE_LEVEL_HIGH 0 203 IRQ_TYPE_LEVEL_HIGH 0 204 IRQ_TYPE_LEVEL_HIGH 0 205 IRQ_TYPE_LEVEL_HIGH 0 206 IRQ_TYPE_LEVEL_HIGH 0 207 IRQ_TYPE_LEVEL_HIGH 0 208 IRQ_TYPE_LEVEL_HIGH 0 209 IRQ_TYPE_LEVEL_HIGH 0 210 IRQ_TYPE_LEVEL_HIGH 0 211 IRQ_TYPE_LEVEL_HIGH 0 212 IRQ_TYPE_LEVEL_HIGH 0 213 IRQ_TYPE_LEVEL_HIGH 0 214 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; clock-names = "fck"; #dma-cells = <1>; dma-channels = <15>; }; dmac1: dma-controller@e6720000 { compatible = "renesas,rcar-dmac"; reg = <0 0xe6720000 0 0x20000>; interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 0 216 IRQ_TYPE_LEVEL_HIGH 0 217 IRQ_TYPE_LEVEL_HIGH 0 218 IRQ_TYPE_LEVEL_HIGH 0 219 IRQ_TYPE_LEVEL_HIGH 0 308 IRQ_TYPE_LEVEL_HIGH 0 309 IRQ_TYPE_LEVEL_HIGH 0 310 IRQ_TYPE_LEVEL_HIGH 0 311 IRQ_TYPE_LEVEL_HIGH 0 312 IRQ_TYPE_LEVEL_HIGH 0 313 IRQ_TYPE_LEVEL_HIGH 0 314 IRQ_TYPE_LEVEL_HIGH 0 315 IRQ_TYPE_LEVEL_HIGH 0 316 IRQ_TYPE_LEVEL_HIGH 0 317 IRQ_TYPE_LEVEL_HIGH 0 318 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; clock-names = "fck"; #dma-cells = <1>; dma-channels = <15>; }; scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; clock-names = "sci_ick"; status = "disabled"; }; scifa1: serial@e6c50000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; clock-names = "sci_ick"; status = "disabled"; }; scifa2: serial@e6c60000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; clock-names = "sci_ick"; status = "disabled"; }; scifa3: serial@e6c70000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; clock-names = "sci_ick"; status = "disabled"; }; scifa4: serial@e6c78000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; clock-names = "sci_ick"; status = "disabled"; }; scifa5: serial@e6c80000 { compatible = "renesas,scifa-r8a7794", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; clock-names = "sci_ick"; status = "disabled"; }; scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a7794", "renesas,scifb"; reg = <0 0xe6c20000 0 64>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; clock-names = "sci_ick"; status = "disabled"; }; scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a7794", "renesas,scifb"; reg = <0 0xe6c30000 0 64>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; clock-names = "sci_ick"; status = "disabled"; }; scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a7794", "renesas,scifb"; reg = <0 0xe6ce0000 0 64>; interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; clock-names = "sci_ick"; status = "disabled"; }; scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; clock-names = "sci_ick"; status = "disabled"; }; scif1: serial@e6e68000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; clock-names = "sci_ick"; status = "disabled"; }; scif2: serial@e6e58000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; clock-names = "sci_ick"; status = "disabled"; }; scif3: serial@e6ea8000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; clock-names = "sci_ick"; status = "disabled"; }; scif4: serial@e6ee0000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; clock-names = "sci_ick"; status = "disabled"; }; scif5: serial@e6ee8000 { compatible = "renesas,scif-r8a7794", "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; clock-names = "sci_ick"; status = "disabled"; }; hscif0: serial@e62c0000 { compatible = "renesas,hscif-r8a7794", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; clock-names = "sci_ick"; status = "disabled"; }; hscif1: serial@e62c8000 { compatible = "renesas,hscif-r8a7794", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; clock-names = "sci_ick"; status = "disabled"; }; hscif2: serial@e62d0000 { compatible = "renesas,hscif-r8a7794", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; clock-names = "sci_ick"; status = "disabled"; }; ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7794"; reg = <0 0xee700000 0 0x400>; interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7794_CLK_ETHER>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee100000 0 0x200>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; status = "disabled"; }; sdhi1: sd@ee140000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; status = "disabled"; }; sdhi2: sd@ee160000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; status = "disabled"; }; clocks { #address-cells = <2>; #size-cells = <2>; ranges; /* External root clock */ extal_clk: extal_clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; clock-output-names = "extal"; }; /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7794-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "z"; }; /* Variable factor clocks */ sd2_clk: sd2_clk@e6150078 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "sd2"; }; sd3_clk: sd3_clk@e615026c { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "sd3"; }; mmc0_clk: mmc0_clk@e6150240 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "mmc0"; }; /* Fixed factor clocks */ pll1_div2_clk: pll1_div2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "pll1_div2"; }; zg_clk: zg_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; clock-output-names = "zg"; }; zx_clk: zx_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; clock-output-names = "zx"; }; zs_clk: zs_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; clock-output-names = "zs"; }; hp_clk: hp_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; clock-output-names = "hp"; }; i_clk: i_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "i"; }; b_clk: b_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; clock-output-names = "b"; }; p_clk: p_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; clock-output-names = "p"; }; cl_clk: cl_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; clock-output-names = "cl"; }; m2_clk: m2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "m2"; }; imp_clk: imp_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; clock-output-names = "imp"; }; rclk_clk: rclk_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; clock-output-names = "rclk"; }; oscclk_clk: oscclk_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; clock-output-names = "oscclk"; }; zb3_clk: zb3_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; clock-output-names = "zb3"; }; zb3d2_clk: zb3d2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "zb3d2"; }; ddr_clk: ddr_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; clock-output-names = "ddr"; }; mp_clk: mp_clk { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; clock-outp