/* * Device Tree file for Marvell Armada XP development board * (DB-MV784MP-GP) * * Copyright (C) 2013-2014 Marvell * * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default * 0xd0000000). The 0xf1000000 is the default used by the recent, * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier * boards were delivered with an older version of the bootloader that * left internal registers mapped at 0xd0000000. If you are in this * situation, you should either update your bootloader (preferred * solution) or the below Device Tree should be adjusted. */ /dts-v1/; #include #include "armada-xp-mv78460.dtsi" / { model = "Marvell Armada XP Development Board DB-MV784MP-GP"; compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; chosen { stdout-path = "serial0:115200n8"; }; memory { device_type = "memory"; /* * 8 GB of plug-in RAM modules by default.The amount * of memory available can be changed by the * bootloader according the size of the module * actually plugged. However, memory between * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is * the address range used for I/O (internal registers, * MBus windows). */ reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, <0x00000001 0x00000000 0x00000001 0x00000000>; }; cpus { pm_pic { ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, <&gpio0 17 GPIO_ACTIVE_LOW>, <&gpio0 18 GPIO_ACTIVE_LOW>; }; }; soc { ranges = ; devbus-bootcs { status = "okay"; /* Device Bus parameters are required */ /* Read parameters */ devbus,bus-width = <16>; devbus,turn-off-ps = <60000>; devbus,badr-skew-ps = <0>; devbus,acc-first-ps = <124000>; devbus,acc-next-ps = <248000>; devbus,rd-setup-ps = <0>; devbus,rd-hold-ps = <0>; /* Write parameters */ devbus,sync-enable = <0>; devbus,wr-high-ps = <60000>; devbus,wr-low-ps = <60000>; devbus,ale-wr-ps = <60000>; /* NOR 16 MiB */ nor@0 { compatible = "cfi-flash"; reg = <0 0x1000000>; bank-width = <2>; }; }; pcie-controller { status = "okay"; /* * The 3 slots are physically present as * standard PCIe slots on the board. */ pcie@1,0 { /* Port 0, Lane 0 */ status = "okay"; }; pcie@9,0 { /* Port 2, Lane 0 */ status = "okay"; }; pcie@10,0 { /* Port 3, Lane 0 */ status = "okay"; }; }; internal-regs { serial@12000 { status = "okay"; }; serial@12100 { status = "okay"; }; serial@12200 { status = "okay"; }; serial@12300 { status = "okay"; }; pinctrl { pinctrl-0 = <&pic_pins>; pinctrl-names = "default"; pic_pins: pic-pins-0 { marvell,pins = "mpp16", "mpp17", "mpp18"; marvell,function = "gpio"; }; }; sata@a0000 { nr-ports = <2>; status = "okay"; }; mdio { phy0: ethernet-phy@0 { reg = <16>; }; phy1: ethernet-phy@1 { reg = <17>; }; phy2: ethernet-phy@2 { reg = <18>; }; phy3: ethernet-phy@3 { reg = <19>; }; }; ethernet@70000 { status = "okay"; phy = <&phy0>; phy-mode = "qsgmii"; }; ethern