/* $Id: sunqe.h,v 1.13 2000/02/09 11:15:42 davem Exp $ * sunqe.h: Definitions for the Sun QuadEthernet driver. * * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) */ #ifndef _SUNQE_H #define _SUNQE_H /* QEC global registers. */ #define GLOB_CTRL 0x00UL /* Control */ #define GLOB_STAT 0x04UL /* Status */ #define GLOB_PSIZE 0x08UL /* Packet Size */ #define GLOB_MSIZE 0x0cUL /* Local-memory Size */ #define GLOB_RSIZE 0x10UL /* Receive partition size */ #define GLOB_TSIZE 0x14UL /* Transmit partition size */ #define GLOB_REG_SIZE 0x18UL #define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */ #define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */ #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */ #define GLOB_CTRL_ACNTRL 0x00000018 /* SBUS arbitration control */ #define GLOB_CTRL_B64 0x00000004 /* 64 byte dvma bursts */ #define GLOB_CTRL_B32 0x00000002 /* 32 byte dvma bursts */ #define GLOB_CTRL_B16 0x00000000 /* 16 byte dvma bursts */ #define GLOB_CTRL_RESET 0x00000001 /* Reset the QEC */ #define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */ #define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */ #define GLOB_STAT_BM 0x00000002 /* BigMAC Global IRQ */ #define GLOB_STAT_ER 0x00000001 /* BigMAC Error IRQ */ #define GLOB_PSIZE_2048 0x00 /* 2k packet size */ #define GLOB_PSIZE_4096 0x01 /* 4k packet size */ #define GLOB_PSIZE_6144 0x10 /* 6k packet size */ #define GLOB_PSIZE_8192 0x11 /* 8k packet size */ /* In MACE mode, there are four qe channels. Each channel has it's own * status bits in the QEC status register. This macro picks out the * ones you want. */ #define GLOB_STAT_PER_QE(status, channel) (((status) >> ((channel) * 4)) & 0xf) /* The following registers are for per-qe channel information/status. */ #define CREG_CTRL 0x00UL /* Control */ #define CREG_STAT 0x04UL /* Status */ #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */ #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */ #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */ #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */ #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */ #define CREG_MMASK 0x1cUL /* MACE Error Interrupt Mask */ #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */ #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */ #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */ #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */ #define CREG_CCNT 0x30UL /* Collision Counter */ #define CREG_PIPG 0x34UL /* Inter-Frame Gap */ #define CREG_REG_SIZE 0x38UL #define CREG_CTRL_RXOFF 0x00000004 /* Disable this qe's receiver*/ #define CREG_CTRL_RESET 0x00000002 /* Reset this qe channel */ #define CREG_CTRL_TWAKEUP 0x00000001 /* Transmitter Wakeup, 'go'. */ #define CREG_STAT_EDEFER 0x10000000 /* Excessive Defers */ #define CREG_STAT_CLOSS 0x08000000 /* Carrier Loss */ #define CREG_STAT_ERETRIES 0x04000000 /* More than 16 retries */ #define CREG_STAT_LCOLL 0x02000000 /* Late TX Collision */ #define CREG_STAT_FUFLOW 0x01000000 /* FIFO Underflow */ #define CREG_STAT_JERROR 0x00800000 /* Jabber Error */ #define CREG_STAT_BERROR 0x00400000 /* Babble Error */ #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */ #define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */ #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */ #define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */ #define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */ #define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */ #define CREG_STAT_RCCOFLOW 0x00001000 /* RX Coll-counter Overflow */ #define CREG_STAT_RUOFLOW 0x00000800 /* Runt Counter Overflow */ #define CREG_STAT_MCOFLOW 0x00000400 /* Missed Counter Overflow */ #define CREG_STAT_RXFOFLOW 0x00000200 /* RX FIFO Overflow */ #define CREG_STAT_RLCOLL 0x00000100 /* RX Late Collision */ #define CREG_STAT_FCOFLOW 0x00000080 /* Frame Counter Overflow */ #define CREG_STAT_CECOFLOW 0x00000040 /* CRC Error-counter Overflow*/ #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */ #define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */ #define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */ #define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */ #define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */ #define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */ #define CREG_STAT_ERRORS (CREG_STAT_EDEFER|CREG_STAT_CLOSS|CREG_STAT_ERETRIES| \ CREG_STAT_LCOLL|CREG_STAT_FUFLOW|CREG_STAT_JERROR| \ CREG_STAT_BERROR|CREG_STAT_CCOFLOW|CREG_STAT_TXDERROR| \ CREG_STAT_TXLERR|CREG_STAT_TXPERR|CREG_STAT_TXSERR| \ CREG_STAT_RCCOFLOW|CREG_STAT_RUOFLOW|CREG_STAT_MCOFLOW| \ CREG_STAT_RXFOFLOW|CREG_STAT_RLCOLL|CREG_STAT_FCOFLOW| \ CREG_STAT_CECOFLOW|CREG_STAT_RXDROP|CREG_STAT_RXSMALL| \ CREG_STAT_RXLERR|CREG_STAT_RXPERR|CREG_STAT_RXSERR) #define CREG_QMASK_COFLOW 0x00100000 /* CollCntr overflow */ #define CREG_QMASK_TXDERROR 0x00080000 /* TXD error */ #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */ #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */ #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */ #define CREG_QMASK_RXDROP 0x00000010 /* RX drop */ #define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */ #define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */ #define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */ #define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */ #define CREG_MMASK_EDEFER 0x10000000 /* Excess defer */ #define CREG_MMASK_CLOSS 0x08000000 /* Carrier loss */ #define CREG_MMASK_ERETRY 0x04000000 /* Excess retry */ #define CREG_MMASK_LCOLL 0x02000000 /* Late collision error */ #define CREG_MMASK_UFLOW 0x01000000 /* Underflow */ #define CREG_MMASK_JABBER 0x00800000 /* Jabber error */ #define CREG_MMASK_BABBLE 0x00400000 /* Babble error */ #define CREG_MMASK_OFLOW 0x00000800 /* Overflow */ #define CREG_MMASK_RXCOLL 0x00000400 /* RX Coll-Cntr overflow */ #define CREG_MMASK_RPKT 0x00000200 /* Runt pkt overflow */ #define CREG_MMASK_MPKT 0x00000100 /* Missed pkt overflow */ #define CREG_PIPG_TENAB 0x00000020 /* Enable Throttle */ #define CREG_PIPG_MMODE 0x00000010 /* Manual Mode */ #define CREG_PIPG_WMASK 0x0000000f /* SBUS Wait Mask */ /* Per-channel AMD 79C940 MACE registers. */ #define MREGS_RXFIFO 0x00UL /* Receive FIFO */ #define MREGS_TXFIFO 0x01UL /* Transmit FIFO */ #define MREGS_TXFCNTL 0x02UL /* Transmit Frame Control */ #define MREGS_TXFSTAT 0x03UL /* Transmit Frame Status */ #define MREGS_TXRCNT 0x04UL /* Transmit Retry Count */ #define MREGS_RXFCNTL 0x05UL /* Receive Frame Control */ #define MREGS_RXFSTAT 0x06UL /* Receive Frame Status */ #define MREGS_FFCNT 0x07UL /* FIFO Frame Count */ #define MREGS_IREG 0x08UL /* Interrupt Register */ #define MREGS_IMASK 0x09UL /* Interrupt Mask */ #define MREGS_POLL 0x0aUL /* POLL Register */ #define MREGS_BCONFIG 0x0bUL /* BIU Config */ #define MREGS_FCONFIG 0x0cUL /* FIFO Config */ #define MREGS_MCONFIG 0x0dUL /* MAC Config */ #define MREGS_PLSCONFIG 0x0eUL /* PLS Config */ #define MREGS_PHYCONFIG 0x0fUL /* PHY Config */ #define MREGS_CHIPID1 0x1
/*
 * arch/alpha/lib/ev6-csum_ipv6_magic.S
 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
 *
 * unsigned short csum_ipv6_magic(struct in6_addr *saddr,
 *                                struct in6_addr *daddr,
 *                                __u32 len,
 *                                unsigned short proto,
 *                                unsigned int csum);
 *