/* * Performance counter support for PPC970-family processors. * * Copyright 2008-2009 Paul Mackerras, IBM Corporation. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #include #include #include #include /* * Bits in event code for PPC970 */ #define PM_PMC_SH 12 /* PMC number (1-based) for direct events */ #define PM_PMC_MSK 0xf #define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */ #define PM_UNIT_MSK 0xf #define PM_SPCSEL_SH 6 #define PM_SPCSEL_MSK 3 #define PM_BYTE_SH 4 /* Byte number of event bus to use */ #define PM_BYTE_MSK 3 #define PM_PMCSEL_MSK 0xf /* Values in PM_UNIT field */ #define PM_NONE 0 #define PM_FPU 1 #define PM_VPU 2 #define PM_ISU 3 #define PM_IFU 4 #define PM_IDU 5 #define PM_STS 6 #define PM_LSU0 7 #define PM_LSU1U 8 #define PM_LSU1L 9 #define PM_LASTUNIT 9 /* * Bits in MMCR0 for PPC970 */ #define MMCR0_PMC1SEL_SH 8 #define MMCR0_PMC2SEL_SH 1 #define MMCR_PMCSEL_MSK 0x1f /* * Bits in MMCR1 for PPC970 */ #define MMCR1_TTM0SEL_SH 62 #define MMCR1_TTM1SEL_SH 59 #define MMCR1_TTM3SEL_SH 53 #define MMCR1_TTMSEL_MSK 3 #define MMCR1_TD_CP_DBG0SEL_SH 50 #define MMCR1_TD_CP_DBG1SEL_SH 48 #define MMCR1_TD_CP_DBG2SEL_SH 46 #define MMCR1_TD_CP_DBG3SEL_SH 44 #define MMCR1_PMC1_ADDER_SEL_SH 39 #define MMCR1_PMC2_ADDER_SEL_SH 38 #define MMCR1_PMC6_ADDER_SEL_SH 37 #define MMCR1_PMC5_ADDER_SEL_SH 36 #define MMCR1_PMC8_ADDER_SEL_SH 35 #define MMCR1_PMC7_ADDER_SEL_SH 34 #define MMCR1_PMC3_ADDER_SEL_SH 33 #define MMCR1_PMC4_ADDER_SEL_SH 32 #define MMCR1_PMC3SEL_SH 27 #define MMCR1_PMC4SEL_SH 22 #define MMCR1_PMC5SEL_SH 17 #define MMCR1_PMC6SEL_SH 12 #define MMCR1_PMC7SEL_SH 7 #define MMCR1_PMC8SEL_SH 2 static short mmcr1_adder_bits[8] = { MMCR1_PMC1_ADDER_SEL_SH, MMCR1_PMC2_ADDER_SEL_SH, MMCR1_PMC3_ADDER_SEL_SH, MMCR1_PMC4_ADDER_SEL_SH, MMCR1_PMC5_ADDER_SEL_SH, MMCR1_PMC6_ADDER_SEL_SH, MMCR1_PMC7_ADDER_SEL_SH, MMCR1_PMC8_ADDER_SEL_SH }; /* * Layout of constraint bits: * 6666555555555544444444443333333333222222222211111111110000000000 * 3210987654321098765432109876543210987654321098765432109876543210 * <><><>[ >[ >[ >< >< >< >< ><><><><><><><><> * SPT0T1 UC PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8 * * SP - SPCSEL constraint * 48-49: SPCSEL value 0x3_0000_0000_0000 * * T0 - TTM0 constraint * 46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000 * * T1 - TTM1 constraint * 44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000 * * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS * 43: UC3 error 0x0800_0000_0000 * 42: FPU|IFU|VPU events needed 0x0400_0000_0000 * 41: ISU events needed 0x0200_0000_0000 * 40: IDU|STS events needed 0x0100_0000_0000 * * PS1 * 39: PS1 error 0x0080_0000_0000 * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000 * * PS2 * 35: PS2 error 0x0008_0000_0000 * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000 * * B0 * 28-31: Byte 0 event source 0xf000_0000 * Encoding as for the event code * * B1, B2, B3 * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources * * P1 * 15: P1 error 0x8000 * 14-15: Count of events needing PMC1 * * P2..P8 * 0-13: Count of events needing PMC2..PMC8 */ static unsigned char direct_marked_event[8] = { (1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */ (1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */ (1<<3) | (1<<5), /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */ (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */ (1<<4) | (1<<5), /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */ (1<<3) | (1<<4) | (1<<5), /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */ (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */ (1<<4) /* PMC8: PM_MRK_LSU_FIN */ }; /* * Returns 1 if event counts things relating to marked instructions * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. */ static int p970_marked_instr_event(u64 event) { int pmc, psel, unit, byte, bit; unsigned int mask; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; psel = event & PM_PMCSEL_MSK; if (pmc) { if (direct_marked_event[pmc - 1] & (1 << psel)) return 1; if (psel == 0) /* add events */ bit = (pmc <= 4)? pmc - 1: 8 - pmc; else if (psel == 7 || psel == 13) /* decode events */ bit = 4; else return 0; } else bit = psel; byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; mask = 0; switch (unit) { case PM_VPU: mask = 0x4c; /* byte 0 bits 2,3,6 */ break; case PM_LSU0: /* byte 2 bits 0,2,3,4,6; all of byte 1 */ mask = 0x085dff00; break; case PM_LSU1L: mask = 0x50 << 24; /* byte 3 bits 4,6 */ break; } return (mask >> (byte * 8 + bit)) & 1; } /* Masks and values for using events from the various units */ static unsigned long unit_cons[PM_LASTUNIT+1][2] = { [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull }, [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull }, [PM_ISU] = { 0x080000000000ull, 0x020000000000ull }, [PM_IFU] = { 0xc80000000000ull, 0x840000000000ull }, [PM_IDU] = { 0x380000000000ull, 0x010000000000ull }, [PM_ST