From e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb Mon Sep 17 00:00:00 2001 From: Yang Zhang Date: Fri, 28 Aug 2015 09:58:54 +0800 Subject: Add qemu 2.4.0 Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang --- qemu/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c | 41 +++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 qemu/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c (limited to 'qemu/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c') diff --git a/qemu/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c b/qemu/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c new file mode 100644 index 000000000..61da3331f --- /dev/null +++ b/qemu/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c @@ -0,0 +1,41 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12348765; + + __asm + ("precrq_rs.ph.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("1 precrq_rs.ph.w wrong\n"); + + return -1; + } + + rs = 0x7fffC678; + rt = 0x865432A0; + result = 0x7fff8654; + + __asm + ("precrq_rs.ph.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((result != rd) || (((dsp >> 22) & 0x01) != 1)) { + printf("2 precrq_rs.ph.w wrong\n"); + + return -1; + } + + return 0; +} -- cgit 1.2.3-korg