From e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb Mon Sep 17 00:00:00 2001 From: Yang Zhang Date: Fri, 28 Aug 2015 09:58:54 +0800 Subject: Add qemu 2.4.0 Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang --- qemu/tests/tcg/mips/mips32-dsp/shll_s_w.c | 52 +++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 qemu/tests/tcg/mips/mips32-dsp/shll_s_w.c (limited to 'qemu/tests/tcg/mips/mips32-dsp/shll_s_w.c') diff --git a/qemu/tests/tcg/mips/mips32-dsp/shll_s_w.c b/qemu/tests/tcg/mips/mips32-dsp/shll_s_w.c new file mode 100644 index 000000000..628c75210 --- /dev/null +++ b/qemu/tests/tcg/mips/mips32-dsp/shll_s_w.c @@ -0,0 +1,52 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x82345678; + result = 0x82345678; + resultdsp = 0x00; + + __asm + ("shll_s.w %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rt = 0x82345678; + result = 0x80000000; + resultdsp = 0x01; + + __asm + ("shll_s.w %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rt = 0x12345678; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm + ("shll_s.w %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} -- cgit 1.2.3-korg