From 437fd90c0250dee670290f9b714253671a990160 Mon Sep 17 00:00:00 2001 From: José Pekkarinen Date: Wed, 18 May 2016 13:18:31 +0300 Subject: These changes are the raw update to qemu-2.6. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Collission happened in the following patches: migration: do cleanup operation after completion(738df5b9) Bug fix.(1750c932f86) kvmclock: add a new function to update env->tsc.(b52baab2) The code provided by the patches was already in the upstreamed version. Change-Id: I3cc11841a6a76ae20887b2e245710199e1ea7f9a Signed-off-by: José Pekkarinen --- qemu/target-lm32/cpu.c | 16 ++++++ qemu/target-lm32/cpu.h | 6 +-- qemu/target-lm32/gdbstub.c | 2 +- qemu/target-lm32/helper.c | 4 +- qemu/target-lm32/lm32-semi.c | 5 +- qemu/target-lm32/machine.c | 1 + qemu/target-lm32/op_helper.c | 2 +- qemu/target-lm32/translate.c | 116 +++++++++++++++---------------------------- 8 files changed, 63 insertions(+), 89 deletions(-) (limited to 'qemu/target-lm32') diff --git a/qemu/target-lm32/cpu.c b/qemu/target-lm32/cpu.c index c2b77c698..6e7e1b8e6 100644 --- a/qemu/target-lm32/cpu.c +++ b/qemu/target-lm32/cpu.c @@ -18,6 +18,8 @@ * */ +#include "qemu/osdep.h" +#include "qapi/error.h" #include "cpu.h" #include "qemu-common.h" @@ -131,6 +133,12 @@ static void lm32_cpu_reset(CPUState *s) tlb_flush(s, 1); } +static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->mach = bfd_mach_lm32; + info->print_insn = print_insn_lm32; +} + static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -275,6 +283,14 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_num_core_regs = 32 + 7; cc->gdb_stop_before_watchpoint = true; cc->debug_excp_handler = lm32_debug_excp_handler; + cc->disas_set_info = lm32_cpu_disas_set_info; + + /* + * Reason: lm32_cpu_initfn() calls cpu_exec_init(), which saves + * the object in cpus -> dangling pointer after final + * object_unref(). + */ + dc->cannot_destroy_with_object_finalize_yet = true; } static void lm32_register_cpu_type(const LM32CPUInfo *info) diff --git a/qemu/target-lm32/cpu.h b/qemu/target-lm32/cpu.h index 944777d05..f220fc0bb 100644 --- a/qemu/target-lm32/cpu.h +++ b/qemu/target-lm32/cpu.h @@ -24,17 +24,14 @@ #define CPUArchState struct CPULM32State -#include "config.h" #include "qemu-common.h" #include "exec/cpu-defs.h" struct CPULM32State; typedef struct CPULM32State CPULM32State; -#define ELF_MACHINE EM_LATTICEMICO32 - #define NB_MMU_MODES 1 #define TARGET_PAGE_BITS 12 -static inline int cpu_mmu_index(CPULM32State *env) +static inline int cpu_mmu_index(CPULM32State *env, bool ifetch) { return 0; } @@ -221,7 +218,6 @@ bool lm32_cpu_do_semihosting(CPUState *cs); #define cpu_list lm32_cpu_list #define cpu_exec cpu_lm32_exec -#define cpu_gen_code cpu_lm32_gen_code #define cpu_signal_handler cpu_lm32_signal_handler int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, diff --git a/qemu/target-lm32/gdbstub.c b/qemu/target-lm32/gdbstub.c index 4979a98d7..8ac1288bb 100644 --- a/qemu/target-lm32/gdbstub.c +++ b/qemu/target-lm32/gdbstub.c @@ -17,7 +17,7 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ -#include "config.h" +#include "qemu/osdep.h" #include "qemu-common.h" #include "exec/gdbstub.h" #include "hw/lm32/lm32_pic.h" diff --git a/qemu/target-lm32/helper.c b/qemu/target-lm32/helper.c index a88aa5ad1..655248f81 100644 --- a/qemu/target-lm32/helper.c +++ b/qemu/target-lm32/helper.c @@ -17,10 +17,12 @@ * License along with this library; if not, see . */ +#include "qemu/osdep.h" #include "cpu.h" #include "qemu/host-utils.h" #include "sysemu/sysemu.h" #include "exec/semihost.h" +#include "exec/log.h" int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx) @@ -81,7 +83,7 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, switch (wp_type) { case LM32_WP_DISABLED: - /* nothing to to */ + /* nothing to do */ break; case LM32_WP_READ: flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ; diff --git a/qemu/target-lm32/lm32-semi.c b/qemu/target-lm32/lm32-semi.c index ec6524f37..20f1a1cd4 100644 --- a/qemu/target-lm32/lm32-semi.c +++ b/qemu/target-lm32/lm32-semi.c @@ -10,10 +10,7 @@ * See the COPYING file in the top-level directory. */ -#include -#include -#include -#include +#include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/log.h" diff --git a/qemu/target-lm32/machine.c b/qemu/target-lm32/machine.c index 8327c6d97..91c943d19 100644 --- a/qemu/target-lm32/machine.c +++ b/qemu/target-lm32/machine.c @@ -1,3 +1,4 @@ +#include "qemu/osdep.h" #include "hw/hw.h" #include "hw/boards.h" diff --git a/qemu/target-lm32/op_helper.c b/qemu/target-lm32/op_helper.c index 61209c19b..b6759e022 100644 --- a/qemu/target-lm32/op_helper.c +++ b/qemu/target-lm32/op_helper.c @@ -1,4 +1,4 @@ -#include +#include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/qemu/target-lm32/translate.c b/qemu/target-lm32/translate.c index cf7042e3e..256a51f84 100644 --- a/qemu/target-lm32/translate.c +++ b/qemu/target-lm32/translate.c @@ -17,6 +17,7 @@ * License along with this library; if not, see . */ +#include "qemu/osdep.h" #include "cpu.h" #include "disas/disas.h" #include "exec/helper-proto.h" @@ -28,6 +29,7 @@ #include "exec/helper-gen.h" #include "trace-tcg.h" +#include "exec/log.h" #define DISAS_LM32 1 @@ -42,7 +44,7 @@ #define MEM_INDEX 0 -static TCGv_ptr cpu_env; +static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; static TCGv cpu_ie; @@ -1005,10 +1007,6 @@ static const DecoderInfo decinfo[] = { static inline void decode(DisasContext *dc, uint32_t ir) { - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { - tcg_gen_debug_insn_start(dc->pc); - } - dc->ir = ir; LOG_DIS("%8.8x\t", dc->ir); @@ -1036,32 +1034,13 @@ static inline void decode(DisasContext *dc, uint32_t ir) decinfo[dc->opcode](dc); } -static void check_breakpoint(CPULM32State *env, DisasContext *dc) -{ - CPUState *cs = CPU(lm32_env_get_cpu(env)); - CPUBreakpoint *bp; - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->pc) { - tcg_gen_movi_tl(cpu_pc, dc->pc); - t_gen_raise_exception(dc, EXCP_DEBUG); - dc->is_jmp = DISAS_UPDATE; - } - } - } -} - /* generate intermediate code for basic block 'tb'. */ -static inline -void gen_intermediate_code_internal(LM32CPU *cpu, - TranslationBlock *tb, bool search_pc) +void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) { + LM32CPU *cpu = lm32_env_get_cpu(env); CPUState *cs = CPU(cpu); - CPULM32State *env = &cpu->env; struct DisasContext ctx, *dc = &ctx; uint32_t pc_start; - int j, lj; uint32_t next_page_start; int num_insns; int max_insns; @@ -1083,41 +1062,41 @@ void gen_intermediate_code_internal(LM32CPU *cpu, } next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - lj = -1; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } gen_tb_start(tb); do { - check_breakpoint(env, dc); - - if (search_pc) { - j = tcg_op_buf_count(); - if (lj < j) { - lj++; - while (lj < j) { - tcg_ctx.gen_opc_instr_start[lj++] = 0; - } - } - tcg_ctx.gen_opc_pc[lj] = dc->pc; - tcg_ctx.gen_opc_instr_start[lj] = 1; - tcg_ctx.gen_opc_icount[lj] = num_insns; + tcg_gen_insn_start(dc->pc); + num_insns++; + + if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + tcg_gen_movi_tl(cpu_pc, dc->pc); + t_gen_raise_exception(dc, EXCP_DEBUG); + dc->is_jmp = DISAS_UPDATE; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->pc += 4; + break; } /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } decode(dc, cpu_ldl_code(env, dc->pc)); dc->pc += 4; - num_insns++; - } while (!dc->is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled @@ -1154,16 +1133,8 @@ void gen_intermediate_code_internal(LM32CPU *cpu, gen_tb_end(tb, num_insns); - if (search_pc) { - j = tcg_op_buf_count(); - lj++; - while (lj <= j) { - tcg_ctx.gen_opc_instr_start[lj++] = 0; - } - } else { - tb->size = dc->pc - pc_start; - tb->icount = num_insns; - } + tb->size = dc->pc - pc_start; + tb->icount = num_insns; #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { @@ -1175,16 +1146,6 @@ void gen_intermediate_code_internal(LM32CPU *cpu, #endif } -void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) -{ - gen_intermediate_code_internal(lm32_env_get_cpu(env), tb, false); -} - -void gen_intermediate_code_pc(CPULM32State *env, struct TranslationBlock *tb) -{ - gen_intermediate_code_internal(lm32_env_get_cpu(env), tb, true); -} - void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -1219,9 +1180,10 @@ void lm32_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, "\n\n"); } -void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos) +void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, + target_ulong *data) { - env->pc = tcg_ctx.gen_opc_pc[pc_pos]; + env->pc = data[0]; } void lm32_translate_init(void) @@ -1231,48 +1193,48 @@ void lm32_translate_init(void) cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { - cpu_R[i] = tcg_global_mem_new(TCG_AREG0, + cpu_R[i] = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, regs[i]), regnames[i]); } for (i = 0; i < ARRAY_SIZE(cpu_bp); i++) { - cpu_bp[i] = tcg_global_mem_new(TCG_AREG0, + cpu_bp[i] = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, bp[i]), regnames[32+i]); } for (i = 0; i < ARRAY_SIZE(cpu_wp); i++) { - cpu_wp[i] = tcg_global_mem_new(TCG_AREG0, + cpu_wp[i] = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, wp[i]), regnames[36+i]); } - cpu_pc = tcg_global_mem_new(TCG_AREG0, + cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, pc), "pc"); - cpu_ie = tcg_global_mem_new(TCG_AREG0, + cpu_ie = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, ie), "ie"); - cpu_icc = tcg_global_mem_new(TCG_AREG0, + cpu_icc = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, icc), "icc"); - cpu_dcc = tcg_global_mem_new(TCG_AREG0, + cpu_dcc = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, dcc), "dcc"); - cpu_cc = tcg_global_mem_new(TCG_AREG0, + cpu_cc = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, cc), "cc"); - cpu_cfg = tcg_global_mem_new(TCG_AREG0, + cpu_cfg = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, cfg), "cfg"); - cpu_eba = tcg_global_mem_new(TCG_AREG0, + cpu_eba = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, eba), "eba"); - cpu_dc = tcg_global_mem_new(TCG_AREG0, + cpu_dc = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, dc), "dc"); - cpu_deba = tcg_global_mem_new(TCG_AREG0, + cpu_deba = tcg_global_mem_new(cpu_env, offsetof(CPULM32State, deba), "deba"); } -- cgit 1.2.3-korg