From bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 Mon Sep 17 00:00:00 2001 From: RajithaY Date: Tue, 25 Apr 2017 03:31:15 -0700 Subject: Adding qemu as a submodule of KVMFORNFV This Patch includes the changes to add qemu as a submodule to kvmfornfv repo and make use of the updated latest qemu for the execution of all testcase Change-Id: I1280af507a857675c7f81d30c95255635667bdd7 Signed-off-by:RajithaY --- qemu/roms/u-boot/drivers/gpio/mxs_gpio.c | 116 ------------------------------- 1 file changed, 116 deletions(-) delete mode 100644 qemu/roms/u-boot/drivers/gpio/mxs_gpio.c (limited to 'qemu/roms/u-boot/drivers/gpio/mxs_gpio.c') diff --git a/qemu/roms/u-boot/drivers/gpio/mxs_gpio.c b/qemu/roms/u-boot/drivers/gpio/mxs_gpio.c deleted file mode 100644 index da0199b16..000000000 --- a/qemu/roms/u-boot/drivers/gpio/mxs_gpio.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Freescale i.MX28 GPIO control code - * - * Copyright (C) 2011 Marek Vasut - * on behalf of DENX Software Engineering GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_MX23) -#define PINCTRL_BANKS 3 -#define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10)) -#define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10)) -#define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10)) -#define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10)) -#define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10)) -#define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10)) -#elif defined(CONFIG_MX28) -#define PINCTRL_BANKS 5 -#define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10)) -#define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10)) -#define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10)) -#define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10)) -#define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10)) -#define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10)) -#else -#error "Please select CONFIG_MX23 or CONFIG_MX28" -#endif - -#define GPIO_INT_FALL_EDGE 0x0 -#define GPIO_INT_LOW_LEV 0x1 -#define GPIO_INT_RISE_EDGE 0x2 -#define GPIO_INT_HIGH_LEV 0x3 -#define GPIO_INT_LEV_MASK (1 << 0) -#define GPIO_INT_POL_MASK (1 << 1) - -void mxs_gpio_init(void) -{ - int i; - - for (i = 0; i < PINCTRL_BANKS; i++) { - writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i)); - writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i)); - /* Use SCT address here to clear the IRQSTAT bits */ - writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8); - } -} - -int gpio_get_value(unsigned gpio) -{ - uint32_t bank = PAD_BANK(gpio); - uint32_t offset = PINCTRL_DIN(bank); - struct mxs_register_32 *reg = - (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); - - return (readl(®->reg) >> PAD_PIN(gpio)) & 1; -} - -void gpio_set_value(unsigned gpio, int value) -{ - uint32_t bank = PAD_BANK(gpio); - uint32_t offset = PINCTRL_DOUT(bank); - struct mxs_register_32 *reg = - (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); - - if (value) - writel(1 << PAD_PIN(gpio), ®->reg_set); - else - writel(1 << PAD_PIN(gpio), ®->reg_clr); -} - -int gpio_direction_input(unsigned gpio) -{ - uint32_t bank = PAD_BANK(gpio); - uint32_t offset = PINCTRL_DOE(bank); - struct mxs_register_32 *reg = - (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); - - writel(1 << PAD_PIN(gpio), ®->reg_clr); - - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - uint32_t bank = PAD_BANK(gpio); - uint32_t offset = PINCTRL_DOE(bank); - struct mxs_register_32 *reg = - (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); - - gpio_set_value(gpio, value); - - writel(1 << PAD_PIN(gpio), ®->reg_set); - - return 0; -} - -int gpio_request(unsigned gpio, const char *label) -{ - if (PAD_BANK(gpio) >= PINCTRL_BANKS) - return -1; - - return 0; -} - -int gpio_free(unsigned gpio) -{ - return 0; -} -- cgit