From e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb Mon Sep 17 00:00:00 2001 From: Yang Zhang Date: Fri, 28 Aug 2015 09:58:54 +0800 Subject: Add qemu 2.4.0 Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang --- qemu/roms/u-boot/board/kup/common/flash.c | 499 +++++++++++++++++++++ qemu/roms/u-boot/board/kup/common/kup.c | 68 +++ qemu/roms/u-boot/board/kup/common/kup.h | 40 ++ .../u-boot/board/kup/common/load_sernum_ethaddr.c | 78 ++++ qemu/roms/u-boot/board/kup/common/pcmcia.c | 221 +++++++++ qemu/roms/u-boot/board/kup/kup4k/Makefile | 8 + qemu/roms/u-boot/board/kup/kup4k/kup4k.c | 287 ++++++++++++ qemu/roms/u-boot/board/kup/kup4k/u-boot.lds | 82 ++++ qemu/roms/u-boot/board/kup/kup4k/u-boot.lds.debug | 121 +++++ qemu/roms/u-boot/board/kup/kup4x/Makefile | 8 + qemu/roms/u-boot/board/kup/kup4x/kup4x.c | 185 ++++++++ qemu/roms/u-boot/board/kup/kup4x/u-boot.lds | 82 ++++ qemu/roms/u-boot/board/kup/kup4x/u-boot.lds.debug | 121 +++++ 13 files changed, 1800 insertions(+) create mode 100644 qemu/roms/u-boot/board/kup/common/flash.c create mode 100644 qemu/roms/u-boot/board/kup/common/kup.c create mode 100644 qemu/roms/u-boot/board/kup/common/kup.h create mode 100644 qemu/roms/u-boot/board/kup/common/load_sernum_ethaddr.c create mode 100644 qemu/roms/u-boot/board/kup/common/pcmcia.c create mode 100644 qemu/roms/u-boot/board/kup/kup4k/Makefile create mode 100644 qemu/roms/u-boot/board/kup/kup4k/kup4k.c create mode 100644 qemu/roms/u-boot/board/kup/kup4k/u-boot.lds create mode 100644 qemu/roms/u-boot/board/kup/kup4k/u-boot.lds.debug create mode 100644 qemu/roms/u-boot/board/kup/kup4x/Makefile create mode 100644 qemu/roms/u-boot/board/kup/kup4x/kup4x.c create mode 100644 qemu/roms/u-boot/board/kup/kup4x/u-boot.lds create mode 100644 qemu/roms/u-boot/board/kup/kup4x/u-boot.lds.debug (limited to 'qemu/roms/u-boot/board/kup') diff --git a/qemu/roms/u-boot/board/kup/common/flash.c b/qemu/roms/u-boot/board/kup/common/flash.c new file mode 100644 index 000000000..77c7b6ca8 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/common/flash.c @@ -0,0 +1,499 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#endif + +#define CONFIG_FLASH_16BIT + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CONFIG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + vu_short *s_addr=(vu_short*)addr; + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x0090; + + value = s_addr[0]; + value = value|(value<<16); + + switch (value) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = s_addr[1]; + value = value|(value<<16); + + switch (value) { + case FUJI_ID_29F800BA: + info->flash_id += FLASH_AM400T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + s_addr = (volatile unsigned short *)(info->start[i]); + info->protect[i] = s_addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + s_addr = (volatile unsigned short *)info->start[0]; + *s_addr = 0x00F0; /* reset bank */ + } + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect; + ulong start, now, last; +#ifdef CONFIG_FLASH_16BIT + vu_short *s_addr = (vu_short*)addr; +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } +/*#ifndef CONFIG_FLASH_16BIT + ulong type; + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return; + } +#endif*/ + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ +#ifdef CONFIG_FLASH_16BIT + vu_short *s_sect_addr = (vu_short*)(info->start[sect]); +#else + vu_long *sect_addr = (vu_long*)(info->start[sect]); +#endif + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + +#ifdef CONFIG_FLASH_16BIT + + /*printf("\ns_sect_addr=%x",s_sect_addr);*/ + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x0080; + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_sect_addr[0] = 0x0030; +#else + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + addr[0x5555] = 0x00800080; + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + sect_addr[0] = 0x00300030; +#endif + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + +#ifdef CONFIG_FLASH_16BIT + while ((s_sect_addr[0] & 0x0080) != 0x0080) { +#else + while ((sect_addr[0] & 0x00800080) != 0x00800080) { +#endif + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + } + } + + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; +#ifdef CONFIG_FLASH_16BIT + s_addr[0] = 0x00F0; /* reset bank */ +#else + addr[0] = 0x00F000F0; /* reset bank */ +#endif + + printf (" done\n"); + return 0; +} + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + +#ifdef CONFIG_FLASH_16BIT + vu_short high_data; + vu_short low_data; + vu_short *s_addr = (vu_short*)addr; +#endif + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + +#ifdef CONFIG_FLASH_16BIT + /* Write the 16 higher-bits */ + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + high_data = ((data>>16) & 0x0000ffff); + + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x00A0; + + *((vu_short *)dest) = high_data; + + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { + return (1); + } + } + + + /* Write the 16 lower-bits */ +#endif + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); +#ifdef CONFIG_FLASH_16BIT + dest += 0x2; + low_data = (data & 0x0000ffff); + + s_addr[0x5555] = 0x00AA; + s_addr[0x2AAA] = 0x0055; + s_addr[0x5555] = 0x00A0; + *((vu_short *)dest) = low_data; + +#else + addr[0x5555] = 0x00AA00AA; + addr[0x2AAA] = 0x00550055; + addr[0x5555] = 0x00A000A0; + *((vu_long *)dest) = data; +#endif + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + +#ifdef CONFIG_FLASH_16BIT + while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { +#else + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { +#endif + + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/qemu/roms/u-boot/board/kup/common/kup.c b/qemu/roms/u-boot/board/kup/common/kup.c new file mode 100644 index 000000000..03ab018c8 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/common/kup.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2004 + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "kup.h" +#include + + +int misc_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile sysconf8xx_t *siu = &immap->im_siu_conf; + + while (in_be32(&siu->sc_sipend) & 0x20000000) { + debug("waiting for 5V VCC\n"); + } + + /* RS232 / RS485 default is RS232 */ + clrbits_be16(&immap->im_ioport.iop_padat, PA_RS485); + clrbits_be16(&immap->im_ioport.iop_papar, PA_RS485); + clrbits_be16(&immap->im_ioport.iop_paodr, PA_RS485); + setbits_be16(&immap->im_ioport.iop_padir, PA_RS485); + + /* IO Reset min 1 msec */ + setbits_be16(&immap->im_ioport.iop_padat, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + clrbits_be16(&immap->im_ioport.iop_papar, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + clrbits_be16(&immap->im_ioport.iop_paodr, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + setbits_be16(&immap->im_ioport.iop_padir, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + udelay(1000); + clrbits_be16(&immap->im_ioport.iop_padat, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + return (0); +} + +#ifdef CONFIG_IDE_LED +void ide_led(uchar led, uchar status) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + /* We have one led for both pcmcia slots */ + if (status) + clrbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW); + else + setbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW); +} +#endif + +void poweron_key(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + clrbits_be16(&immap->im_ioport.iop_pcpar, PC_SWITCH1); + clrbits_be16(&immap->im_ioport.iop_pcdir, PC_SWITCH1); + + if (in_be16(&immap->im_ioport.iop_pcdat) & (PC_SWITCH1)) + setenv("key1", "off"); + else + setenv("key1", "on"); +} diff --git a/qemu/roms/u-boot/board/kup/common/kup.h b/qemu/roms/u-boot/board/kup/common/kup.h new file mode 100644 index 000000000..a1369aed6 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/common/kup.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2004 + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KUP_H +#define __KUP_H + +#define PA_8 0x0080 +#define PA_9 0x0040 +#define PA_10 0x0020 +#define PA_11 0x0010 +#define PA_12 0x0008 + +#define PB_14 0x00020000 +#define PB_15 0x00010000 +#define PB_16 0x00008000 +#define PB_17 0x00004000 + +#define PC_4 0x0800 +#define PC_5 0x0400 +#define PC_9 0x0040 + +#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ +#define PA_LED_YELLOW PA_8 +#define PA_RESET_IO_01 PA_9 /* Reset left IO */ +#define PA_RESET_IO_02 PA_10 /* Reset right IO */ +#define PB_PROG_IO_01 PB_15 /* Program left IO */ +#define PB_PROG_IO_02 PB_16 /* Program right IO */ +#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off */ +#define PB_LCD_PWM PB_17 /* PB 17 */ +#define PC_SWITCH1 PC_9 /* Reboot switch */ + + +extern void poweron_key(void); +extern void load_sernum_ethaddr(void); + +#endif /* __KUP_H */ diff --git a/qemu/roms/u-boot/board/kup/common/load_sernum_ethaddr.c b/qemu/roms/u-boot/board/kup/common/load_sernum_ethaddr.c new file mode 100644 index 000000000..20fe799cd --- /dev/null +++ b/qemu/roms/u-boot/board/kup/common/load_sernum_ethaddr.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +/*----------------------------------------------------------------------- + * Process Hardware Information Block: + * + * If we boot on a system fresh from factory, check if the Hardware + * Information Block exists and save the information it contains. + * + * The KUP Hardware Information Block is defined as + * follows: + * - located in first flash bank + * - starts at offset CONFIG_SYS_HWINFO_OFFSET + * - size CONFIG_SYS_HWINFO_SIZE + * + * Internal structure: + * - sequence of ASCII character lines + * - fields separated by + * - last field terminated by NUL character (0x00) + * + * Fields in Hardware Information Block: + * 1) Module Type + * 2) MAC Address + * 3) .... + */ + + +#define ETHADDR_TOKEN "ethaddr=" +#define LCD_TOKEN "lcd=" + +void load_sernum_ethaddr (void) +{ + unsigned char *hwi; + char *var; + unsigned char hwi_stack[CONFIG_SYS_HWINFO_SIZE]; + char *p; + + hwi = (unsigned char *) (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); + if (*((unsigned long *) hwi) != (unsigned long) CONFIG_SYS_HWINFO_MAGIC) { + printf ("HardwareInfo not found!\n"); + return; + } + memcpy (hwi_stack, hwi, CONFIG_SYS_HWINFO_SIZE); + + /* + ** ethaddr + */ + var = strstr ((char *)hwi_stack, ETHADDR_TOKEN); + if (var) { + var += sizeof (ETHADDR_TOKEN) - 1; + p = strchr (var, '\r'); + if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) { + *p = '\0'; + setenv ("ethaddr", var); + *p = '\r'; + } + } + /* + ** lcd + */ + var = strstr ((char *)hwi_stack, LCD_TOKEN); + if (var) { + var += sizeof (LCD_TOKEN) - 1; + p = strchr (var, '\r'); + if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) { + *p = '\0'; + setenv ("lcd", var); + *p = '\r'; + } + } +} diff --git a/qemu/roms/u-boot/board/kup/common/pcmcia.c b/qemu/roms/u-boot/board/kup/common/pcmcia.c new file mode 100644 index 000000000..61ba586e1 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/common/pcmcia.c @@ -0,0 +1,221 @@ +#include +#include +#include + +#undef CONFIG_PCMCIA + +#if defined(CONFIG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#ifdef CONFIG_PCMCIA + +#define PCMCIA_BOARD_MSG "KUP" + +#define KUP4K_PCMCIA_B_3V3 (0x00020000) + +int pcmcia_hardware_enable(int slot) +{ + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + volatile sysconf8xx_t *sysp; + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(slot); + pcmp->pcmc_per &= ~PCMCIA_MASK(slot); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(2500); + + /* + * Configure Port B pins for + * 3 Volts enable + */ + if (slot) { /* Slot A is built-in */ + cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; + cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; + /* remove all power */ + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ + } + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", + __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot); + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + if ((reg & mask) == mask) { + puts (" 5.0V card found: NOT SUPPORTED !!!\n"); + } else { + if(slot) + cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; + puts (" 3.3V card found: "); + } +#if 0 + /* VCC switch error flag, PCMCIA slot INPACK_ pin */ + cp->cp_pbdir &= ~(0x0020 | 0x0010); + cp->cp_pbpar &= ~(0x0020 | 0x0010); + udelay(500000); +#endif + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if defined(CONFIG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + volatile immap_t *immap; + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); + + /* remove all power */ + if (slot) + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; + + /* Configure PCMCIA General Control Register */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + + udelay(10000); + + return (0); +} +#endif + + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + volatile cpm8xx_t *cp; + volatile pcmconf8xx_t *pcmp; + u_long reg; + + debug ("voltage_set: " \ + PCMCIA_BOARD_MSG \ + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + if (!slot) /* Slot A is not configurable */ + return 0; + + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); + + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("PCMCIA power OFF\n"); + /* + * Configure Port B pins for + * 3 Volts enable + */ + cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; + cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; + /* remove all power */ + cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ + + switch(vcc) { + case 0: break; + case 33: + cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; + debug ("PCMCIA powered at 3.3V\n"); + break; + case 50: + debug ("PCMCIA: 5Volt vcc not supported\n"); + break; + default: + puts("PCMCIA: vcc not supported"); + break; + } + udelay(10000); + /* Checking supported voltages */ + + debug ("PIPR: 0x%x --> %s\n", + pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & (0x80000000 >> (slot << 4))) + ? "only 5 V --> NOT SUPPORTED" + : "can do 3.3V"); + + + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", + slot+'A'); + return (0); +} + +#endif /* CONFIG_PCMCIA */ diff --git a/qemu/roms/u-boot/board/kup/kup4k/Makefile b/qemu/roms/u-boot/board/kup/kup4k/Makefile new file mode 100644 index 000000000..c896fcd64 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/kup4k/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = kup4k.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o diff --git a/qemu/roms/u-boot/board/kup/kup4k/kup4k.c b/qemu/roms/u-boot/board/kup/kup4k/kup4k.c new file mode 100644 index 000000000..a4c199859 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/kup4k/kup4k.c @@ -0,0 +1,287 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "../common/kup.h" +#include + +static unsigned char swapbyte(unsigned char c); +static int read_diag(void); + +DECLARE_GLOBAL_DATA_PTR; + +/* ----------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ----------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + uchar rev,mod,tmp,pcf,ak_rev,ak_mod; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); + out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); + + /* + * Init ChipSelect #5 (S1D13768) + */ + out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5); + out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5); + + tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR)); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + if (read_diag()) + gd->flags &= ~GD_FLG_SILENT; + + printf("Board: KUP4K Rev %d.%d AK:",rev,mod); + /* + * TI Application report: Before using the IO as an input, + * a high must be written to the IO first + */ + pcf = 0xFF; + i2c_write(0x21, 0, 0 , &pcf, 1); + if (i2c_read(0x21, 0, 0, &pcf, 1)) { + puts("n/a\n"); + } else { + ak_rev = (pcf & 0xF8) >> 3; + ak_mod = (pcf & 0x07); + printf("%d.%d\n", ak_rev, ak_mod); + } + return 0; +} + +/* ----------------------------------------------------------------------- */ + + +phys_size_t initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size = 0; + uchar *latch, rev, tmp; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision + * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB + */ + out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); + out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); + + latch = (uchar *)0x90000200; + tmp = swapbyte(*latch); + rev = (tmp & 0xF8) >> 3; + + upmconfig(UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); + + out_be32(&memctl->memc_mar, 0x00000088); + /* no refresh yet */ + if(rev >= 7) { + out_be32(&memctl->memc_mamr, + CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE))); + } else { + out_be32(&memctl->memc_mamr, + CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE))); + } + + udelay(200); + + /* perform SDRAM initializsation sequence */ + + /* SDRAM bank 0 */ + out_be32(&memctl->memc_mcr, 0x80002105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 1 */ + out_be32(&memctl->memc_mcr, 0x80004105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 2 */ + out_be32(&memctl->memc_mcr, 0x80006105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ + udelay(1000); + + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); + udelay(1000); + if(rev >= 7) { + size = 32 * 3 * 1024 * 1024; + out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL); + out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL); + out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL); + out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL); + out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL); + out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL); + } else { + size = 16 * 3 * 1024 * 1024; + out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL); + out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL); + out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL); + out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL); + out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL); + out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL); + } + return (size); +} + +/* ----------------------------------------------------------------------- */ + + +int misc_init_r(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + +#ifdef CONFIG_IDE_LED + /* Configure PA8 as output port */ + setbits_be16(&immap->im_ioport.iop_padir, PA_8); + setbits_be16(&immap->im_ioport.iop_paodr, PA_8); + clrbits_be16(&immap->im_ioport.iop_papar, PA_8); + setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */ +#endif + load_sernum_ethaddr(); + setenv("hw","4k"); + poweron_key(); + return (0); +} + + +static int read_diag(void) +{ + int diag; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */ + clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ + setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */ + clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ + setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */ + udelay(500); + if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) { + clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */ + udelay(500); + if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4) + diag = 0; + else + diag = 1; + } else { + diag = 0; + } + clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */ + return (diag); +} + +static unsigned char swapbyte(unsigned char c) +{ + unsigned char result = 0; + int i = 0; + + for(i = 0; i < 8; ++i) { + result = result << 1; + result |= (c & 1); + c = c >> 1; + } + return result; +} + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/qemu/roms/u-boot/board/kup/kup4k/u-boot.lds b/qemu/roms/u-boot/board/kup/kup4k/u-boot.lds new file mode 100644 index 000000000..0eb2fba00 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/kup4k/u-boot.lds @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2000-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .text : + { + arch/powerpc/cpu/mpc8xx/start.o (.text*) + arch/powerpc/cpu/mpc8xx/traps.o (.text*) + + *(.text*) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + } + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/qemu/roms/u-boot/board/kup/kup4k/u-boot.lds.debug b/qemu/roms/u-boot/board/kup/kup4k/u-boot.lds.debug new file mode 100644 index 000000000..0ea27e875 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/kup4k/u-boot.lds.debug @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + arch/powerpc/cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + + . = env_offset; + common/env_embedded.o(.text) + + *(.text) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/qemu/roms/u-boot/board/kup/kup4x/Makefile b/qemu/roms/u-boot/board/kup/kup4x/Makefile new file mode 100644 index 000000000..6945943d0 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/kup4x/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = kup4x.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o diff --git a/qemu/roms/u-boot/board/kup/kup4x/kup4x.c b/qemu/roms/u-boot/board/kup/kup4x/kup4x.c new file mode 100644 index 000000000..0e51bd1c8 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/kup4x/kup4x.c @@ -0,0 +1,185 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "../common/kup.h" +#include + + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + + +/* + * Check Board Identity: + */ + +int checkboard(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + uchar latch, rev, mod; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + out_be32(&memctl->memc_or4, 0xFFFF8926); + out_be32(&memctl->memc_br4, 0x90000401); + + latch = in_8( (unsigned char *) LATCH_ADDR); + rev = (latch & 0xF8) >> 3; + mod = (latch & 0x03); + + printf("Board: KUP4X Rev %d.%d\n", rev, mod); + + return 0; +} + + +phys_size_t initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + upmconfig(UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); + + out_be32(&memctl->memc_mar, 0x00000088); + + out_be32(&memctl->memc_mamr, + CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initializsation sequence */ + + /* SDRAM bank 0 */ + out_be32(&memctl->memc_mcr, 0x80002105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 1 */ + out_be32(&memctl->memc_mcr, 0x80004105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 2 */ + out_be32(&memctl->memc_mcr, 0x80006105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 3 */ + out_be32(&memctl->memc_mcr, 0x8000C105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ + + udelay(1000); + /* 4 x 16 MB */ + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); + udelay(1000); + out_be32(&memctl->memc_or1, 0xFF000A00); + out_be32(&memctl->memc_br1, 0x00000081); + out_be32(&memctl->memc_or2, 0xFE000A00); + out_be32(&memctl->memc_br2, 0x01000081); + out_be32(&memctl->memc_or3, 0xFD000A00); + out_be32(&memctl->memc_br3, 0x02000081); + out_be32(&memctl->memc_or6, 0xFC000A00); + out_be32(&memctl->memc_br6, 0x03000081); + udelay(10000); + + return (4 * 16 * 1024 * 1024); +} + +int misc_init_r(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + +#ifdef CONFIG_IDE_LED + /* Configure PA8 as output port */ + setbits_be16(&immap->im_ioport.iop_padir, PA_8); + setbits_be16(&immap->im_ioport.iop_paodr, PA_8); + clrbits_be16(&immap->im_ioport.iop_papar, PA_8); + setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */ +#endif + load_sernum_ethaddr(); + setenv("hw", "4x"); + poweron_key(); + return 0; +} diff --git a/qemu/roms/u-boot/board/kup/kup4x/u-boot.lds b/qemu/roms/u-boot/board/kup/kup4x/u-boot.lds new file mode 100644 index 000000000..0eb2fba00 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/kup4x/u-boot.lds @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2000-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .text : + { + arch/powerpc/cpu/mpc8xx/start.o (.text*) + arch/powerpc/cpu/mpc8xx/traps.o (.text*) + + *(.text*) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + } + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/qemu/roms/u-boot/board/kup/kup4x/u-boot.lds.debug b/qemu/roms/u-boot/board/kup/kup4x/u-boot.lds.debug new file mode 100644 index 000000000..0ea27e875 --- /dev/null +++ b/qemu/roms/u-boot/board/kup/kup4x/u-boot.lds.debug @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + arch/powerpc/cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + + . = env_offset; + common/env_embedded.o(.text) + + *(.text) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + __bss_end = . ; + PROVIDE (end = .); +} -- cgit 1.2.3-korg