From e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb Mon Sep 17 00:00:00 2001 From: Yang Zhang Date: Fri, 28 Aug 2015 09:58:54 +0800 Subject: Add qemu 2.4.0 Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang --- .../u-boot/board/freescale/mpc8349itx/Makefile | 8 + qemu/roms/u-boot/board/freescale/mpc8349itx/README | 187 ++++++++++ .../u-boot/board/freescale/mpc8349itx/mpc8349itx.c | 388 +++++++++++++++++++++ qemu/roms/u-boot/board/freescale/mpc8349itx/pci.c | 105 ++++++ 4 files changed, 688 insertions(+) create mode 100644 qemu/roms/u-boot/board/freescale/mpc8349itx/Makefile create mode 100644 qemu/roms/u-boot/board/freescale/mpc8349itx/README create mode 100644 qemu/roms/u-boot/board/freescale/mpc8349itx/mpc8349itx.c create mode 100644 qemu/roms/u-boot/board/freescale/mpc8349itx/pci.c (limited to 'qemu/roms/u-boot/board/freescale/mpc8349itx') diff --git a/qemu/roms/u-boot/board/freescale/mpc8349itx/Makefile b/qemu/roms/u-boot/board/freescale/mpc8349itx/Makefile new file mode 100644 index 000000000..e9092adba --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/mpc8349itx/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += mpc8349itx.o +obj-$(CONFIG_PCI) += pci.o diff --git a/qemu/roms/u-boot/board/freescale/mpc8349itx/README b/qemu/roms/u-boot/board/freescale/mpc8349itx/README new file mode 100644 index 000000000..48bbd5035 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/mpc8349itx/README @@ -0,0 +1,187 @@ +Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards +--------------------------------------------------- + +1. Board Description + + The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring + the Freescale MPC8349E processor in a Mini-ITX form factor. + + The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: + + A) One 8MB on-board flash EEPROM chip, instead of two. + B) No SATA controller + C) No Compact Flash slot + D) No Mini-PCI slot + E) No Vitesse 7385 5-port Ethernet switch + F) No 4-port USB Type-A interface + +2. Board Switches and Jumpers + +2.0 Descriptions for all of the board jumpers can be found in the User + Guide. Of particular interest to U-Boot developers is jumper J22: + + Pos. Name Default Description + ----------------------------------------------------------------------- + A LGPL0 ON (0) HRCW source, bit 0 + B LGPL1 ON (0) HRCW source, bit 1 + C LGPL3 ON (0) HRCW source, bit 2 + D LGPL5 OFF (1) PCI_SYNC_OUT frequency + E BOOT1 ON (0) Flash EEPROM boot device + F PCI_M66EN ON (0) PCI 66MHz enable + G I2C-WP ON (0) I2C EEPROM write protection + H F_WP OFF (1) Flash EEPROM write protection + + Jumper J22.E is only for the ITX, and it decides the configuration + of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip + U4 is located at address FE000000 and flash chip U7 is at FE800000. + If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. + + For U-Boot development, J22.E can be used to switch back-and-forth + between two U-Boot images. + +3. Memory Map + +3.1. The memory map should look pretty much like this: + + 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) + 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) + 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) + 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) + 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) + 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) + 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) + 0xF001_0000 - 0xF001_FFFF Local bus expansion slot + 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) + 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) + +3.2 Flash EEPROM layout. + + On the ITX, jumper J22.E is used to determine which flash chips are + at which address. When J22.E is switched, addresses from FE000000 + to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. + + On the ITX, at the normal boot address (aka HIGHBOOT): + + FE00_0000 HRCW + FE70_0000 Alternative U-Boot image + FE80_0000 Alternative HRCW + FEF0_0000 U-Boot image + FEFF_FFFF End of flash + + On the ITX, at the low boot address (LOWBOOT) + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + FE80_0000 Alternative HRCW and U-Boot image + FEFF_FFFF End of flash + + On the ITX-GP, the only option is LOWBOOT and there is only one chip + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + F7FF_FFFF End of flash + +4. Definitions + +4.1 Explanation of NEW definitions in: + + include/configs/MPC8349ITX.h + + CONFIG_MPC83xx MPC83xx family + CONFIG_MPC8349 MPC8349 specific + CONFIG_MPC8349ITX MPC8349E-mITX + CONFIG_MPC8349ITXGP MPC8349E-mITX-GP + +5. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + + make MPC8349ITX_config + or: + make MPC8349ITXGP_config + or: + make MPC8349ITX_LOWBOOT_config + + make + +6. Downloading and Flashing Images + +6.1 Download via tftp: + + tftp $loadaddr + + where "" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.1 Reflash U-Boot Image using U-Boot + + setenv uboot + run tftpflash + + where "" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.2 Using the HRCW to switch between two different U-Boot images on the ITX + + Because the ITX has 16MB of flash, it is possible to keep two U-Boot + images in flash, and use the HRCW to specify which one is to be used + when the board boots. This trick is especially effective with a + hardware debugger that can override the HRCW, such as the BDI-2000. + + When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image + at address FE000000. When the BMS bit is 1, the ITX will boot the + image at address FEF00000. + + Therefore, just put a U-Boot image at both FE000000 and FEF00000 and + change the BMS bit whenever you want to boot the other image. + + Step-by-step instructions: + + 1) Build an ITX image to be loaded at FEF00000 + + make distclean + make MPC8349ITX_config + make + + 2) Take the u-boot.bin image and flash it at FEF00000. + + tftp $loadaddr u-boot.bin + protect off all + erase FEF00000 +$filesize + cp.b $loadaddr FEF00000 $filesize + + 3) Build an ITX image to be loaded at FE000000 + + make distclean + make MPC8349ITX_LOWBOOT_config + make + + 4) Take the u-boot.bin image and flash it at FE000000. + + tftp $loadaddr u-boot.bin + protect off FE000000 +$filesize + erase FE000000 +$filesize + cp.b $loadaddr FE000000 $filesize + + The HRCW in flash is currently set to boot the image at FE000000. + + If you have a hardware debugger, configure it to set the HRCW to + B460A000 04040000 if you want to boot the image at FEF00000, or set + it to B060A000 04040000 if you want to boot the image at FE000000. + + To change the HRCW in flash to boot the image at FEF00000, use these + U-Boot commands: + + cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 + mw.b 1020 b4 8 ; modify BMS bit + protect off FE000000 +10000 + erase FE000000 +10000 + cp.b 1000 FE000000 10000 + +7. Notes + 1) The console baudrate for MPC8349EITX is 115200bps. diff --git a/qemu/roms/u-boot/board/freescale/mpc8349itx/mpc8349itx.c b/qemu/roms/u-boot/board/freescale/mpc8349itx/mpc8349itx.c new file mode 100644 index 000000000..803d72280 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/mpc8349itx/mpc8349itx.c @@ -0,0 +1,388 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_PCI +#include +#include +#endif +#include +#include +#if defined(CONFIG_OF_LIBFDT) +#include +#endif + +#ifndef CONFIG_SPD_EEPROM +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + /* The size of RAM, in bytes */ + u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20; + u32 ddr_size_log2 = __ilog2(ddr_size); + + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; + +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + + /* Only one CS for DDR */ + im->ddr.cs_config[1] = 0; + im->ddr.cs_config[2] = 0; + im->ddr.cs_config[3] = 0; + + debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); + debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); + + debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); + debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); + + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ + im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; + im->ddr.sdram_mode = + (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); + im->ddr.sdram_interval = + (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << + SDRAM_INTERVAL_BSTOPRE_SHIFT); + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); + debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); + debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); + debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); + debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); + + return CONFIG_SYS_DDR_SIZE; +} +#endif + +#ifdef CONFIG_PCI +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxmitx_config_table[] = { + { + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + PCI_ANY_ID, + 0x0f, + PCI_ANY_ID, + pci_cfgfunc_config_device, + { + PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} + }, + {} +} +#endif + +volatile static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxmitx_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxmitx_config_table, +#endif + } +}; +#endif /* CONFIG_PCI */ + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = 0; +#ifdef CONFIG_DDR_ECC + volatile ddr83xx_t *ddr = &im->ddr; +#endif + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; +#ifdef CONFIG_SPD_EEPROM + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#ifdef CONFIG_DDR_ECC + if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) + /* Unlike every other board, on the 83xx spd_sdram() returns + megabytes instead of just bytes. That's why we need to + multiple by 1MB when calling ddr_enable_ecc(). */ + ddr_enable_ecc(msize * 1048576); +#endif + + /* return total bus RAM size(bytes) */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ +#ifdef CONFIG_MPC8349ITX + puts("Board: Freescale MPC8349E-mITX\n"); +#else + puts("Board: Freescale MPC8349E-mITX-GP\n"); +#endif + + return 0; +} + +/* + * Implement a work-around for a hardware problem with compact + * flash. + * + * Program the UPM if compact flash is enabled. + */ +int misc_init_f(void) +{ +#ifdef CONFIG_VSC7385_ENET + volatile u32 *vsc7385_cpuctrl; + + /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up + default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That + means it is 0 when the IRQ is not active. This makes the wire-AND + logic always assert IRQ7 to CPU even if there is no request from the + switch. Since the compact flash and the switch share the same IRQ, + the Linux kernel will think that the compact flash is requesting irq + and get stuck when it tries to clear the IRQ. Thus we need to set + the L2_IRQ0 and L2_IRQ1 to active low. + + The following code sets the L1_IRQ and L2_IRQ polarity to active low. + Without this code, compact flash will not work in Linux because + unlike U-Boot, Linux uses the IRQ, so this code is necessary if we + don't enable compact flash for U-Boot. + */ + + vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0); + *vsc7385_cpuctrl |= 0x0c; +#endif + +#ifdef CONFIG_COMPACT_FLASH + /* UPM Table Configuration Code */ + static uint UPMATable[] = { + 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, + 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, + 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 + }; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); + + /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, + GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 + */ + immap->im_lbc.mamr = 0x08404440; + + upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); + + puts("UPMA: Configured for compact flash\n"); +#endif + + return 0; +} + +/* + * Miscellaneous late-boot configurations + * + * Make sure the EEPROM has the HRCW correctly programmed. + * Make sure the RTC is correctly programmed. + * + * The MPC8349E-mITX can be configured to load the HRCW from + * EEPROM instead of flash. This is controlled via jumpers + * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all + * jumpered), but if they're set to 001 or 010, then the HRCW is + * read from the "I2C EEPROM". + * + * This function makes sure that the I2C EEPROM is programmed + * correctly. + * + * If a VSC7385 microcode image is present, then upload it. + */ +int misc_init_r(void) +{ + int rc = 0; + +#if defined(CONFIG_SYS_I2C) + unsigned int orig_bus = i2c_get_bus_num(); + u8 i2c_data; + +#ifdef CONFIG_SYS_I2C_RTC_ADDR + u8 ds1339_data[17]; +#endif + +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR + static u8 eeprom_data[] = /* HRCW data */ + { + 0xAA, 0x55, 0xAA, /* Preamble */ + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ + (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF, + (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF, + (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF, + CONFIG_SYS_HRCW_LOW & 0xFF, + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ + (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF, + (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF, + (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF, + CONFIG_SYS_HRCW_HIGH & 0xFF + }; + + u8 data[sizeof(eeprom_data)]; +#endif + + printf("Board revision: "); + i2c_set_bus_num(1); + if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); + else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); + else { + printf("Unknown\n"); + rc = 1; + } + +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR + i2c_set_bus_num(0); + + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { + if (memcmp(data, eeprom_data, sizeof(data)) != 0) { + if (i2c_write + (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data, + sizeof(eeprom_data)) != 0) { + puts("Failure writing the HRCW to EEPROM via I2C.\n"); + rc = 1; + } + } + } else { + puts("Failure reading the HRCW from EEPROM via I2C.\n"); + rc = 1; + } +#endif + +#ifdef CONFIG_SYS_I2C_RTC_ADDR + i2c_set_bus_num(1); + + if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) + == 0) { + + /* Work-around for MPC8349E-mITX bug #13601. + If the RTC does not contain valid register values, the DS1339 + Linux driver will not work. + */ + + /* Make sure status register bits 6-2 are zero */ + ds1339_data[0x0f] &= ~0x7c; + + /* Check for a valid day register value */ + ds1339_data[0x03] &= ~0xf8; + if (ds1339_data[0x03] == 0) { + ds1339_data[0x03] = 1; + } + + /* Check for a valid date register value */ + ds1339_data[0x04] &= ~0xc0; + if ((ds1339_data[0x04] == 0) || + ((ds1339_data[0x04] & 0x0f) > 9) || + (ds1339_data[0x04] >= 0x32)) { + ds1339_data[0x04] = 1; + } + + /* Check for a valid month register value */ + ds1339_data[0x05] &= ~0x60; + + if ((ds1339_data[0x05] == 0) || + ((ds1339_data[0x05] & 0x0f) > 9) || + ((ds1339_data[0x05] >= 0x13) + && (ds1339_data[0x05] <= 0x19))) { + ds1339_data[0x05] = 1; + } + + /* Enable Oscillator and rate select */ + ds1339_data[0x0e] = 0x1c; + + /* Work-around for MPC8349E-mITX bug #13330. + Ensure that the RTC control register contains the value 0x1c. + This affects SATA performance. + */ + + if (i2c_write + (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, + sizeof(ds1339_data))) { + puts("Failure writing to the RTC via I2C.\n"); + rc = 1; + } + } else { + puts("Failure reading from the RTC via I2C.\n"); + rc = 1; + } +#endif + + i2c_set_bus_num(orig_bus); +#endif + +#ifdef CONFIG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, + CONFIG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif diff --git a/qemu/roms/u-boot/board/freescale/mpc8349itx/pci.c b/qemu/roms/u-boot/board/freescale/mpc8349itx/pci.c new file mode 100644 index 000000000..afc9df092 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/mpc8349itx/pci.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, +}; + +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { + { + bus_start: CONFIG_SYS_PCI2_MEM_BASE, + phys_start: CONFIG_SYS_PCI2_MEM_PHYS, + size: CONFIG_SYS_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI2_IO_BASE, + phys_start: CONFIG_SYS_PCI2_IO_PHYS, + size: CONFIG_SYS_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI2_MMIO_BASE, + phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, + size: CONFIG_SYS_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM + }, +}; +#endif + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif + u8 reg8; + +#if defined(CONFIG_SYS_I2C) + i2c_set_bus_num(1); + /* Read the PCI_M66EN jumper setting */ + if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || + (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { + if (reg8 & I2C_8574_PCI66) + clk->occr = 0xff000000; /* 66 MHz PCI */ + else + clk->occr = 0xff600001; /* 33 MHz PCI */ + } else { + clk->occr = 0xff600001; /* 33 MHz PCI */ + } +#else + clk->occr = 0xff000000; /* 66 MHz PCI */ +#endif + udelay(2000); + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; + + udelay(2000); + +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg); +#else + mpc83xx_pci_init(2, reg); +#endif +} -- cgit 1.2.3-korg