From e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb Mon Sep 17 00:00:00 2001
From: Yang Zhang <yang.z.zhang@intel.com>
Date: Fri, 28 Aug 2015 09:58:54 +0800
Subject: Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
---
 .../u-boot/board/compulab/trimslice/trimslice.c    | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 qemu/roms/u-boot/board/compulab/trimslice/trimslice.c

(limited to 'qemu/roms/u-boot/board/compulab/trimslice/trimslice.c')

diff --git a/qemu/roms/u-boot/board/compulab/trimslice/trimslice.c b/qemu/roms/u-boot/board/compulab/trimslice/trimslice.c
new file mode 100644
index 000000000..723293fef
--- /dev/null
+++ b/qemu/roms/u-boot/board/compulab/trimslice/trimslice.c
@@ -0,0 +1,42 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+void pin_mux_usb(void)
+{
+	/*
+	 * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
+	 * in the current device tree.
+	 */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
+}
+
+void pin_mux_spi(void)
+{
+	funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+	funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
+	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+
+	/* For CD GPIO PP1 */
+	pinmux_tristate_disable(PMUX_PINGRP_DAP3);
+}
-- 
cgit