From bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 Mon Sep 17 00:00:00 2001 From: RajithaY Date: Tue, 25 Apr 2017 03:31:15 -0700 Subject: Adding qemu as a submodule of KVMFORNFV This Patch includes the changes to add qemu as a submodule to kvmfornfv repo and make use of the updated latest qemu for the execution of all testcase Change-Id: I1280af507a857675c7f81d30c95255635667bdd7 Signed-off-by:RajithaY --- qemu/roms/u-boot/board/amcc/luan/init.S | 59 --------------------------------- 1 file changed, 59 deletions(-) delete mode 100644 qemu/roms/u-boot/board/amcc/luan/init.S (limited to 'qemu/roms/u-boot/board/amcc/luan/init.S') diff --git a/qemu/roms/u-boot/board/amcc/luan/init.S b/qemu/roms/u-boot/board/amcc/luan/init.S deleted file mode 100644 index 0f4a78e1e..000000000 --- a/qemu/roms/u-boot/board/amcc/luan/init.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G) - - tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG) - tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG) - tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG) - tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG) - tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - /* internal ram (l2 cache) */ - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I) - - /* peripherals at f0000000 */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG) - - /* PCI */ - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG) - tlbtab_end -- cgit