From e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb Mon Sep 17 00:00:00 2001 From: Yang Zhang Date: Fri, 28 Aug 2015 09:58:54 +0800 Subject: Add qemu 2.4.0 Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang --- .../arch/nds32/include/asm/arch-ag101/ag101.h | 91 ++++ .../arch/nds32/include/asm/arch-ag102/ag102.h | 85 ++++ qemu/roms/u-boot/arch/nds32/include/asm/bitops.h | 186 ++++++++ .../roms/u-boot/arch/nds32/include/asm/byteorder.h | 36 ++ qemu/roms/u-boot/arch/nds32/include/asm/cache.h | 49 ++ qemu/roms/u-boot/arch/nds32/include/asm/config.h | 14 + .../u-boot/arch/nds32/include/asm/dma-mapping.h | 33 ++ qemu/roms/u-boot/arch/nds32/include/asm/errno.h | 1 + .../u-boot/arch/nds32/include/asm/global_data.h | 34 ++ qemu/roms/u-boot/arch/nds32/include/asm/io.h | 497 +++++++++++++++++++++ qemu/roms/u-boot/arch/nds32/include/asm/linkage.h | 12 + .../u-boot/arch/nds32/include/asm/mach-types.h | 57 +++ qemu/roms/u-boot/arch/nds32/include/asm/macro.h | 80 ++++ .../u-boot/arch/nds32/include/asm/posix_types.h | 84 ++++ .../roms/u-boot/arch/nds32/include/asm/processor.h | 25 ++ qemu/roms/u-boot/arch/nds32/include/asm/ptrace.h | 90 ++++ qemu/roms/u-boot/arch/nds32/include/asm/sections.h | 11 + qemu/roms/u-boot/arch/nds32/include/asm/setup.h | 190 ++++++++ qemu/roms/u-boot/arch/nds32/include/asm/string.h | 57 +++ qemu/roms/u-boot/arch/nds32/include/asm/system.h | 72 +++ qemu/roms/u-boot/arch/nds32/include/asm/types.h | 63 +++ .../u-boot/arch/nds32/include/asm/u-boot-nds32.h | 30 ++ qemu/roms/u-boot/arch/nds32/include/asm/u-boot.h | 44 ++ .../roms/u-boot/arch/nds32/include/asm/unaligned.h | 1 + 24 files changed, 1842 insertions(+) create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/arch-ag101/ag101.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/arch-ag102/ag102.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/bitops.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/byteorder.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/cache.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/config.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/dma-mapping.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/errno.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/global_data.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/io.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/linkage.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/mach-types.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/macro.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/posix_types.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/processor.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/ptrace.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/sections.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/setup.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/string.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/system.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/types.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/u-boot-nds32.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/u-boot.h create mode 100644 qemu/roms/u-boot/arch/nds32/include/asm/unaligned.h (limited to 'qemu/roms/u-boot/arch/nds32/include') diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/arch-ag101/ag101.h b/qemu/roms/u-boot/arch/nds32/include/asm/arch-ag101/ag101.h new file mode 100644 index 000000000..490f28b62 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/arch-ag101/ag101.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Nobuhiro Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AG101_H +#define __AG101_H + +/* Hardware register bases */ + +/* AHB Controller */ +#define CONFIG_FTAHBC020S_BASE 0x90100000 +/* Static Memory Controller (SRAM) */ +#define CONFIG_FTSMC020_BASE 0x90200000 +/* FTSDMC021 SDRAM Controller */ +#define CONFIG_FTSDMC021_BASE 0x90300000 +/* DMA Controller */ +#define CONFIG_FTDMAC020_BASE 0x90400000 +/* AHB-to-APB Bridge */ +#define CONFIG_FTAPBBRG020S_01_BASE 0x90500000 +/* LCD Controller */ +#define CONFIG_FTLCDC100_BASE 0x90600000 +/* Reserved */ +#define CONFIG_RESERVED_01_BASE 0x90700000 +/* Reserved */ +#define CONFIG_RESERVED_02_BASE 0x90800000 +/* Ethernet */ +#define CONFIG_FTMAC100_BASE 0x90900000 +/* External USB host */ +#define CONFIG_EXT_USB_HOST_BASE 0x90A00000 +/* USB Device */ +#define CONFIG_USB_DEV_BASE 0x90B00000 +/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */ +#define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000 +/* Reserved */ +#define CONFIG_RESERVED_03_BASE 0x90D00000 +/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */ +#define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000 +/* External AHB slave1 (LCD) */ +#define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000 +/* External AHB slave2 (FUSBH200) */ +#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000 + +/* DEBUG LED */ +#define CONFIG_DEBUG_LED 0x902FFFFC + +/* APB Device definitions */ + +/* Power Management Unit */ +#define CONFIG_FTPMU010_BASE 0x98100000 +/* BT UART 2/IrDA (UART 01 in Linux) */ +#define CONFIG_FTUART010_01_BASE 0x98300000 +/* Counter/Timers */ +#define CONFIG_FTTMR010_BASE 0x98400000 +/* Watchdog Timer */ +#define CONFIG_FTWDT010_BASE 0x98500000 +/* Real Time Clock */ +#define CONFIG_FTRTC010_BASE 0x98600000 +/* GPIO */ +#define CONFIG_FTGPIO010_BASE 0x98700000 +/* Interrupt Controller */ +#define CONFIG_FTINTC010_BASE 0x98800000 +/* I2C */ +#define CONFIG_FTIIC010_BASE 0x98A00000 +/* Reserved */ +#define CONFIG_RESERVED_04_BASE 0x98C00000 +/* Compat Flash Controller */ +#define CONFIG_FTCFC010_BASE 0x98D00000 +/* SD Controller */ +#define CONFIG_FTSDC010_BASE 0x98E00000 + +/* Synchronous Serial Port Controller (SSP) I2S/AC97 */ +#define CONFIG_FTSSP010_02_BASE 0x99400000 +/* ST UART ? SSP 02 (UART 02 in Linux) */ +#define CONFIG_FTUART010_02_BASE 0x99600000 + +/* The following address was not defined in Linux */ + +/* FF UART 3 */ +#define CONFIG_FTUART010_03_BASE 0x98200000 +/* Synchronous Serial Port Controller (SSP) 01 */ +#define CONFIG_FTSSP010_01_BASE 0x98B00000 +/* IrDA */ +#define CONFIG_IRDA_BASE 0x98900000 +/* PWM - Pulse Width Modulator Controller */ +#define CONFIG_PMW_BASE 0x99100000 + +#endif /* __AG101_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/arch-ag102/ag102.h b/qemu/roms/u-boot/arch/nds32/include/asm/arch-ag102/ag102.h new file mode 100644 index 000000000..c5ee3d949 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/arch-ag102/ag102.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AG102_H +#define __AG102_H + +/* + * Hardware register bases + */ + +/* PCI Controller */ +#define CONFIG_FTPCI100_BASE 0x90000000 +/* LPC Controller */ +#define CONFIG_LPC_IO_BASE 0x90100000 +/* LPC Controller */ +#define CONFIG_LPC_BASE 0x90200000 + +/* NDS32 Data Local Memory 01 */ +#define CONFIG_NDS_DLM1_BASE 0x90300000 +/* NDS32 Data Local Memory 02 */ +#define CONFIG_NDS_DLM2_BASE 0x90400000 + +/* Synopsys DWC DDR2/1 Controller */ +#define CONFIG_DWCDDR21MCTL_BASE 0x90500000 +/* DMA Controller */ +#define CONFIG_FTDMAC020_BASE 0x90600000 +/* FTIDE020_S IDE (ATA) Controller */ +#define CONFIG_FTIDE020S_BASE 0x90700000 +/* USB OTG Controller */ +#define CONFIG_FZOTG266HD0A_BASE 0x90800000 +/* Andes L2 Cache Controller */ +#define CONFIG_NCEL2C100_BASE 0x90900000 +/* XGI XG22 GPU */ +#define CONFIG_XGI_XG22_BASE 0x90A00000 +/* GMAC Ethernet Controller */ +#define CONFIG_FTGMAC100_BASE 0x90B00000 +/* AHB Controller */ +#define CONFIG_FTAHBC020S_BASE 0x90C00000 +/* AHB-to-APB Bridge Controller */ +#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 +/* External AHB2AHB Controller */ +#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 +/* Andes Multi-core Interrupt Controller */ +#define CONFIG_NCEMIC100_BASE 0x90F00000 + +/* + * APB Device definitions + */ +/* Compat Flash Controller */ +#define CONFIG_FTCFC010_BASE 0x94000000 +/* APB - SSP (SPI) (without AC97) Controller */ +#define CONFIG_FTSSP010_01_BASE 0x94100000 +/* UART1 - APB STUART Controller (UART0 in Linux) */ +#define CONFIG_FTUART010_01_BASE 0x94200000 +/* FTSDC010 SD Controller */ +#define CONFIG_FTSDC010_BASE 0x94400000 +/* APB - SSP with HDA/AC97 Controller */ +#define CONFIG_FTSSP010_02_BASE 0x94500000 +/* UART2 - APB STUART Controller (UART1 in Linux) */ +#define CONFIG_FTUART010_02_BASE 0x94600000 +/* PCU Controller */ +#define CONFIG_ANDES_PCU_BASE 0x94800000 +/* FTTMR010 Timer */ +#define CONFIG_FTTMR010_BASE 0x94900000 +/* Watch Dog Controller */ +#define CONFIG_FTWDT010_BASE 0x94A00000 +/* FTRTC010 Real Time Clock */ +#define CONFIG_FTRTC010_BASE 0x98B00000 +/* GPIO Controller */ +#define CONFIG_FTGPIO010_BASE 0x94C00000 +/* I2C Controller */ +#define CONFIG_FTIIC010_BASE 0x94E00000 +/* PWM - Pulse Width Modulator Controller */ +#define CONFIG_FTPWM010_BASE 0x94F00000 + +/* Debug LED */ +#define CONFIG_DEBUG_LED 0x902FFFFC +/* Power Management Unit */ +#define CONFIG_FTPMU010_BASE 0x98100000 + +#endif /* __AG102_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/bitops.h b/qemu/roms/u-boot/arch/nds32/include/asm/bitops.h new file mode 100644 index 000000000..f1aa9a356 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/bitops.h @@ -0,0 +1,186 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + * + * Please note that the code in this file should never be included + * from user space. Many of these are not implemented in assembler + * since they would be too costly. Also, they require priviledged + * instructions (which are not available from user mode) to ensure + * that they are atomic. + */ + +#ifndef __ASM_NDS_BITOPS_H +#define __ASM_NDS_BITOPS_H + +#ifdef __KERNEL__ + +#include + +#define smp_mb__before_clear_bit() do { } while (0) +#define smp_mb__after_clear_bit() do { } while (0) + +/* + * Function prototypes to keep gcc -Wall happy. + */ +extern void set_bit(int nr, void *addr); + +static inline void __set_bit(int nr, void *addr) +{ + int *a = (int *)addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +extern void clear_bit(int nr, void *addr); + +static inline void __clear_bit(int nr, void *addr) +{ + int *a = (int *)addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a &= ~mask; + local_irq_restore(flags); +} + +extern void change_bit(int nr, void *addr); + +static inline void __change_bit(int nr, void *addr) +{ + int mask; + unsigned long *ADDR = (unsigned long *)addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + *ADDR ^= mask; +} + +extern int test_and_set_bit(int nr, void *addr); + +static inline int __test_and_set_bit(int nr, void *addr) +{ + int mask, retval; + unsigned int *a = (unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + return retval; +} + +extern int test_and_clear_bit(int nr, void *addr); + +static inline int __test_and_clear_bit(int nr, void *addr) +{ + int mask, retval; + unsigned int *a = (unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + return retval; +} + +extern int test_and_change_bit(int nr, void *addr); + +static inline int __test_and_change_bit(int nr, void *addr) +{ + int mask, retval; + unsigned int *a = (unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + return retval; +} + +extern int find_first_zero_bit(void *addr, unsigned size); +extern int find_next_zero_bit(void *addr, int size, int offset); + +/* + * This routine doesn't need to be atomic. + */ +static inline int test_bit(int nr, const void *addr) +{ + return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); +} + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) +{ + int k; + + word = ~word; + k = 31; + if (word & 0x0000ffff) { + k -= 16; word <<= 16; + } + if (word & 0x00ff0000) { + k -= 8; word <<= 8; + } + if (word & 0x0f000000) { + k -= 4; word <<= 4; + } + if (word & 0x30000000) { + k -= 2; word <<= 2; + } + if (word & 0x40000000) + k -= 1; + + return k; +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +/* + * redefined in include/linux/bitops.h + * #define ffs(x) generic_ffs(x) + */ + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#define ext2_set_bit test_and_set_bit +#define ext2_clear_bit test_and_clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr, addr) test_and_set_bit(nr, addr) +#define minix_set_bit(nr, addr) set_bit(nr, addr) +#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr) +#define minix_test_bit(nr, addr) test_bit(nr, addr) +#define minix_find_first_zero_bit(addr, size) find_first_zero_bit(addr, size) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_NDS_BITOPS_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/byteorder.h b/qemu/roms/u-boot/arch/nds32/include/asm/byteorder.h new file mode 100644 index 000000000..39fd9eddf --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/byteorder.h @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ + +#ifndef __ASM_NDS_BYTEORDER_H +#define __ASM_NDS_BYTEORDER_H + +#include + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __NDSEB__ +#include +#else +#include +#endif + +#endif diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/cache.h b/qemu/roms/u-boot/arch/nds32/include/asm/cache.h new file mode 100644 index 000000000..9038821b4 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/cache.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +/* cache */ +int icache_status(void); +void icache_enable(void); +void icache_disable(void); +int dcache_status(void); +void dcache_enable(void); +void dcache_disable(void); + +#define DEFINE_GET_SYS_REG(reg) \ + static inline unsigned long GET_##reg(void) \ + { \ + unsigned long val; \ + __asm__ volatile ( \ + "mfsr %0, $"#reg : "=&r" (val) : : "memory" \ + ); \ + return val; \ + } + +enum cache_t {ICACHE, DCACHE}; +DEFINE_GET_SYS_REG(ICM_CFG); +DEFINE_GET_SYS_REG(DCM_CFG); +#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ +#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) +#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ +#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) + +/* + * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + +#endif /* _ASM_CACHE_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/config.h b/qemu/roms/u-boot/arch/nds32/include/asm/config.h new file mode 100644 index 000000000..3d1886e35 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/config.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#define CONFIG_NEEDS_MANUAL_RELOC + +#endif diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/dma-mapping.h b/qemu/roms/u-boot/arch/nds32/include/asm/dma-mapping.h new file mode 100644 index 000000000..25e5a1b6e --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/dma-mapping.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2013 Andes Technology Corporation + * Ken Kuo, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_NDS_DMA_MAPPING_H +#define __ASM_NDS_DMA_MAPPING_H + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, +}; + +static void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + return (void *)*handle; +} + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + return (unsigned long)vaddr; +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ +} + +#endif /* __ASM_NDS_DMA_MAPPING_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/errno.h b/qemu/roms/u-boot/arch/nds32/include/asm/errno.h new file mode 100644 index 000000000..4c82b503d --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/errno.h @@ -0,0 +1 @@ +#include diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/global_data.h b/qemu/roms/u-boot/arch/nds32/include/asm/global_data.h new file mode 100644 index 000000000..1f5ec1ff1 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/global_data.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - so far no one uses the macros defined in this head file. + **************************************************************/ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +/* Architecture-specific global data */ +struct arch_global_data { +}; + +#include + +#ifdef CONFIG_GLOBAL_DATA_NOT_REG10 +extern volatile gd_t g_gd; +#define DECLARE_GLOBAL_DATA_PTR static volatile gd_t *gd = &g_gd +#else +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("$r10") +#endif + +#endif /* __ASM_GBL_DATA_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/io.h b/qemu/roms/u-boot/arch/nds32/include/asm/io.h new file mode 100644 index 000000000..04708e935 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/io.h @@ -0,0 +1,497 @@ +/* + * linux/include/asm-nds/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0 + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_NDS_IO_H +#define __ASM_NDS_IO_H + +/* + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc... + * iinclude asm/io.h + */ + +#ifdef __KERNEL__ + +#include +#include + +static inline void sync(void) +{ +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +static inline phys_addr_t virt_to_phys(void *vaddr) +{ + return (phys_addr_t)(vaddr); +} + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(unsigned char *)(a)) +#define __arch_getw(a) (*(unsigned short *)(a)) +#define __arch_getl(a) (*(unsigned int *)(a)) + +#define __arch_putb(v, a) (*(unsigned char *)(a) = (v)) +#define __arch_putw(v, a) (*(unsigned short *)(a) = (v)) +#define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) + +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v, a) __arch_putb(v, a) +#define __raw_writew(v, a) __arch_putw(v, a) +#define __raw_writel(v, a) __arch_putl(v, a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +/* + * TODO: The kernel offers some more advanced versions of barriers, it might + * have some advantages to use them instead of the simple one here. + */ +#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define __iormb() dmb() +#define __iowmb() dmb() + +static inline void writeb(unsigned char val, unsigned char *addr) +{ + __iowmb(); + __arch_putb(val, addr); +} + +static inline void writew(unsigned short val, unsigned short *addr) +{ + __iowmb(); + __arch_putw(val, addr); + +} + +static inline void writel(unsigned int val, unsigned int *addr) +{ + __iowmb(); + __arch_putl(val, addr); +} + +static inline unsigned char readb(unsigned char *addr) +{ + u8 val; + + val = __arch_getb(addr); + __iormb(); + return val; +} + +static inline unsigned short readw(unsigned short *addr) +{ + u16 val; + + val = __arch_getw(addr); + __iormb(); + return val; +} + +static inline unsigned int readl(unsigned int *addr) +{ + u32 val; + + val = __arch_getl(addr); + __iormb(); + return val; +} + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off) +#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off) +#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off) + +#define __raw_base_readb(base, off) __arch_base_getb(base, off) +#define __raw_base_readw(base, off) __arch_base_getw(base, off) +#define __raw_base_readl(base, off) __arch_base_getl(base, off) + +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) + +/* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +/* + * Now, pick up the machine-defined IO definitions + * #include + */ + +/* + * IO port access primitives + * ------------------------- + * + * The NDS32 doesn't have special IO access instructions just like ARM; + * all IO is memory mapped. + * Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerious + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v, p) __raw_writeb(v, __io(p)) +#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p)) +#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p, d, l) writesb(__io(p), d, l) +#define outsw(p, d, l) writesw(__io(p), d, l) +#define outsl(p, d, l) writesl(__io(p), d, l) + +#define insb(p, d, l) readsb(__io(p), d, l) +#define insw(p, d, l) readsw(__io(p), d, l) +#define insl(p, d, l) readsl(__io(p), d, l) + +static inline void readsb(unsigned int *addr, void * data, int bytelen) +{ + unsigned char *ptr = (unsigned char *)addr; + unsigned char *ptr2 = (unsigned char *)data; + while (bytelen) { + *ptr2 = *ptr; + ptr2++; + bytelen--; + } +} + +static inline void readsw(unsigned int *addr, void * data, int wordlen) +{ + unsigned short *ptr = (unsigned short *)addr; + unsigned short *ptr2 = (unsigned short *)data; + while (wordlen) { + *ptr2 = *ptr; + ptr2++; + wordlen--; + } +} + +static inline void readsl(unsigned int *addr, void * data, int longlen) +{ + unsigned int *ptr = (unsigned int *)addr; + unsigned int *ptr2 = (unsigned int *)data; + while (longlen) { + *ptr2 = *ptr; + ptr2++; + longlen--; + } +} +static inline void writesb(unsigned int *addr, const void * data, int bytelen) +{ + unsigned char *ptr = (unsigned char *)addr; + unsigned char *ptr2 = (unsigned char *)data; + while (bytelen) { + *ptr = *ptr2; + ptr2++; + bytelen--; + } +} +static inline void writesw(unsigned int *addr, const void * data, int wordlen) +{ + unsigned short *ptr = (unsigned short *)addr; + unsigned short *ptr2 = (unsigned short *)data; + while (wordlen) { + *ptr = *ptr2; + ptr2++; + wordlen--; + } +} +static inline void writesl(unsigned int *addr, const void * data, int longlen) +{ + unsigned int *ptr = (unsigned int *)addr; + unsigned int *ptr2 = (unsigned int *)data; + while (longlen) { + *ptr = *ptr2; + ptr2++; + longlen--; + } +} +#endif + +#define outb_p(val, port) outb((val), (port)) +#define outw_p(val, port) outw((val), (port)) +#define outl_p(val, port) outl((val), (port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port, from, len) outsb(port, from, len) +#define outsw_p(port, from, len) outsw(port, from, len) +#define outsl_p(port, from, len) outsl(port, from, len) +#define insb_p(port, to, len) insb(port, to, len) +#define insw_p(port, to, len) insw(port, to, len) +#define insl_p(port, to, len) insl(port, to, len) + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. If you want a + * physical address, use __ioremap instead. + */ +extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags); +extern void __iounmap(void *addr); + +/* + * Generic ioremap support. + * + * Define: + * iomem_valid_addr(off,size) + * iomem_to_phys(off) + */ +#ifdef iomem_valid_addr +#define __arch_ioremap(off, sz, nocache) \ +({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off), _size, 0); \ + _ret; \ +}) + +#define __arch_iounmap __iounmap +#endif + +#define ioremap(off, sz) __arch_ioremap((off), (sz), 0) +#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1) +#define iounmap(_addr) __arch_iounmap(_addr) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +extern void __readwrite_bug(const char *fn); + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = \ + __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = \ + le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = \ + le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v, c) __raw_writeb(v, __mem_pci(c)) +#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) +#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) + +#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) +#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) +#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) + +#define eth_io_copy_and_sum(s, c, l, b) \ + eth_copy_and_sum((s), __mem_pci(c), (l), (b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} +#endif /* __mem_pci */ + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr)) +#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr)) +#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr)) +#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c)) +#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c)) +#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c)) + +#define isa_eth_io_copy_and_sum(a, b, c, d) \ + eth_copy_and_sum((a), __mem_isa(b), (c), (d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0) +#define isa_writeb(val, addr) __readwrite_bug("isa_writeb") +#define isa_writew(val, addr) __readwrite_bug("isa_writew") +#define isa_writel(val, addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a, b, c, d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io, sig, len) (0) + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ +#endif /* __ASM_NDS_IO_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/linkage.h b/qemu/roms/u-boot/arch/nds32/include/asm/linkage.h new file mode 100644 index 000000000..7e06bc712 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/linkage.h @@ -0,0 +1,12 @@ +/* + * U-boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#endif diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/mach-types.h b/qemu/roms/u-boot/arch/nds32/include/asm/mach-types.h new file mode 100644 index 000000000..259e4e7ad --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/mach-types.h @@ -0,0 +1,57 @@ +/* + * This was automagically generated from arch/nds/tools/mach-types! + * Do NOT edit + */ + +#ifndef __ASM_NDS32_MACH_TYPE_H +#define __ASM_NDS32_MACH_TYPE_H + +#ifndef __ASSEMBLY__ +/* The type of machine we're running on */ +extern unsigned int __machine_arch_type; +#endif + +/* see arch/arm/kernel/arch.c for a description of these */ +#define MACH_TYPE_ADPAG101 0 + +#ifdef CONFIG_ARCH_ADPAG101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG101 +# endif +# define machine_is_adpag101() (machine_arch_type == MACH_TYPE_ADPAG101) +#else +# define machine_is_adpag101() (0) +#endif + +#define MACH_TYPE_ADPAG101P 1 + +#ifdef CONFIG_ARCH_ADPAG101P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG101P +# endif +# define machine_is_adpag101p() (machine_arch_type == MACH_TYPE_ADPAG101P) +#else +# define machine_is_adpag101p() (1) +#endif + +#define MACH_TYPE_ADPAG102 2 + +#ifdef CONFIG_ARCH_ADPAG102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG102 +# endif +# define machine_is_adpag102() (machine_arch_type == MACH_TYPE_ADPAG102) +#else +# define machine_is_adpag102() (2) +#endif + +#endif /* __ASM_NDS32_MACH_TYPE_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/macro.h b/qemu/roms/u-boot/arch/nds32/include/asm/macro.h new file mode 100644 index 000000000..f5c853991 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/macro.h @@ -0,0 +1,80 @@ +/* + * include/asm-nds32/macro.h + * + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NDS_MACRO_H +#define __ASM_NDS_MACRO_H +#ifdef __ASSEMBLY__ + +/* + * These macros provide a convenient way to write 8, 16 and 32 bit data + * to an "immediate address (address used by periphal)" only. + * Registers r4 and r5 are used, any data in these registers are + * overwritten by the macros. + * The macros are valid for any NDS32 architecture, they do not implement + * any memory barriers so caution is recommended when using these when the + * caches are enabled or on a multi-core system. + */ + +.macro write32, addr, data + li $r4, addr + li $r5, data + swi $r5, [$r4] +.endm + +.macro write16, addr, data + li $r4, addr + li $r5, data + shi $r5, [$r4] +.endm + +.macro write8, addr, data + li $r4, addr + li $r5, data + sbi $r5, [$r4] +.endm + +/* + * This macro read a value from a register, then do OR operation + * (set bit fields) to the value, and then store it back to the register. + * Note: Instruction 'ori' supports immediate value up to 15 bits. + */ +.macro setbf32, addr, data + li $r4, addr + lwi $r5, [$r4] + li $r6, data + or $r5, $r5, $r6 + swi $r5, [$r4] +.endm + +.macro setbf15, addr, data + li $r4, addr + lwi $r5, [$r4] + ori $r5, $r5, data + swi $r5, [$r4] +.endm + +/* + * This macro generates a loop that can be used for delays in the code. + * Register r4 is used, any data in this register is overwritten by the + * macro. + * The macro is valid for any NDS32 architeture. The actual time spent in the + * loop will vary from CPU to CPU though. + */ + +.macro wait_timer, time + li $r4, time +1: + nop + addi $r4, $r4, -1 + bnez $r4, 1b +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARM_MACRO_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/posix_types.h b/qemu/roms/u-boot/arch/nds32/include/asm/posix_types.h new file mode 100644 index 000000000..a92803878 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/posix_types.h @@ -0,0 +1,84 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 05-03-2010 Modified for arch NDS32 + */ +#ifndef __ARCH_NDS_POSIX_TYPES_H +#define __ARCH_NDS_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp))) + +#endif + +#endif /* __ARCH_NDS_POSIX_TYPES_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/processor.h b/qemu/roms/u-boot/arch/nds32/include/asm/processor.h new file mode 100644 index 000000000..e5d186cc5 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/processor.h @@ -0,0 +1,25 @@ +/* + * linux/include/asm-arm/processor.h + * + * Copyright (C) 1995-2002 Russell King + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_NDS_PROCESSOR_H +#define __ASM_NDS_PROCESSOR_H + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - so far some files include /asm/processor.h, but + * no one uses the macros defined in this head file. + **************************************************************/ + +#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/ptrace.h b/qemu/roms/u-boot/arch/nds32/include/asm/ptrace.h new file mode 100644 index 000000000..ee181b267 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/ptrace.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_NDS_PTRACE_H +#define __ASM_NDS_PTRACE_H + +#define USR_MODE 0x00 +#define SU_MODE 0x01 +#define HV_MODE 0x10 +#define MODE_MASK (0x03<<3) +#define GIE_BIT 0x01 + +#ifndef __ASSEMBLY__ + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +#define NDS32_REG long + +struct pt_regs { + NDS32_REG ir0; + NDS32_REG ipsw; + NDS32_REG ipc; + NDS32_REG sp; + NDS32_REG orig_r0; + NDS32_REG pipsw; + NDS32_REG pipc; + NDS32_REG pp0; + NDS32_REG pp1; + NDS32_REG d0hi; + NDS32_REG d0lo; + NDS32_REG d1hi; + NDS32_REG d1lo; + NDS32_REG r[26]; /* r0 - r25 */ + NDS32_REG p0; /* r26 - used by OS */ + NDS32_REG p1; /* r27 - used by OS */ + NDS32_REG fp; /* r28 */ + NDS32_REG gp; /* r29 */ + NDS32_REG lp; /* r30 */ + NDS32_REG fucop_ctl; + NDS32_REG osp; +}; + +#define processor_mode(regs) \ + (((regs)->ipsw & MODE_MASK) >> 3) + +#define interrupts_enabled(regs) \ + ((regs)->ipsw & GIE_BIT) + +/* + * Offsets used by 'ptrace' system call interface. + * These can't be changed without breaking binary compatibility + * with MkLinux, etc. + */ +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_NDS_PTRACE_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/sections.h b/qemu/roms/u-boot/arch/nds32/include/asm/sections.h new file mode 100644 index 000000000..c5f3caab8 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/sections.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NDS32_SECTIONS_H +#define __ASM_NDS32_SECTIONS_H + +#include + +#endif diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/setup.h b/qemu/roms/u-boot/arch/nds32/include/asm/setup.h new file mode 100644 index 000000000..833d979af --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/setup.h @@ -0,0 +1,190 @@ +/* + * linux/arch/nds32/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * Copyright (C) 2008 Andes Technology Corporation + * Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com) + * + * SPDX-License-Identifier: GPL-2.0 + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See Documentation/arm/Setup + * for more info. + */ +#ifndef __ASMNDS32_SETUP_H +#define __ASMNDS32_SETUP_H + +#define COMMAND_LINE_SIZE 256 + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; /* bit 0 = read-only */ + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + u32 size; + u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + u8 x; + u8 y; + u16 video_page; + u8 video_mode; + u8 video_cols; + u16 video_ega_bx; + u8 video_lines; + u8 video_isvga; + u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RAMDISK 0x54410004 + +struct tag_ramdisk { + u32 flags; /* bit 0 = load, bit 1 = prompt */ + u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* + * this one accidentally used virtual addresses - as such, + * it's deprecated. + * describes where the compressed ramdisk image lives (virtual address) + */ +#define ATAG_INITRD 0x54410005 + +/* describes where the compressed ramdisk image lives (physical address) */ +#define ATAG_INITRD2 0x54420005 + +struct tag_initrd { + u32 start; /* physical start address */ + u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + u32 low; + u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + u16 lfb_width; + u16 lfb_height; + u16 lfb_depth; + u16 lfb_linelength; + u32 lfb_base; + u32 lfb_size; + u8 red_size; + u8 red_pos; + u8 green_size; + u8 green_pos; + u8 blue_size; + u8 blue_pos; + u8 rsvd_size; + u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[COMMAND_LINE_SIZE]; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(const struct tag *); +}; + +#define tag_member_present(tag, member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t, base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +#ifdef __KERNEL__ + +#define __tag __used __attribute__((__section__(".taglist"))) +#define __tagtable(tag, fn) \ +static struct tagtable __tagtable_##fn __tag = { tag, fn } + +/* + * Memory map description + */ +#define NR_BANKS 8 + +struct meminfo { + int nr_banks; + struct { + unsigned long start; + unsigned long size; + int node; + } bank[NR_BANKS]; +}; + +/* + * Early command line parameters. + */ +struct early_params { + const char *arg; + void (*fn)(char **p); +}; + +#define __early_param(name, fn) \ +static struct early_params __early_##fn __used \ +__attribute__((__section__("__early_param"))) = { name, fn } + +#endif +#endif diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/string.h b/qemu/roms/u-boot/arch/nds32/include/asm/string.h new file mode 100644 index 000000000..610aa9e4e --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/string.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_NDS_STRING_H +#define __ASM_NDS_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char *strrchr(const char *s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char *strchr(const char *s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void *memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void *memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void *memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +#undef __HAVE_ARCH_MEMSET +extern void *memset(void *, int, __kernel_size_t); + +#ifdef CONFIG_MARCO_MEMSET +extern void __memzero(void *ptr, __kernel_size_t n); + +#define memset(p, v, n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p), (n)); \ + else \ + memset((p), (v), (n)); \ + } \ + (p); \ + }) + +#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); }) +#else +extern void memzero(void *ptr, __kernel_size_t n); +#endif + +#endif /* __ASM_NDS_STRING_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/system.h b/qemu/roms/u-boot/arch/nds32/include/asm/system.h new file mode 100644 index 000000000..007e66bd6 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/system.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NDS_SYSTEM_H +#define __ASM_NDS_SYSTEM_H + +/* + * Interrupt configuring macros. + */ + +extern int irq_flags; + +#define local_irq_enable() \ + __asm__ __volatile__ ( \ + "mfsr %0, $psw\n\t" \ + "andi %0, %0, 0x1\n\t" \ + "setgie.e\n\t" \ + : \ + : "r" (irq_flags) \ + ) + +#define local_irq_disable() \ + do { \ + int __tmp_dummy; \ + __asm__ __volatile__ ( \ + "mfsr %0, $psw\n\t" \ + "andi %0, %0, 0x1\n\t" \ + "setgie.d\n\t" \ + "dsb\n\t" \ + : "=r" (__tmp_dummy) \ + ); \ + } while (0) + +#define local_irq_save(x) \ + __asm__ __volatile__ ( \ + "mfsr %0, $psw\n\t" \ + "andi %0, %0, 0x1\n\t" \ + "setgie.d\n\t" \ + "dsb\n\t" \ + : "=&r" (x) \ + ) + +#define local_save_flags(x) \ + __asm__ __volatile__ ( \ + "mfsr %0, $psw\n\t" \ + "andi %0, %0, 0x1\n\t" \ + "setgie.e\n\t" \ + "setgie.d\n\t" \ + : "=r" (x) \ + ) + +#define irqs_enabled_from_flags(x) ((x) != 0x1f) + +#define local_irq_restore(x) \ + do { \ + if (irqs_enabled_from_flags(x)) \ + local_irq_enable(); \ + } while (0) + +/* + * Force strict CPU ordering. + */ +#define nop() asm volatile ("nop;\n\t" : : ) +#define mb() asm volatile ("" : : : "memory") +#define rmb() asm volatile ("" : : : "memory") +#define wmb() asm volatile ("" : : : "memory") + +#endif /* __ASM_NDS_SYSTEM_H */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/types.h b/qemu/roms/u-boot/arch/nds32/include/asm/types.h new file mode 100644 index 000000000..2e8924f76 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/types.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_NDS_TYPES_H +#define __ASM_NDS_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +#include + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/u-boot-nds32.h b/qemu/roms/u-boot/arch/nds32/include/asm/u-boot-nds32.h new file mode 100644 index 000000000..b07908692 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/u-boot-nds32.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _U_BOOT_NDS32_H_ +#define _U_BOOT_NDS32_H_ 1 + +/* for the following variables, see start.S */ +extern ulong IRQ_STACK_START; /* top of IRQ stack */ +extern ulong FIQ_STACK_START; /* top of FIQ stack */ + +/* cpu/.../cpu.c */ +int cleanup_before_linux(void); + +/* board/.../... */ +int board_init(void); +int dram_init(void); + +/* cpu/.../interrupt.c */ +void reset_timer_masked(void); + +#endif /* _U_BOOT_NDS32_H_ */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/u-boot.h b/qemu/roms/u-boot/arch/nds32/include/asm/u-boot.h new file mode 100644 index 000000000..44e72d414 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/u-boot.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com) + * + * SPDX-License-Identifier: GPL-2.0+ + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +#include + +typedef struct bd_info { + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + + struct /* RAM configuration */ + { + unsigned long start; + unsigned long size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; +} bd_t; + +/* For image.h:image_check_target_arch() */ +#define IH_ARCH_DEFAULT IH_ARCH_NDS32 + +#endif /* _U_BOOT_H_ */ diff --git a/qemu/roms/u-boot/arch/nds32/include/asm/unaligned.h b/qemu/roms/u-boot/arch/nds32/include/asm/unaligned.h new file mode 100644 index 000000000..6cecbbb21 --- /dev/null +++ b/qemu/roms/u-boot/arch/nds32/include/asm/unaligned.h @@ -0,0 +1 @@ +#include -- cgit 1.2.3-korg