From bb756eebdac6fd24e8919e2c43f7d2c8c4091f59 Mon Sep 17 00:00:00 2001 From: RajithaY Date: Tue, 25 Apr 2017 03:31:15 -0700 Subject: Adding qemu as a submodule of KVMFORNFV This Patch includes the changes to add qemu as a submodule to kvmfornfv repo and make use of the updated latest qemu for the execution of all testcase Change-Id: I1280af507a857675c7f81d30c95255635667bdd7 Signed-off-by:RajithaY --- qemu/hw/isa/Makefile.objs | 8 - qemu/hw/isa/apm.c | 103 ------- qemu/hw/isa/i82378.c | 148 --------- qemu/hw/isa/isa-bus.c | 310 ------------------- qemu/hw/isa/lpc_ich9.c | 752 ---------------------------------------------- qemu/hw/isa/pc87312.c | 404 ------------------------- qemu/hw/isa/piix4.c | 142 --------- qemu/hw/isa/vt82c686.c | 515 ------------------------------- 8 files changed, 2382 deletions(-) delete mode 100644 qemu/hw/isa/Makefile.objs delete mode 100644 qemu/hw/isa/apm.c delete mode 100644 qemu/hw/isa/i82378.c delete mode 100644 qemu/hw/isa/isa-bus.c delete mode 100644 qemu/hw/isa/lpc_ich9.c delete mode 100644 qemu/hw/isa/pc87312.c delete mode 100644 qemu/hw/isa/piix4.c delete mode 100644 qemu/hw/isa/vt82c686.c (limited to 'qemu/hw/isa') diff --git a/qemu/hw/isa/Makefile.objs b/qemu/hw/isa/Makefile.objs deleted file mode 100644 index 9164556a4..000000000 --- a/qemu/hw/isa/Makefile.objs +++ /dev/null @@ -1,8 +0,0 @@ -common-obj-y += isa-bus.o -common-obj-$(CONFIG_APM) += apm.o -common-obj-$(CONFIG_I82378) += i82378.o -common-obj-$(CONFIG_PC87312) += pc87312.o -common-obj-$(CONFIG_PIIX4) += piix4.o -common-obj-$(CONFIG_VT82C686) += vt82c686.o - -obj-$(CONFIG_LPC_ICH9) += lpc_ich9.o diff --git a/qemu/hw/isa/apm.c b/qemu/hw/isa/apm.c deleted file mode 100644 index e232b0da0..000000000 --- a/qemu/hw/isa/apm.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * QEMU PC APM controller Emulation - * This is split out from acpi.c - * - * Copyright (c) 2006 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License version 2 as published by the Free Software Foundation. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include "qemu/osdep.h" -#include "hw/isa/apm.h" -#include "hw/hw.h" -#include "hw/pci/pci.h" - -//#define DEBUG - -#ifdef DEBUG -# define APM_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) -#else -# define APM_DPRINTF(format, ...) do { } while (0) -#endif - -/* fixed I/O location */ -#define APM_CNT_IOPORT 0xb2 -#define APM_STS_IOPORT 0xb3 - -static void apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, - unsigned size) -{ - APMState *apm = opaque; - addr &= 1; - APM_DPRINTF("apm_ioport_writeb addr=0x%" HWADDR_PRIx - " val=0x%02" PRIx64 "\n", addr, val); - if (addr == 0) { - apm->apmc = val; - - if (apm->callback) { - (apm->callback)(val, apm->arg); - } - } else { - apm->apms = val; - } -} - -static uint64_t apm_ioport_readb(void *opaque, hwaddr addr, unsigned size) -{ - APMState *apm = opaque; - uint32_t val; - - addr &= 1; - if (addr == 0) { - val = apm->apmc; - } else { - val = apm->apms; - } - APM_DPRINTF("apm_ioport_readb addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, val); - return val; -} - -const VMStateDescription vmstate_apm = { - .name = "APM State", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT8(apmc, APMState), - VMSTATE_UINT8(apms, APMState), - VMSTATE_END_OF_LIST() - } -}; - -static const MemoryRegionOps apm_ops = { - .read = apm_ioport_readb, - .write = apm_ioport_writeb, - .impl = { - .min_access_size = 1, - .max_access_size = 1, - }, -}; - -void apm_init(PCIDevice *dev, APMState *apm, apm_ctrl_changed_t callback, - void *arg) -{ - apm->callback = callback; - apm->arg = arg; - - /* ioport 0xb2, 0xb3 */ - memory_region_init_io(&apm->io, OBJECT(dev), &apm_ops, apm, "apm-io", 2); - memory_region_add_subregion(pci_address_space_io(dev), APM_CNT_IOPORT, - &apm->io); -} diff --git a/qemu/hw/isa/i82378.c b/qemu/hw/isa/i82378.c deleted file mode 100644 index 4d29a9900..000000000 --- a/qemu/hw/isa/i82378.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * QEMU Intel i82378 emulation (PCI to ISA bridge) - * - * Copyright (c) 2010-2011 Hervé Poussineau - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "hw/pci/pci.h" -#include "hw/i386/pc.h" -#include "hw/timer/i8254.h" -#include "hw/audio/pcspk.h" - -#define TYPE_I82378 "i82378" -#define I82378(obj) \ - OBJECT_CHECK(I82378State, (obj), TYPE_I82378) - -typedef struct I82378State { - PCIDevice parent_obj; - - qemu_irq out[2]; - qemu_irq *i8259; - MemoryRegion io; -} I82378State; - -static const VMStateDescription vmstate_i82378 = { - .name = "pci-i82378", - .version_id = 0, - .minimum_version_id = 0, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(parent_obj, I82378State), - VMSTATE_END_OF_LIST() - }, -}; - -static void i82378_request_out0_irq(void *opaque, int irq, int level) -{ - I82378State *s = opaque; - qemu_set_irq(s->out[0], level); -} - -static void i82378_request_pic_irq(void *opaque, int irq, int level) -{ - DeviceState *dev = opaque; - I82378State *s = I82378(dev); - - qemu_set_irq(s->i8259[irq], level); -} - -static void i82378_realize(PCIDevice *pci, Error **errp) -{ - DeviceState *dev = DEVICE(pci); - I82378State *s = I82378(dev); - uint8_t *pci_conf; - ISABus *isabus; - ISADevice *isa; - - pci_conf = pci->config; - pci_set_word(pci_conf + PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - pci_set_word(pci_conf + PCI_STATUS, - PCI_STATUS_DEVSEL_MEDIUM); - - pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */ - - isabus = isa_bus_new(dev, get_system_memory(), - pci_address_space_io(pci), errp); - if (!isabus) { - return; - } - - /* This device has: - 2 82C59 (irq) - 1 82C54 (pit) - 2 82C37 (dma) - NMI - Utility Bus Support Registers - - All devices accept byte access only, except timer - */ - - /* 2 82C59 (irq) */ - s->i8259 = i8259_init(isabus, - qemu_allocate_irq(i82378_request_out0_irq, s, 0)); - isa_bus_irqs(isabus, s->i8259); - - /* 1 82C54 (pit) */ - isa = pit_init(isabus, 0x40, 0, NULL); - - /* speaker */ - pcspk_init(isabus, isa); - - /* 2 82C37 (dma) */ - isa = isa_create_simple(isabus, "i82374"); - - /* timer */ - isa_create_simple(isabus, "mc146818rtc"); -} - -static void i82378_init(Object *obj) -{ - DeviceState *dev = DEVICE(obj); - I82378State *s = I82378(obj); - - qdev_init_gpio_out(dev, s->out, 1); - qdev_init_gpio_in(dev, i82378_request_pic_irq, 16); -} - -static void i82378_class_init(ObjectClass *klass, void *data) -{ - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - DeviceClass *dc = DEVICE_CLASS(klass); - - k->realize = i82378_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82378; - k->revision = 0x03; - k->class_id = PCI_CLASS_BRIDGE_ISA; - dc->vmsd = &vmstate_i82378; - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); -} - -static const TypeInfo i82378_type_info = { - .name = TYPE_I82378, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(I82378State), - .instance_init = i82378_init, - .class_init = i82378_class_init, -}; - -static void i82378_register_types(void) -{ - type_register_static(&i82378_type_info); -} - -type_init(i82378_register_types) diff --git a/qemu/hw/isa/isa-bus.c b/qemu/hw/isa/isa-bus.c deleted file mode 100644 index 7aa115caf..000000000 --- a/qemu/hw/isa/isa-bus.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * isa bus support for qdev. - * - * Copyright (c) 2009 Gerd Hoffmann - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/hw.h" -#include "monitor/monitor.h" -#include "hw/sysbus.h" -#include "sysemu/sysemu.h" -#include "hw/isa/isa.h" -#include "hw/i386/pc.h" - -static ISABus *isabus; - -static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent); -static char *isabus_get_fw_dev_path(DeviceState *dev); - -static void isa_bus_class_init(ObjectClass *klass, void *data) -{ - BusClass *k = BUS_CLASS(klass); - - k->print_dev = isabus_dev_print; - k->get_fw_dev_path = isabus_get_fw_dev_path; -} - -static const TypeInfo isa_dma_info = { - .name = TYPE_ISADMA, - .parent = TYPE_INTERFACE, - .class_size = sizeof(IsaDmaClass), -}; - -static const TypeInfo isa_bus_info = { - .name = TYPE_ISA_BUS, - .parent = TYPE_BUS, - .instance_size = sizeof(ISABus), - .class_init = isa_bus_class_init, -}; - -ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space, - MemoryRegion *address_space_io, Error **errp) -{ - if (isabus) { - error_setg(errp, "Can't create a second ISA bus"); - return NULL; - } - if (!dev) { - dev = qdev_create(NULL, "isabus-bridge"); - qdev_init_nofail(dev); - } - - isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL)); - isabus->address_space = address_space; - isabus->address_space_io = address_space_io; - return isabus; -} - -void isa_bus_irqs(ISABus *bus, qemu_irq *irqs) -{ - bus->irqs = irqs; -} - -/* - * isa_get_irq() returns the corresponding qemu_irq entry for the i8259. - * - * This function is only for special cases such as the 'ferr', and - * temporary use for normal devices until they are converted to qdev. - */ -qemu_irq isa_get_irq(ISADevice *dev, int isairq) -{ - assert(!dev || ISA_BUS(qdev_get_parent_bus(DEVICE(dev))) == isabus); - if (isairq < 0 || isairq > 15) { - hw_error("isa irq %d invalid", isairq); - } - return isabus->irqs[isairq]; -} - -void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq) -{ - assert(dev->nirqs < ARRAY_SIZE(dev->isairq)); - dev->isairq[dev->nirqs] = isairq; - *p = isa_get_irq(dev, isairq); - dev->nirqs++; -} - -void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16) -{ - assert(bus && dma8 && dma16); - assert(!bus->dma[0] && !bus->dma[1]); - bus->dma[0] = dma8; - bus->dma[1] = dma16; -} - -IsaDma *isa_get_dma(ISABus *bus, int nchan) -{ - assert(bus); - return bus->dma[nchan > 3 ? 1 : 0]; -} - -static inline void isa_init_ioport(ISADevice *dev, uint16_t ioport) -{ - if (dev && (dev->ioport_id == 0 || ioport < dev->ioport_id)) { - dev->ioport_id = ioport; - } -} - -void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start) -{ - memory_region_add_subregion(isabus->address_space_io, start, io); - isa_init_ioport(dev, start); -} - -void isa_register_portio_list(ISADevice *dev, uint16_t start, - const MemoryRegionPortio *pio_start, - void *opaque, const char *name) -{ - PortioList piolist; - - /* START is how we should treat DEV, regardless of the actual - contents of the portio array. This is how the old code - actually handled e.g. the FDC device. */ - isa_init_ioport(dev, start); - - /* FIXME: the device should store created PortioList in its state. Note - that DEV can be NULL here and that single device can register several - portio lists. Current implementation is leaking memory allocated - in portio_list_init. The leak is not critical because it happens only - at initialization time. */ - portio_list_init(&piolist, OBJECT(dev), pio_start, opaque, name); - portio_list_add(&piolist, isabus->address_space_io, start); -} - -static void isa_device_init(Object *obj) -{ - ISADevice *dev = ISA_DEVICE(obj); - - dev->isairq[0] = -1; - dev->isairq[1] = -1; -} - -ISADevice *isa_create(ISABus *bus, const char *name) -{ - DeviceState *dev; - - dev = qdev_create(BUS(bus), name); - return ISA_DEVICE(dev); -} - -ISADevice *isa_try_create(ISABus *bus, const char *name) -{ - DeviceState *dev; - - dev = qdev_try_create(BUS(bus), name); - return ISA_DEVICE(dev); -} - -ISADevice *isa_create_simple(ISABus *bus, const char *name) -{ - ISADevice *dev; - - dev = isa_create(bus, name); - qdev_init_nofail(DEVICE(dev)); - return dev; -} - -ISADevice *isa_vga_init(ISABus *bus) -{ - switch (vga_interface_type) { - case VGA_CIRRUS: - return isa_create_simple(bus, "isa-cirrus-vga"); - case VGA_QXL: - fprintf(stderr, "%s: qxl: no PCI bus\n", __func__); - return NULL; - case VGA_STD: - return isa_create_simple(bus, "isa-vga"); - case VGA_VMWARE: - fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __func__); - return NULL; - case VGA_VIRTIO: - fprintf(stderr, "%s: virtio-vga: no PCI bus\n", __func__); - return NULL; - case VGA_NONE: - default: - return NULL; - } -} - -static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent) -{ - ISADevice *d = ISA_DEVICE(dev); - - if (d->isairq[1] != -1) { - monitor_printf(mon, "%*sisa irqs %d,%d\n", indent, "", - d->isairq[0], d->isairq[1]); - } else if (d->isairq[0] != -1) { - monitor_printf(mon, "%*sisa irq %d\n", indent, "", - d->isairq[0]); - } -} - -static void isabus_bridge_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->fw_name = "isa"; -} - -static const TypeInfo isabus_bridge_info = { - .name = "isabus-bridge", - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SysBusDevice), - .class_init = isabus_bridge_class_init, -}; - -static void isa_device_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *k = DEVICE_CLASS(klass); - k->bus_type = TYPE_ISA_BUS; -} - -static const TypeInfo isa_device_type_info = { - .name = TYPE_ISA_DEVICE, - .parent = TYPE_DEVICE, - .instance_size = sizeof(ISADevice), - .instance_init = isa_device_init, - .abstract = true, - .class_size = sizeof(ISADeviceClass), - .class_init = isa_device_class_init, -}; - -static void isabus_register_types(void) -{ - type_register_static(&isa_dma_info); - type_register_static(&isa_bus_info); - type_register_static(&isabus_bridge_info); - type_register_static(&isa_device_type_info); -} - -static char *isabus_get_fw_dev_path(DeviceState *dev) -{ - ISADevice *d = ISA_DEVICE(dev); - char path[40]; - int off; - - off = snprintf(path, sizeof(path), "%s", qdev_fw_name(dev)); - if (d->ioport_id) { - snprintf(path + off, sizeof(path) - off, "@%04x", d->ioport_id); - } - - return g_strdup(path); -} - -MemoryRegion *isa_address_space(ISADevice *dev) -{ - if (dev) { - return isa_bus_from_device(dev)->address_space; - } - - return isabus->address_space; -} - -MemoryRegion *isa_address_space_io(ISADevice *dev) -{ - if (dev) { - return isa_bus_from_device(dev)->address_space_io; - } - - return isabus->address_space_io; -} - -type_init(isabus_register_types) - -static void parallel_init(ISABus *bus, int index, CharDriverState *chr) -{ - DeviceState *dev; - ISADevice *isadev; - - isadev = isa_create(bus, "isa-parallel"); - dev = DEVICE(isadev); - qdev_prop_set_uint32(dev, "index", index); - qdev_prop_set_chr(dev, "chardev", chr); - qdev_init_nofail(dev); -} - -void parallel_hds_isa_init(ISABus *bus, int n) -{ - int i; - - assert(n <= MAX_PARALLEL_PORTS); - - for (i = 0; i < n; i++) { - if (parallel_hds[i]) { - parallel_init(bus, i, parallel_hds[i]); - } - } -} diff --git a/qemu/hw/isa/lpc_ich9.c b/qemu/hw/isa/lpc_ich9.c deleted file mode 100644 index 99cd3ba9e..000000000 --- a/qemu/hw/isa/lpc_ich9.c +++ /dev/null @@ -1,752 +0,0 @@ -/* - * QEMU ICH9 Emulation - * - * Copyright (c) 2006 Fabrice Bellard - * Copyright (c) 2009, 2010, 2011 - * Isaku Yamahata - * VA Linux Systems Japan K.K. - * Copyright (C) 2012 Jason Baron - * - * This is based on piix.c, but heavily modified. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ -#include "qemu/osdep.h" -#include "qemu-common.h" -#include "cpu.h" -#include "hw/hw.h" -#include "qapi/visitor.h" -#include "qemu/range.h" -#include "hw/isa/isa.h" -#include "hw/sysbus.h" -#include "hw/i386/pc.h" -#include "hw/isa/apm.h" -#include "hw/i386/ioapic.h" -#include "hw/pci/pci.h" -#include "hw/pci/pcie_host.h" -#include "hw/pci/pci_bridge.h" -#include "hw/i386/ich9.h" -#include "hw/acpi/acpi.h" -#include "hw/acpi/ich9.h" -#include "hw/pci/pci_bus.h" -#include "exec/address-spaces.h" -#include "sysemu/sysemu.h" - -static int ich9_lpc_sci_irq(ICH9LPCState *lpc); - -/*****************************************************************************/ -/* ICH9 LPC PCI to ISA bridge */ - -static void ich9_lpc_reset(DeviceState *qdev); - -/* chipset configuration register - * to access chipset configuration registers, pci_[sg]et_{byte, word, long} - * are used. - * Although it's not pci configuration space, it's little endian as Intel. - */ - -static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) -{ - int intx; - for (intx = 0; intx < PCI_NUM_PINS; intx++) { - irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; - } -} - -static void ich9_cc_update(ICH9LPCState *lpc) -{ - int slot; - int pci_intx; - - const int reg_offsets[] = { - ICH9_CC_D25IR, - ICH9_CC_D26IR, - ICH9_CC_D27IR, - ICH9_CC_D28IR, - ICH9_CC_D29IR, - ICH9_CC_D30IR, - ICH9_CC_D31IR, - }; - const int *offset; - - /* D{25 - 31}IR, but D30IR is read only to 0. */ - for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { - if (slot == 30) { - continue; - } - ich9_cc_update_ir(lpc->irr[slot], - pci_get_word(lpc->chip_config + *offset)); - } - - /* - * D30: DMI2PCI bridge - * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge - * are connected to pirq lines. Our choice is PIRQ[E-H]. - * INT[A-D] are connected to PIRQ[E-H] - */ - for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { - lpc->irr[30][pci_intx] = pci_intx + 4; - } -} - -static void ich9_cc_init(ICH9LPCState *lpc) -{ - int slot; - int intx; - - /* the default irq routing is arbitrary as long as it matches with - * acpi irq routing table. - * The one that is incompatible with piix_pci(= bochs) one is - * intentionally chosen to let the users know that the different - * board is used. - * - * int[A-D] -> pirq[E-F] - * avoid pirq A-D because they are used for pci express port - */ - for (slot = 0; slot < PCI_SLOT_MAX; slot++) { - for (intx = 0; intx < PCI_NUM_PINS; intx++) { - lpc->irr[slot][intx] = (slot + intx) % 4 + 4; - } - } - ich9_cc_update(lpc); -} - -static void ich9_cc_reset(ICH9LPCState *lpc) -{ - uint8_t *c = lpc->chip_config; - - memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); - - pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); - pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); - pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); - pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); - pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); - pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); - pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); - pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); - - ich9_cc_update(lpc); -} - -static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) -{ - *addr &= ICH9_CC_ADDR_MASK; - if (*addr + *len >= ICH9_CC_SIZE) { - *len = ICH9_CC_SIZE - *addr; - } -} - -/* val: little endian */ -static void ich9_cc_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - ICH9LPCState *lpc = (ICH9LPCState *)opaque; - - ich9_cc_addr_len(&addr, &len); - memcpy(lpc->chip_config + addr, &val, len); - pci_bus_fire_intx_routing_notifier(lpc->d.bus); - ich9_cc_update(lpc); -} - -/* return value: little endian */ -static uint64_t ich9_cc_read(void *opaque, hwaddr addr, - unsigned len) -{ - ICH9LPCState *lpc = (ICH9LPCState *)opaque; - - uint32_t val = 0; - ich9_cc_addr_len(&addr, &len); - memcpy(&val, lpc->chip_config + addr, len); - return val; -} - -/* IRQ routing */ -/* */ -static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) -{ - *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; - *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; -} - -static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, - int *pic_irq, int *pic_dis) -{ - switch (pirq_num) { - case 0 ... 3: /* A-D */ - ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], - pic_irq, pic_dis); - return; - case 4 ... 7: /* E-H */ - ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], - pic_irq, pic_dis); - return; - default: - break; - } - abort(); -} - -/* pic_irq: i8254 irq 0-15 */ -static void ich9_lpc_update_pic(ICH9LPCState *lpc, int pic_irq) -{ - int i, pic_level; - - /* The pic level is the logical OR of all the PCI irqs mapped to it */ - pic_level = 0; - for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { - int tmp_irq; - int tmp_dis; - ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); - if (!tmp_dis && pic_irq == tmp_irq) { - pic_level |= pci_bus_get_irq_level(lpc->d.bus, i); - } - } - if (pic_irq == ich9_lpc_sci_irq(lpc)) { - pic_level |= lpc->sci_level; - } - - qemu_set_irq(lpc->pic[pic_irq], pic_level); -} - -/* pirq: pirq[A-H] 0-7*/ -static void ich9_lpc_update_by_pirq(ICH9LPCState *lpc, int pirq) -{ - int pic_irq; - int pic_dis; - - ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); - assert(pic_irq < ICH9_LPC_PIC_NUM_PINS); - if (pic_dis) { - return; - } - - ich9_lpc_update_pic(lpc, pic_irq); -} - -/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ -static int ich9_pirq_to_gsi(int pirq) -{ - return pirq + ICH9_LPC_PIC_NUM_PINS; -} - -static int ich9_gsi_to_pirq(int gsi) -{ - return gsi - ICH9_LPC_PIC_NUM_PINS; -} - -static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) -{ - int level = 0; - - if (gsi >= ICH9_LPC_PIC_NUM_PINS) { - level |= pci_bus_get_irq_level(lpc->d.bus, ich9_gsi_to_pirq(gsi)); - } - if (gsi == ich9_lpc_sci_irq(lpc)) { - level |= lpc->sci_level; - } - - qemu_set_irq(lpc->ioapic[gsi], level); -} - -void ich9_lpc_set_irq(void *opaque, int pirq, int level) -{ - ICH9LPCState *lpc = opaque; - - assert(0 <= pirq); - assert(pirq < ICH9_LPC_NB_PIRQS); - - ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); - ich9_lpc_update_by_pirq(lpc, pirq); -} - -/* return the pirq number (PIRQ[A-H]:0-7) corresponding to - * a given device irq pin. - */ -int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) -{ - BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); - PCIBus *pci_bus = PCI_BUS(bus); - PCIDevice *lpc_pdev = - pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; - ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); - - return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; -} - -PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) -{ - ICH9LPCState *lpc = opaque; - PCIINTxRoute route; - int pic_irq; - int pic_dis; - - assert(0 <= pirq_pin); - assert(pirq_pin < ICH9_LPC_NB_PIRQS); - - route.mode = PCI_INTX_ENABLED; - ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); - if (!pic_dis) { - if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { - route.irq = pic_irq; - } else { - route.mode = PCI_INTX_DISABLED; - route.irq = -1; - } - } else { - route.irq = ich9_pirq_to_gsi(pirq_pin); - } - - return route; -} - -void ich9_generate_smi(void) -{ - cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); -} - -void ich9_generate_nmi(void) -{ - cpu_interrupt(first_cpu, CPU_INTERRUPT_NMI); -} - -static int ich9_lpc_sci_irq(ICH9LPCState *lpc) -{ - switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & - ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { - case ICH9_LPC_ACPI_CTRL_9: - return 9; - case ICH9_LPC_ACPI_CTRL_10: - return 10; - case ICH9_LPC_ACPI_CTRL_11: - return 11; - case ICH9_LPC_ACPI_CTRL_20: - return 20; - case ICH9_LPC_ACPI_CTRL_21: - return 21; - default: - /* reserved */ - break; - } - return -1; -} - -static void ich9_set_sci(void *opaque, int irq_num, int level) -{ - ICH9LPCState *lpc = opaque; - int irq; - - assert(irq_num == 0); - level = !!level; - if (level == lpc->sci_level) { - return; - } - lpc->sci_level = level; - - irq = ich9_lpc_sci_irq(lpc); - if (irq < 0) { - return; - } - - ich9_lpc_update_apic(lpc, irq); - if (irq < ICH9_LPC_PIC_NUM_PINS) { - ich9_lpc_update_pic(lpc, irq); - } -} - -void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) -{ - ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); - qemu_irq sci_irq; - - sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); - ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); - ich9_lpc_reset(&lpc->d.qdev); -} - -/* APM */ - -static void ich9_apm_ctrl_changed(uint32_t val, void *arg) -{ - ICH9LPCState *lpc = arg; - - /* ACPI specs 3.0, 4.7.2.5 */ - acpi_pm1_cnt_update(&lpc->pm.acpi_regs, - val == ICH9_APM_ACPI_ENABLE, - val == ICH9_APM_ACPI_DISABLE); - if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { - return; - } - - /* SMI_EN = PMBASE + 30. SMI control and enable register */ - if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { - cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); - } -} - -/* config:PMBASE */ -static void -ich9_lpc_pmbase_update(ICH9LPCState *lpc) -{ - uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); - pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; - - ich9_pm_iospace_update(&lpc->pm, pm_io_base); -} - -/* config:RCBA */ -static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) -{ - uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); - - if (rcba_old & ICH9_LPC_RCBA_EN) { - memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); - } - if (rcba & ICH9_LPC_RCBA_EN) { - memory_region_add_subregion_overlap(get_system_memory(), - rcba & ICH9_LPC_RCBA_BA_MASK, - &lpc->rcrb_mem, 1); - } -} - -/* config:GEN_PMCON* */ -static void -ich9_lpc_pmcon_update(ICH9LPCState *lpc) -{ - uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); - uint16_t wmask; - - if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { - wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); - wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; - pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); - lpc->pm.smi_en_wmask &= ~1; - } -} - -static int ich9_lpc_post_load(void *opaque, int version_id) -{ - ICH9LPCState *lpc = opaque; - - ich9_lpc_pmbase_update(lpc); - ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); - ich9_lpc_pmcon_update(lpc); - return 0; -} - -static void ich9_lpc_config_write(PCIDevice *d, - uint32_t addr, uint32_t val, int len) -{ - ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); - uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); - - pci_default_write_config(d, addr, val, len); - if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) { - ich9_lpc_pmbase_update(lpc); - } - if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { - ich9_lpc_rcba_update(lpc, rcba_old); - } - if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { - pci_bus_fire_intx_routing_notifier(lpc->d.bus); - } - if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { - pci_bus_fire_intx_routing_notifier(lpc->d.bus); - } - if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { - ich9_lpc_pmcon_update(lpc); - } -} - -static void ich9_lpc_reset(DeviceState *qdev) -{ - PCIDevice *d = PCI_DEVICE(qdev); - ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); - uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); - int i; - - for (i = 0; i < 4; i++) { - pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, - ICH9_LPC_PIRQ_ROUT_DEFAULT); - } - for (i = 0; i < 4; i++) { - pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, - ICH9_LPC_PIRQ_ROUT_DEFAULT); - } - pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); - - pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); - pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); - - ich9_cc_reset(lpc); - - ich9_lpc_pmbase_update(lpc); - ich9_lpc_rcba_update(lpc, rcba_old); - - lpc->sci_level = 0; - lpc->rst_cnt = 0; -} - -/* root complex register block is mapped into memory space */ -static const MemoryRegionOps rcrb_mmio_ops = { - .read = ich9_cc_read, - .write = ich9_cc_write, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static void ich9_lpc_machine_ready(Notifier *n, void *opaque) -{ - ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); - MemoryRegion *io_as = pci_address_space_io(&s->d); - uint8_t *pci_conf; - - pci_conf = s->d.config; - if (memory_region_present(io_as, 0x3f8)) { - /* com1 */ - pci_conf[0x82] |= 0x01; - } - if (memory_region_present(io_as, 0x2f8)) { - /* com2 */ - pci_conf[0x82] |= 0x02; - } - if (memory_region_present(io_as, 0x378)) { - /* lpt */ - pci_conf[0x82] |= 0x04; - } - if (memory_region_present(io_as, 0x3f2)) { - /* floppy */ - pci_conf[0x82] |= 0x08; - } -} - -/* reset control */ -static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, - unsigned len) -{ - ICH9LPCState *lpc = opaque; - - if (val & 4) { - qemu_system_reset_request(); - return; - } - lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ -} - -static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) -{ - ICH9LPCState *lpc = opaque; - - return lpc->rst_cnt; -} - -static const MemoryRegionOps ich9_rst_cnt_ops = { - .read = ich9_rst_cnt_read, - .write = ich9_rst_cnt_write, - .endianness = DEVICE_LITTLE_ENDIAN -}; - -Object *ich9_lpc_find(void) -{ - bool ambig; - Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig); - - if (ambig) { - return NULL; - } - return o; -} - -static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); - uint32_t value = ich9_lpc_sci_irq(lpc); - - visit_type_uint32(v, name, &value, errp); -} - -static void ich9_lpc_add_properties(ICH9LPCState *lpc) -{ - static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; - static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; - - object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32", - ich9_lpc_get_sci_int, - NULL, NULL, NULL, NULL); - object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, - &acpi_enable_cmd, NULL); - object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, - &acpi_disable_cmd, NULL); - - ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL); -} - -static void ich9_lpc_initfn(Object *obj) -{ - ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); - - ich9_lpc_add_properties(lpc); -} - -static void ich9_lpc_realize(PCIDevice *d, Error **errp) -{ - ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); - ISABus *isa_bus; - - isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), - errp); - if (!isa_bus) { - return; - } - - pci_set_long(d->wmask + ICH9_LPC_PMBASE, - ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); - - memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, - "lpc-rcrb-mmio", ICH9_CC_SIZE); - - lpc->isa_bus = isa_bus; - - ich9_cc_init(lpc); - apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); - - lpc->machine_ready.notify = ich9_lpc_machine_ready; - qemu_add_machine_init_done_notifier(&lpc->machine_ready); - - memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, - "lpc-reset-control", 1); - memory_region_add_subregion_overlap(pci_address_space_io(d), - ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, - 1); -} - -static void ich9_device_plug_cb(HotplugHandler *hotplug_dev, - DeviceState *dev, Error **errp) -{ - ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); - - ich9_pm_device_plug_cb(&lpc->pm, dev, errp); -} - -static void ich9_device_unplug_request_cb(HotplugHandler *hotplug_dev, - DeviceState *dev, Error **errp) -{ - ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); - - ich9_pm_device_unplug_request_cb(&lpc->pm, dev, errp); -} - -static void ich9_device_unplug_cb(HotplugHandler *hotplug_dev, - DeviceState *dev, Error **errp) -{ - ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); - - ich9_pm_device_unplug_cb(&lpc->pm, dev, errp); -} - -static bool ich9_rst_cnt_needed(void *opaque) -{ - ICH9LPCState *lpc = opaque; - - return (lpc->rst_cnt != 0); -} - -static const VMStateDescription vmstate_ich9_rst_cnt = { - .name = "ICH9LPC/rst_cnt", - .version_id = 1, - .minimum_version_id = 1, - .needed = ich9_rst_cnt_needed, - .fields = (VMStateField[]) { - VMSTATE_UINT8(rst_cnt, ICH9LPCState), - VMSTATE_END_OF_LIST() - } -}; - -static const VMStateDescription vmstate_ich9_lpc = { - .name = "ICH9LPC", - .version_id = 1, - .minimum_version_id = 1, - .post_load = ich9_lpc_post_load, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(d, ICH9LPCState), - VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), - VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), - VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), - VMSTATE_UINT32(sci_level, ICH9LPCState), - VMSTATE_END_OF_LIST() - }, - .subsections = (const VMStateDescription*[]) { - &vmstate_ich9_rst_cnt, - NULL - } -}; - -static Property ich9_lpc_properties[] = { - DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), - DEFINE_PROP_END_OF_LIST(), -}; - -static void ich9_lpc_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); - AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); - - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->reset = ich9_lpc_reset; - k->realize = ich9_lpc_realize; - dc->vmsd = &vmstate_ich9_lpc; - dc->props = ich9_lpc_properties; - k->config_write = ich9_lpc_config_write; - dc->desc = "ICH9 LPC bridge"; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; - k->revision = ICH9_A2_LPC_REVISION; - k->class_id = PCI_CLASS_BRIDGE_ISA; - /* - * Reason: part of ICH9 southbridge, needs to be wired up by - * pc_q35_init() - */ - dc->cannot_instantiate_with_device_add_yet = true; - hc->plug = ich9_device_plug_cb; - hc->unplug_request = ich9_device_unplug_request_cb; - hc->unplug = ich9_device_unplug_cb; - adevc->ospm_status = ich9_pm_ospm_status; -} - -static const TypeInfo ich9_lpc_info = { - .name = TYPE_ICH9_LPC_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(struct ICH9LPCState), - .instance_init = ich9_lpc_initfn, - .class_init = ich9_lpc_class_init, - .interfaces = (InterfaceInfo[]) { - { TYPE_HOTPLUG_HANDLER }, - { TYPE_ACPI_DEVICE_IF }, - { } - } -}; - -static void ich9_lpc_register(void) -{ - type_register_static(&ich9_lpc_info); -} - -type_init(ich9_lpc_register); diff --git a/qemu/hw/isa/pc87312.c b/qemu/hw/isa/pc87312.c deleted file mode 100644 index c3ebf3e7a..000000000 --- a/qemu/hw/isa/pc87312.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * QEMU National Semiconductor PC87312 (Super I/O) - * - * Copyright (c) 2010-2012 Herve Poussineau - * Copyright (c) 2011-2012 Andreas Färber - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "hw/isa/pc87312.h" -#include "qapi/error.h" -#include "qemu/error-report.h" -#include "sysemu/block-backend.h" -#include "sysemu/blockdev.h" -#include "sysemu/sysemu.h" -#include "sysemu/char.h" -#include "trace.h" - - -#define REG_FER 0 -#define REG_FAR 1 -#define REG_PTR 2 - -#define FER_PARALLEL_EN 0x01 -#define FER_UART1_EN 0x02 -#define FER_UART2_EN 0x04 -#define FER_FDC_EN 0x08 -#define FER_FDC_4 0x10 -#define FER_FDC_ADDR 0x20 -#define FER_IDE_EN 0x40 -#define FER_IDE_ADDR 0x80 - -#define FAR_PARALLEL_ADDR 0x03 -#define FAR_UART1_ADDR 0x0C -#define FAR_UART2_ADDR 0x30 -#define FAR_UART_3_4 0xC0 - -#define PTR_POWER_DOWN 0x01 -#define PTR_CLOCK_DOWN 0x02 -#define PTR_PWDN 0x04 -#define PTR_IRQ_5_7 0x08 -#define PTR_UART1_TEST 0x10 -#define PTR_UART2_TEST 0x20 -#define PTR_LOCK_CONF 0x40 -#define PTR_EPP_MODE 0x80 - - -/* Parallel port */ - -static inline bool is_parallel_enabled(PC87312State *s) -{ - return s->regs[REG_FER] & FER_PARALLEL_EN; -} - -static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 }; - -static inline uint32_t get_parallel_iobase(PC87312State *s) -{ - return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR]; -} - -static const uint32_t parallel_irq[] = { 5, 7, 5, 0 }; - -static inline uint32_t get_parallel_irq(PC87312State *s) -{ - int idx; - idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR); - if (idx == 0) { - return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5; - } else { - return parallel_irq[idx]; - } -} - - -/* UARTs */ - -static const uint32_t uart_base[2][4] = { - { 0x3e8, 0x338, 0x2e8, 0x220 }, - { 0x2e8, 0x238, 0x2e0, 0x228 } -}; - -static inline uint32_t get_uart_iobase(PC87312State *s, int i) -{ - int idx; - idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; - if (idx == 0) { - return 0x3f8; - } else if (idx == 1) { - return 0x2f8; - } else { - return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6]; - } -} - -static inline uint32_t get_uart_irq(PC87312State *s, int i) -{ - int idx; - idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; - return (idx & 1) ? 3 : 4; -} - -static inline bool is_uart_enabled(PC87312State *s, int i) -{ - return s->regs[REG_FER] & (FER_UART1_EN << i); -} - - -/* Floppy controller */ - -static inline bool is_fdc_enabled(PC87312State *s) -{ - return s->regs[REG_FER] & FER_FDC_EN; -} - -static inline uint32_t get_fdc_iobase(PC87312State *s) -{ - return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0; -} - - -/* IDE controller */ - -static inline bool is_ide_enabled(PC87312State *s) -{ - return s->regs[REG_FER] & FER_IDE_EN; -} - -static inline uint32_t get_ide_iobase(PC87312State *s) -{ - return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0; -} - - -static void reconfigure_devices(PC87312State *s) -{ - error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)", - s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]); -} - -static void pc87312_soft_reset(PC87312State *s) -{ - static const uint8_t fer_init[] = { - 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b, - 0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f, - 0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07, - 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00, - }; - static const uint8_t far_init[] = { - 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01, - 0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24, - 0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24, - 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10, - }; - static const uint8_t ptr_init[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - }; - - s->read_id_step = 0; - s->selected_index = REG_FER; - - s->regs[REG_FER] = fer_init[s->config & 0x1f]; - s->regs[REG_FAR] = far_init[s->config & 0x1f]; - s->regs[REG_PTR] = ptr_init[s->config & 0x1f]; -} - -static void pc87312_hard_reset(PC87312State *s) -{ - pc87312_soft_reset(s); -} - -static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int size) -{ - PC87312State *s = opaque; - - trace_pc87312_io_write(addr, val); - - if ((addr & 1) == 0) { - /* Index register */ - s->read_id_step = 2; - s->selected_index = val; - } else { - /* Data register */ - if (s->selected_index < 3) { - s->regs[s->selected_index] = val; - reconfigure_devices(s); - } - } -} - -static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size) -{ - PC87312State *s = opaque; - uint32_t val; - - if ((addr & 1) == 0) { - /* Index register */ - if (s->read_id_step++ == 0) { - val = 0x88; - } else if (s->read_id_step++ == 1) { - val = 0; - } else { - val = s->selected_index; - } - } else { - /* Data register */ - if (s->selected_index < 3) { - val = s->regs[s->selected_index]; - } else { - /* Invalid selected index */ - val = 0; - } - } - - trace_pc87312_io_read(addr, val); - return val; -} - -static const MemoryRegionOps pc87312_io_ops = { - .read = pc87312_io_read, - .write = pc87312_io_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 1, - }, -}; - -static int pc87312_post_load(void *opaque, int version_id) -{ - PC87312State *s = opaque; - - reconfigure_devices(s); - return 0; -} - -static void pc87312_reset(DeviceState *d) -{ - PC87312State *s = PC87312(d); - - pc87312_soft_reset(s); -} - -static void pc87312_realize(DeviceState *dev, Error **errp) -{ - PC87312State *s; - DeviceState *d; - ISADevice *isa; - ISABus *bus; - CharDriverState *chr; - DriveInfo *drive; - char name[5]; - int i; - - s = PC87312(dev); - isa = ISA_DEVICE(dev); - bus = isa_bus_from_device(isa); - isa_register_ioport(isa, &s->io, s->iobase); - pc87312_hard_reset(s); - - if (is_parallel_enabled(s)) { - /* FIXME use a qdev chardev prop instead of parallel_hds[] */ - chr = parallel_hds[0]; - if (chr == NULL) { - chr = qemu_chr_new("par0", "null", NULL); - } - isa = isa_create(bus, "isa-parallel"); - d = DEVICE(isa); - qdev_prop_set_uint32(d, "index", 0); - qdev_prop_set_uint32(d, "iobase", get_parallel_iobase(s)); - qdev_prop_set_uint32(d, "irq", get_parallel_irq(s)); - qdev_prop_set_chr(d, "chardev", chr); - qdev_init_nofail(d); - s->parallel.dev = isa; - trace_pc87312_info_parallel(get_parallel_iobase(s), - get_parallel_irq(s)); - } - - for (i = 0; i < 2; i++) { - if (is_uart_enabled(s, i)) { - /* FIXME use a qdev chardev prop instead of serial_hds[] */ - chr = serial_hds[i]; - if (chr == NULL) { - snprintf(name, sizeof(name), "ser%d", i); - chr = qemu_chr_new(name, "null", NULL); - } - isa = isa_create(bus, "isa-serial"); - d = DEVICE(isa); - qdev_prop_set_uint32(d, "index", i); - qdev_prop_set_uint32(d, "iobase", get_uart_iobase(s, i)); - qdev_prop_set_uint32(d, "irq", get_uart_irq(s, i)); - qdev_prop_set_chr(d, "chardev", chr); - qdev_init_nofail(d); - s->uart[i].dev = isa; - trace_pc87312_info_serial(i, get_uart_iobase(s, i), - get_uart_irq(s, i)); - } - } - - if (is_fdc_enabled(s)) { - isa = isa_create(bus, "isa-fdc"); - d = DEVICE(isa); - qdev_prop_set_uint32(d, "iobase", get_fdc_iobase(s)); - qdev_prop_set_uint32(d, "irq", 6); - /* FIXME use a qdev drive property instead of drive_get() */ - drive = drive_get(IF_FLOPPY, 0, 0); - if (drive != NULL) { - qdev_prop_set_drive(d, "driveA", blk_by_legacy_dinfo(drive), - &error_fatal); - } - /* FIXME use a qdev drive property instead of drive_get() */ - drive = drive_get(IF_FLOPPY, 0, 1); - if (drive != NULL) { - qdev_prop_set_drive(d, "driveB", blk_by_legacy_dinfo(drive), - &error_fatal); - } - qdev_init_nofail(d); - s->fdc.dev = isa; - trace_pc87312_info_floppy(get_fdc_iobase(s)); - } - - if (is_ide_enabled(s)) { - isa = isa_create(bus, "isa-ide"); - d = DEVICE(isa); - qdev_prop_set_uint32(d, "iobase", get_ide_iobase(s)); - qdev_prop_set_uint32(d, "iobase2", get_ide_iobase(s) + 0x206); - qdev_prop_set_uint32(d, "irq", 14); - qdev_init_nofail(d); - s->ide.dev = isa; - trace_pc87312_info_ide(get_ide_iobase(s)); - } -} - -static void pc87312_initfn(Object *obj) -{ - PC87312State *s = PC87312(obj); - - memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2); -} - -static const VMStateDescription vmstate_pc87312 = { - .name = "pc87312", - .version_id = 1, - .minimum_version_id = 1, - .post_load = pc87312_post_load, - .fields = (VMStateField[]) { - VMSTATE_UINT8(read_id_step, PC87312State), - VMSTATE_UINT8(selected_index, PC87312State), - VMSTATE_UINT8_ARRAY(regs, PC87312State, 3), - VMSTATE_END_OF_LIST() - } -}; - -static Property pc87312_properties[] = { - DEFINE_PROP_UINT32("iobase", PC87312State, iobase, 0x398), - DEFINE_PROP_UINT8("config", PC87312State, config, 1), - DEFINE_PROP_END_OF_LIST() -}; - -static void pc87312_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->realize = pc87312_realize; - dc->reset = pc87312_reset; - dc->vmsd = &vmstate_pc87312; - dc->props = pc87312_properties; -} - -static const TypeInfo pc87312_type_info = { - .name = TYPE_PC87312, - .parent = TYPE_ISA_DEVICE, - .instance_size = sizeof(PC87312State), - .instance_init = pc87312_initfn, - .class_init = pc87312_class_init, -}; - -static void pc87312_register_types(void) -{ - type_register_static(&pc87312_type_info); -} - -type_init(pc87312_register_types) diff --git a/qemu/hw/isa/piix4.c b/qemu/hw/isa/piix4.c deleted file mode 100644 index 5500fcc4d..000000000 --- a/qemu/hw/isa/piix4.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * QEMU PIIX4 PCI Bridge Emulation - * - * Copyright (c) 2006 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "hw/hw.h" -#include "hw/i386/pc.h" -#include "hw/pci/pci.h" -#include "hw/isa/isa.h" -#include "hw/sysbus.h" - -PCIDevice *piix4_dev; - -typedef struct PIIX4State { - PCIDevice dev; -} PIIX4State; - -#define TYPE_PIIX4_PCI_DEVICE "PIIX4" -#define PIIX4_PCI_DEVICE(obj) \ - OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE) - -static void piix4_reset(void *opaque) -{ - PIIX4State *d = opaque; - uint8_t *pci_conf = d->dev.config; - - pci_conf[0x04] = 0x07; // master, memory and I/O - pci_conf[0x05] = 0x00; - pci_conf[0x06] = 0x00; - pci_conf[0x07] = 0x02; // PCI_status_devsel_medium - pci_conf[0x4c] = 0x4d; - pci_conf[0x4e] = 0x03; - pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 - pci_conf[0x69] = 0x02; - pci_conf[0x70] = 0x80; - pci_conf[0x76] = 0x0c; - pci_conf[0x77] = 0x0c; - pci_conf[0x78] = 0x02; - pci_conf[0x79] = 0x00; - pci_conf[0x80] = 0x00; - pci_conf[0x82] = 0x00; - pci_conf[0xa0] = 0x08; - pci_conf[0xa2] = 0x00; - pci_conf[0xa3] = 0x00; - pci_conf[0xa4] = 0x00; - pci_conf[0xa5] = 0x00; - pci_conf[0xa6] = 0x00; - pci_conf[0xa7] = 0x00; - pci_conf[0xa8] = 0x0f; - pci_conf[0xaa] = 0x00; - pci_conf[0xab] = 0x00; - pci_conf[0xac] = 0x00; - pci_conf[0xae] = 0x00; -} - -static const VMStateDescription vmstate_piix4 = { - .name = "PIIX4", - .version_id = 2, - .minimum_version_id = 2, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, PIIX4State), - VMSTATE_END_OF_LIST() - } -}; - -static void piix4_realize(PCIDevice *dev, Error **errp) -{ - PIIX4State *d = PIIX4_PCI_DEVICE(dev); - - if (!isa_bus_new(DEVICE(d), pci_address_space(dev), - pci_address_space_io(dev), errp)) { - return; - } - piix4_dev = &d->dev; - qemu_register_reset(piix4_reset, d); -} - -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) -{ - PCIDevice *d; - - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4"); - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); - return d->devfn; -} - -static void piix4_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = piix4_realize; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0; - k->class_id = PCI_CLASS_BRIDGE_ISA; - dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_piix4; - /* - * Reason: part of PIIX4 southbridge, needs to be wired up, - * e.g. by mips_malta_init() - */ - dc->cannot_instantiate_with_device_add_yet = true; - dc->hotpluggable = false; -} - -static const TypeInfo piix4_info = { - .name = TYPE_PIIX4_PCI_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PIIX4State), - .class_init = piix4_class_init, -}; - -static void piix4_register_types(void) -{ - type_register_static(&piix4_info); -} - -type_init(piix4_register_types) diff --git a/qemu/hw/isa/vt82c686.c b/qemu/hw/isa/vt82c686.c deleted file mode 100644 index 41d5254f8..000000000 --- a/qemu/hw/isa/vt82c686.c +++ /dev/null @@ -1,515 +0,0 @@ -/* - * VT82C686B south bridge support - * - * Copyright (c) 2008 yajin (yajin@vm-kernel.org) - * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) - * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) - * This code is licensed under the GNU GPL v2. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include "qemu/osdep.h" -#include "hw/hw.h" -#include "hw/i386/pc.h" -#include "hw/isa/vt82c686.h" -#include "hw/i2c/i2c.h" -#include "hw/i2c/smbus.h" -#include "hw/pci/pci.h" -#include "hw/isa/isa.h" -#include "hw/sysbus.h" -#include "hw/mips/mips.h" -#include "hw/isa/apm.h" -#include "hw/acpi/acpi.h" -#include "hw/i2c/pm_smbus.h" -#include "sysemu/sysemu.h" -#include "qemu/timer.h" -#include "exec/address-spaces.h" - -//#define DEBUG_VT82C686B - -#ifdef DEBUG_VT82C686B -#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) -#else -#define DPRINTF(fmt, ...) -#endif - -typedef struct SuperIOConfig -{ - uint8_t config[0x100]; - uint8_t index; - uint8_t data; -} SuperIOConfig; - -typedef struct VT82C686BState { - PCIDevice dev; - MemoryRegion superio; - SuperIOConfig superio_conf; -} VT82C686BState; - -#define TYPE_VT82C686B_DEVICE "VT82C686B" -#define VT82C686B_DEVICE(obj) \ - OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE) - -static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, - unsigned size) -{ - SuperIOConfig *superio_conf = opaque; - - DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); - if (addr == 0x3f0) { - superio_conf->index = data & 0xff; - } else { - bool can_write = true; - /* 0x3f1 */ - switch (superio_conf->index) { - case 0x00 ... 0xdf: - case 0xe4: - case 0xe5: - case 0xe9 ... 0xed: - case 0xf3: - case 0xf5: - case 0xf7: - case 0xf9 ... 0xfb: - case 0xfd ... 0xff: - can_write = false; - break; - case 0xe7: - if ((data & 0xff) != 0xfe) { - DPRINTF("change uart 1 base. unsupported yet\n"); - can_write = false; - } - break; - case 0xe8: - if ((data & 0xff) != 0xbe) { - DPRINTF("change uart 2 base. unsupported yet\n"); - can_write = false; - } - break; - default: - break; - - } - if (can_write) { - superio_conf->config[superio_conf->index] = data & 0xff; - } - } -} - -static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) -{ - SuperIOConfig *superio_conf = opaque; - - DPRINTF("superio_ioport_readb address 0x%x\n", addr); - return (superio_conf->config[superio_conf->index]); -} - -static const MemoryRegionOps superio_ops = { - .read = superio_ioport_readb, - .write = superio_ioport_writeb, - .endianness = DEVICE_NATIVE_ENDIAN, - .impl = { - .min_access_size = 1, - .max_access_size = 1, - }, -}; - -static void vt82c686b_reset(void * opaque) -{ - PCIDevice *d = opaque; - uint8_t *pci_conf = d->config; - VT82C686BState *vt82c = VT82C686B_DEVICE(d); - - pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); - pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); - pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); - - pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ - pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ - pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ - pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ - pci_conf[0x59] = 0x04; - pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ - pci_conf[0x5f] = 0x04; - pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ - - vt82c->superio_conf.config[0xe0] = 0x3c; - vt82c->superio_conf.config[0xe2] = 0x03; - vt82c->superio_conf.config[0xe3] = 0xfc; - vt82c->superio_conf.config[0xe6] = 0xde; - vt82c->superio_conf.config[0xe7] = 0xfe; - vt82c->superio_conf.config[0xe8] = 0xbe; -} - -/* write config pci function0 registers. PCI-ISA bridge */ -static void vt82c686b_write_config(PCIDevice * d, uint32_t address, - uint32_t val, int len) -{ - VT82C686BState *vt686 = VT82C686B_DEVICE(d); - - DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", - address, val, len); - - pci_default_write_config(d, address, val, len); - if (address == 0x85) { /* enable or disable super IO configure */ - memory_region_set_enabled(&vt686->superio, val & 0x2); - } -} - -#define ACPI_DBG_IO_ADDR 0xb044 - -typedef struct VT686PMState { - PCIDevice dev; - MemoryRegion io; - ACPIREGS ar; - APMState apm; - PMSMBus smb; - uint32_t smb_io_base; -} VT686PMState; - -typedef struct VT686AC97State { - PCIDevice dev; -} VT686AC97State; - -typedef struct VT686MC97State { - PCIDevice dev; -} VT686MC97State; - -#define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM" -#define VT82C686B_PM_DEVICE(obj) \ - OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE) - -#define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97" -#define VT82C686B_MC97_DEVICE(obj) \ - OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE) - -#define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97" -#define VT82C686B_AC97_DEVICE(obj) \ - OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE) - -static void pm_update_sci(VT686PMState *s) -{ - int sci_level, pmsts; - - pmsts = acpi_pm1_evt_get_sts(&s->ar); - sci_level = (((pmsts & s->ar.pm1.evt.en) & - (ACPI_BITMASK_RT_CLOCK_ENABLE | - ACPI_BITMASK_POWER_BUTTON_ENABLE | - ACPI_BITMASK_GLOBAL_LOCK_ENABLE | - ACPI_BITMASK_TIMER_ENABLE)) != 0); - pci_set_irq(&s->dev, sci_level); - /* schedule a timer interruption if needed */ - acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && - !(pmsts & ACPI_BITMASK_TIMER_STATUS)); -} - -static void pm_tmr_timer(ACPIREGS *ar) -{ - VT686PMState *s = container_of(ar, VT686PMState, ar); - pm_update_sci(s); -} - -static void pm_io_space_update(VT686PMState *s) -{ - uint32_t pm_io_base; - - pm_io_base = pci_get_long(s->dev.config + 0x40); - pm_io_base &= 0xffc0; - - memory_region_transaction_begin(); - memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); - memory_region_set_address(&s->io, pm_io_base); - memory_region_transaction_commit(); -} - -static void pm_write_config(PCIDevice *d, - uint32_t address, uint32_t val, int len) -{ - DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", - address, val, len); - pci_default_write_config(d, address, val, len); -} - -static int vmstate_acpi_post_load(void *opaque, int version_id) -{ - VT686PMState *s = opaque; - - pm_io_space_update(s); - return 0; -} - -static const VMStateDescription vmstate_acpi = { - .name = "vt82c686b_pm", - .version_id = 1, - .minimum_version_id = 1, - .post_load = vmstate_acpi_post_load, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, VT686PMState), - VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), - VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), - VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), - VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), - VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), - VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), - VMSTATE_END_OF_LIST() - } -}; - -/* - * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() - * just register a PCI device now, functionalities will be implemented later. - */ - -static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) -{ - VT686AC97State *s = VT82C686B_AC97_DEVICE(dev); - uint8_t *pci_conf = s->dev.config; - - pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | - PCI_COMMAND_PARITY); - pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | - PCI_STATUS_DEVSEL_MEDIUM); - pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); -} - -void vt82c686b_ac97_init(PCIBus *bus, int devfn) -{ - PCIDevice *dev; - - dev = pci_create(bus, devfn, TYPE_VT82C686B_AC97_DEVICE); - qdev_init_nofail(&dev->qdev); -} - -static void via_ac97_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = vt82c686b_ac97_realize; - k->vendor_id = PCI_VENDOR_ID_VIA; - k->device_id = PCI_DEVICE_ID_VIA_AC97; - k->revision = 0x50; - k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; - set_bit(DEVICE_CATEGORY_SOUND, dc->categories); - dc->desc = "AC97"; -} - -static const TypeInfo via_ac97_info = { - .name = TYPE_VT82C686B_AC97_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(VT686AC97State), - .class_init = via_ac97_class_init, -}; - -static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) -{ - VT686MC97State *s = VT82C686B_MC97_DEVICE(dev); - uint8_t *pci_conf = s->dev.config; - - pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | - PCI_COMMAND_VGA_PALETTE); - pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); - pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); -} - -void vt82c686b_mc97_init(PCIBus *bus, int devfn) -{ - PCIDevice *dev; - - dev = pci_create(bus, devfn, TYPE_VT82C686B_MC97_DEVICE); - qdev_init_nofail(&dev->qdev); -} - -static void via_mc97_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = vt82c686b_mc97_realize; - k->vendor_id = PCI_VENDOR_ID_VIA; - k->device_id = PCI_DEVICE_ID_VIA_MC97; - k->class_id = PCI_CLASS_COMMUNICATION_OTHER; - k->revision = 0x30; - set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); - dc->desc = "MC97"; -} - -static const TypeInfo via_mc97_info = { - .name = TYPE_VT82C686B_MC97_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(VT686MC97State), - .class_init = via_mc97_class_init, -}; - -/* vt82c686 pm init */ -static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) -{ - VT686PMState *s = VT82C686B_PM_DEVICE(dev); - uint8_t *pci_conf; - - pci_conf = s->dev.config; - pci_set_word(pci_conf + PCI_COMMAND, 0); - pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | - PCI_STATUS_DEVSEL_MEDIUM); - - /* 0x48-0x4B is Power Management I/O Base */ - pci_set_long(pci_conf + 0x48, 0x00000001); - - /* SMB ports:0xeee0~0xeeef */ - s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); - pci_conf[0x90] = s->smb_io_base | 1; - pci_conf[0x91] = s->smb_io_base >> 8; - pci_conf[0xd2] = 0x90; - pm_smbus_init(&s->dev.qdev, &s->smb); - memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); - - apm_init(dev, &s->apm, NULL, s); - - memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); - memory_region_set_enabled(&s->io, false); - memory_region_add_subregion(get_system_io(), 0, &s->io); - - acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); - acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); - acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); -} - -I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq) -{ - PCIDevice *dev; - VT686PMState *s; - - dev = pci_create(bus, devfn, TYPE_VT82C686B_PM_DEVICE); - qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); - - s = VT82C686B_PM_DEVICE(dev); - - qdev_init_nofail(&dev->qdev); - - return s->smb.smbus; -} - -static Property via_pm_properties[] = { - DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), - DEFINE_PROP_END_OF_LIST(), -}; - -static void via_pm_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = vt82c686b_pm_realize; - k->config_write = pm_write_config; - k->vendor_id = PCI_VENDOR_ID_VIA; - k->device_id = PCI_DEVICE_ID_VIA_ACPI; - k->class_id = PCI_CLASS_BRIDGE_OTHER; - k->revision = 0x40; - dc->desc = "PM"; - dc->vmsd = &vmstate_acpi; - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->props = via_pm_properties; -} - -static const TypeInfo via_pm_info = { - .name = TYPE_VT82C686B_PM_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(VT686PMState), - .class_init = via_pm_class_init, -}; - -static const VMStateDescription vmstate_via = { - .name = "vt82c686b", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, VT82C686BState), - VMSTATE_END_OF_LIST() - } -}; - -/* init the PCI-to-ISA bridge */ -static void vt82c686b_realize(PCIDevice *d, Error **errp) -{ - VT82C686BState *vt82c = VT82C686B_DEVICE(d); - uint8_t *pci_conf; - ISABus *isa_bus; - uint8_t *wmask; - int i; - - isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), - pci_address_space_io(d), errp); - if (!isa_bus) { - return; - } - - pci_conf = d->config; - pci_config_set_prog_interface(pci_conf, 0x0); - - wmask = d->wmask; - for (i = 0x00; i < 0xff; i++) { - if (i<=0x03 || (i>=0x08 && i<=0x3f)) { - wmask[i] = 0x00; - } - } - - memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, - &vt82c->superio_conf, "superio", 2); - memory_region_set_enabled(&vt82c->superio, false); - /* The floppy also uses 0x3f0 and 0x3f1. - * But we do not emulate a floppy, so just set it here. */ - memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, - &vt82c->superio); - - qemu_register_reset(vt82c686b_reset, d); -} - -ISABus *vt82c686b_init(PCIBus *bus, int devfn) -{ - PCIDevice *d; - - d = pci_create_simple_multifunction(bus, devfn, true, - TYPE_VT82C686B_DEVICE); - - return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); -} - -static void via_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = vt82c686b_realize; - k->config_write = vt82c686b_write_config; - k->vendor_id = PCI_VENDOR_ID_VIA; - k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; - k->class_id = PCI_CLASS_BRIDGE_ISA; - k->revision = 0x40; - dc->desc = "ISA bridge"; - dc->vmsd = &vmstate_via; - /* - * Reason: part of VIA VT82C686 southbridge, needs to be wired up, - * e.g. by mips_fulong2e_init() - */ - dc->cannot_instantiate_with_device_add_yet = true; -} - -static const TypeInfo via_info = { - .name = TYPE_VT82C686B_DEVICE, - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(VT82C686BState), - .class_init = via_class_init, -}; - -static void vt82c686b_register_types(void) -{ - type_register_static(&via_ac97_info); - type_register_static(&via_mc97_info); - type_register_static(&via_pm_info); - type_register_static(&via_info); -} - -type_init(vt82c686b_register_types) -- cgit 1.2.3-korg