From e09b41010ba33a20a87472ee821fa407a5b8da36 Mon Sep 17 00:00:00 2001 From: José Pekkarinen Date: Mon, 11 Apr 2016 10:41:07 +0300 Subject: These changes are the raw update to linux-4.4.6-rt14. Kernel sources are taken from kernel.org, and rt patch from the rt wiki download page. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit During the rebasing, the following patch collided: Force tick interrupt and get rid of softirq magic(I70131fb85). Collisions have been removed because its logic was found on the source already. Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769 Signed-off-by: José Pekkarinen --- kernel/drivers/clk/qcom/Kconfig | 9 + kernel/drivers/clk/qcom/Makefile | 1 + kernel/drivers/clk/qcom/clk-branch.c | 2 +- kernel/drivers/clk/qcom/clk-pll.c | 93 ++++- kernel/drivers/clk/qcom/clk-pll.h | 1 + kernel/drivers/clk/qcom/clk-rcg.c | 293 ++++++++++++++-- kernel/drivers/clk/qcom/clk-rcg.h | 8 +- kernel/drivers/clk/qcom/clk-rcg2.c | 265 +++++++++++---- kernel/drivers/clk/qcom/common.c | 45 ++- kernel/drivers/clk/qcom/common.h | 4 +- kernel/drivers/clk/qcom/gcc-apq8084.c | 61 +++- kernel/drivers/clk/qcom/gcc-ipq806x.c | 605 ++++++++++++++++++++++++++++++++- kernel/drivers/clk/qcom/gcc-msm8660.c | 15 +- kernel/drivers/clk/qcom/gcc-msm8916.c | 593 ++++++++++++++++++++++++++++++-- kernel/drivers/clk/qcom/gcc-msm8960.c | 32 +- kernel/drivers/clk/qcom/gcc-msm8974.c | 26 +- kernel/drivers/clk/qcom/gdsc.c | 237 +++++++++++++ kernel/drivers/clk/qcom/gdsc.h | 68 ++++ kernel/drivers/clk/qcom/lcc-ipq806x.c | 13 +- kernel/drivers/clk/qcom/lcc-msm8960.c | 15 +- kernel/drivers/clk/qcom/mmcc-apq8084.c | 131 +++++-- kernel/drivers/clk/qcom/mmcc-msm8960.c | 438 ++++++++++++++++++++++-- kernel/drivers/clk/qcom/mmcc-msm8974.c | 108 ++++-- 23 files changed, 2773 insertions(+), 290 deletions(-) create mode 100644 kernel/drivers/clk/qcom/gdsc.c create mode 100644 kernel/drivers/clk/qcom/gdsc.h (limited to 'kernel/drivers/clk/qcom') diff --git a/kernel/drivers/clk/qcom/Kconfig b/kernel/drivers/clk/qcom/Kconfig index 59d16668b..ee4c83aab 100644 --- a/kernel/drivers/clk/qcom/Kconfig +++ b/kernel/drivers/clk/qcom/Kconfig @@ -1,3 +1,7 @@ +config QCOM_GDSC + bool + select PM_GENERIC_DOMAINS if PM + config COMMON_CLK_QCOM tristate "Support for Qualcomm's clock controllers" depends on OF @@ -7,6 +11,7 @@ config COMMON_CLK_QCOM config APQ_GCC_8084 tristate "APQ8084 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on apq8084 devices. @@ -16,6 +21,7 @@ config APQ_GCC_8084 config APQ_MMCC_8084 tristate "APQ8084 Multimedia Clock Controller" select APQ_GCC_8084 + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on apq8084 devices. @@ -49,6 +55,7 @@ config MSM_GCC_8660 config MSM_GCC_8916 tristate "MSM8916 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on msm8916 devices. @@ -83,6 +90,7 @@ config MSM_MMCC_8960 config MSM_GCC_8974 tristate "MSM8974 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on msm8974 devices. @@ -92,6 +100,7 @@ config MSM_GCC_8974 config MSM_MMCC_8974 tristate "MSM8974 Multimedia Clock Controller" select MSM_GCC_8974 + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on msm8974 devices. diff --git a/kernel/drivers/clk/qcom/Makefile b/kernel/drivers/clk/qcom/Makefile index 50b337a24..fe6252349 100644 --- a/kernel/drivers/clk/qcom/Makefile +++ b/kernel/drivers/clk/qcom/Makefile @@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o clk-qcom-y += clk-regmap-divider.o clk-qcom-y += clk-regmap-mux.o clk-qcom-y += reset.o +clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o diff --git a/kernel/drivers/clk/qcom/clk-branch.c b/kernel/drivers/clk/qcom/clk-branch.c index 6b4d2bcb1..26f7af315 100644 --- a/kernel/drivers/clk/qcom/clk-branch.c +++ b/kernel/drivers/clk/qcom/clk-branch.c @@ -75,7 +75,7 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling, bool (check_halt)(const struct clk_branch *, bool)) { bool voted = br->halt_check & BRANCH_VOTED; - const char *name = __clk_get_name(br->clkr.hw.clk); + const char *name = clk_hw_get_name(&br->clkr.hw); /* Skip checking halt bit if the clock is in hardware gated mode */ if (clk_branch_in_hwcg_mode(br)) diff --git a/kernel/drivers/clk/qcom/clk-pll.c b/kernel/drivers/clk/qcom/clk-pll.c index 245d5063a..5b940d629 100644 --- a/kernel/drivers/clk/qcom/clk-pll.c +++ b/kernel/drivers/clk/qcom/clk-pll.c @@ -135,19 +135,19 @@ struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate) return NULL; } -static long -clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p) +static int +clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_pll *pll = to_clk_pll(hw); const struct pll_freq_tbl *f; - f = find_freq(pll->freq_tbl, rate); + f = find_freq(pll->freq_tbl, req->rate); if (!f) - return clk_pll_recalc_rate(hw, *p_rate); + req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate); + else + req->rate = f->freq; - return f->freq; + return 0; } static int @@ -194,7 +194,7 @@ static int wait_for_pll(struct clk_pll *pll) u32 val; int count; int ret; - const char *name = __clk_get_name(pll->clkr.hw.clk); + const char *name = clk_hw_get_name(&pll->clkr.hw); /* Wait for pll to enable. */ for (count = 200; count > 0; count--) { @@ -213,7 +213,7 @@ static int wait_for_pll(struct clk_pll *pll) static int clk_pll_vote_enable(struct clk_hw *hw) { int ret; - struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk))); + struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw)); ret = clk_enable_regmap(hw); if (ret) @@ -292,3 +292,78 @@ void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, clk_pll_set_fsm_mode(pll, regmap, 0); } EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp); + +static int clk_pll_sr2_enable(struct clk_hw *hw) +{ + struct clk_pll *pll = to_clk_pll(hw); + int ret; + u32 mode; + + ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); + if (ret) + return ret; + + /* Disable PLL bypass mode. */ + ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, + PLL_BYPASSNL); + if (ret) + return ret; + + /* + * H/W requires a 5us delay between disabling the bypass and + * de-asserting the reset. Delay 10us just to be safe. + */ + udelay(10); + + /* De-assert active-low PLL reset. */ + ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, + PLL_RESET_N); + if (ret) + return ret; + + ret = wait_for_pll(pll); + if (ret) + return ret; + + /* Enable PLL output. */ + return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, + PLL_OUTCTRL); +} + +static int +clk_pll_sr2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) +{ + struct clk_pll *pll = to_clk_pll(hw); + const struct pll_freq_tbl *f; + bool enabled; + u32 mode; + u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; + + f = find_freq(pll->freq_tbl, rate); + if (!f) + return -EINVAL; + + regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); + enabled = (mode & enable_mask) == enable_mask; + + if (enabled) + clk_pll_disable(hw); + + regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l); + regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m); + regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n); + + if (enabled) + clk_pll_sr2_enable(hw); + + return 0; +} + +const struct clk_ops clk_pll_sr2_ops = { + .enable = clk_pll_sr2_enable, + .disable = clk_pll_disable, + .set_rate = clk_pll_sr2_set_rate, + .recalc_rate = clk_pll_recalc_rate, + .determine_rate = clk_pll_determine_rate, +}; +EXPORT_SYMBOL_GPL(clk_pll_sr2_ops); diff --git a/kernel/drivers/clk/qcom/clk-pll.h b/kernel/drivers/clk/qcom/clk-pll.h index c9c0cda30..ffd0c63bd 100644 --- a/kernel/drivers/clk/qcom/clk-pll.h +++ b/kernel/drivers/clk/qcom/clk-pll.h @@ -62,6 +62,7 @@ struct clk_pll { extern const struct clk_ops clk_pll_ops; extern const struct clk_ops clk_pll_vote_ops; +extern const struct clk_ops clk_pll_sr2_ops; #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr) diff --git a/kernel/drivers/clk/qcom/clk-rcg.c b/kernel/drivers/clk/qcom/clk-rcg.c index 7b3d62674..bfbb28f45 100644 --- a/kernel/drivers/clk/qcom/clk-rcg.c +++ b/kernel/drivers/clk/qcom/clk-rcg.c @@ -45,7 +45,7 @@ static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns) static u8 clk_rcg_get_parent(struct clk_hw *hw) { struct clk_rcg *rcg = to_clk_rcg(hw); - int num_parents = __clk_get_num_parents(hw->clk); + int num_parents = clk_hw_get_num_parents(hw); u32 ns; int i, ret; @@ -59,7 +59,7 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw) err: pr_debug("%s: Clock %s has invalid parent, using default.\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); return 0; } @@ -72,7 +72,7 @@ static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw) { struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); - int num_parents = __clk_get_num_parents(hw->clk); + int num_parents = clk_hw_get_num_parents(hw); u32 ns, reg; int bank; int i, ret; @@ -95,7 +95,7 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw) err: pr_debug("%s: Clock %s has invalid parent, using default.\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); return 0; } @@ -404,14 +404,12 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) return calc_rate(parent_rate, m, n, mode, pre_div); } -static long _freq_tbl_determine_rate(struct clk_hw *hw, - const struct freq_tbl *f, unsigned long rate, - unsigned long min_rate, unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p_hw, +static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, + struct clk_rate_request *req, const struct parent_map *parent_map) { - unsigned long clk_flags; - struct clk *p; + unsigned long clk_flags, rate = req->rate; + struct clk_hw *p; int index; f = qcom_find_freq(f, rate); @@ -422,8 +420,8 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, if (index < 0) return index; - clk_flags = __clk_get_flags(hw->clk); - p = clk_get_parent_by_index(hw->clk, index); + clk_flags = clk_hw_get_flags(hw); + p = clk_hw_get_parent_by_index(hw, index); if (clk_flags & CLK_SET_RATE_PARENT) { rate = rate * f->pre_div; if (f->n) { @@ -433,27 +431,26 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, rate = tmp; } } else { - rate = __clk_get_rate(p); + rate = clk_hw_get_rate(p); } - *p_hw = __clk_get_hw(p); - *p_rate = rate; + req->best_parent_hw = p; + req->best_parent_rate = rate; + req->rate = f->freq; - return f->freq; + return 0; } -static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p) +static int clk_rcg_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_rcg *rcg = to_clk_rcg(hw); - return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate, - max_rate, p_rate, p, rcg->s.parent_map); + return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, + rcg->s.parent_map); } -static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p) +static int clk_dyn_rcg_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); u32 reg; @@ -464,24 +461,22 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, bank = reg_to_bank(rcg, reg); s = &rcg->s[bank]; - return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate, - max_rate, p_rate, p, s->parent_map); + return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map); } -static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p_hw) +static int clk_rcg_bypass_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_rcg *rcg = to_clk_rcg(hw); const struct freq_tbl *f = rcg->freq_tbl; - struct clk *p; + struct clk_hw *p; int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src); - p = clk_get_parent_by_index(hw->clk, index); - *p_hw = __clk_get_hw(p); - *p_rate = __clk_round_rate(p, rate); + req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); + req->best_parent_rate = clk_hw_round_rate(p, req->rate); + req->rate = req->best_parent_rate; - return *p_rate; + return 0; } static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f) @@ -547,6 +542,200 @@ static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate, return __clk_rcg_set_rate(rcg, rcg->freq_tbl); } +static int clk_rcg_bypass2_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *p; + + p = req->best_parent_hw; + req->best_parent_rate = clk_hw_round_rate(p, req->rate); + req->rate = req->best_parent_rate; + + return 0; +} + +static int clk_rcg_bypass2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg *rcg = to_clk_rcg(hw); + struct freq_tbl f = { 0 }; + u32 ns, src; + int i, ret, num_parents = clk_hw_get_num_parents(hw); + + ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); + if (ret) + return ret; + + src = ns_to_src(&rcg->s, ns); + f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1; + + for (i = 0; i < num_parents; i++) { + if (src == rcg->s.parent_map[i].cfg) { + f.src = rcg->s.parent_map[i].src; + return __clk_rcg_set_rate(rcg, &f); + } + } + + return -EINVAL; +} + +static int clk_rcg_bypass2_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate, u8 index) +{ + /* Read the hardware to determine parent during set_rate */ + return clk_rcg_bypass2_set_rate(hw, rate, parent_rate); +} + +struct frac_entry { + int num; + int den; +}; + +static const struct frac_entry pixel_table[] = { + { 1, 2 }, + { 1, 3 }, + { 3, 16 }, + { } +}; + +static int clk_rcg_pixel_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + int delta = 100000; + const struct frac_entry *frac = pixel_table; + unsigned long request, src_rate; + + for (; frac->num; frac++) { + request = (req->rate * frac->den) / frac->num; + + src_rate = clk_hw_round_rate(req->best_parent_hw, request); + + if ((src_rate < (request - delta)) || + (src_rate > (request + delta))) + continue; + + req->best_parent_rate = src_rate; + req->rate = (src_rate * frac->num) / frac->den; + return 0; + } + + return -EINVAL; +} + +static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg *rcg = to_clk_rcg(hw); + int delta = 100000; + const struct frac_entry *frac = pixel_table; + unsigned long request; + struct freq_tbl f = { 0 }; + u32 ns, src; + int i, ret, num_parents = clk_hw_get_num_parents(hw); + + ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); + if (ret) + return ret; + + src = ns_to_src(&rcg->s, ns); + f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1; + + for (i = 0; i < num_parents; i++) { + if (src == rcg->s.parent_map[i].cfg) { + f.src = rcg->s.parent_map[i].src; + break; + } + } + + /* let us find appropriate m/n values for this */ + for (; frac->num; frac++) { + request = (rate * frac->den) / frac->num; + + if ((parent_rate < (request - delta)) || + (parent_rate > (request + delta))) + continue; + + f.m = frac->num; + f.n = frac->den; + + return __clk_rcg_set_rate(rcg, &f); + } + + return -EINVAL; +} + +static int clk_rcg_pixel_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate, u8 index) +{ + return clk_rcg_pixel_set_rate(hw, rate, parent_rate); +} + +static int clk_rcg_esc_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_rcg *rcg = to_clk_rcg(hw); + int pre_div_max = BIT(rcg->p.pre_div_width); + int div; + unsigned long src_rate; + + if (req->rate == 0) + return -EINVAL; + + src_rate = clk_hw_get_rate(req->best_parent_hw); + + div = src_rate / req->rate; + + if (div >= 1 && div <= pre_div_max) { + req->best_parent_rate = src_rate; + req->rate = src_rate / div; + return 0; + } + + return -EINVAL; +} + +static int clk_rcg_esc_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg *rcg = to_clk_rcg(hw); + struct freq_tbl f = { 0 }; + int pre_div_max = BIT(rcg->p.pre_div_width); + int div; + u32 ns; + int i, ret, num_parents = clk_hw_get_num_parents(hw); + + if (rate == 0) + return -EINVAL; + + ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); + if (ret) + return ret; + + ns = ns_to_src(&rcg->s, ns); + + for (i = 0; i < num_parents; i++) { + if (ns == rcg->s.parent_map[i].cfg) { + f.src = rcg->s.parent_map[i].src; + break; + } + } + + div = parent_rate / rate; + + if (div >= 1 && div <= pre_div_max) { + f.pre_div = div; + return __clk_rcg_set_rate(rcg, &f); + } + + return -EINVAL; +} + +static int clk_rcg_esc_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate, u8 index) +{ + return clk_rcg_esc_set_rate(hw, rate, parent_rate); +} + /* * This type of clock has a glitch-free mux that switches between the output of * the M/N counter and an always on clock source (XO). When clk_set_rate() is @@ -644,6 +833,42 @@ const struct clk_ops clk_rcg_bypass_ops = { }; EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops); +const struct clk_ops clk_rcg_bypass2_ops = { + .enable = clk_enable_regmap, + .disable = clk_disable_regmap, + .get_parent = clk_rcg_get_parent, + .set_parent = clk_rcg_set_parent, + .recalc_rate = clk_rcg_recalc_rate, + .determine_rate = clk_rcg_bypass2_determine_rate, + .set_rate = clk_rcg_bypass2_set_rate, + .set_rate_and_parent = clk_rcg_bypass2_set_rate_and_parent, +}; +EXPORT_SYMBOL_GPL(clk_rcg_bypass2_ops); + +const struct clk_ops clk_rcg_pixel_ops = { + .enable = clk_enable_regmap, + .disable = clk_disable_regmap, + .get_parent = clk_rcg_get_parent, + .set_parent = clk_rcg_set_parent, + .recalc_rate = clk_rcg_recalc_rate, + .determine_rate = clk_rcg_pixel_determine_rate, + .set_rate = clk_rcg_pixel_set_rate, + .set_rate_and_parent = clk_rcg_pixel_set_rate_and_parent, +}; +EXPORT_SYMBOL_GPL(clk_rcg_pixel_ops); + +const struct clk_ops clk_rcg_esc_ops = { + .enable = clk_enable_regmap, + .disable = clk_disable_regmap, + .get_parent = clk_rcg_get_parent, + .set_parent = clk_rcg_set_parent, + .recalc_rate = clk_rcg_recalc_rate, + .determine_rate = clk_rcg_esc_determine_rate, + .set_rate = clk_rcg_esc_set_rate, + .set_rate_and_parent = clk_rcg_esc_set_rate_and_parent, +}; +EXPORT_SYMBOL_GPL(clk_rcg_esc_ops); + const struct clk_ops clk_rcg_lcc_ops = { .enable = clk_rcg_lcc_enable, .disable = clk_rcg_lcc_disable, diff --git a/kernel/drivers/clk/qcom/clk-rcg.h b/kernel/drivers/clk/qcom/clk-rcg.h index 56028bb31..4b1e94bdf 100644 --- a/kernel/drivers/clk/qcom/clk-rcg.h +++ b/kernel/drivers/clk/qcom/clk-rcg.h @@ -106,6 +106,9 @@ struct clk_rcg { extern const struct clk_ops clk_rcg_ops; extern const struct clk_ops clk_rcg_bypass_ops; +extern const struct clk_ops clk_rcg_bypass2_ops; +extern const struct clk_ops clk_rcg_pixel_ops; +extern const struct clk_ops clk_rcg_esc_ops; extern const struct clk_ops clk_rcg_lcc_ops; #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) @@ -153,8 +156,8 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @hid_width: number of bits in half integer divider * @parent_map: map from software's parent index to hardware's src_sel field * @freq_tbl: frequency table + * @current_freq: last cached frequency when using branches with shared RCGs * @clkr: regmap clock handle - * @lock: register lock * */ struct clk_rcg2 { @@ -163,14 +166,17 @@ struct clk_rcg2 { u8 hid_width; const struct parent_map *parent_map; const struct freq_tbl *freq_tbl; + unsigned long current_freq; struct clk_regmap clkr; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) extern const struct clk_ops clk_rcg2_ops; +extern const struct clk_ops clk_rcg2_shared_ops; extern const struct clk_ops clk_edp_pixel_ops; extern const struct clk_ops clk_byte_ops; +extern const struct clk_ops clk_byte2_ops; extern const struct clk_ops clk_pixel_ops; #endif diff --git a/kernel/drivers/clk/qcom/clk-rcg2.c b/kernel/drivers/clk/qcom/clk-rcg2.c index 92936f091..b544bb302 100644 --- a/kernel/drivers/clk/qcom/clk-rcg2.c +++ b/kernel/drivers/clk/qcom/clk-rcg2.c @@ -63,7 +63,7 @@ static int clk_rcg2_is_enabled(struct clk_hw *hw) static u8 clk_rcg2_get_parent(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - int num_parents = __clk_get_num_parents(hw->clk); + int num_parents = clk_hw_get_num_parents(hw); u32 cfg; int i, ret; @@ -80,7 +80,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) err: pr_debug("%s: Clock %s has invalid parent, using default.\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); return 0; } @@ -89,7 +89,7 @@ static int update_config(struct clk_rcg2 *rcg) int count, ret; u32 cmd; struct clk_hw *hw = &rcg->clkr.hw; - const char *name = __clk_get_name(hw->clk); + const char *name = clk_hw_get_name(hw); ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, CMD_UPDATE, CMD_UPDATE); @@ -176,12 +176,11 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) return calc_rate(parent_rate, m, n, mode, hid_div); } -static long _freq_tbl_determine_rate(struct clk_hw *hw, - const struct freq_tbl *f, unsigned long rate, - unsigned long *p_rate, struct clk_hw **p_hw) +static int _freq_tbl_determine_rate(struct clk_hw *hw, + const struct freq_tbl *f, struct clk_rate_request *req) { - unsigned long clk_flags; - struct clk *p; + unsigned long clk_flags, rate = req->rate; + struct clk_hw *p; struct clk_rcg2 *rcg = to_clk_rcg2(hw); int index; @@ -193,8 +192,8 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, if (index < 0) return index; - clk_flags = __clk_get_flags(hw->clk); - p = clk_get_parent_by_index(hw->clk, index); + clk_flags = clk_hw_get_flags(hw); + p = clk_hw_get_parent_by_index(hw, index); if (clk_flags & CLK_SET_RATE_PARENT) { if (f->pre_div) { rate /= 2; @@ -208,21 +207,21 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw, rate = tmp; } } else { - rate = __clk_get_rate(p); + rate = clk_hw_get_rate(p); } - *p_hw = __clk_get_hw(p); - *p_rate = rate; + req->best_parent_hw = p; + req->best_parent_rate = rate; + req->rate = f->freq; - return f->freq; + return 0; } -static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p) +static int clk_rcg2_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p); + return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req); } static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) @@ -301,6 +300,85 @@ const struct clk_ops clk_rcg2_ops = { }; EXPORT_SYMBOL_GPL(clk_rcg2_ops); +static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + const char *name = clk_hw_get_name(hw); + int ret, count; + + /* force enable RCG */ + ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, CMD_ROOT_EN); + if (ret) + return ret; + + /* wait for RCG to turn ON */ + for (count = 500; count > 0; count--) { + ret = clk_rcg2_is_enabled(hw); + if (ret) + break; + udelay(1); + } + if (!count) + pr_err("%s: RCG did not turn on\n", name); + + /* set clock rate */ + ret = __clk_rcg2_set_rate(hw, rate); + if (ret) + return ret; + + /* clear force enable RCG */ + return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, 0); +} + +static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* cache the rate */ + rcg->current_freq = rate; + + if (!__clk_is_enabled(hw->clk)) + return 0; + + return clk_rcg2_shared_force_enable(hw, rcg->current_freq); +} + +static unsigned long +clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + return rcg->current_freq = clk_rcg2_recalc_rate(hw, parent_rate); +} + +static int clk_rcg2_shared_enable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + return clk_rcg2_shared_force_enable(hw, rcg->current_freq); +} + +static void clk_rcg2_shared_disable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* switch to XO, which is the lowest entry in the freq table */ + clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0); +} + +const struct clk_ops clk_rcg2_shared_ops = { + .enable = clk_rcg2_shared_enable, + .disable = clk_rcg2_shared_disable, + .get_parent = clk_rcg2_get_parent, + .recalc_rate = clk_rcg2_shared_recalc_rate, + .determine_rate = clk_rcg2_determine_rate, + .set_rate = clk_rcg2_shared_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops); + struct frac_entry { int num; int den; @@ -374,35 +452,33 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw, return clk_edp_pixel_set_rate(hw, rate, parent_rate); } -static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p) +static int clk_edp_pixel_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; const struct frac_entry *frac; int delta = 100000; - s64 src_rate = *p_rate; s64 request; u32 mask = BIT(rcg->hid_width) - 1; u32 hid_div; int index = qcom_find_src_index(hw, rcg->parent_map, f->src); /* Force the correct parent */ - *p = __clk_get_hw(clk_get_parent_by_index(hw->clk, index)); + req->best_parent_hw = clk_hw_get_parent_by_index(hw, index); + req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw); - if (src_rate == 810000000) + if (req->best_parent_rate == 810000000) frac = frac_table_810m; else frac = frac_table_675m; for (; frac->num; frac++) { - request = rate; + request = req->rate; request *= frac->den; request = div_s64(request, frac->num); - if ((src_rate < (request - delta)) || - (src_rate > (request + delta))) + if ((req->best_parent_rate < (request - delta)) || + (req->best_parent_rate > (request + delta))) continue; regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, @@ -410,8 +486,10 @@ static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, hid_div >>= CFG_SRC_DIV_SHIFT; hid_div &= mask; - return calc_rate(src_rate, frac->num, frac->den, !!frac->den, - hid_div); + req->rate = calc_rate(req->best_parent_rate, + frac->num, frac->den, + !!frac->den, hid_div); + return 0; } return -EINVAL; @@ -428,28 +506,28 @@ const struct clk_ops clk_edp_pixel_ops = { }; EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); -static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p_hw) +static int clk_byte_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); const struct freq_tbl *f = rcg->freq_tbl; int index = qcom_find_src_index(hw, rcg->parent_map, f->src); unsigned long parent_rate, div; u32 mask = BIT(rcg->hid_width) - 1; - struct clk *p; + struct clk_hw *p; - if (rate == 0) + if (req->rate == 0) return -EINVAL; - p = clk_get_parent_by_index(hw->clk, index); - *p_hw = __clk_get_hw(p); - *p_rate = parent_rate = __clk_round_rate(p, rate); + req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index); + req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate); - div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; + div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1; div = min_t(u32, div, mask); - return calc_rate(parent_rate, 0, 0, 0, div); + req->rate = calc_rate(parent_rate, 0, 0, 0, div); + + return 0; } static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate, @@ -486,6 +564,76 @@ const struct clk_ops clk_byte_ops = { }; EXPORT_SYMBOL_GPL(clk_byte_ops); +static int clk_byte2_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + unsigned long parent_rate, div; + u32 mask = BIT(rcg->hid_width) - 1; + struct clk_hw *p; + unsigned long rate = req->rate; + + if (rate == 0) + return -EINVAL; + + p = req->best_parent_hw; + req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate); + + div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; + div = min_t(u32, div, mask); + + req->rate = calc_rate(parent_rate, 0, 0, 0, div); + + return 0; +} + +static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + struct freq_tbl f = { 0 }; + unsigned long div; + int i, num_parents = clk_hw_get_num_parents(hw); + u32 mask = BIT(rcg->hid_width) - 1; + u32 cfg; + + div = DIV_ROUND_UP((2 * parent_rate), rate) - 1; + div = min_t(u32, div, mask); + + f.pre_div = div; + + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + cfg &= CFG_SRC_SEL_MASK; + cfg >>= CFG_SRC_SEL_SHIFT; + + for (i = 0; i < num_parents; i++) { + if (cfg == rcg->parent_map[i].cfg) { + f.src = rcg->parent_map[i].src; + return clk_rcg2_configure(rcg, &f); + } + } + + return -EINVAL; +} + +static int clk_byte2_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate, u8 index) +{ + /* Read the hardware to determine parent during set_rate */ + return clk_byte2_set_rate(hw, rate, parent_rate); +} + +const struct clk_ops clk_byte2_ops = { + .is_enabled = clk_rcg2_is_enabled, + .get_parent = clk_rcg2_get_parent, + .set_parent = clk_rcg2_set_parent, + .recalc_rate = clk_rcg2_recalc_rate, + .set_rate = clk_byte2_set_rate, + .set_rate_and_parent = clk_byte2_set_rate_and_parent, + .determine_rate = clk_byte2_determine_rate, +}; +EXPORT_SYMBOL_GPL(clk_byte2_ops); + static const struct frac_entry frac_table_pixel[] = { { 3, 8 }, { 2, 9 }, @@ -494,31 +642,24 @@ static const struct frac_entry frac_table_pixel[] = { { } }; -static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, - unsigned long min_rate, - unsigned long max_rate, - unsigned long *p_rate, struct clk_hw **p) +static int clk_pixel_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - struct clk_rcg2 *rcg = to_clk_rcg2(hw); unsigned long request, src_rate; int delta = 100000; - const struct freq_tbl *f = rcg->freq_tbl; const struct frac_entry *frac = frac_table_pixel; - int index = qcom_find_src_index(hw, rcg->parent_map, f->src); - struct clk *parent = clk_get_parent_by_index(hw->clk, index); - - *p = __clk_get_hw(parent); for (; frac->num; frac++) { - request = (rate * frac->den) / frac->num; + request = (req->rate * frac->den) / frac->num; - src_rate = __clk_round_rate(parent, request); + src_rate = clk_hw_round_rate(req->best_parent_hw, request); if ((src_rate < (request - delta)) || (src_rate > (request + delta))) continue; - *p_rate = src_rate; - return (src_rate * frac->num) / frac->den; + req->best_parent_rate = src_rate; + req->rate = (src_rate * frac->num) / frac->den; + return 0; } return -EINVAL; @@ -528,12 +669,23 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - struct freq_tbl f = *rcg->freq_tbl; + struct freq_tbl f = { 0 }; const struct frac_entry *frac = frac_table_pixel; unsigned long request; int delta = 100000; u32 mask = BIT(rcg->hid_width) - 1; - u32 hid_div; + u32 hid_div, cfg; + int i, num_parents = clk_hw_get_num_parents(hw); + + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + cfg &= CFG_SRC_SEL_MASK; + cfg >>= CFG_SRC_SEL_SHIFT; + + for (i = 0; i < num_parents; i++) + if (cfg == rcg->parent_map[i].cfg) { + f.src = rcg->parent_map[i].src; + break; + } for (; frac->num; frac++) { request = (rate * frac->den) / frac->num; @@ -558,7 +710,6 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index) { - /* Parent index is set statically in frequency table */ return clk_pixel_set_rate(hw, rate, parent_rate); } diff --git a/kernel/drivers/clk/qcom/common.c b/kernel/drivers/clk/qcom/common.c index f7101e330..8fa477293 100644 --- a/kernel/drivers/clk/qcom/common.c +++ b/kernel/drivers/clk/qcom/common.c @@ -12,6 +12,7 @@ */ #include +#include #include #include #include @@ -21,6 +22,7 @@ #include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" +#include "gdsc.h" struct qcom_cc { struct qcom_reset_controller reset; @@ -45,7 +47,7 @@ EXPORT_SYMBOL_GPL(qcom_find_freq); int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src) { - int i, num_parents = __clk_get_num_parents(hw->clk); + int i, num_parents = clk_hw_get_num_parents(hw); for (i = 0; i < num_parents; i++) if (src == map[i].src) @@ -71,6 +73,21 @@ qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) } EXPORT_SYMBOL_GPL(qcom_cc_map); +static void qcom_cc_del_clk_provider(void *data) +{ + of_clk_del_provider(data); +} + +static void qcom_cc_reset_unregister(void *data) +{ + reset_controller_unregister(data); +} + +static void qcom_cc_gdsc_unregister(void *data) +{ + gdsc_unregister(data); +} + int qcom_cc_really_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -109,6 +126,8 @@ int qcom_cc_really_probe(struct platform_device *pdev, if (ret) return ret; + devm_add_action(dev, qcom_cc_del_clk_provider, pdev->dev.of_node); + reset = &cc->reset; reset->rcdev.of_node = dev->of_node; reset->rcdev.ops = &qcom_reset_ops; @@ -116,13 +135,24 @@ int qcom_cc_really_probe(struct platform_device *pdev, reset->rcdev.nr_resets = desc->num_resets; reset->regmap = regmap; reset->reset_map = desc->resets; - platform_set_drvdata(pdev, &reset->rcdev); ret = reset_controller_register(&reset->rcdev); if (ret) - of_clk_del_provider(dev->of_node); + return ret; + + devm_add_action(dev, qcom_cc_reset_unregister, &reset->rcdev); + + if (desc->gdscs && desc->num_gdscs) { + ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, + &reset->rcdev, regmap); + if (ret) + return ret; + } - return ret; + devm_add_action(dev, qcom_cc_gdsc_unregister, dev); + + + return 0; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); @@ -138,9 +168,4 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) } EXPORT_SYMBOL_GPL(qcom_cc_probe); -void qcom_cc_remove(struct platform_device *pdev) -{ - of_clk_del_provider(pdev->dev.of_node); - reset_controller_unregister(platform_get_drvdata(pdev)); -} -EXPORT_SYMBOL_GPL(qcom_cc_remove); +MODULE_LICENSE("GPL v2"); diff --git a/kernel/drivers/clk/qcom/common.h b/kernel/drivers/clk/qcom/common.h index 7a0e73713..7c1fba3eb 100644 --- a/kernel/drivers/clk/qcom/common.h +++ b/kernel/drivers/clk/qcom/common.h @@ -28,6 +28,8 @@ struct qcom_cc_desc { size_t num_clks; const struct qcom_reset_map *resets; size_t num_resets; + struct gdsc **gdscs; + size_t num_gdscs; }; extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, @@ -43,6 +45,4 @@ extern int qcom_cc_really_probe(struct platform_device *pdev, extern int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc); -extern void qcom_cc_remove(struct platform_device *pdev); - #endif diff --git a/kernel/drivers/clk/qcom/gcc-apq8084.c b/kernel/drivers/clk/qcom/gcc-apq8084.c index 457c54058..1567c3a79 100644 --- a/kernel/drivers/clk/qcom/gcc-apq8084.c +++ b/kernel/drivers/clk/qcom/gcc-apq8084.c @@ -31,6 +31,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -48,7 +49,7 @@ static const struct parent_map gcc_xo_gpll0_map[] = { { P_GPLL0, 1 } }; -static const char *gcc_xo_gpll0[] = { +static const char * const gcc_xo_gpll0[] = { "xo", "gpll0_vote", }; @@ -59,7 +60,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { { P_GPLL4, 5 } }; -static const char *gcc_xo_gpll0_gpll4[] = { +static const char * const gcc_xo_gpll0_gpll4[] = { "xo", "gpll0_vote", "gpll4_vote", @@ -70,7 +71,7 @@ static const struct parent_map gcc_xo_sata_asic0_map[] = { { P_SATA_ASIC0_CLK, 2 } }; -static const char *gcc_xo_sata_asic0[] = { +static const char * const gcc_xo_sata_asic0[] = { "xo", "sata_asic0_clk", }; @@ -80,7 +81,7 @@ static const struct parent_map gcc_xo_sata_rx_map[] = { { P_SATA_RX_CLK, 2} }; -static const char *gcc_xo_sata_rx[] = { +static const char * const gcc_xo_sata_rx[] = { "xo", "sata_rx_clk", }; @@ -90,7 +91,7 @@ static const struct parent_map gcc_xo_pcie_map[] = { { P_PCIE_0_1_PIPE_CLK, 2 } }; -static const char *gcc_xo_pcie[] = { +static const char * const gcc_xo_pcie[] = { "xo", "pcie_pipe", }; @@ -100,7 +101,7 @@ static const struct parent_map gcc_xo_pcie_sleep_map[] = { { P_SLEEP_CLK, 6 } }; -static const char *gcc_xo_pcie_sleep[] = { +static const char * const gcc_xo_pcie_sleep[] = { "xo", "sleep_clk_src", }; @@ -3254,6 +3255,38 @@ static struct clk_branch gcc_usb_hsic_system_clk = { }, }; +static struct gdsc usb_hs_hsic_gdsc = { + .gdscr = 0x404, + .pd = { + .name = "usb_hs_hsic", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie0_gdsc = { + .gdscr = 0x1ac4, + .pd = { + .name = "pcie0", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie1_gdsc = { + .gdscr = 0x1b44, + .pd = { + .name = "pcie1", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_gdsc = { + .gdscr = 0x1e84, + .pd = { + .name = "usb30", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_apq8084_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_VOTE] = &gpll0_vote, @@ -3447,6 +3480,13 @@ static struct clk_regmap *gcc_apq8084_clocks[] = { [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, }; +static struct gdsc *gcc_apq8084_gdscs[] = { + [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, + [PCIE0_GDSC] = &pcie0_gdsc, + [PCIE1_GDSC] = &pcie1_gdsc, + [USB30_GDSC] = &usb30_gdsc, +}; + static const struct qcom_reset_map gcc_apq8084_resets[] = { [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, [GCC_CONFIG_NOC_BCR] = { 0x0140 }, @@ -3555,6 +3595,8 @@ static const struct qcom_cc_desc gcc_apq8084_desc = { .num_clks = ARRAY_SIZE(gcc_apq8084_clocks), .resets = gcc_apq8084_resets, .num_resets = ARRAY_SIZE(gcc_apq8084_resets), + .gdscs = gcc_apq8084_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs), }; static const struct of_device_id gcc_apq8084_match_table[] = { @@ -3581,15 +3623,8 @@ static int gcc_apq8084_probe(struct platform_device *pdev) return qcom_cc_probe(pdev, &gcc_apq8084_desc); } -static int gcc_apq8084_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); - return 0; -} - static struct platform_driver gcc_apq8084_driver = { .probe = gcc_apq8084_probe, - .remove = gcc_apq8084_remove, .driver = { .name = "gcc-apq8084", .of_match_table = gcc_apq8084_match_table, diff --git a/kernel/drivers/clk/qcom/gcc-ipq806x.c b/kernel/drivers/clk/qcom/gcc-ipq806x.c index a50936a17..16fc64c08 100644 --- a/kernel/drivers/clk/qcom/gcc-ipq806x.c +++ b/kernel/drivers/clk/qcom/gcc-ipq806x.c @@ -140,12 +140,47 @@ static struct clk_regmap pll14_vote = { }, }; +#define NSS_PLL_RATE(f, _l, _m, _n, i) \ + { \ + .freq = f, \ + .l = _l, \ + .m = _m, \ + .n = _n, \ + .ibits = i, \ + } + +static struct pll_freq_tbl pll18_freq_tbl[] = { + NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), + NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), +}; + +static struct clk_pll pll18 = { + .l_reg = 0x31a4, + .m_reg = 0x31a8, + .n_reg = 0x31ac, + .config_reg = 0x31b4, + .mode_reg = 0x31a0, + .status_reg = 0x31b8, + .status_bit = 16, + .post_div_shift = 16, + .post_div_width = 1, + .freq_tbl = pll18_freq_tbl, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll18", + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + enum { P_PXO, P_PLL8, P_PLL3, P_PLL0, P_CXO, + P_PLL14, + P_PLL18, }; static const struct parent_map gcc_pxo_pll8_map[] = { @@ -153,7 +188,7 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char *gcc_pxo_pll8[] = { +static const char * const gcc_pxo_pll8[] = { "pxo", "pll8_vote", }; @@ -164,7 +199,7 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char *gcc_pxo_pll8_cxo[] = { +static const char * const gcc_pxo_pll8_cxo[] = { "pxo", "pll8_vote", "cxo", @@ -180,7 +215,7 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = { { P_PLL3, 6 } }; -static const char *gcc_pxo_pll3[] = { +static const char * const gcc_pxo_pll3[] = { "pxo", "pll3", }; @@ -191,10 +226,26 @@ static const struct parent_map gcc_pxo_pll8_pll0[] = { { P_PLL0, 2 } }; -static const char *gcc_pxo_pll8_pll0_map[] = { +static const char * const gcc_pxo_pll8_pll0_map[] = { + "pxo", + "pll8_vote", + "pll0_vote", +}; + +static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { + { P_PXO, 0 }, + { P_PLL8, 4 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 } +}; + +static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { "pxo", "pll8_vote", "pll0_vote", + "pll14", + "pll18", }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -2202,6 +2253,472 @@ static struct clk_branch ebi2_aon_clk = { }, }; +static const struct freq_tbl clk_tbl_gmac[] = { + { 133000000, P_PLL0, 1, 50, 301 }, + { 266000000, P_PLL0, 1, 127, 382 }, + { } +}; + +static struct clk_dyn_rcg gmac_core1_src = { + .ns_reg[0] = 0x3cac, + .ns_reg[1] = 0x3cb0, + .md_reg[0] = 0x3ca4, + .md_reg[1] = 0x3ca8, + .bank_reg = 0x3ca0, + .mn[0] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .mn[1] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_gmac, + .clkr = { + .enable_reg = 0x3ca0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core1_src", + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch gmac_core1_clk = { + .halt_reg = 0x3c20, + .halt_bit = 4, + .hwcg_reg = 0x3cb4, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3cb4, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core1_clk", + .parent_names = (const char *[]){ + "gmac_core1_src", + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_dyn_rcg gmac_core2_src = { + .ns_reg[0] = 0x3ccc, + .ns_reg[1] = 0x3cd0, + .md_reg[0] = 0x3cc4, + .md_reg[1] = 0x3cc8, + .bank_reg = 0x3ca0, + .mn[0] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .mn[1] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_gmac, + .clkr = { + .enable_reg = 0x3cc0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core2_src", + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch gmac_core2_clk = { + .halt_reg = 0x3c20, + .halt_bit = 5, + .hwcg_reg = 0x3cd4, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3cd4, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core2_clk", + .parent_names = (const char *[]){ + "gmac_core2_src", + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_dyn_rcg gmac_core3_src = { + .ns_reg[0] = 0x3cec, + .ns_reg[1] = 0x3cf0, + .md_reg[0] = 0x3ce4, + .md_reg[1] = 0x3ce8, + .bank_reg = 0x3ce0, + .mn[0] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .mn[1] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_gmac, + .clkr = { + .enable_reg = 0x3ce0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core3_src", + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch gmac_core3_clk = { + .halt_reg = 0x3c20, + .halt_bit = 6, + .hwcg_reg = 0x3cf4, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3cf4, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core3_clk", + .parent_names = (const char *[]){ + "gmac_core3_src", + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_dyn_rcg gmac_core4_src = { + .ns_reg[0] = 0x3d0c, + .ns_reg[1] = 0x3d10, + .md_reg[0] = 0x3d04, + .md_reg[1] = 0x3d08, + .bank_reg = 0x3d00, + .mn[0] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .mn[1] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_gmac, + .clkr = { + .enable_reg = 0x3d00, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core4_src", + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch gmac_core4_clk = { + .halt_reg = 0x3c20, + .halt_bit = 7, + .hwcg_reg = 0x3d14, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3d14, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core4_clk", + .parent_names = (const char *[]){ + "gmac_core4_src", + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_nss_tcm[] = { + { 266000000, P_PLL0, 3, 0, 0 }, + { 400000000, P_PLL0, 2, 0, 0 }, + { } +}; + +static struct clk_dyn_rcg nss_tcm_src = { + .ns_reg[0] = 0x3dc4, + .ns_reg[1] = 0x3dc8, + .bank_reg = 0x3dc0, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_nss_tcm, + .clkr = { + .enable_reg = 0x3dc0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "nss_tcm_src", + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch nss_tcm_clk = { + .halt_reg = 0x3c20, + .halt_bit = 14, + .clkr = { + .enable_reg = 0x3dd0, + .enable_mask = BIT(6) | BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "nss_tcm_clk", + .parent_names = (const char *[]){ + "nss_tcm_src", + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_nss[] = { + { 110000000, P_PLL18, 1, 1, 5 }, + { 275000000, P_PLL18, 2, 0, 0 }, + { 550000000, P_PLL18, 1, 0, 0 }, + { 733000000, P_PLL18, 1, 0, 0 }, + { } +}; + +static struct clk_dyn_rcg ubi32_core1_src_clk = { + .ns_reg[0] = 0x3d2c, + .ns_reg[1] = 0x3d30, + .md_reg[0] = 0x3d24, + .md_reg[1] = 0x3d28, + .bank_reg = 0x3d20, + .mn[0] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .mn[1] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_nss, + .clkr = { + .enable_reg = 0x3d20, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core1_src_clk", + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, + }, +}; + +static struct clk_dyn_rcg ubi32_core2_src_clk = { + .ns_reg[0] = 0x3d4c, + .ns_reg[1] = 0x3d50, + .md_reg[0] = 0x3d44, + .md_reg[1] = 0x3d48, + .bank_reg = 0x3d40, + .mn[0] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .mn[1] = { + .mnctr_en_bit = 8, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 5, + .n_val_shift = 16, + .m_val_shift = 16, + .width = 8, + }, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 2, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_nss, + .clkr = { + .enable_reg = 0x3d40, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core2_src_clk", + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, + }, +}; + static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -2211,6 +2728,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL8_VOTE] = &pll8_vote, [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, + [PLL18] = &pll18.clkr, [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, @@ -2307,6 +2825,18 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, [EBI2_CLK] = &ebi2_clk.clkr, [EBI2_AON_CLK] = &ebi2_aon_clk.clkr, + [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr, + [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr, + [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr, + [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr, + [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr, + [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr, + [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr, + [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr, + [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr, + [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, + [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, + [NSSTCM_CLK] = &nss_tcm_clk.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { @@ -2425,6 +2955,48 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = { [USB30_1_PHY_RESET] = { 0x3b58, 0 }, [NSSFB0_RESET] = { 0x3b60, 6 }, [NSSFB1_RESET] = { 0x3b60, 7 }, + [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3}, + [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 }, + [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 }, + [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 }, + [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 }, + [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 }, + [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 }, + [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 }, + [GMAC_CORE1_RESET] = { 0x3cbc, 0 }, + [GMAC_CORE2_RESET] = { 0x3cdc, 0 }, + [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, + [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, + [GMAC_AHB_RESET] = { 0x3e24, 0 }, + [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, + [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, + [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, + [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 }, + [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 }, + [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 }, + [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 }, + [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 }, + [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 }, + [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 }, + [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 }, + [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 }, + [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 }, + [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 }, + [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 }, + [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 }, + [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 }, + [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 }, + [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 }, + [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 }, + [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 }, + [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 }, + [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 }, + [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 }, + [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 }, + [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 }, + [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 }, + [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 }, + [NSS_SRDS_N_RESET] = { 0x3b60, 28 }, }; static const struct regmap_config gcc_ipq806x_regmap_config = { @@ -2453,6 +3025,8 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) { struct clk *clk; struct device *dev = &pdev->dev; + struct regmap *regmap; + int ret; /* Temporary until RPM clocks supported */ clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); @@ -2463,18 +3037,29 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) if (IS_ERR(clk)) return PTR_ERR(clk); - return qcom_cc_probe(pdev, &gcc_ipq806x_desc); -} + ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); + if (ret) + return ret; + + regmap = dev_get_regmap(dev, NULL); + if (!regmap) + return -ENODEV; + + /* Setup PLL18 static bits */ + regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); + regmap_write(regmap, 0x31b0, 0x3080); + + /* Set GMAC footswitch sleep/wakeup values */ + regmap_write(regmap, 0x3cb8, 8); + regmap_write(regmap, 0x3cd8, 8); + regmap_write(regmap, 0x3cf8, 8); + regmap_write(regmap, 0x3d18, 8); -static int gcc_ipq806x_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); return 0; } static struct platform_driver gcc_ipq806x_driver = { .probe = gcc_ipq806x_probe, - .remove = gcc_ipq806x_remove, .driver = { .name = "gcc-ipq806x", .of_match_table = gcc_ipq806x_match_table, diff --git a/kernel/drivers/clk/qcom/gcc-msm8660.c b/kernel/drivers/clk/qcom/gcc-msm8660.c index fc6b12da5..f110bb5a1 100644 --- a/kernel/drivers/clk/qcom/gcc-msm8660.c +++ b/kernel/drivers/clk/qcom/gcc-msm8660.c @@ -70,7 +70,7 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char *gcc_pxo_pll8[] = { +static const char * const gcc_pxo_pll8[] = { "pxo", "pll8_vote", }; @@ -81,7 +81,7 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char *gcc_pxo_pll8_cxo[] = { +static const char * const gcc_pxo_pll8_cxo[] = { "pxo", "pll8_vote", "cxo", @@ -1917,7 +1917,7 @@ static struct clk_rcg usb_fs1_xcvr_fs_src = { } }; -static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; +static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; static struct clk_branch usb_fs1_xcvr_fs_clk = { .halt_reg = 0x2fcc, @@ -1984,7 +1984,7 @@ static struct clk_rcg usb_fs2_xcvr_fs_src = { } }; -static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; +static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; static struct clk_branch usb_fs2_xcvr_fs_clk = { .halt_reg = 0x2fcc, @@ -2735,15 +2735,8 @@ static int gcc_msm8660_probe(struct platform_device *pdev) return qcom_cc_probe(pdev, &gcc_msm8660_desc); } -static int gcc_msm8660_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); - return 0; -} - static struct platform_driver gcc_msm8660_driver = { .probe = gcc_msm8660_probe, - .remove = gcc_msm8660_remove, .driver = { .name = "gcc-msm8660", .of_match_table = gcc_msm8660_match_table, diff --git a/kernel/drivers/clk/qcom/gcc-msm8916.c b/kernel/drivers/clk/qcom/gcc-msm8916.c index 5d75bffab..d0a0313d6 100644 --- a/kernel/drivers/clk/qcom/gcc-msm8916.c +++ b/kernel/drivers/clk/qcom/gcc-msm8916.c @@ -31,6 +31,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -44,6 +45,9 @@ enum { P_SLEEP_CLK, P_DSI0_PHYPLL_BYTE, P_DSI0_PHYPLL_DSI, + P_EXT_PRI_I2S, + P_EXT_SEC_I2S, + P_EXT_MCLK, }; static const struct parent_map gcc_xo_gpll0_map[] = { @@ -51,7 +55,7 @@ static const struct parent_map gcc_xo_gpll0_map[] = { { P_GPLL0, 1 }, }; -static const char *gcc_xo_gpll0[] = { +static const char * const gcc_xo_gpll0[] = { "xo", "gpll0_vote", }; @@ -62,7 +66,7 @@ static const struct parent_map gcc_xo_gpll0_bimc_map[] = { { P_BIMC, 2 }, }; -static const char *gcc_xo_gpll0_bimc[] = { +static const char * const gcc_xo_gpll0_bimc[] = { "xo", "gpll0_vote", "bimc_pll_vote", @@ -75,7 +79,7 @@ static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { { P_GPLL2_AUX, 2 }, }; -static const char *gcc_xo_gpll0a_gpll1_gpll2a[] = { +static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = { "xo", "gpll0_vote", "gpll1_vote", @@ -88,7 +92,7 @@ static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { { P_GPLL2, 2 }, }; -static const char *gcc_xo_gpll0_gpll2[] = { +static const char * const gcc_xo_gpll0_gpll2[] = { "xo", "gpll0_vote", "gpll2_vote", @@ -99,7 +103,7 @@ static const struct parent_map gcc_xo_gpll0a_map[] = { { P_GPLL0_AUX, 2 }, }; -static const char *gcc_xo_gpll0a[] = { +static const char * const gcc_xo_gpll0a[] = { "xo", "gpll0_vote", }; @@ -111,7 +115,7 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { { P_SLEEP_CLK, 6 }, }; -static const char *gcc_xo_gpll0_gpll1a_sleep[] = { +static const char * const gcc_xo_gpll0_gpll1a_sleep[] = { "xo", "gpll0_vote", "gpll1_vote", @@ -124,7 +128,7 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { { P_GPLL1_AUX, 2 }, }; -static const char *gcc_xo_gpll0_gpll1a[] = { +static const char * const gcc_xo_gpll0_gpll1a[] = { "xo", "gpll0_vote", "gpll1_vote", @@ -135,7 +139,7 @@ static const struct parent_map gcc_xo_dsibyte_map[] = { { P_DSI0_PHYPLL_BYTE, 2 }, }; -static const char *gcc_xo_dsibyte[] = { +static const char * const gcc_xo_dsibyte[] = { "xo", "dsi0pllbyte", }; @@ -146,7 +150,7 @@ static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { { P_DSI0_PHYPLL_BYTE, 1 }, }; -static const char *gcc_xo_gpll0a_dsibyte[] = { +static const char * const gcc_xo_gpll0a_dsibyte[] = { "xo", "gpll0_vote", "dsi0pllbyte", @@ -158,7 +162,7 @@ static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = { { P_DSI0_PHYPLL_DSI, 2 }, }; -static const char *gcc_xo_gpll0_dsiphy[] = { +static const char * const gcc_xo_gpll0_dsiphy[] = { "xo", "gpll0_vote", "dsi0pll", @@ -170,7 +174,7 @@ static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { { P_DSI0_PHYPLL_DSI, 1 }, }; -static const char *gcc_xo_gpll0a_dsiphy[] = { +static const char * const gcc_xo_gpll0a_dsiphy[] = { "xo", "gpll0_vote", "dsi0pll", @@ -183,13 +187,83 @@ static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = { { P_GPLL2, 2 }, }; -static const char *gcc_xo_gpll0a_gpll1_gpll2[] = { +static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = { "xo", "gpll0_vote", "gpll1_vote", "gpll2_vote", }; +static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL1, 2 }, + { P_SLEEP_CLK, 6 } +}; + +static const char * const gcc_xo_gpll0_gpll1_sleep[] = { + "xo", + "gpll0_vote", + "gpll1_vote", + "sleep_clk", +}; + +static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { + { P_XO, 0 }, + { P_GPLL1, 1 }, + { P_EXT_PRI_I2S, 2 }, + { P_EXT_MCLK, 3 }, + { P_SLEEP_CLK, 6 } +}; + +static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = { + "xo", + "gpll1_vote", + "ext_pri_i2s", + "ext_mclk", + "sleep_clk", +}; + +static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { + { P_XO, 0 }, + { P_GPLL1, 1 }, + { P_EXT_SEC_I2S, 2 }, + { P_EXT_MCLK, 3 }, + { P_SLEEP_CLK, 6 } +}; + +static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = { + "xo", + "gpll1_vote", + "ext_sec_i2s", + "ext_mclk", + "sleep_clk", +}; + +static const struct parent_map gcc_xo_sleep_map[] = { + { P_XO, 0 }, + { P_SLEEP_CLK, 6 } +}; + +static const char * const gcc_xo_sleep[] = { + "xo", + "sleep_clk", +}; + +static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { + { P_XO, 0 }, + { P_GPLL1, 1 }, + { P_EXT_MCLK, 2 }, + { P_SLEEP_CLK, 6 } +}; + +static const char * const gcc_xo_gpll1_emclk_sleep[] = { + "xo", + "gpll1_vote", + "ext_mclk", + "sleep_clk", +}; + #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } static struct clk_pll gpll0 = { @@ -906,21 +980,15 @@ static struct clk_rcg2 gp3_clk_src = { }, }; -static struct freq_tbl ftbl_gcc_mdss_byte0_clk[] = { - { .src = P_DSI0_PHYPLL_BYTE }, - { } -}; - static struct clk_rcg2 byte0_clk_src = { .cmd_rcgr = 0x4d044, .hid_width = 5, .parent_map = gcc_xo_gpll0a_dsibyte_map, - .freq_tbl = ftbl_gcc_mdss_byte0_clk, .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = gcc_xo_gpll0a_dsibyte, .num_parents = 3, - .ops = &clk_byte_ops, + .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, }; @@ -968,17 +1036,11 @@ static struct clk_rcg2 mdp_clk_src = { }, }; -static struct freq_tbl ftbl_gcc_mdss_pclk[] = { - { .src = P_DSI0_PHYPLL_DSI }, - { } -}; - static struct clk_rcg2 pclk0_clk_src = { .cmd_rcgr = 0x4d000, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll0a_dsiphy_map, - .freq_tbl = ftbl_gcc_mdss_pclk, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = gcc_xo_gpll0a_dsiphy, @@ -1094,6 +1156,30 @@ static struct clk_rcg2 apss_tcu_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { + F(19200000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266500000, P_BIMC, 4, 0, 0), + F(400000000, P_GPLL0, 2, 0, 0), + F(533000000, P_BIMC, 2, 0, 0), + { } +}; + +static struct clk_rcg2 bimc_gpu_clk_src = { + .cmd_rcgr = 0x31028, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_bimc_map, + .freq_tbl = ftbl_gcc_bimc_gpu_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_gpu_clk_src", + .parent_names = gcc_xo_gpll0_bimc, + .num_parents = 3, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_shared_ops, + }, +}; + static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { F(80000000, P_GPLL0, 10, 0, 0), { } @@ -1112,6 +1198,305 @@ static struct clk_rcg2 usb_hs_system_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = { + F(3200000, P_XO, 6, 0, 0), + F(6400000, P_XO, 3, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(19200000, P_XO, 1, 0, 0), + F(40000000, P_GPLL0, 10, 1, 2), + F(66670000, P_GPLL0, 12, 0, 0), + F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { + .cmd_rcgr = 0x1c010, + .hid_width = 5, + .mnd_width = 8, + .parent_map = gcc_xo_gpll0_gpll1_sleep_map, + .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ultaudio_ahbfabric_clk_src", + .parent_names = gcc_xo_gpll0_gpll1_sleep, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = { + .halt_reg = 0x1c028, + .clkr = { + .enable_reg = 0x1c028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_ahbfabric_ixfabric_clk", + .parent_names = (const char *[]){ + "ultaudio_ahbfabric_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { + .halt_reg = 0x1c024, + .clkr = { + .enable_reg = 0x1c024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk", + .parent_names = (const char *[]){ + "ultaudio_ahbfabric_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { + F(256000, P_XO, 5, 1, 15), + F(512000, P_XO, 5, 2, 15), + F(705600, P_GPLL1, 16, 1, 80), + F(768000, P_XO, 5, 1, 5), + F(800000, P_XO, 5, 5, 24), + F(1024000, P_GPLL1, 14, 1, 63), + F(1152000, P_XO, 1, 3, 50), + F(1411200, P_GPLL1, 16, 1, 40), + F(1536000, P_XO, 1, 2, 25), + F(1600000, P_XO, 12, 0, 0), + F(2048000, P_GPLL1, 9, 1, 49), + F(2400000, P_XO, 8, 0, 0), + F(2822400, P_GPLL1, 16, 1, 20), + F(3072000, P_GPLL1, 14, 1, 21), + F(4096000, P_GPLL1, 9, 2, 49), + F(4800000, P_XO, 4, 0, 0), + F(5644800, P_GPLL1, 16, 1, 10), + F(6144000, P_GPLL1, 7, 1, 21), + F(8192000, P_GPLL1, 9, 4, 49), + F(9600000, P_XO, 2, 0, 0), + F(11289600, P_GPLL1, 16, 1, 5), + F(12288000, P_GPLL1, 7, 2, 21), + { } +}; + +static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { + .cmd_rcgr = 0x1c054, + .hid_width = 5, + .mnd_width = 8, + .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map, + .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ultaudio_lpaif_pri_i2s_clk_src", + .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = { + .halt_reg = 0x1c068, + .clkr = { + .enable_reg = 0x1c068, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_lpaif_pri_i2s_clk", + .parent_names = (const char *[]){ + "ultaudio_lpaif_pri_i2s_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { + .cmd_rcgr = 0x1c06c, + .hid_width = 5, + .mnd_width = 8, + .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map, + .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ultaudio_lpaif_sec_i2s_clk_src", + .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = { + .halt_reg = 0x1c080, + .clkr = { + .enable_reg = 0x1c080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_lpaif_sec_i2s_clk", + .parent_names = (const char *[]){ + "ultaudio_lpaif_sec_i2s_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { + .cmd_rcgr = 0x1c084, + .hid_width = 5, + .mnd_width = 8, + .parent_map = gcc_xo_gpll1_emclk_sleep_map, + .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ultaudio_lpaif_aux_i2s_clk_src", + .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = { + .halt_reg = 0x1c098, + .clkr = { + .enable_reg = 0x1c098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_lpaif_aux_i2s_clk", + .parent_names = (const char *[]){ + "ultaudio_lpaif_aux_i2s_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ultaudio_xo_clk_src = { + .cmd_rcgr = 0x1c034, + .hid_width = 5, + .parent_map = gcc_xo_sleep_map, + .freq_tbl = ftbl_gcc_ultaudio_xo_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ultaudio_xo_clk_src", + .parent_names = gcc_xo_sleep, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_ultaudio_avsync_xo_clk = { + .halt_reg = 0x1c04c, + .clkr = { + .enable_reg = 0x1c04c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_avsync_xo_clk", + .parent_names = (const char *[]){ + "ultaudio_xo_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ultaudio_stc_xo_clk = { + .halt_reg = 0x1c050, + .clkr = { + .enable_reg = 0x1c050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_stc_xo_clk", + .parent_names = (const char *[]){ + "ultaudio_xo_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_codec_clk[] = { + F(19200000, P_XO, 1, 0, 0), + F(11289600, P_EXT_MCLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 codec_digcodec_clk_src = { + .cmd_rcgr = 0x1c09c, + .hid_width = 5, + .parent_map = gcc_xo_gpll1_emclk_sleep_map, + .freq_tbl = ftbl_codec_clk, + .clkr.hw.init = &(struct clk_init_data){ + .name = "codec_digcodec_clk_src", + .parent_names = gcc_xo_gpll1_emclk_sleep, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_codec_digcodec_clk = { + .halt_reg = 0x1c0b0, + .clkr = { + .enable_reg = 0x1c0b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_codec_digcodec_clk", + .parent_names = (const char *[]){ + "codec_digcodec_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = { + .halt_reg = 0x1c000, + .clkr = { + .enable_reg = 0x1c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_pcnoc_mport_clk", + .parent_names = (const char *[]){ + "pcnoc_bfdcd_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { + .halt_reg = 0x1c004, + .clkr = { + .enable_reg = 0x1c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ultaudio_pcnoc_sway_clk", + .parent_names = (const char *[]){ + "pcnoc_bfdcd_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { F(100000000, P_GPLL0, 8, 0, 0), F(160000000, P_GPLL0, 5, 0, 0), @@ -2358,6 +2743,51 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; +static struct clk_rcg2 bimc_ddr_clk_src = { + .cmd_rcgr = 0x32004, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_bimc_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_ddr_clk_src", + .parent_names = gcc_xo_gpll0_bimc, + .num_parents = 3, + .ops = &clk_rcg2_ops, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_branch gcc_apss_tcu_clk = { + .halt_reg = 0x12018, + .clkr = { + .enable_reg = 0x4500c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_apss_tcu_clk", + .parent_names = (const char *[]){ + "bimc_ddr_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gfx_tcu_clk = { + .halt_reg = 0x12020, + .clkr = { + .enable_reg = 0x4500c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gfx_tcu_clk", + .parent_names = (const char *[]){ + "bimc_ddr_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_gtcu_ahb_clk = { .halt_reg = 0x12044, .clkr = { @@ -2375,6 +2805,40 @@ static struct clk_branch gcc_gtcu_ahb_clk = { }, }; +static struct clk_branch gcc_bimc_gfx_clk = { + .halt_reg = 0x31024, + .clkr = { + .enable_reg = 0x31024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gfx_clk", + .parent_names = (const char *[]){ + "bimc_gpu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_clk = { + .halt_reg = 0x31040, + .clkr = { + .enable_reg = 0x31040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gpu_clk", + .parent_names = (const char *[]){ + "bimc_gpu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_jpeg_tbu_clk = { .halt_reg = 0x12034, .clkr = { @@ -2562,6 +3026,46 @@ static struct clk_branch gcc_venus0_vcodec0_clk = { }, }; +static struct gdsc venus_gdsc = { + .gdscr = 0x4c018, + .pd = { + .name = "venus", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x4d078, + .pd = { + .name = "mdss", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc jpeg_gdsc = { + .gdscr = 0x5701c, + .pd = { + .name = "jpeg", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc vfe_gdsc = { + .gdscr = 0x58034, + .pd = { + .name = "vfe", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc oxili_gdsc = { + .gdscr = 0x5901c, + .pd = { + .name = "oxili", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_msm8916_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_VOTE] = &gpll0_vote, @@ -2701,6 +3205,36 @@ static struct clk_regmap *gcc_msm8916_clocks[] = { [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, + [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, + [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, + [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, + [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, + [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr, + [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr, + [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr, + [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr, + [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr, + [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr, + [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr, + [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr, + [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr, + [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr, + [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr, + [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr, + [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr, + [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr, + [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr, + [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr, +}; + +static struct gdsc *gcc_msm8916_gdscs[] = { + [VENUS_GDSC] = &venus_gdsc, + [MDSS_GDSC] = &mdss_gdsc, + [JPEG_GDSC] = &jpeg_gdsc, + [VFE_GDSC] = &vfe_gdsc, + [OXILI_GDSC] = &oxili_gdsc, }; static const struct qcom_reset_map gcc_msm8916_resets[] = { @@ -2810,6 +3344,8 @@ static const struct qcom_cc_desc gcc_msm8916_desc = { .num_clks = ARRAY_SIZE(gcc_msm8916_clocks), .resets = gcc_msm8916_resets, .num_resets = ARRAY_SIZE(gcc_msm8916_resets), + .gdscs = gcc_msm8916_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs), }; static const struct of_device_id gcc_msm8916_match_table[] = { @@ -2836,15 +3372,8 @@ static int gcc_msm8916_probe(struct platform_device *pdev) return qcom_cc_probe(pdev, &gcc_msm8916_desc); } -static int gcc_msm8916_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); - return 0; -} - static struct platform_driver gcc_msm8916_driver = { .probe = gcc_msm8916_probe, - .remove = gcc_msm8916_remove, .driver = { .name = "gcc-msm8916", .of_match_table = gcc_msm8916_match_table, diff --git a/kernel/drivers/clk/qcom/gcc-msm8960.c b/kernel/drivers/clk/qcom/gcc-msm8960.c index eb6a4f9fa..66c18bc97 100644 --- a/kernel/drivers/clk/qcom/gcc-msm8960.c +++ b/kernel/drivers/clk/qcom/gcc-msm8960.c @@ -125,7 +125,7 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char *gcc_pxo_pll8[] = { +static const char * const gcc_pxo_pll8[] = { "pxo", "pll8_vote", }; @@ -136,7 +136,7 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char *gcc_pxo_pll8_cxo[] = { +static const char * const gcc_pxo_pll8_cxo[] = { "pxo", "pll8_vote", "cxo", @@ -148,7 +148,7 @@ static const struct parent_map gcc_pxo_pll8_pll3_map[] = { { P_PLL3, 6 } }; -static const char *gcc_pxo_pll8_pll3[] = { +static const char * const gcc_pxo_pll8_pll3[] = { "pxo", "pll8_vote", "pll3", @@ -2085,7 +2085,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = { } }; -static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" }; +static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" }; static struct clk_branch usb_hsic_xcvr_fs_clk = { .halt_reg = 0x2fc8, @@ -2181,7 +2181,7 @@ static struct clk_rcg usb_fs1_xcvr_fs_src = { } }; -static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; +static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; static struct clk_branch usb_fs1_xcvr_fs_clk = { .halt_reg = 0x2fcc, @@ -2248,7 +2248,7 @@ static struct clk_rcg usb_fs2_xcvr_fs_src = { } }; -static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; +static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; static struct clk_branch usb_fs2_xcvr_fs_clk = { .halt_reg = 0x2fcc, @@ -3506,6 +3506,8 @@ static int gcc_msm8960_probe(struct platform_device *pdev) struct clk *clk; struct device *dev = &pdev->dev; const struct of_device_id *match; + struct platform_device *tsens; + int ret; match = of_match_device(gcc_msm8960_match_table, &pdev->dev); if (!match) @@ -3520,12 +3522,26 @@ static int gcc_msm8960_probe(struct platform_device *pdev) if (IS_ERR(clk)) return PTR_ERR(clk); - return qcom_cc_probe(pdev, match->data); + ret = qcom_cc_probe(pdev, match->data); + if (ret) + return ret; + + tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1, + NULL, 0); + if (IS_ERR(tsens)) + return PTR_ERR(tsens); + + platform_set_drvdata(pdev, tsens); + + return 0; } static int gcc_msm8960_remove(struct platform_device *pdev) { - qcom_cc_remove(pdev); + struct platform_device *tsens = platform_get_drvdata(pdev); + + platform_device_unregister(tsens); + return 0; } diff --git a/kernel/drivers/clk/qcom/gcc-msm8974.c b/kernel/drivers/clk/qcom/gcc-msm8974.c index f06a082e3..28abb8f8f 100644 --- a/kernel/drivers/clk/qcom/gcc-msm8974.c +++ b/kernel/drivers/clk/qcom/gcc-msm8974.c @@ -31,6 +31,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -44,7 +45,7 @@ static const struct parent_map gcc_xo_gpll0_map[] = { { P_GPLL0, 1 } }; -static const char *gcc_xo_gpll0[] = { +static const char * const gcc_xo_gpll0[] = { "xo", "gpll0_vote", }; @@ -55,7 +56,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { { P_GPLL4, 5 } }; -static const char *gcc_xo_gpll0_gpll4[] = { +static const char * const gcc_xo_gpll0_gpll4[] = { "xo", "gpll0_vote", "gpll4_vote", @@ -2432,6 +2433,14 @@ static struct clk_branch gcc_usb_hsic_system_clk = { }, }; +static struct gdsc usb_hs_hsic_gdsc = { + .gdscr = 0x404, + .pd = { + .name = "usb_hs_hsic", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_msm8974_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_VOTE] = &gpll0_vote, @@ -2661,6 +2670,10 @@ static const struct qcom_reset_map gcc_msm8974_resets[] = { [GCC_VENUS_RESTART] = { 0x1740 }, }; +static struct gdsc *gcc_msm8974_gdscs[] = { + [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, +}; + static const struct regmap_config gcc_msm8974_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -2675,6 +2688,8 @@ static const struct qcom_cc_desc gcc_msm8974_desc = { .num_clks = ARRAY_SIZE(gcc_msm8974_clocks), .resets = gcc_msm8974_resets, .num_resets = ARRAY_SIZE(gcc_msm8974_resets), + .gdscs = gcc_msm8974_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs), }; static const struct of_device_id gcc_msm8974_match_table[] = { @@ -2729,15 +2744,8 @@ static int gcc_msm8974_probe(struct platform_device *pdev) return qcom_cc_probe(pdev, &gcc_msm8974_desc); } -static int gcc_msm8974_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); - return 0; -} - static struct platform_driver gcc_msm8974_driver = { .probe = gcc_msm8974_probe, - .remove = gcc_msm8974_remove, .driver = { .name = "gcc-msm8974", .of_match_table = gcc_msm8974_match_table, diff --git a/kernel/drivers/clk/qcom/gdsc.c b/kernel/drivers/clk/qcom/gdsc.c new file mode 100644 index 000000000..da9fad8b6 --- /dev/null +++ b/kernel/drivers/clk/qcom/gdsc.c @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gdsc.h" + +#define PWR_ON_MASK BIT(31) +#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20) +#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16) +#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12) +#define SW_OVERRIDE_MASK BIT(2) +#define HW_CONTROL_MASK BIT(1) +#define SW_COLLAPSE_MASK BIT(0) + +/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ +#define EN_REST_WAIT_VAL (0x2 << 20) +#define EN_FEW_WAIT_VAL (0x8 << 16) +#define CLK_DIS_WAIT_VAL (0x2 << 12) + +#define RETAIN_MEM BIT(14) +#define RETAIN_PERIPH BIT(13) + +#define TIMEOUT_US 100 + +#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd) + +static int gdsc_is_enabled(struct gdsc *sc) +{ + u32 val; + int ret; + + ret = regmap_read(sc->regmap, sc->gdscr, &val); + if (ret) + return ret; + + return !!(val & PWR_ON_MASK); +} + +static int gdsc_toggle_logic(struct gdsc *sc, bool en) +{ + int ret; + u32 val = en ? 0 : SW_COLLAPSE_MASK; + u32 check = en ? PWR_ON_MASK : 0; + unsigned long timeout; + + ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val); + if (ret) + return ret; + + timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); + do { + ret = regmap_read(sc->regmap, sc->gdscr, &val); + if (ret) + return ret; + + if ((val & PWR_ON_MASK) == check) + return 0; + } while (time_before(jiffies, timeout)); + + ret = regmap_read(sc->regmap, sc->gdscr, &val); + if (ret) + return ret; + + if ((val & PWR_ON_MASK) == check) + return 0; + + return -ETIMEDOUT; +} + +static inline int gdsc_deassert_reset(struct gdsc *sc) +{ + int i; + + for (i = 0; i < sc->reset_count; i++) + sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]); + return 0; +} + +static inline int gdsc_assert_reset(struct gdsc *sc) +{ + int i; + + for (i = 0; i < sc->reset_count; i++) + sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]); + return 0; +} + +static inline void gdsc_force_mem_on(struct gdsc *sc) +{ + int i; + u32 mask = RETAIN_MEM | RETAIN_PERIPH; + + for (i = 0; i < sc->cxc_count; i++) + regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask); +} + +static inline void gdsc_clear_mem_on(struct gdsc *sc) +{ + int i; + u32 mask = RETAIN_MEM | RETAIN_PERIPH; + + for (i = 0; i < sc->cxc_count; i++) + regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0); +} + +static int gdsc_enable(struct generic_pm_domain *domain) +{ + struct gdsc *sc = domain_to_gdsc(domain); + int ret; + + if (sc->pwrsts == PWRSTS_ON) + return gdsc_deassert_reset(sc); + + ret = gdsc_toggle_logic(sc, true); + if (ret) + return ret; + + if (sc->pwrsts & PWRSTS_OFF) + gdsc_force_mem_on(sc); + + /* + * If clocks to this power domain were already on, they will take an + * additional 4 clock cycles to re-enable after the power domain is + * enabled. Delay to account for this. A delay is also needed to ensure + * clocks are not enabled within 400ns of enabling power to the + * memories. + */ + udelay(1); + + return 0; +} + +static int gdsc_disable(struct generic_pm_domain *domain) +{ + struct gdsc *sc = domain_to_gdsc(domain); + + if (sc->pwrsts == PWRSTS_ON) + return gdsc_assert_reset(sc); + + if (sc->pwrsts & PWRSTS_OFF) + gdsc_clear_mem_on(sc); + + return gdsc_toggle_logic(sc, false); +} + +static int gdsc_init(struct gdsc *sc) +{ + u32 mask, val; + int on, ret; + + /* + * Disable HW trigger: collapse/restore occur based on registers writes. + * Disable SW override: Use hardware state-machine for sequencing. + * Configure wait time between states. + */ + mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK | + EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK; + val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; + ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); + if (ret) + return ret; + + /* Force gdsc ON if only ON state is supported */ + if (sc->pwrsts == PWRSTS_ON) { + ret = gdsc_toggle_logic(sc, true); + if (ret) + return ret; + } + + on = gdsc_is_enabled(sc); + if (on < 0) + return on; + + if (on || (sc->pwrsts & PWRSTS_RET)) + gdsc_force_mem_on(sc); + else + gdsc_clear_mem_on(sc); + + sc->pd.power_off = gdsc_disable; + sc->pd.power_on = gdsc_enable; + pm_genpd_init(&sc->pd, NULL, !on); + + return 0; +} + +int gdsc_register(struct device *dev, struct gdsc **scs, size_t num, + struct reset_controller_dev *rcdev, struct regmap *regmap) +{ + int i, ret; + struct genpd_onecell_data *data; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->domains = devm_kcalloc(dev, num, sizeof(*data->domains), + GFP_KERNEL); + if (!data->domains) + return -ENOMEM; + + data->num_domains = num; + for (i = 0; i < num; i++) { + if (!scs[i]) + continue; + scs[i]->regmap = regmap; + scs[i]->rcdev = rcdev; + ret = gdsc_init(scs[i]); + if (ret) + return ret; + data->domains[i] = &scs[i]->pd; + } + + return of_genpd_add_provider_onecell(dev->of_node, data); +} + +void gdsc_unregister(struct device *dev) +{ + of_genpd_del_provider(dev->of_node); +} diff --git a/kernel/drivers/clk/qcom/gdsc.h b/kernel/drivers/clk/qcom/gdsc.h new file mode 100644 index 000000000..5ded26884 --- /dev/null +++ b/kernel/drivers/clk/qcom/gdsc.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_GDSC_H__ +#define __QCOM_GDSC_H__ + +#include +#include + +struct regmap; +struct reset_controller_dev; + +/* Powerdomain allowable state bitfields */ +#define PWRSTS_OFF BIT(0) +#define PWRSTS_RET BIT(1) +#define PWRSTS_ON BIT(2) +#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) +#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) + +/** + * struct gdsc - Globally Distributed Switch Controller + * @pd: generic power domain + * @regmap: regmap for MMIO accesses + * @gdscr: gsdc control register + * @cxcs: offsets of branch registers to toggle mem/periph bits in + * @cxc_count: number of @cxcs + * @pwrsts: Possible powerdomain power states + * @resets: ids of resets associated with this gdsc + * @reset_count: number of @resets + * @rcdev: reset controller + */ +struct gdsc { + struct generic_pm_domain pd; + struct regmap *regmap; + unsigned int gdscr; + unsigned int *cxcs; + unsigned int cxc_count; + const u8 pwrsts; + struct reset_controller_dev *rcdev; + unsigned int *resets; + unsigned int reset_count; +}; + +#ifdef CONFIG_QCOM_GDSC +int gdsc_register(struct device *, struct gdsc **, size_t n, + struct reset_controller_dev *, struct regmap *); +void gdsc_unregister(struct device *); +#else +static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n, + struct reset_controller_dev *rcdev, + struct regmap *r) +{ + return -ENOSYS; +} + +static inline void gdsc_unregister(struct device *d) {}; +#endif /* CONFIG_QCOM_GDSC */ +#endif /* __QCOM_GDSC_H__ */ diff --git a/kernel/drivers/clk/qcom/lcc-ipq806x.c b/kernel/drivers/clk/qcom/lcc-ipq806x.c index 47f0ac16d..db3998e5e 100644 --- a/kernel/drivers/clk/qcom/lcc-ipq806x.c +++ b/kernel/drivers/clk/qcom/lcc-ipq806x.c @@ -71,7 +71,7 @@ static const struct parent_map lcc_pxo_pll4_map[] = { { P_PLL4, 2 } }; -static const char *lcc_pxo_pll4[] = { +static const char * const lcc_pxo_pll4[] = { "pxo", "pll4_vote", }; @@ -146,7 +146,7 @@ static struct clk_rcg mi2s_osr_src = { }, }; -static const char *lcc_mi2s_parents[] = { +static const char * const lcc_mi2s_parents[] = { "mi2s_osr_src", }; @@ -340,7 +340,7 @@ static struct clk_rcg spdif_src = { }, }; -static const char *lcc_spdif_parents[] = { +static const char * const lcc_spdif_parents[] = { "spdif_src", }; @@ -452,15 +452,8 @@ static int lcc_ipq806x_probe(struct platform_device *pdev) return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap); } -static int lcc_ipq806x_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); - return 0; -} - static struct platform_driver lcc_ipq806x_driver = { .probe = lcc_ipq806x_probe, - .remove = lcc_ipq806x_remove, .driver = { .name = "lcc-ipq806x", .of_match_table = lcc_ipq806x_match_table, diff --git a/kernel/drivers/clk/qcom/lcc-msm8960.c b/kernel/drivers/clk/qcom/lcc-msm8960.c index d0df9d5fc..4fcf9d1d2 100644 --- a/kernel/drivers/clk/qcom/lcc-msm8960.c +++ b/kernel/drivers/clk/qcom/lcc-msm8960.c @@ -57,7 +57,7 @@ static const struct parent_map lcc_pxo_pll4_map[] = { { P_PLL4, 2 } }; -static const char *lcc_pxo_pll4[] = { +static const char * const lcc_pxo_pll4[] = { "pxo", "pll4_vote", }; @@ -127,7 +127,7 @@ static struct clk_rcg mi2s_osr_src = { }, }; -static const char *lcc_mi2s_parents[] = { +static const char * const lcc_mi2s_parents[] = { "mi2s_osr_src", }; @@ -233,7 +233,7 @@ static struct clk_rcg prefix##_osr_src = { \ }, \ }; \ \ -static const char *lcc_##prefix##_parents[] = { \ +static const char * const lcc_##prefix##_parents[] = { \ #prefix "_osr_src", \ }; \ \ @@ -445,7 +445,7 @@ static struct clk_rcg slimbus_src = { }, }; -static const char *lcc_slimbus_parents[] = { +static const char * const lcc_slimbus_parents[] = { "slimbus_src", }; @@ -565,15 +565,8 @@ static int lcc_msm8960_probe(struct platform_device *pdev) return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap); } -static int lcc_msm8960_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); - return 0; -} - static struct platform_driver lcc_msm8960_driver = { .probe = lcc_msm8960_probe, - .remove = lcc_msm8960_remove, .driver = { .name = "lcc-msm8960", .of_match_table = lcc_msm8960_match_table, diff --git a/kernel/drivers/clk/qcom/mmcc-apq8084.c b/kernel/drivers/clk/qcom/mmcc-apq8084.c index 1b17df2cb..30777f9f1 100644 --- a/kernel/drivers/clk/qcom/mmcc-apq8084.c +++ b/kernel/drivers/clk/qcom/mmcc-apq8084.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -26,6 +26,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -53,7 +54,7 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { { P_GPLL0, 5 } }; -static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { +static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = { "xo", "mmpll0_vote", "mmpll1_vote", @@ -69,7 +70,7 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { { P_DSI1PLL, 3 } }; -static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { +static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { "xo", "mmpll0_vote", "hdmipll", @@ -86,7 +87,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { { P_MMPLL2, 3 } }; -static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { +static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = { "xo", "mmpll0_vote", "mmpll1_vote", @@ -102,7 +103,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { { P_MMPLL3, 3 } }; -static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { +static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = { "xo", "mmpll0_vote", "mmpll1_vote", @@ -119,7 +120,7 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { { P_DSI1PLL, 2 } }; -static const char *mmcc_xo_dsi_hdmi_edp[] = { +static const char * const mmcc_xo_dsi_hdmi_edp[] = { "xo", "edp_link_clk", "hdmipll", @@ -137,7 +138,7 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { { P_DSI1PLL, 2 } }; -static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { +static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = { "xo", "edp_link_clk", "hdmipll", @@ -155,7 +156,7 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { { P_DSI1PLL_BYTE, 2 } }; -static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { +static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { "xo", "edp_link_clk", "hdmipll", @@ -172,7 +173,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = { { P_MMPLL4, 3 } }; -static const char *mmcc_xo_mmpll0_1_4_gpll0[] = { +static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = { "xo", "mmpll0", "mmpll1", @@ -189,7 +190,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { { P_GPLL1, 4 } }; -static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = { +static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = { "xo", "mmpll0", "mmpll1", @@ -208,7 +209,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { { P_MMSLEEP, 6 } }; -static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { +static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { "xo", "mmpll0", "mmpll1", @@ -571,17 +572,11 @@ static struct clk_rcg2 jpeg2_clk_src = { }, }; -static struct freq_tbl pixel_freq_tbl[] = { - { .src = P_DSI0PLL }, - { } -}; - static struct clk_rcg2 pclk0_clk_src = { .cmd_rcgr = 0x2000, .mnd_width = 8, .hid_width = 5, .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, - .freq_tbl = pixel_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, @@ -596,7 +591,6 @@ static struct clk_rcg2 pclk1_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, - .freq_tbl = pixel_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, @@ -844,21 +838,15 @@ static struct clk_rcg2 cpp_clk_src = { }, }; -static struct freq_tbl byte_freq_tbl[] = { - { .src = P_DSI0PLL_BYTE }, - { } -}; - static struct clk_rcg2 byte0_clk_src = { .cmd_rcgr = 0x2120, .hid_width = 5, .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, - .freq_tbl = byte_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, .num_parents = 6, - .ops = &clk_byte_ops, + .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, }; @@ -867,12 +855,11 @@ static struct clk_rcg2 byte1_clk_src = { .cmd_rcgr = 0x2140, .hid_width = 5, .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, - .freq_tbl = byte_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "byte1_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, .num_parents = 6, - .ops = &clk_byte_ops, + .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, }; @@ -3077,6 +3064,76 @@ static const struct pll_config mmpll3_config = { .aux_output_mask = BIT(1), }; +static struct gdsc venus0_gdsc = { + .gdscr = 0x1024, + .pd = { + .name = "venus0", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc venus0_core0_gdsc = { + .gdscr = 0x1040, + .pd = { + .name = "venus0_core0", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc venus0_core1_gdsc = { + .gdscr = 0x1044, + .pd = { + .name = "venus0_core1", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x2304, + .cxcs = (unsigned int []){ 0x231c, 0x2320 }, + .cxc_count = 2, + .pd = { + .name = "mdss", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camss_jpeg_gdsc = { + .gdscr = 0x35a4, + .pd = { + .name = "camss_jpeg", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camss_vfe_gdsc = { + .gdscr = 0x36a4, + .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 }, + .cxc_count = 3, + .pd = { + .name = "camss_vfe", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc oxili_gdsc = { + .gdscr = 0x4024, + .cxcs = (unsigned int []){ 0x4028 }, + .cxc_count = 1, + .pd = { + .name = "oxili", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc oxilicx_gdsc = { + .gdscr = 0x4034, + .pd = { + .name = "oxilicx", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *mmcc_apq8084_clocks[] = { [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, @@ -3294,6 +3351,17 @@ static const struct qcom_reset_map mmcc_apq8084_resets[] = { [MMSSNOCAXI_RESET] = { 0x5060 }, }; +static struct gdsc *mmcc_apq8084_gdscs[] = { + [VENUS0_GDSC] = &venus0_gdsc, + [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc, + [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc, + [MDSS_GDSC] = &mdss_gdsc, + [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, + [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, + [OXILI_GDSC] = &oxili_gdsc, + [OXILICX_GDSC] = &oxilicx_gdsc, +}; + static const struct regmap_config mmcc_apq8084_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -3308,6 +3376,8 @@ static const struct qcom_cc_desc mmcc_apq8084_desc = { .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks), .resets = mmcc_apq8084_resets, .num_resets = ARRAY_SIZE(mmcc_apq8084_resets), + .gdscs = mmcc_apq8084_gdscs, + .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs), }; static const struct of_device_id mmcc_apq8084_match_table[] = { @@ -3332,15 +3402,8 @@ static int mmcc_apq8084_probe(struct platform_device *pdev) return 0; } -static int mmcc_apq8084_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); - return 0; -} - static struct platform_driver mmcc_apq8084_driver = { .probe = mmcc_apq8084_probe, - .remove = mmcc_apq8084_remove, .driver = { .name = "mmcc-apq8084", .of_match_table = mmcc_apq8084_match_table, diff --git a/kernel/drivers/clk/qcom/mmcc-msm8960.c b/kernel/drivers/clk/qcom/mmcc-msm8960.c index 9711bca9c..00e36192a 100644 --- a/kernel/drivers/clk/qcom/mmcc-msm8960.c +++ b/kernel/drivers/clk/qcom/mmcc-msm8960.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,10 @@ enum { P_PLL3, P_PLL15, P_HDMI_PLL, + P_DSI1_PLL_DSICLK, + P_DSI2_PLL_DSICLK, + P_DSI1_PLL_BYTECLK, + P_DSI2_PLL_BYTECLK, }; #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } @@ -50,7 +55,7 @@ static const struct parent_map mmcc_pxo_pll8_pll2_map[] = { { P_PLL2, 1 } }; -static const char *mmcc_pxo_pll8_pll2[] = { +static const char * const mmcc_pxo_pll8_pll2[] = { "pxo", "pll8_vote", "pll2", @@ -63,7 +68,7 @@ static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = { { P_PLL3, 3 } }; -static const char *mmcc_pxo_pll8_pll2_pll15[] = { +static const char * const mmcc_pxo_pll8_pll2_pll15[] = { "pxo", "pll8_vote", "pll2", @@ -77,13 +82,37 @@ static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = { { P_PLL15, 3 } }; -static const char *mmcc_pxo_pll8_pll2_pll3[] = { +static const char * const mmcc_pxo_pll8_pll2_pll3[] = { "pxo", "pll8_vote", "pll2", "pll3", }; +static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = { + { P_PXO, 0 }, + { P_DSI2_PLL_DSICLK, 1 }, + { P_DSI1_PLL_DSICLK, 3 }, +}; + +static const char * const mmcc_pxo_dsi2_dsi1[] = { + "pxo", + "dsi2pll", + "dsi1pll", +}; + +static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = { + { P_PXO, 0 }, + { P_DSI1_PLL_BYTECLK, 1 }, + { P_DSI2_PLL_BYTECLK, 2 }, +}; + +static const char * const mmcc_pxo_dsi1_dsi2_byte[] = { + "pxo", + "dsi1pllbyte", + "dsi2pllbyte", +}; + static struct clk_pll pll2 = { .l_reg = 0x320, .m_reg = 0x324, @@ -508,8 +537,7 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) int ret = 0; u32 val; struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw); - struct clk *clk = hw->clk; - int num_parents = __clk_get_num_parents(hw->clk); + int num_parents = clk_hw_get_num_parents(hw); /* * These clocks select three inputs via two muxes. One mux selects @@ -520,7 +548,8 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) * needs to be on at what time. */ for (i = 0; i < num_parents; i++) { - ret = clk_prepare_enable(clk_get_parent_by_index(clk, i)); + struct clk_hw *p = clk_hw_get_parent_by_index(hw, i); + ret = clk_prepare_enable(p->clk); if (ret) goto err; } @@ -548,8 +577,10 @@ static int pix_rdi_set_parent(struct clk_hw *hw, u8 index) udelay(1); err: - for (i--; i >= 0; i--) - clk_disable_unprepare(clk_get_parent_by_index(clk, i)); + for (i--; i >= 0; i--) { + struct clk_hw *p = clk_hw_get_parent_by_index(hw, i); + clk_disable_unprepare(p->clk); + } return ret; } @@ -579,7 +610,7 @@ static const struct clk_ops clk_ops_pix_rdi = { .determine_rate = __clk_mux_determine_rate, }; -static const char *pix_rdi_parents[] = { +static const char * const pix_rdi_parents[] = { "csi0_clk", "csi1_clk", "csi2_clk", @@ -709,7 +740,7 @@ static struct clk_rcg csiphytimer_src = { }, }; -static const char *csixphy_timer_src[] = { "csiphytimer_src" }; +static const char * const csixphy_timer_src[] = { "csiphytimer_src" }; static struct clk_branch csiphy0_timer_clk = { .halt_reg = 0x01e8, @@ -1385,7 +1416,7 @@ static const struct parent_map mmcc_pxo_hdmi_map[] = { { P_HDMI_PLL, 3 } }; -static const char *mmcc_pxo_hdmi[] = { +static const char * const mmcc_pxo_hdmi[] = { "pxo", "hdmi_pll", }; @@ -1428,7 +1459,7 @@ static struct clk_rcg tv_src = { }, }; -static const char *tv_src_name[] = { "tv_src" }; +static const char * const tv_src_name[] = { "tv_src" }; static struct clk_branch tv_enc_clk = { .halt_reg = 0x01d4, @@ -2039,6 +2070,350 @@ static struct clk_branch dsi2_s_ahb_clk = { }, }; +static struct clk_rcg dsi1_src = { + .ns_reg = 0x0054, + .md_reg = 0x0050, + .mn = { + .mnctr_en_bit = 5, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 6, + .n_val_shift = 24, + .m_val_shift = 8, + .width = 8, + }, + .p = { + .pre_div_shift = 14, + .pre_div_width = 2, + }, + .s = { + .src_sel_shift = 0, + .parent_map = mmcc_pxo_dsi2_dsi1_map, + }, + .clkr = { + .enable_reg = 0x004c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "dsi1_src", + .parent_names = mmcc_pxo_dsi2_dsi1, + .num_parents = 3, + .ops = &clk_rcg_bypass2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch dsi1_clk = { + .halt_reg = 0x01d0, + .halt_bit = 2, + .clkr = { + .enable_reg = 0x004c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "dsi1_clk", + .parent_names = (const char *[]){ "dsi1_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_rcg dsi2_src = { + .ns_reg = 0x012c, + .md_reg = 0x00a8, + .mn = { + .mnctr_en_bit = 5, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 6, + .n_val_shift = 24, + .m_val_shift = 8, + .width = 8, + }, + .p = { + .pre_div_shift = 14, + .pre_div_width = 2, + }, + .s = { + .src_sel_shift = 0, + .parent_map = mmcc_pxo_dsi2_dsi1_map, + }, + .clkr = { + .enable_reg = 0x003c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "dsi2_src", + .parent_names = mmcc_pxo_dsi2_dsi1, + .num_parents = 3, + .ops = &clk_rcg_bypass2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch dsi2_clk = { + .halt_reg = 0x01d0, + .halt_bit = 20, + .clkr = { + .enable_reg = 0x003c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "dsi2_clk", + .parent_names = (const char *[]){ "dsi2_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_rcg dsi1_byte_src = { + .ns_reg = 0x00b0, + .p = { + .pre_div_shift = 12, + .pre_div_width = 4, + }, + .s = { + .src_sel_shift = 0, + .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, + }, + .clkr = { + .enable_reg = 0x0090, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "dsi1_byte_src", + .parent_names = mmcc_pxo_dsi1_dsi2_byte, + .num_parents = 3, + .ops = &clk_rcg_bypass2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch dsi1_byte_clk = { + .halt_reg = 0x01cc, + .halt_bit = 21, + .clkr = { + .enable_reg = 0x0090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "dsi1_byte_clk", + .parent_names = (const char *[]){ "dsi1_byte_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_rcg dsi2_byte_src = { + .ns_reg = 0x012c, + .p = { + .pre_div_shift = 12, + .pre_div_width = 4, + }, + .s = { + .src_sel_shift = 0, + .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, + }, + .clkr = { + .enable_reg = 0x0130, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "dsi2_byte_src", + .parent_names = mmcc_pxo_dsi1_dsi2_byte, + .num_parents = 3, + .ops = &clk_rcg_bypass2_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_branch dsi2_byte_clk = { + .halt_reg = 0x01cc, + .halt_bit = 20, + .clkr = { + .enable_reg = 0x00b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "dsi2_byte_clk", + .parent_names = (const char *[]){ "dsi2_byte_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_rcg dsi1_esc_src = { + .ns_reg = 0x0011c, + .p = { + .pre_div_shift = 12, + .pre_div_width = 4, + }, + .s = { + .src_sel_shift = 0, + .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, + }, + .clkr = { + .enable_reg = 0x00cc, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "dsi1_esc_src", + .parent_names = mmcc_pxo_dsi1_dsi2_byte, + .num_parents = 3, + .ops = &clk_rcg_esc_ops, + }, + }, +}; + +static struct clk_branch dsi1_esc_clk = { + .halt_reg = 0x01e8, + .halt_bit = 1, + .clkr = { + .enable_reg = 0x00cc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "dsi1_esc_clk", + .parent_names = (const char *[]){ "dsi1_esc_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_rcg dsi2_esc_src = { + .ns_reg = 0x0150, + .p = { + .pre_div_shift = 12, + .pre_div_width = 4, + }, + .s = { + .src_sel_shift = 0, + .parent_map = mmcc_pxo_dsi1_dsi2_byte_map, + }, + .clkr = { + .enable_reg = 0x013c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "dsi2_esc_src", + .parent_names = mmcc_pxo_dsi1_dsi2_byte, + .num_parents = 3, + .ops = &clk_rcg_esc_ops, + }, + }, +}; + +static struct clk_branch dsi2_esc_clk = { + .halt_reg = 0x01e8, + .halt_bit = 3, + .clkr = { + .enable_reg = 0x013c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "dsi2_esc_clk", + .parent_names = (const char *[]){ "dsi2_esc_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_rcg dsi1_pixel_src = { + .ns_reg = 0x0138, + .md_reg = 0x0134, + .mn = { + .mnctr_en_bit = 5, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 6, + .n_val_shift = 16, + .m_val_shift = 8, + .width = 8, + }, + .p = { + .pre_div_shift = 12, + .pre_div_width = 4, + }, + .s = { + .src_sel_shift = 0, + .parent_map = mmcc_pxo_dsi2_dsi1_map, + }, + .clkr = { + .enable_reg = 0x0130, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "dsi1_pixel_src", + .parent_names = mmcc_pxo_dsi2_dsi1, + .num_parents = 3, + .ops = &clk_rcg_pixel_ops, + }, + }, +}; + +static struct clk_branch dsi1_pixel_clk = { + .halt_reg = 0x01d0, + .halt_bit = 6, + .clkr = { + .enable_reg = 0x0130, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mdp_pclk1_clk", + .parent_names = (const char *[]){ "dsi1_pixel_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static struct clk_rcg dsi2_pixel_src = { + .ns_reg = 0x00e4, + .md_reg = 0x00b8, + .mn = { + .mnctr_en_bit = 5, + .mnctr_reset_bit = 7, + .mnctr_mode_shift = 6, + .n_val_shift = 16, + .m_val_shift = 8, + .width = 8, + }, + .p = { + .pre_div_shift = 12, + .pre_div_width = 4, + }, + .s = { + .src_sel_shift = 0, + .parent_map = mmcc_pxo_dsi2_dsi1_map, + }, + .clkr = { + .enable_reg = 0x0094, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "dsi2_pixel_src", + .parent_names = mmcc_pxo_dsi2_dsi1, + .num_parents = 3, + .ops = &clk_rcg_pixel_ops, + }, + }, +}; + +static struct clk_branch dsi2_pixel_clk = { + .halt_reg = 0x01d0, + .halt_bit = 19, + .clkr = { + .enable_reg = 0x0094, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mdp_pclk2_clk", + .parent_names = (const char *[]){ "dsi2_pixel_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_branch gfx2d0_ahb_clk = { .hwcg_reg = 0x0038, .hwcg_bit = 28, @@ -2322,6 +2697,8 @@ static struct clk_regmap *mmcc_msm8960_clks[] = { [CSI2_SRC] = &csi2_src.clkr, [CSI2_CLK] = &csi2_clk.clkr, [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, + [DSI_SRC] = &dsi1_src.clkr, + [DSI_CLK] = &dsi1_clk.clkr, [CSI_PIX_CLK] = &csi_pix_clk.clkr, [CSI_RDI_CLK] = &csi_rdi_clk.clkr, [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, @@ -2342,6 +2719,18 @@ static struct clk_regmap *mmcc_msm8960_clks[] = { [MDP_SRC] = &mdp_src.clkr, [MDP_CLK] = &mdp_clk.clkr, [MDP_LUT_CLK] = &mdp_lut_clk.clkr, + [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr, + [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr, + [DSI2_SRC] = &dsi2_src.clkr, + [DSI2_CLK] = &dsi2_clk.clkr, + [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr, + [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr, + [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr, + [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr, + [DSI1_ESC_SRC] = &dsi1_esc_src.clkr, + [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr, + [DSI2_ESC_SRC] = &dsi2_esc_src.clkr, + [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr, [ROT_SRC] = &rot_src.clkr, [ROT_CLK] = &rot_clk.clkr, [TV_ENC_CLK] = &tv_enc_clk.clkr, @@ -2356,6 +2745,8 @@ static struct clk_regmap *mmcc_msm8960_clks[] = { [VFE_CSI_CLK] = &vfe_csi_clk.clkr, [VPE_SRC] = &vpe_src.clkr, [VPE_CLK] = &vpe_clk.clkr, + [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr, + [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr, [CAMCLK0_SRC] = &camclk0_src.clkr, [CAMCLK0_CLK] = &camclk0_clk.clkr, [CAMCLK1_SRC] = &camclk1_src.clkr, @@ -2487,6 +2878,8 @@ static struct clk_regmap *mmcc_apq8064_clks[] = { [CSI2_SRC] = &csi2_src.clkr, [CSI2_CLK] = &csi2_clk.clkr, [CSI2_PHY_CLK] = &csi2_phy_clk.clkr, + [DSI_SRC] = &dsi1_src.clkr, + [DSI_CLK] = &dsi1_clk.clkr, [CSI_PIX_CLK] = &csi_pix_clk.clkr, [CSI_RDI_CLK] = &csi_rdi_clk.clkr, [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr, @@ -2503,6 +2896,18 @@ static struct clk_regmap *mmcc_apq8064_clks[] = { [MDP_SRC] = &mdp_src.clkr, [MDP_CLK] = &mdp_clk.clkr, [MDP_LUT_CLK] = &mdp_lut_clk.clkr, + [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr, + [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr, + [DSI2_SRC] = &dsi2_src.clkr, + [DSI2_CLK] = &dsi2_clk.clkr, + [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr, + [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr, + [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr, + [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr, + [DSI1_ESC_SRC] = &dsi1_esc_src.clkr, + [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr, + [DSI2_ESC_SRC] = &dsi2_esc_src.clkr, + [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr, [ROT_SRC] = &rot_src.clkr, [ROT_CLK] = &rot_clk.clkr, [TV_DAC_CLK] = &tv_dac_clk.clkr, @@ -2516,6 +2921,8 @@ static struct clk_regmap *mmcc_apq8064_clks[] = { [VFE_CSI_CLK] = &vfe_csi_clk.clkr, [VPE_SRC] = &vpe_src.clkr, [VPE_CLK] = &vpe_clk.clkr, + [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr, + [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr, [CAMCLK0_SRC] = &camclk0_src.clkr, [CAMCLK0_CLK] = &camclk0_clk.clkr, [CAMCLK1_SRC] = &camclk1_src.clkr, @@ -2683,15 +3090,8 @@ static int mmcc_msm8960_probe(struct platform_device *pdev) return qcom_cc_really_probe(pdev, match->data, regmap); } -static int mmcc_msm8960_remove(struct platform_device *pdev) -{ - qcom_cc_remove(pdev); - return 0; -} - static struct platform_driver mmcc_msm8960_driver = { .probe = mmcc_msm8960_probe, - .remove = mmcc_msm8960_remove, .driver = { .name = "mmcc-msm8960", .of_match_table = mmcc_msm8960_match_table, diff --git a/kernel/drivers/clk/qcom/mmcc-msm8974.c b/kernel/drivers/clk/qcom/mmcc-msm8974.c index 07f4cc159..9d790bcad 100644 --- a/kernel/drivers/clk/qcom/mmcc-msm8974.c +++ b/kernel/drivers/clk/qcom/mmcc-msm8974.c @@ -31,6 +31,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -56,7 +57,7 @@ static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { { P_GPLL0, 5 } }; -static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { +static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = { "xo", "mmpll0_vote", "mmpll1_vote", @@ -72,7 +73,7 @@ static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { { P_DSI1PLL, 3 } }; -static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { +static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { "xo", "mmpll0_vote", "hdmipll", @@ -89,7 +90,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { { P_MMPLL2, 3 } }; -static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { +static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = { "xo", "mmpll0_vote", "mmpll1_vote", @@ -105,7 +106,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { { P_MMPLL3, 3 } }; -static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { +static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = { "xo", "mmpll0_vote", "mmpll1_vote", @@ -121,7 +122,7 @@ static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = { { P_GPLL1, 4 } }; -static const char *mmcc_xo_mmpll0_1_gpll1_0[] = { +static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = { "xo", "mmpll0_vote", "mmpll1_vote", @@ -138,7 +139,7 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { { P_DSI1PLL, 2 } }; -static const char *mmcc_xo_dsi_hdmi_edp[] = { +static const char * const mmcc_xo_dsi_hdmi_edp[] = { "xo", "edp_link_clk", "hdmipll", @@ -156,7 +157,7 @@ static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { { P_DSI1PLL, 2 } }; -static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { +static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = { "xo", "edp_link_clk", "hdmipll", @@ -174,7 +175,7 @@ static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { { P_DSI1PLL_BYTE, 2 } }; -static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { +static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { "xo", "edp_link_clk", "hdmipll", @@ -522,17 +523,11 @@ static struct clk_rcg2 jpeg2_clk_src = { }, }; -static struct freq_tbl pixel_freq_tbl[] = { - { .src = P_DSI0PLL }, - { } -}; - static struct clk_rcg2 pclk0_clk_src = { .cmd_rcgr = 0x2000, .mnd_width = 8, .hid_width = 5, .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, - .freq_tbl = pixel_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, @@ -547,7 +542,6 @@ static struct clk_rcg2 pclk1_clk_src = { .mnd_width = 8, .hid_width = 5, .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, - .freq_tbl = pixel_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, @@ -785,7 +779,7 @@ static struct clk_rcg2 byte0_clk_src = { .name = "byte0_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, .num_parents = 6, - .ops = &clk_byte_ops, + .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, }; @@ -799,7 +793,7 @@ static struct clk_rcg2 byte1_clk_src = { .name = "byte1_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, .num_parents = 6, - .ops = &clk_byte_ops, + .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, }; @@ -2349,6 +2343,66 @@ static struct pll_config mmpll3_config = { .aux_output_mask = BIT(1), }; +static struct gdsc venus0_gdsc = { + .gdscr = 0x1024, + .cxcs = (unsigned int []){ 0x1028 }, + .cxc_count = 1, + .resets = (unsigned int []){ VENUS0_RESET }, + .reset_count = 1, + .pd = { + .name = "venus0", + }, + .pwrsts = PWRSTS_ON, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x2304, + .cxcs = (unsigned int []){ 0x231c, 0x2320 }, + .cxc_count = 2, + .pd = { + .name = "mdss", + }, + .pwrsts = PWRSTS_RET_ON, +}; + +static struct gdsc camss_jpeg_gdsc = { + .gdscr = 0x35a4, + .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 }, + .cxc_count = 3, + .pd = { + .name = "camss_jpeg", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc camss_vfe_gdsc = { + .gdscr = 0x36a4, + .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 }, + .cxc_count = 5, + .pd = { + .name = "camss_vfe", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc oxili_gdsc = { + .gdscr = 0x4024, + .cxcs = (unsigned int []){ 0x4028 }, + .cxc_count = 1, + .pd = { + .name = "oxili", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc oxilicx_gdsc = { + .gdscr = 0x4034, + .pd = { + .name = "oxilicx", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *mmcc_msm8974_clocks[] = { [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, @@ -2525,6 +2579,15 @@ static const struct qcom_reset_map mmcc_msm8974_resets[] = { [OCMEMNOC_RESET] = { 0x50b0 }, }; +static struct gdsc *mmcc_msm8974_gdscs[] = { + [VENUS0_GDSC] = &venus0_gdsc, + [MDSS_GDSC] = &mdss_gdsc, + [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, + [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, + [OXILI_GDSC] = &oxili_gdsc, + [OXILICX_GDSC] = &oxilicx_gdsc, +}; + static const struct regmap_config mmcc_msm8974_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -2539,6 +2602,8 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = { .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks), .resets = mmcc_msm8974_resets, .num_resets = ARRAY_SIZE(mmcc_msm8974_resets), + .gdscs = mmcc_msm8974_gdscs, + .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs), }; static const struct of_device_id mmcc_msm8974_match_table[] = { @@ -2550,6 +2615,7 @@ MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table); static int mmcc_msm8974_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc); if (IS_ERR(regmap)) @@ -2558,12 +2624,16 @@ static int mmcc_msm8974_probe(struct platform_device *pdev) clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); - return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap); + ret = qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap); + if (ret) + return ret; + + return pm_genpd_add_subdomain(&oxili_gdsc.pd, &oxilicx_gdsc.pd); } static int mmcc_msm8974_remove(struct platform_device *pdev) { - qcom_cc_remove(pdev); + pm_genpd_remove_subdomain(&oxili_gdsc.pd, &oxilicx_gdsc.pd); return 0; } -- cgit 1.2.3-korg