From 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 Mon Sep 17 00:00:00 2001 From: Yunhong Jiang Date: Tue, 4 Aug 2015 12:17:53 -0700 Subject: Add the rt linux 4.1.3-rt3 as base Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang --- kernel/arch/cris/Kconfig | 577 ++ kernel/arch/cris/Kconfig.debug | 40 + kernel/arch/cris/Makefile | 104 + kernel/arch/cris/arch-v10/Kconfig | 398 ++ kernel/arch/cris/arch-v10/README.mm | 244 + kernel/arch/cris/arch-v10/drivers/Kconfig | 560 ++ kernel/arch/cris/arch-v10/drivers/Makefile | 10 + kernel/arch/cris/arch-v10/drivers/axisflashmap.c | 432 ++ kernel/arch/cris/arch-v10/drivers/eeprom.c | 852 +++ kernel/arch/cris/arch-v10/drivers/gpio.c | 856 +++ kernel/arch/cris/arch-v10/drivers/i2c.c | 698 ++ kernel/arch/cris/arch-v10/drivers/i2c.h | 17 + kernel/arch/cris/arch-v10/drivers/sync_serial.c | 1462 ++++ kernel/arch/cris/arch-v10/kernel/Makefile | 17 + kernel/arch/cris/arch-v10/kernel/crisksyms.c | 16 + kernel/arch/cris/arch-v10/kernel/debugport.c | 559 ++ kernel/arch/cris/arch-v10/kernel/dma.c | 287 + kernel/arch/cris/arch-v10/kernel/entry.S | 969 +++ kernel/arch/cris/arch-v10/kernel/fasttimer.c | 834 +++ kernel/arch/cris/arch-v10/kernel/head.S | 723 ++ .../arch/cris/arch-v10/kernel/io_interface_mux.c | 1182 ++++ kernel/arch/cris/arch-v10/kernel/irq.c | 235 + kernel/arch/cris/arch-v10/kernel/kgdb.c | 1144 +++ kernel/arch/cris/arch-v10/kernel/process.c | 193 + kernel/arch/cris/arch-v10/kernel/ptrace.c | 202 + kernel/arch/cris/arch-v10/kernel/setup.c | 106 + kernel/arch/cris/arch-v10/kernel/shadows.c | 36 + kernel/arch/cris/arch-v10/kernel/signal.c | 438 ++ kernel/arch/cris/arch-v10/kernel/time.c | 267 + kernel/arch/cris/arch-v10/kernel/traps.c | 131 + kernel/arch/cris/arch-v10/lib/Makefile | 6 + kernel/arch/cris/arch-v10/lib/checksum.S | 118 + kernel/arch/cris/arch-v10/lib/checksumcopy.S | 126 + kernel/arch/cris/arch-v10/lib/csumcpfruser.S | 64 + kernel/arch/cris/arch-v10/lib/dmacopy.c | 42 + kernel/arch/cris/arch-v10/lib/dram_init.S | 146 + kernel/arch/cris/arch-v10/lib/hw_settings.S | 60 + kernel/arch/cris/arch-v10/lib/memset.c | 259 + kernel/arch/cris/arch-v10/lib/old_checksum.c | 86 + kernel/arch/cris/arch-v10/lib/string.c | 236 + kernel/arch/cris/arch-v10/lib/usercopy.c | 523 ++ kernel/arch/cris/arch-v10/mm/Makefile | 6 + kernel/arch/cris/arch-v10/mm/fault.c | 95 + kernel/arch/cris/arch-v10/mm/init.c | 263 + kernel/arch/cris/arch-v10/mm/tlb.c | 176 + kernel/arch/cris/arch-v10/output_arch.ld | 2 + kernel/arch/cris/arch-v32/Kconfig | 299 + kernel/arch/cris/arch-v32/drivers/Kconfig | 430 ++ kernel/arch/cris/arch-v32/drivers/Makefile | 12 + kernel/arch/cris/arch-v32/drivers/axisflashmap.c | 619 ++ kernel/arch/cris/arch-v32/drivers/cryptocop.c | 3536 ++++++++++ kernel/arch/cris/arch-v32/drivers/i2c.c | 751 ++ kernel/arch/cris/arch-v32/drivers/i2c.h | 16 + kernel/arch/cris/arch-v32/drivers/iop_fw_load.c | 230 + kernel/arch/cris/arch-v32/drivers/mach-a3/Makefile | 6 + kernel/arch/cris/arch-v32/drivers/mach-a3/gpio.c | 999 +++ .../arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 180 + kernel/arch/cris/arch-v32/drivers/mach-fs/Makefile | 6 + kernel/arch/cris/arch-v32/drivers/mach-fs/gpio.c | 979 +++ .../arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 174 + kernel/arch/cris/arch-v32/drivers/pci/Makefile | 5 + kernel/arch/cris/arch-v32/drivers/pci/bios.c | 99 + kernel/arch/cris/arch-v32/drivers/pci/dma.c | 50 + kernel/arch/cris/arch-v32/drivers/sync_serial.c | 1709 +++++ kernel/arch/cris/arch-v32/kernel/Makefile | 17 + kernel/arch/cris/arch-v32/kernel/cache.c | 33 + kernel/arch/cris/arch-v32/kernel/cacheflush.S | 99 + kernel/arch/cris/arch-v32/kernel/crisksyms.c | 28 + kernel/arch/cris/arch-v32/kernel/debugport.c | 233 + kernel/arch/cris/arch-v32/kernel/entry.S | 889 +++ kernel/arch/cris/arch-v32/kernel/fasttimer.c | 793 +++ kernel/arch/cris/arch-v32/kernel/head.S | 440 ++ kernel/arch/cris/arch-v32/kernel/irq.c | 520 ++ kernel/arch/cris/arch-v32/kernel/kgdb.c | 1612 +++++ kernel/arch/cris/arch-v32/kernel/kgdb_asm.S | 551 ++ kernel/arch/cris/arch-v32/kernel/process.c | 184 + kernel/arch/cris/arch-v32/kernel/ptrace.c | 490 ++ kernel/arch/cris/arch-v32/kernel/setup.c | 170 + kernel/arch/cris/arch-v32/kernel/signal.c | 540 ++ kernel/arch/cris/arch-v32/kernel/time.c | 342 + kernel/arch/cris/arch-v32/kernel/traps.c | 193 + kernel/arch/cris/arch-v32/lib/Makefile | 7 + kernel/arch/cris/arch-v32/lib/checksum.S | 88 + kernel/arch/cris/arch-v32/lib/checksumcopy.S | 94 + kernel/arch/cris/arch-v32/lib/csumcpfruser.S | 69 + kernel/arch/cris/arch-v32/lib/delay.c | 28 + kernel/arch/cris/arch-v32/lib/memset.c | 259 + kernel/arch/cris/arch-v32/lib/strcmp.S | 21 + kernel/arch/cris/arch-v32/lib/string.c | 236 + kernel/arch/cris/arch-v32/lib/usercopy.c | 469 ++ kernel/arch/cris/arch-v32/mach-a3/Kconfig | 110 + kernel/arch/cris/arch-v32/mach-a3/Makefile | 8 + kernel/arch/cris/arch-v32/mach-a3/arbiter.c | 634 ++ kernel/arch/cris/arch-v32/mach-a3/dma.c | 184 + kernel/arch/cris/arch-v32/mach-a3/dram_init.S | 118 + kernel/arch/cris/arch-v32/mach-a3/hw_settings.S | 53 + kernel/arch/cris/arch-v32/mach-a3/io.c | 149 + kernel/arch/cris/arch-v32/mach-a3/pinmux.c | 388 ++ kernel/arch/cris/arch-v32/mach-fs/Kconfig | 216 + kernel/arch/cris/arch-v32/mach-fs/Makefile | 8 + kernel/arch/cris/arch-v32/mach-fs/arbiter.c | 404 ++ kernel/arch/cris/arch-v32/mach-fs/dma.c | 229 + kernel/arch/cris/arch-v32/mach-fs/dram_init.S | 116 + kernel/arch/cris/arch-v32/mach-fs/hw_settings.S | 70 + kernel/arch/cris/arch-v32/mach-fs/io.c | 191 + kernel/arch/cris/arch-v32/mach-fs/pinmux.c | 323 + kernel/arch/cris/arch-v32/mm/Makefile | 4 + kernel/arch/cris/arch-v32/mm/init.c | 162 + kernel/arch/cris/arch-v32/mm/intmem.c | 150 + kernel/arch/cris/arch-v32/mm/l2cache.c | 29 + kernel/arch/cris/arch-v32/mm/mmu.S | 210 + kernel/arch/cris/arch-v32/mm/tlb.c | 207 + kernel/arch/cris/arch-v32/output_arch.ld | 2 + kernel/arch/cris/boot/.gitignore | 2 + kernel/arch/cris/boot/Makefile | 24 + kernel/arch/cris/boot/compressed/Makefile | 38 + kernel/arch/cris/boot/compressed/README | 24 + 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kernel/arch/cris/include/arch-v32/arch/irqflags.h | 46 + kernel/arch/cris/include/arch-v32/arch/memmap.h | 1 + kernel/arch/cris/include/arch-v32/arch/mmu.h | 110 + kernel/arch/cris/include/arch-v32/arch/offset.h | 35 + kernel/arch/cris/include/arch-v32/arch/page.h | 22 + kernel/arch/cris/include/arch-v32/arch/pgtable.h | 17 + kernel/arch/cris/include/arch-v32/arch/processor.h | 53 + kernel/arch/cris/include/arch-v32/arch/ptrace.h | 118 + kernel/arch/cris/include/arch-v32/arch/swab.h | 24 + kernel/arch/cris/include/arch-v32/arch/system.h | 37 + .../arch/cris/include/arch-v32/arch/thread_info.h | 13 + kernel/arch/cris/include/arch-v32/arch/timex.h | 31 + kernel/arch/cris/include/arch-v32/arch/tlb.h | 14 + kernel/arch/cris/include/arch-v32/arch/uaccess.h | 747 ++ kernel/arch/cris/include/arch-v32/arch/unistd.h | 155 + .../cris/include/arch-v32/mach-a3/mach/arbiter.h | 34 + .../arch/cris/include/arch-v32/mach-a3/mach/dma.h | 58 + .../mach-a3/mach/hwregs/asm/clkgen_defs_asm.h | 164 + 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kernel/arch/cris/include/uapi/asm/msgbuf.h create mode 100644 kernel/arch/cris/include/uapi/asm/param.h create mode 100644 kernel/arch/cris/include/uapi/asm/poll.h create mode 100644 kernel/arch/cris/include/uapi/asm/posix_types.h create mode 100644 kernel/arch/cris/include/uapi/asm/ptrace.h create mode 100644 kernel/arch/cris/include/uapi/asm/resource.h create mode 100644 kernel/arch/cris/include/uapi/asm/rs485.h create mode 100644 kernel/arch/cris/include/uapi/asm/sembuf.h create mode 100644 kernel/arch/cris/include/uapi/asm/setup.h create mode 100644 kernel/arch/cris/include/uapi/asm/shmbuf.h create mode 100644 kernel/arch/cris/include/uapi/asm/sigcontext.h create mode 100644 kernel/arch/cris/include/uapi/asm/siginfo.h create mode 100644 kernel/arch/cris/include/uapi/asm/signal.h create mode 100644 kernel/arch/cris/include/uapi/asm/socket.h create mode 100644 kernel/arch/cris/include/uapi/asm/sockios.h create mode 100644 kernel/arch/cris/include/uapi/asm/stat.h create mode 100644 kernel/arch/cris/include/uapi/asm/statfs.h create mode 100644 kernel/arch/cris/include/uapi/asm/swab.h create mode 100644 kernel/arch/cris/include/uapi/asm/sync_serial.h create mode 100644 kernel/arch/cris/include/uapi/asm/termbits.h create mode 100644 kernel/arch/cris/include/uapi/asm/termios.h create mode 100644 kernel/arch/cris/include/uapi/asm/types.h create mode 100644 kernel/arch/cris/include/uapi/asm/unistd.h create mode 100644 kernel/arch/cris/kernel/Makefile create mode 100644 kernel/arch/cris/kernel/asm-offsets.c create mode 100644 kernel/arch/cris/kernel/crisksyms.c create mode 100644 kernel/arch/cris/kernel/devicetree.c create mode 100644 kernel/arch/cris/kernel/irq.c create mode 100644 kernel/arch/cris/kernel/module.c create mode 100644 kernel/arch/cris/kernel/process.c create mode 100644 kernel/arch/cris/kernel/profile.c create mode 100644 kernel/arch/cris/kernel/ptrace.c create mode 100644 kernel/arch/cris/kernel/setup.c create mode 100644 kernel/arch/cris/kernel/sys_cris.c create mode 100644 kernel/arch/cris/kernel/time.c create mode 100644 kernel/arch/cris/kernel/traps.c create mode 100644 kernel/arch/cris/kernel/vmlinux.lds.S create mode 100644 kernel/arch/cris/mm/Makefile create mode 100644 kernel/arch/cris/mm/fault.c create mode 100644 kernel/arch/cris/mm/init.c create mode 100644 kernel/arch/cris/mm/ioremap.c create mode 100644 kernel/arch/cris/mm/tlb.c (limited to 'kernel/arch/cris') diff --git a/kernel/arch/cris/Kconfig b/kernel/arch/cris/Kconfig new file mode 100644 index 000000000..0314e325a --- /dev/null +++ b/kernel/arch/cris/Kconfig @@ -0,0 +1,577 @@ +config MMU + bool + default y + +config ZONE_DMA + bool + default y + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +config RWSEM_XCHGADD_ALGORITHM + bool + +config ARCH_HAS_ILOG2_U32 + bool + default n + +config ARCH_HAS_ILOG2_U64 + bool + default n + +config GENERIC_HWEIGHT + bool + default y + +config GENERIC_CALIBRATE_DELAY + bool + default y + +config NO_IOPORT_MAP + def_bool y + +config FORCE_MAX_ZONEORDER + int + default 6 + +config CRIS + bool + default y + select HAVE_IDE + select GENERIC_ATOMIC64 + select HAVE_UID16 + select VIRT_TO_BUS + select ARCH_WANT_IPC_PARSE_VERSION + select GENERIC_IRQ_SHOW + select GENERIC_IOMAP + select GENERIC_CMOS_UPDATE + select MODULES_USE_ELF_RELA + select CLONE_BACKWARDS2 + select OLD_SIGSUSPEND + select OLD_SIGACTION + select ARCH_REQUIRE_GPIOLIB + select IRQ_DOMAIN if ETRAX_ARCH_V32 + select OF if ETRAX_ARCH_V32 + select OF_EARLY_FLATTREE if ETRAX_ARCH_V32 + select CLKSRC_MMIO if ETRAX_ARCH_V32 + select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32 + select GENERIC_SCHED_CLOCK if ETRAX_ARCH_V32 + +config HZ + int + default 100 + +config NR_CPUS + int + default "1" + +config BUILTIN_DTB + string "DTB to build into the kernel image" + depends on OF + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "General setup" + +source "fs/Kconfig.binfmt" + +config ETRAX_CMDLINE + string "Kernel command line" + default "root=/dev/mtdblock3" + help + Pass additional commands to the kernel. + +config ETRAX_WATCHDOG + bool "Enable ETRAX watchdog" + help + Enable the built-in watchdog timer support on ETRAX based embedded + network computers. + +config ETRAX_WATCHDOG_NICE_DOGGY + bool "Disable watchdog during Oops printouts" + depends on ETRAX_WATCHDOG + help + By enabling this you make sure that the watchdog does not bite while + printing oopses. Recommended for development systems but not for + production releases. + +config ETRAX_FAST_TIMER + bool "Enable ETRAX fast timer API" + help + This options enables the API to a fast timer implementation using + timer1 to get sub jiffie resolution timers (primarily one-shot + timers). + This is needed if CONFIG_ETRAX_SERIAL_FAST_TIMER is enabled. + +config ETRAX_KMALLOCED_MODULES + bool "Enable module allocation with kmalloc" + help + Enable module allocation with kmalloc instead of vmalloc. + +source "kernel/Kconfig.preempt" + +source mm/Kconfig + +endmenu + +menu "Hardware setup" + +choice + prompt "Processor type" + default ETRAX100LX + +config ETRAX100LX + bool "ETRAX-100LX-v1" + select ARCH_USES_GETTIMEOFFSET + help + Support version 1 of the ETRAX 100LX. + +config ETRAX100LX_V2 + bool "ETRAX-100LX-v2" + select ARCH_USES_GETTIMEOFFSET + help + Support version 2 of the ETRAX 100LX. + +config ETRAXFS + bool "ETRAX-FS-V32" + help + Support CRIS V32. + +config CRIS_MACH_ARTPEC3 + bool "ARTPEC-3" + help + Support Axis ARTPEC-3. + +endchoice + +config ETRAX_ARCH_V10 + bool + default y if ETRAX100LX || ETRAX100LX_V2 + default n if !(ETRAX100LX || ETRAX100LX_V2) + select TTY + +config ETRAX_ARCH_V32 + bool + default y if (ETRAXFS || CRIS_MACH_ARTPEC3) + default n if !(ETRAXFS || CRIS_MACH_ARTPEC3) + +config ETRAX_DRAM_SIZE + int "DRAM size (dec, in MB)" + default "8" + help + Size of DRAM (decimal in MB) typically 2, 8 or 16. + +config ETRAX_VMEM_SIZE + int "Video memory size (dec, in MB)" + depends on ETRAX_ARCH_V32 && !ETRAXFS + default 8 if !ETRAXFS + help + Size of Video accessible memory (decimal, in MB). + +config ETRAX_FLASH_BUSWIDTH + int "Buswidth of NOR flash in bytes" + default "2" + help + Width in bytes of the NOR Flash bus (1, 2 or 4). Is usually 2. + +config ETRAX_FLASH1_SIZE + int "FLASH1 size (dec, in MB. 0 = Unknown)" + default "0" + +choice + prompt "Product debug-port" + default ETRAX_DEBUG_PORT0 + +config ETRAX_DEBUG_PORT0 + bool "Serial-0" + help + Choose a serial port for the ETRAX debug console. Default to + port 0. + +config ETRAX_DEBUG_PORT1 + bool "Serial-1" + help + Use serial port 1 for the console. + +config ETRAX_DEBUG_PORT2 + bool "Serial-2" + help + Use serial port 2 for the console. + +config ETRAX_DEBUG_PORT3 + bool "Serial-3" + help + Use serial port 3 for the console. + +config ETRAX_DEBUG_PORT_NULL + bool "disabled" + help + Disable serial-port debugging. + +endchoice + +choice + prompt "Kernel GDB port" + depends on ETRAX_KGDB + default ETRAX_KGDB_PORT0 + help + Choose a serial port for kernel debugging. NOTE: This port should + not be enabled under Drivers for built-in interfaces (as it has its + own initialization code) and should not be the same as the debug port. + +config ETRAX_KGDB_PORT0 + bool "Serial-0" + help + Use serial port 0 for kernel debugging. + +config ETRAX_KGDB_PORT1 + bool "Serial-1" + help + Use serial port 1 for kernel debugging. + +config ETRAX_KGDB_PORT2 + bool "Serial-2" + help + Use serial port 2 for kernel debugging. + +config ETRAX_KGDB_PORT3 + bool "Serial-3" + help + Use serial port 3 for kernel debugging. + +endchoice + +source arch/cris/arch-v10/Kconfig +source arch/cris/arch-v32/Kconfig + +endmenu + +source "net/Kconfig" + +# bring in ETRAX built-in drivers +menu "Drivers for built-in interfaces" +source arch/cris/arch-v10/drivers/Kconfig +source arch/cris/arch-v32/drivers/Kconfig + +config ETRAX_AXISFLASHMAP + bool "Axis flash-map support" + select MTD + select MTD_CFI + select MTD_CFI_AMDSTD + select MTD_JEDECPROBE if ETRAX_ARCH_V32 + select MTD_BLOCK + select MTD_COMPLEX_MAPPINGS + help + This option enables MTD mapping of flash devices. Needed to use + flash memories. If unsure, say Y. + +config ETRAX_SYNCHRONOUS_SERIAL + bool "Synchronous serial-port support" + help + Select this to enable the synchronous serial port driver. + +config ETRAX_SYNCHRONOUS_SERIAL_PORT0 + bool "Synchronous serial port 0 enabled" + depends on ETRAX_SYNCHRONOUS_SERIAL + help + Enabled synchronous serial port 0. + +config ETRAX_SYNCHRONOUS_SERIAL0_DMA + bool "Enable DMA on synchronous serial port 0." + depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0 + help + A synchronous serial port can run in manual or DMA mode. + Selecting this option will make it run in DMA mode. + +config ETRAX_SYNCHRONOUS_SERIAL_PORT1 + bool "Synchronous serial port 1 enabled" + depends on ETRAX_SYNCHRONOUS_SERIAL && (ETRAXFS || ETRAX_ARCH_V10) + help + Enabled synchronous serial port 1. + +config ETRAX_SYNCHRONOUS_SERIAL1_DMA + bool "Enable DMA on synchronous serial port 1." + depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1 + help + A synchronous serial port can run in manual or DMA mode. + Selecting this option will make it run in DMA mode. + +choice + prompt "Network LED behavior" + depends on ETRAX_ETHERNET + default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY + +config ETRAX_NETWORK_LED_ON_WHEN_LINK + bool "LED_on_when_link" + help + Selecting LED_on_when_link will light the LED when there is a + connection and will flash off when there is activity. + + Selecting LED_on_when_activity will light the LED only when + there is activity. + + This setting will also affect the behaviour of other activity LEDs + e.g. Bluetooth. + +config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY + bool "LED_on_when_activity" + help + Selecting LED_on_when_link will light the LED when there is a + connection and will flash off when there is activity. + + Selecting LED_on_when_activity will light the LED only when + there is activity. + + This setting will also affect the behaviour of other activity LEDs + e.g. Bluetooth. + +endchoice + +choice + prompt "Ser0 DMA out channel" + depends on ETRAX_SERIAL_PORT0 + default ETRAX_SERIAL_PORT0_DMA6_OUT if ETRAX_ARCH_V32 + default ETRAX_SERIAL_PORT0_NO_DMA_OUT if ETRAX_ARCH_V10 + +config ETRAX_SERIAL_PORT0_NO_DMA_OUT + bool "Ser0 uses no DMA for output" + help + Do not use DMA for ser0 output. + +config ETRAX_SERIAL_PORT0_DMA6_OUT + bool "Ser0 uses DMA6 for output" + depends on ETRAXFS + help + Enables the DMA6 output channel for ser0 (ttyS0). + If you do not enable DMA, an interrupt for each character will be + used when transmitting data. + Normally you want to use DMA, unless you use the DMA channel for + something else. + +config ETRAX_SERIAL_PORT0_DMA0_OUT + bool "Ser0 uses DMA0 for output" + depends on CRIS_MACH_ARTPEC3 + help + Enables the DMA0 output channel for ser0 (ttyS0). + If you do not enable DMA, an interrupt for each character will be + used when transmitting data. + Normally you want to use DMA, unless you use the DMA channel for + something else. + +endchoice + +choice + prompt "Ser0 DMA in channel " + depends on ETRAX_SERIAL_PORT0 + default ETRAX_SERIAL_PORT0_NO_DMA_IN if ETRAX_ARCH_V32 + default ETRAX_SERIAL_PORT0_DMA7_IN if ETRAX_ARCH_V10 + help + What DMA channel to use for ser0. + +config ETRAX_SERIAL_PORT0_NO_DMA_IN + bool "Ser0 uses no DMA for input" + help + Do not use DMA for ser0 input. + +config ETRAX_SERIAL_PORT0_DMA7_IN + bool "Ser0 uses DMA7 for input" + depends on ETRAXFS + help + Enables the DMA7 input channel for ser0 (ttyS0). + If you do not enable DMA, an interrupt for each character will be + used when receiving data. + Normally you want to use DMA, unless you use the DMA channel for + something else. + +config ETRAX_SERIAL_PORT0_DMA1_IN + bool "Ser0 uses DMA1 for input" + depends on CRIS_MACH_ARTPEC3 + help + Enables the DMA1 input channel for ser0 (ttyS0). + If you do not enable DMA, an interrupt for each character will be + used when receiving data. + Normally you want to use DMA, unless you use the DMA channel for + something else. + +endchoice + +choice + prompt "Ser1 DMA in channel " + depends on ETRAX_SERIAL_PORT1 + default ETRAX_SERIAL_PORT1_NO_DMA_IN if ETRAX_ARCH_V32 + default ETRAX_SERIAL_PORT1_DMA9_IN if ETRAX_ARCH_V10 + help + What DMA channel to use for ser1. + +config ETRAX_SERIAL_PORT1_NO_DMA_IN + bool "Ser1 uses no DMA for input" + help + Do not use DMA for ser1 input. + +config ETRAX_SERIAL_PORT1_DMA5_IN + bool "Ser1 uses DMA5 for input" + depends on ETRAX_ARCH_V32 + help + Enables the DMA5 input channel for ser1 (ttyS1). + If you do not enable DMA, an interrupt for each character will be + used when receiving data. + Normally you want this on, unless you use the DMA channel for + something else. + +config ETRAX_SERIAL_PORT1_DMA9_IN + depends on ETRAX_ARCH_V10 + bool "Ser1 uses DMA9 for input" + +endchoice + + +choice + prompt "Ser1 DMA out channel" + depends on ETRAX_SERIAL_PORT1 + default ETRAX_SERIAL_PORT1_NO_DMA_OUT if ETRAX_ARCH_V32 + default ETRAX_SERIAL_PORT1_DMA8_OUT if ETRAX_ARCH_V10 + help + What DMA channel to use for ser1. + +config ETRAX_SERIAL_PORT1_NO_DMA_OUT + bool "Ser1 uses no DMA for output" + help + Do not use DMA for ser1 output. + +config ETRAX_SERIAL_PORT1_DMA8_OUT + depends on ETRAX_ARCH_V10 + bool "Ser1 uses DMA8 for output" + +config ETRAX_SERIAL_PORT1_DMA4_OUT + depends on ETRAX_ARCH_V32 + bool "Ser1 uses DMA4 for output" + help + Enables the DMA4 output channel for ser1 (ttyS1). + If you do not enable DMA, an interrupt for each character will be + used when transmitting data. + Normally you want this on, unless you use the DMA channel for + something else. + +endchoice + +choice + prompt "Ser2 DMA out channel" + depends on ETRAX_SERIAL_PORT2 + default ETRAX_SERIAL_PORT2_NO_DMA_OUT if ETRAX_ARCH_V32 + default ETRAX_SERIAL_PORT2_DMA2_OUT if ETRAX_ARCH_V10 + +config ETRAX_SERIAL_PORT2_NO_DMA_OUT + bool "Ser2 uses no DMA for output" + help + Do not use DMA for ser2 output. + +config ETRAX_SERIAL_PORT2_DMA2_OUT + bool "Ser2 uses DMA2 for output" + depends on ETRAXFS || ETRAX_ARCH_V10 + help + Enables the DMA2 output channel for ser2 (ttyS2). + If you do not enable DMA, an interrupt for each character will be + used when transmitting data. + Normally you want to use DMA, unless you use the DMA channel for + something else. + +config ETRAX_SERIAL_PORT2_DMA6_OUT + bool "Ser2 uses DMA6 for output" + depends on CRIS_MACH_ARTPEC3 + help + Enables the DMA6 output channel for ser2 (ttyS2). + If you do not enable DMA, an interrupt for each character will be + used when transmitting data. + Normally you want to use DMA, unless you use the DMA channel for + something else. + +endchoice + +choice + prompt "Ser2 DMA in channel" + depends on ETRAX_SERIAL_PORT2 + default ETRAX_SERIAL_PORT2_NO_DMA_IN if ETRAX_ARCH_V32 + default ETRAX_SERIAL_PORT2_DMA3_IN if ETRAX_ARCH_V10 + help + What DMA channel to use for ser2. + +config ETRAX_SERIAL_PORT2_NO_DMA_IN + bool "Ser2 uses no DMA for input" + help + Do not use DMA for ser2 input. + +config ETRAX_SERIAL_PORT2_DMA3_IN + bool "Ser2 uses DMA3 for input" + depends on ETRAXFS || ETRAX_ARCH_V10 + help + Enables the DMA3 input channel for ser2 (ttyS2). + If you do not enable DMA, an interrupt for each character will be + used when receiving data. + Normally you want to use DMA, unless you use the DMA channel for + something else. + +config ETRAX_SERIAL_PORT2_DMA7_IN + bool "Ser2 uses DMA7 for input" + depends on CRIS_MACH_ARTPEC3 + help + Enables the DMA7 input channel for ser2 (ttyS2). + If you do not enable DMA, an interrupt for each character will be + used when receiving data. + Normally you want to use DMA, unless you use the DMA channel for + something else. + +endchoice + +choice + prompt "Ser3 DMA in channel" + depends on ETRAX_SERIAL_PORT3 + default ETRAX_SERIAL_PORT3_NO_DMA_IN if ETRAX_ARCH_V32 + default ETRAX_SERIAL_PORT3_DMA5_IN if ETRAX_ARCH_V10 + help + What DMA channel to use for ser3. + +config ETRAX_SERIAL_PORT3_NO_DMA_IN + bool "Ser3 uses no DMA for input" + help + Do not use DMA for ser3 input. + +config ETRAX_SERIAL_PORT3_DMA5_IN + depends on ETRAX_ARCH_V10 + bool "DMA 5" + +endchoice + +choice + prompt "Ser3 DMA out channel" + depends on ETRAX_SERIAL_PORT3 + default ETRAX_SERIAL_PORT3_NO_DMA_OUT if ETRAX_ARCH_V32 + default ETRAX_SERIAL_PORT3_DMA4_OUT if ETRAX_ARCH_V10 + +config ETRAX_SERIAL_PORT3_NO_DMA_OUT + bool "Ser3 uses no DMA for output" + help + Do not use DMA for ser3 output. + +config ETRAX_SERIAL_PORT3_DMA4_OUT + depends on ETRAX_ARCH_V10 + bool "DMA 4" + +endchoice + +endmenu + +source "drivers/Kconfig" + +source "fs/Kconfig" + +source "arch/cris/Kconfig.debug" + +source "security/Kconfig" + +source "crypto/Kconfig" + +source "lib/Kconfig" diff --git a/kernel/arch/cris/Kconfig.debug b/kernel/arch/cris/Kconfig.debug new file mode 100644 index 000000000..14881e81e --- /dev/null +++ b/kernel/arch/cris/Kconfig.debug @@ -0,0 +1,40 @@ +menu "Kernel hacking" + +config PROFILING + bool "Kernel profiling support" + +config SYSTEM_PROFILER + bool "System profiling support" + +source "lib/Kconfig.debug" + +config ETRAX_KGDB + bool "Use kernel GDB debugger" + depends on DEBUG_KERNEL + ---help--- + The CRIS version of gdb can be used to remotely debug a running + Linux kernel via the serial debug port. Provided you have gdb-cris + installed, run gdb-cris vmlinux, then type + + (gdb) set remotebaud 115200 <- kgdb uses 115200 as default + (gdb) target remote /dev/ttyS0 <- maybe you use another port + + This should connect you to your booted kernel (or boot it now if you + didn't before). The kernel halts when it boots, waiting for gdb if + this option is turned on! + + +config DEBUG_NMI_OOPS + bool "NMI causes oops printout" + depends on DEBUG_KERNEL + help + If the system locks up without any debug information you can say Y + here to make it possible to dump an OOPS with an external NMI. + +config NO_SEGFAULT_TERMINATION + bool "Keep segfaulting processes" + help + Place segfaulting user mode processes on a wait queue instead of + delivering a terminating SIGSEGV to allow debugging with gdb. + +endmenu diff --git a/kernel/arch/cris/Makefile b/kernel/arch/cris/Makefile new file mode 100644 index 000000000..4a5404b3d --- /dev/null +++ b/kernel/arch/cris/Makefile @@ -0,0 +1,104 @@ +# +# cris/Makefile +# +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. Remember to do have actions +# for "archclean" and "archdep" for cleaning up and making dependencies for +# this architecture +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. + +KBUILD_DEFCONFIG := etrax-100lx_v2_defconfig + +arch-y := v10 +arch-$(CONFIG_ETRAX_ARCH_V10) := v10 +arch-$(CONFIG_ETRAX_ARCH_V32) := v32 + +# No config available for make clean etc +mach-y := fs +mach-$(CONFIG_CRIS_MACH_ARTPEC3) := a3 +mach-$(CONFIG_ETRAXFS) := fs + +ifneq ($(arch-y),) +SARCH := arch-$(arch-y) +inc := -Iarch/cris/include/uapi/$(SARCH) +inc += -Iarch/cris/include/$(SARCH) +inc += -Iarch/cris/include/uapi/$(SARCH)/arch +inc += -Iarch/cris/include/$(SARCH)/arch +else +SARCH := +inc := +endif + +ifneq ($(mach-y),) +MACH := mach-$(mach-y) +inc += -Iarch/cris/include/$(SARCH)/$(MACH)/ +inc += -Iarch/cris/include/$(SARCH)/$(MACH)/mach +else +MACH := +endif + +ifneq ($(CONFIG_BUILTIN_DTB),"") +core-$(CONFIG_OF) += arch/cris/boot/dts/ +endif + +LD = $(CROSS_COMPILE)ld -mcrislinux + +OBJCOPYFLAGS := -O binary -R .note -R .comment -S + +KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc) +KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc) +KBUILD_CPPFLAGS += $(inc) + +ifdef CONFIG_FRAME_POINTER +KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g +KBUILD_CFLAGS += -fno-omit-frame-pointer +endif + +head-y := arch/cris/$(SARCH)/kernel/head.o + +LIBGCC = $(shell $(CC) $(KBUILD_CFLAGS) -print-file-name=libgcc.a) + +core-y += arch/cris/kernel/ arch/cris/mm/ +core-y += arch/cris/$(SARCH)/kernel/ arch/cris/$(SARCH)/mm/ +ifdef CONFIG_ETRAX_ARCH_V32 +core-y += arch/cris/$(SARCH)/$(MACH)/ +endif +drivers-y += arch/cris/$(SARCH)/drivers/ +libs-y += arch/cris/$(SARCH)/lib/ $(LIBGCC) + +# cris source path +SRC_ARCH = $(srctree)/arch/cris +# cris object files path +OBJ_ARCH = $(objtree)/arch/cris + +boot := arch/cris/boot +MACHINE := arch/cris/$(SARCH) + +all: zImage + +zImage Image: vmlinux + $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ + +archprepare: + +archclean: + $(Q)if [ -e arch/cris/boot ]; then \ + $(MAKE) $(clean)=arch/cris/boot; \ + fi + +CLEAN_FILES += \ + $(boot)/zImage \ + $(boot)/compressed/decompress.bin \ + $(boot)/compressed/piggy.gz \ + $(boot)/rescue/rescue.bin + + +# MRPROPER_FILES += + +define archhelp + echo '* zImage - Compressed kernel image (arch/cris/boot/zImage)' + echo '* Image - Uncompressed kernel image (arch/cris/boot/Image)' +endef diff --git a/kernel/arch/cris/arch-v10/Kconfig b/kernel/arch/cris/arch-v10/Kconfig new file mode 100644 index 000000000..df9a38b4f --- /dev/null +++ b/kernel/arch/cris/arch-v10/Kconfig @@ -0,0 +1,398 @@ +if ETRAX_ARCH_V10 + +menu "CRIS v10 options" + +# ETRAX 100LX v1 has a MMU "feature" requiring a low mapping +config CRIS_LOW_MAP + bool + depends on ETRAX_ARCH_V10 && ETRAX100LX + default y + +config ETRAX_DRAM_VIRTUAL_BASE + hex + depends on ETRAX_ARCH_V10 + default "c0000000" if !ETRAX100LX + default "60000000" if ETRAX100LX + +choice + prompt "Product LED port" + depends on ETRAX_ARCH_V10 + default ETRAX_PA_LEDS + +config ETRAX_PA_LEDS + bool "Port-PA-LEDs" + help + The ETRAX network driver is responsible for flashing LED's when + packets arrive and are sent. It uses macros defined in + , and those macros are defined after + what YOU choose in this option. The actual bits used are configured + separately. Select this if the LEDs are on port PA. Some products + put the leds on PB or a memory-mapped latch (CSP0) instead. + +config ETRAX_PB_LEDS + bool "Port-PB-LEDs" + help + The ETRAX network driver is responsible for flashing LED's when + packets arrive and are sent. It uses macros defined in + , and those macros are defined after + what YOU choose in this option. The actual bits used are configured + separately. Select this if the LEDs are on port PB. Some products + put the leds on PA or a memory-mapped latch (CSP0) instead. + +config ETRAX_CSP0_LEDS + bool "Port-CSP0-LEDs" + help + The ETRAX network driver is responsible for flashing LED's when + packets arrive and are sent. It uses macros defined in + , and those macros are defined after + what YOU choose in this option. The actual bits used are configured + separately. Select this if the LEDs are on a memory-mapped latch + using chip select CSP0, this is mapped at 0x90000000. + Some products put the leds on PA or PB instead. + +config ETRAX_NO_LEDS + bool "None" + help + Select this option if you don't have any LED at all. + +endchoice + +config ETRAX_LED1G + int "First green LED bit" + depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS + default "2" + help + Bit to use for the first green LED. + Most Axis products use bit 2 here. + +config ETRAX_LED1R + int "First red LED bit" + depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS + default "3" + help + Bit to use for the first red LED. + Most Axis products use bit 3 here. + For products with only one controllable LED, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED2G + int "Second green LED bit" + depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS + default "4" + help + Bit to use for the second green LED. The "Active" LED. + Most Axis products use bit 4 here. + For products with only one controllable LED, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED2R + int "Second red LED bit" + depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS + default "5" + help + Bit to use for the second red LED. + Most Axis products use bit 5 here. + For products with only one controllable LED, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED3G + int "Third green LED bit" + depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS + default "2" + help + Bit to use for the third green LED. The "Drive" LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED3R + int "Third red LED bit" + depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS + default "2" + help + Bit to use for the third red LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED4R + int "Fourth red LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the fourth red LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED4G + int "Fourth green LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the fourth green LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED5R + int "Fifth red LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the fifth red LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED5G + int "Fifth green LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the fifth green LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED6R + int "Sixth red LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the sixth red LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED6G + int "Sixth green LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the sixth green LED. The "Drive" LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED7R + int "Seventh red LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the seventh red LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED7G + int "Seventh green LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the seventh green LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED8Y + int "Eighth yellow LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the eighth yellow LED. The "Drive" LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED9Y + int "Ninth yellow LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the ninth yellow LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED10Y + int "Tenth yellow LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the tenth yellow LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED11Y + int "Eleventh yellow LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the eleventh yellow LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + +config ETRAX_LED12R + int "Twelfth red LED bit" + depends on ETRAX_CSP0_LEDS + default "2" + help + Bit to use for the twelfth red LED. + For products with only one or two controllable LEDs, + set this to same as CONFIG_ETRAX_LED1G (normally 2). + + +choice + prompt "Product rescue-port" + depends on ETRAX_ARCH_V10 + default ETRAX_RESCUE_SER0 + +config ETRAX_RESCUE_SER0 + bool "Serial-0" + help + Select one of the four serial ports as a rescue port. The default + is port 0. + +config ETRAX_RESCUE_SER1 + bool "Serial-1" + help + Use serial port 1 as the rescue port. + +config ETRAX_RESCUE_SER2 + bool "Serial-2" + help + Use serial port 2 as the rescue port. + +config ETRAX_RESCUE_SER3 + bool "Serial-3" + help + Use serial port 3 as the rescue port. + +endchoice + +config ETRAX_DEF_R_WAITSTATES + hex "R_WAITSTATES" + depends on ETRAX_ARCH_V10 + default "95a6" + help + Waitstates for SRAM, Flash and peripherals (not DRAM). 95f8 is a + good choice for most Axis products... + +config ETRAX_DEF_R_BUS_CONFIG + hex "R_BUS_CONFIG" + depends on ETRAX_ARCH_V10 + default "104" + help + Assorted bits controlling write mode, DMA burst length etc. 104 is + a good choice for most Axis products... + +config ETRAX_SDRAM + bool "SDRAM support" + depends on ETRAX_ARCH_V10 + help + Enable this if you use SDRAM chips and configure + R_SDRAM_CONFIG and R_SDRAM_TIMING as well. + +config ETRAX_DEF_R_DRAM_CONFIG + hex "R_DRAM_CONFIG" + depends on ETRAX_ARCH_V10 && !ETRAX_SDRAM + default "1a200040" + help + The R_DRAM_CONFIG register specifies everything on how the DRAM + chips in the system are connected to the ETRAX CPU. This is + different depending on the manufacturer, chip type and number of + chips. So this value often needs to be different for each Axis + product. + +config ETRAX_DEF_R_DRAM_TIMING + hex "R_DRAM_TIMING" + depends on ETRAX_ARCH_V10 && !ETRAX_SDRAM + default "5611" + help + Different DRAM chips have different speeds. Current Axis products + use 50ns DRAM chips which can use the timing: 5611. + +config ETRAX_DEF_R_SDRAM_CONFIG + hex "R_SDRAM_CONFIG" + depends on ETRAX_ARCH_V10 && ETRAX_SDRAM + default "d2fa7878" + help + The R_SDRAM_CONFIG register specifies everything on how the SDRAM + chips in the system are connected to the ETRAX CPU. This is + different depending on the manufacturer, chip type and number of + chips. So this value often needs to be different for each Axis + product. + +config ETRAX_DEF_R_SDRAM_TIMING + hex "R_SDRAM_TIMING" + depends on ETRAX_ARCH_V10 && ETRAX_SDRAM + default "80004801" + help + Different SDRAM chips have different timing. + +config ETRAX_DEF_R_PORT_PA_DIR + hex "R_PORT_PA_DIR" + depends on ETRAX_ARCH_V10 + default "1c" + help + Configures the direction of general port A bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_R_PORT_PA_DATA + hex "R_PORT_PA_DATA" + depends on ETRAX_ARCH_V10 + default "00" + help + Configures the initial data for the general port A bits. Most + products should use 00 here. + +config ETRAX_DEF_R_PORT_PB_CONFIG + hex "R_PORT_PB_CONFIG" + depends on ETRAX_ARCH_V10 + default "00" + help + Configures the type of the general port B bits. 1 is chip select, + 0 is port. Most products should use 00 here. + +config ETRAX_DEF_R_PORT_PB_DIR + hex "R_PORT_PB_DIR" + depends on ETRAX_ARCH_V10 + default "00" + help + Configures the direction of general port B bits. 1 is out, 0 is in. + This is often totally different depending on the product used. Bits + 0 and 1 on port PB are usually used for I2C communication, but the + kernel I2C driver sets the appropriate directions itself so you + don't need to take that into consideration when setting this option. + If you don't know what to use, it is always safe to put all as + inputs. + +config ETRAX_DEF_R_PORT_PB_DATA + hex "R_PORT_PB_DATA" + depends on ETRAX_ARCH_V10 + default "ff" + help + Configures the initial data for the general port A bits. Most + products should use FF here. + +config ETRAX_SOFT_SHUTDOWN + bool "Software Shutdown Support" + depends on ETRAX_ARCH_V10 + help + Enable this if ETRAX is used with a power-supply that can be turned + off and on with PS_ON signal. Gives the possibility to detect + powerbutton and then do a power off after unmounting disks. + +config ETRAX_SHUTDOWN_BIT + int "Shutdown bit on port CSP0" + depends on ETRAX_SOFT_SHUTDOWN + default "12" + help + Configure what pin on CSPO-port that is used for controlling power + supply. + +config ETRAX_POWERBUTTON_BIT + int "Power button bit on port G" + depends on ETRAX_SOFT_SHUTDOWN + default "25" + help + Configure where power button is connected. + +endmenu + +endif diff --git a/kernel/arch/cris/arch-v10/README.mm b/kernel/arch/cris/arch-v10/README.mm new file mode 100644 index 000000000..67731d75c --- /dev/null +++ b/kernel/arch/cris/arch-v10/README.mm @@ -0,0 +1,244 @@ +Memory management for CRIS/MMU +------------------------------ +HISTORY: + +$Log: README.mm,v $ +Revision 1.1 2001/12/17 13:59:27 bjornw +Initial revision + +Revision 1.1 2000/07/10 16:25:21 bjornw +Initial revision + +Revision 1.4 2000/01/17 02:31:59 bjornw +Added discussion of paging and VM. + +Revision 1.3 1999/12/03 16:43:23 hp +Blurb about that the 3.5G-limitation is not a MMU limitation + +Revision 1.2 1999/12/03 16:04:21 hp +Picky comment about not mapping the first page + +Revision 1.1 1999/12/03 15:41:30 bjornw +First version of CRIS/MMU memory layout specification. + + + + + +------------------------------ + +See the ETRAX-NG HSDD for reference. + +We use the page-size of 8 kbytes, as opposed to the i386 page-size of 4 kbytes. + +The MMU can, apart from the normal mapping of pages, also do a top-level +segmentation of the kernel memory space. We use this feature to avoid having +to use page-tables to map the physical memory into the kernel's address +space. We also use it to keep the user-mode virtual mapping in the same +map during kernel-mode, so that the kernel easily can access the corresponding +user-mode process' data. + +As a comparison, the Linux/i386 2.0 puts the kernel and physical RAM at +address 0, overlapping with the user-mode virtual space, so that descriptor +registers are needed for each memory access to specify which MMU space to +map through. That changed in 2.2, putting the kernel/physical RAM at +0xc0000000, to co-exist with the user-mode mapping. We will do something +quite similar, but with the additional complexity of having to map the +internal chip I/O registers and the flash memory area (including SRAM +and peripherial chip-selets). + +The kernel-mode segmentation map: + + ------------------------ ------------------------ +FFFFFFFF| | => cached | | + | kernel seg_f | flash | | +F0000000|______________________| | | +EFFFFFFF| | => uncached | | + | kernel seg_e | flash | | +E0000000|______________________| | DRAM | +DFFFFFFF| | paged to any | Un-cached | + | kernel seg_d | =======> | | +D0000000|______________________| | | +CFFFFFFF| | | | + | kernel seg_c |==\ | | +C0000000|______________________| \ |______________________| +BFFFFFFF| | uncached | | + | kernel seg_b |=====\=========>| Registers | +B0000000|______________________| \c |______________________| +AFFFFFFF| | \a | | + | | \c | FLASH/SRAM/Peripheral| + | | \h |______________________| + | | \e | | + | | \d | | + | kernel seg_0 - seg_a | \==>| DRAM | + | | | Cached | + | | paged to any | | + | | =======> |______________________| + | | | | + | | | Illegal | + | | |______________________| + | | | | + | | | FLASH/SRAM/Peripheral| +00000000|______________________| |______________________| + +In user-mode it looks the same except that only the space 0-AFFFFFFF is +available. Therefore, in this model, the virtual address space per process +is limited to 0xb0000000 bytes (minus 8192 bytes, since the first page, +0..8191, is never mapped, in order to trap NULL references). + +It also means that the total physical RAM that can be mapped is 256 MB +(kseg_c above). More RAM can be mapped by choosing a different segmentation +and shrinking the user-mode memory space. + +The MMU can map all 4 GB in user mode, but doing that would mean that a +few extra instructions would be needed for each access to user mode +memory. + +The kernel needs access to both cached and uncached flash. Uncached is +necessary because of the special write/erase sequences. Also, the +peripherial chip-selects are decoded from that region. + +The kernel also needs its own virtual memory space. That is kseg_d. It +is used by the vmalloc() kernel function to allocate virtual contiguous +chunks of memory not possible using the normal kmalloc physical RAM +allocator. + +The setting of the actual MMU control registers to use this layout would +be something like this: + +R_MMU_KSEG = ( ( seg_f, seg ) | // Flash cached + ( seg_e, seg ) | // Flash uncached + ( seg_d, page ) | // kernel vmalloc area + ( seg_c, seg ) | // kernel linear segment + ( seg_b, seg ) | // kernel linear segment + ( seg_a, page ) | + ( seg_9, page ) | + ( seg_8, page ) | + ( seg_7, page ) | + ( seg_6, page ) | + ( seg_5, page ) | + ( seg_4, page ) | + ( seg_3, page ) | + ( seg_2, page ) | + ( seg_1, page ) | + ( seg_0, page ) ); + +R_MMU_KBASE_HI = ( ( base_f, 0x0 ) | // flash/sram/periph cached + ( base_e, 0x8 ) | // flash/sram/periph uncached + ( base_d, 0x0 ) | // don't care + ( base_c, 0x4 ) | // physical RAM cached area + ( base_b, 0xb ) | // uncached on-chip registers + ( base_a, 0x0 ) | // don't care + ( base_9, 0x0 ) | // don't care + ( base_8, 0x0 ) ); // don't care + +R_MMU_KBASE_LO = ( ( base_7, 0x0 ) | // don't care + ( base_6, 0x0 ) | // don't care + ( base_5, 0x0 ) | // don't care + ( base_4, 0x0 ) | // don't care + ( base_3, 0x0 ) | // don't care + ( base_2, 0x0 ) | // don't care + ( base_1, 0x0 ) | // don't care + ( base_0, 0x0 ) ); // don't care + +NOTE: while setting up the MMU, we run in a non-mapped mode in the DRAM (0x40 +segment) and need to setup the seg_4 to a unity mapping, so that we don't get +a fault before we have had time to jump into the real kernel segment (0xc0). This +is done in head.S temporarily, but fixed by the kernel later in paging_init. + + +Paging - PTE's, PMD's and PGD's +------------------------------- + +[ References: asm/pgtable.h, asm/page.h, asm/mmu.h ] + +The paging mechanism uses virtual addresses to split a process memory-space into +pages, a page being the smallest unit that can be freely remapped in memory. On +Linux/CRIS, a page is 8192 bytes (for technical reasons not equal to 4096 as in +most other 32-bit architectures). It would be inefficient to let a virtual memory +mapping be controlled by a long table of page mappings, so it is broken down into +a 2-level structure with a Page Directory containing pointers to Page Tables which +each have maps of up to 2048 pages (8192 / sizeof(void *)). Linux can actually +handle 3-level structures as well, with a Page Middle Directory in between, but +in many cases, this is folded into a two-level structure by excluding the Middle +Directory. + +We'll take a look at how an address is translated while we discuss how it's handled +in the Linux kernel. + +The example address is 0xd004000c; in binary this is: + +31 23 15 7 0 +11010000 00000100 00000000 00001100 + +|______| |__________||____________| + PGD PTE page offset + +Given the top-level Page Directory, the offset in that directory is calculated +using the upper 8 bits: + +static inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) +{ + return mm->pgd + (address >> PGDIR_SHIFT); +} + +PGDIR_SHIFT is the log2 of the amount of memory an entry in the PGD can map; in our +case it is 24, corresponding to 16 MB. This means that each entry in the PGD +corresponds to 16 MB of virtual memory. + +The pgd_t from our example will therefore be the 208'th (0xd0) entry in mm->pgd. + +Since the Middle Directory does not exist, it is a unity mapping: + +static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) +{ + return (pmd_t *) dir; +} + +The Page Table provides the final lookup by using bits 13 to 23 as index: + +static inline pte_t * pte_offset(pmd_t * dir, unsigned long address) +{ + return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & + (PTRS_PER_PTE - 1)); +} + +PAGE_SHIFT is the log2 of the size of a page; 13 in our case. PTRS_PER_PTE is +the number of pointers that fit in a Page Table and is used to mask off the +PGD-part of the address. + +The so-far unused bits 0 to 12 are used to index inside a page linearily. + +The VM system +------------- + +The kernels own page-directory is the swapper_pg_dir, cleared in paging_init, +and contains the kernels virtual mappings (the kernel itself is not paged - it +is mapped linearily using kseg_c as described above). Architectures without +kernel segments like the i386, need to setup swapper_pg_dir directly in head.S +to map the kernel itself. swapper_pg_dir is pointed to by init_mm.pgd as the +init-task's PGD. + +To see what support functions are used to setup a page-table, let's look at the +kernel's internal paged memory system, vmalloc/vfree. + +void * vmalloc(unsigned long size) + +The vmalloc-system keeps a paged segment in kernel-space at 0xd0000000. What +happens first is that a virtual address chunk is allocated to the request using +get_vm_area(size). After that, physical RAM pages are allocated and put into +the kernel's page-table using alloc_area_pages(addr, size). + +static int alloc_area_pages(unsigned long address, unsigned long size) + +First the PGD entry is found using init_mm.pgd. This is passed to +alloc_area_pmd (remember the 3->2 folding). It uses pte_alloc_kernel to +check if the PGD entry points anywhere - if not, a page table page is +allocated and the PGD entry updated. Then the alloc_area_pte function is +used just like alloc_area_pmd to check which page table entry is desired, +and a physical page is allocated and the table entry updated. All of this +is repeated at the top-level until the entire address range specified has +been mapped. + + + diff --git a/kernel/arch/cris/arch-v10/drivers/Kconfig b/kernel/arch/cris/arch-v10/drivers/Kconfig new file mode 100644 index 000000000..239dab0b9 --- /dev/null +++ b/kernel/arch/cris/arch-v10/drivers/Kconfig @@ -0,0 +1,560 @@ +if ETRAX_ARCH_V10 + +config ETRAX_ETHERNET + bool "Ethernet support" + depends on ETRAX_ARCH_V10 && NETDEVICES + select MII + help + This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet + controller. + +config ETRAX_SERIAL + bool "Serial-port support" + depends on ETRAX_ARCH_V10 + help + Enables the ETRAX 100 serial driver for ser0 (ttyS0) + You probably want this enabled. + +config ETRAX_SERIAL_FAST_TIMER + bool "Use fast timers for serial DMA flush (experimental)" + depends on ETRAX_SERIAL + help + Select this to have the serial DMAs flushed at a higher rate than + normally, possible by using the fast timer API, the timeout is + approx. 4 character times. + If unsure, say N. + +config ETRAX_SERIAL_FLUSH_DMA_FAST + bool "Fast serial port DMA flush" + depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER + help + Select this to have the serial DMAs flushed at a higher rate than + normally possible through a fast timer interrupt (currently at + 15360 Hz). + If unsure, say N. + +config ETRAX_SERIAL_RX_TIMEOUT_TICKS + int "Receive flush timeout (ticks) " + depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER && !ETRAX_SERIAL_FLUSH_DMA_FAST + default "5" + help + Number of timer ticks between flush of receive fifo (1 tick = 10ms). + Try 0-3 for low latency applications. Approx 5 for high load + applications (e.g. PPP). Maybe this should be more adaptive some + day... + +config ETRAX_SERIAL_PORT0 + bool "Serial port 0 enabled" + depends on ETRAX_SERIAL + help + Enables the ETRAX 100 serial driver for ser0 (ttyS0) + Normally you want this on, unless you use external DMA 1 that uses + the same DMA channels. + +choice + prompt "Ser0 DTR, RI, DSR and CD assignment" + depends on ETRAX_SERIAL_PORT0 + default ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE + +config ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE + bool "No_DTR_RI_DSR_CD" + +config ETRAX_SER0_DTR_RI_DSR_CD_ON_PA + bool "DTR_RI_DSR_CD_on_PA" + +config ETRAX_SER0_DTR_RI_DSR_CD_ON_PB + bool "DTR_RI_DSR_CD_on_PB" + help + Enables the status and control signals DTR, RI, DSR and CD on PB for + ser0. + +config ETRAX_SER0_DTR_RI_DSR_CD_MIXED + bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB" + +endchoice + +config ETRAX_SER0_DTR_ON_PA_BIT + int "Ser0 DTR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT0 + default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED + default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER0_RI_ON_PA_BIT + int "Ser0 RI on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT0 + default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED + default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER0_DSR_ON_PA_BIT + int "Ser0 DSR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT0 + default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED + default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER0_CD_ON_PA_BIT + int "Ser0 CD on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT0 + default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED + default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER0_DTR_ON_PB_BIT + int "Ser0 DTR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT0 + default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED + default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PB port to carry the DTR signal for serial + port 0. + +config ETRAX_SER0_RI_ON_PB_BIT + int "Ser0 RI on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT0 + default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED + default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PB port to carry the RI signal for serial + port 0. + +config ETRAX_SER0_DSR_ON_PB_BIT + int "Ser0 DSR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT0 + default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED + default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PB port to carry the DSR signal for serial + port 0. + +config ETRAX_SER0_CD_ON_PB_BIT + int "Ser0 CD on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT0 + default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED + default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PB port to carry the CD signal for serial + port 0. + +config ETRAX_SERIAL_PORT1 + bool "Serial port 1 enabled" + depends on ETRAX_SERIAL + help + Enables the ETRAX 100 serial driver for ser1 (ttyS1). + +choice + prompt "Ser1 DTR, RI, DSR and CD assignment" + depends on ETRAX_SERIAL_PORT1 + default ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE + +config ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE + bool "No_DTR_RI_DSR_CD" + +config ETRAX_SER1_DTR_RI_DSR_CD_ON_PA + bool "DTR_RI_DSR_CD_on_PA" + +config ETRAX_SER1_DTR_RI_DSR_CD_ON_PB + bool "DTR_RI_DSR_CD_on_PB" + help + Enables the status and control signals DTR, RI, DSR and CD on PB for + ser1. + +config ETRAX_SER1_DTR_RI_DSR_CD_MIXED + bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB" + +endchoice + +config ETRAX_SER1_DTR_ON_PA_BIT + int "Ser1 DTR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT1 + default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED + default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER1_RI_ON_PA_BIT + int "Ser1 RI on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT1 + default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED + default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER1_DSR_ON_PA_BIT + int "Ser1 DSR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT1 + default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED + default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER1_CD_ON_PA_BIT + int "Ser1 CD on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT1 + default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED + default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER1_DTR_ON_PB_BIT + int "Ser1 DTR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT1 + default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED + default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PB port to carry the DTR signal for serial + port 1. + +config ETRAX_SER1_RI_ON_PB_BIT + int "Ser1 RI on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT1 + default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED + default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PB port to carry the RI signal for serial + port 1. + +config ETRAX_SER1_DSR_ON_PB_BIT + int "Ser1 DSR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT1 + default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED + default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PB port to carry the DSR signal for serial + port 1. + +config ETRAX_SER1_CD_ON_PB_BIT + int "Ser1 CD on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT1 + default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED + default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PB port to carry the CD signal for serial + port 1. + +comment "Make sure you do not have the same PB bits more than once!" + depends on ETRAX_SERIAL && ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && ETRAX_SER1_DTR_RI_DSR_CD_ON_PB + +config ETRAX_SERIAL_PORT2 + bool "Serial port 2 enabled" + depends on ETRAX_SERIAL + help + Enables the ETRAX 100 serial driver for ser2 (ttyS2). + +choice + prompt "Ser2 DTR, RI, DSR and CD assignment" + depends on ETRAX_SERIAL_PORT2 + default ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE + +config ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE + bool "No_DTR_RI_DSR_CD" + +config ETRAX_SER2_DTR_RI_DSR_CD_ON_PA + bool "DTR_RI_DSR_CD_on_PA" + help + Enables the status and control signals DTR, RI, DSR and CD on PA for + ser2. + +config ETRAX_SER2_DTR_RI_DSR_CD_ON_PB + bool "DTR_RI_DSR_CD_on_PB" + +config ETRAX_SER2_DTR_RI_DSR_CD_MIXED + bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB" + +endchoice + +config ETRAX_SER2_DTR_ON_PA_BIT + int "Ser2 DTR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT2 + default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED + default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PA port to carry the DTR signal for serial + port 2. + +config ETRAX_SER2_RI_ON_PA_BIT + int "Ser2 RI on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT2 + default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED + default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PA port to carry the RI signal for serial + port 2. + +config ETRAX_SER2_DSR_ON_PA_BIT + int "Ser2 DSR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT2 + default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED + default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PA port to carry the DTR signal for serial + port 2. + +config ETRAX_SER2_CD_ON_PA_BIT + int "Ser2 CD on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT2 + default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED + default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + help + Specify the pin of the PA port to carry the CD signal for serial + port 2. + +config ETRAX_SER2_DTR_ON_PB_BIT + int "Ser2 DTR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT2 + default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED + default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER2_RI_ON_PB_BIT + int "Ser2 RI on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT2 + default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED + default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER2_DSR_ON_PB_BIT + int "Ser2 DSR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT2 + default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED + default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + +config ETRAX_SER2_CD_ON_PB_BIT + int "Ser2 CD on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT2 + default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED + default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED + +config ETRAX_SERIAL_PORT3 + bool "Serial port 3 enabled" + depends on ETRAX_SERIAL + help + Enables the ETRAX 100 serial driver for ser3 (ttyS3). + +choice + prompt "Ser3 DTR, RI, DSR and CD assignment" + depends on ETRAX_SERIAL_PORT3 + default ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE + +config ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE + bool "No_DTR_RI_DSR_CD" + +config ETRAX_SER3_DTR_RI_DSR_CD_ON_PA + bool "DTR_RI_DSR_CD_on_PA" + +config ETRAX_SER3_DTR_RI_DSR_CD_ON_PB + bool "DTR_RI_DSR_CD_on_PB" + +config ETRAX_SER3_DTR_RI_DSR_CD_MIXED + bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB" + +endchoice + +config ETRAX_SER3_DTR_ON_PA_BIT + int "Ser3 DTR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT3 + default "-1" + +config ETRAX_SER3_RI_ON_PA_BIT + int "Ser3 RI on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT3 + default "-1" + +config ETRAX_SER3_DSR_ON_PA_BIT + int "Ser3 DSR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT3 + default "-1" + +config ETRAX_SER3_CD_ON_PA_BIT + int "Ser3 CD on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT3 + default "-1" + +config ETRAX_SER3_DTR_ON_PB_BIT + int "Ser3 DTR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT3 + default "-1" + +config ETRAX_SER3_RI_ON_PB_BIT + int "Ser3 RI on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT3 + default "-1" + +config ETRAX_SER3_DSR_ON_PB_BIT + int "Ser3 DSR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT3 + default "-1" + +config ETRAX_SER3_CD_ON_PB_BIT + int "Ser3 CD on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED + depends on ETRAX_SERIAL_PORT3 + default "-1" + +config ETRAX_RS485 + bool "RS-485 support" + depends on ETRAX_SERIAL + help + Enables support for RS-485 serial communication. For a primer on + RS-485, see + +config ETRAX_RS485_ON_PA + bool "RS-485 mode on PA" + depends on ETRAX_RS485 + help + Control Driver Output Enable on RS485 transceiver using a pin on PA + port: + Axis 2400/2401 uses PA 3. + +config ETRAX_RS485_ON_PA_BIT + int "RS-485 mode on PA bit" + depends on ETRAX_RS485_ON_PA + default "3" + help + Control Driver Output Enable on RS485 transceiver using a this bit + on PA port. + +config ETRAX_RS485_DISABLE_RECEIVER + bool "Disable serial receiver" + depends on ETRAX_RS485 + help + It's necessary to disable the serial receiver to avoid serial + loopback. Not all products are able to do this in software only. + Axis 2400/2401 must disable receiver. + +config ETRAX_USB_HOST + bool "USB host" + select USB + help + This option enables the host functionality of the ETRAX 100LX + built-in USB controller. In host mode the controller is designed + for CTRL and BULK traffic only, INTR traffic may work as well + however (depending on the requirements of timeliness). + +config ETRAX_PTABLE_SECTOR + int "Byte-offset of partition table sector" + depends on ETRAX_AXISFLASHMAP + default "65536" + help + Byte-offset of the partition table in the first flash chip. + The default value is 64kB and should not be changed unless + you know exactly what you are doing. The only valid reason + for changing this is when the flash block size is bigger + than 64kB (e.g. when using two parallel 16 bit flashes). + +config ETRAX_I2C + bool "I2C support" + depends on ETRAX_ARCH_V10 + help + Enables an I2C driver on ETRAX100. + EXAMPLE usage: + i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); + ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); + i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); + val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); + +# this is true for most products since PB-I2C seems to be somewhat +# flawed.. +config ETRAX_I2C_USES_PB_NOT_PB_I2C + bool "I2C uses PB not PB-I2C" + depends on ETRAX_I2C + help + Select whether to use the special I2C mode in the PB I/O register or + not. This option needs to be selected in order to use some drivers + that access the I2C I/O pins directly instead of going through the + I2C driver, like the DS1302 realtime-clock driver. If you are + uncertain, choose Y here. + +config ETRAX_I2C_DATA_PORT + int "I2C SDA bit number" + depends on ETRAX_I2C_USES_PB_NOT_PB_I2C + default "0" + help + Selects the pin on Port B where the data pin is connected + +config ETRAX_I2C_CLK_PORT + int "I2C SCL bit number" + depends on ETRAX_I2C_USES_PB_NOT_PB_I2C + default "1" + help + Select the pin on Port B where the clock pin is connected + +config ETRAX_I2C_EEPROM + bool "I2C EEPROM (non-volatile RAM) support" + depends on ETRAX_I2C + help + Enables I2C EEPROM (non-volatile RAM) on PB0 and PB1 using the I2C + driver. Select size option: Probed, 2k, 8k, 16k. + (Probing works for 2k and 8k but not that well for 16k) + +choice + prompt "EEPROM size" + depends on ETRAX_I2C_EEPROM + default ETRAX_I2C_EEPROM_PROBE + +config ETRAX_I2C_EEPROM_PROBE + bool "Probed" + help + Specifies size or auto probe of the EEPROM size. + Options: Probed, 2k, 8k, 16k. + (Probing works for 2k and 8k but not that well for 16k) + +config ETRAX_I2C_EEPROM_2KB + bool "2kB" + help + Use a 2kB EEPROM. + +config ETRAX_I2C_EEPROM_8KB + bool "8kB" + help + Use a 8kB EEPROM. + +config ETRAX_I2C_EEPROM_16KB + bool "16kB" + help + Use a 16kB EEPROM. + +endchoice + +config ETRAX_GPIO + bool "GPIO support" + depends on ETRAX_ARCH_V10 + ---help--- + Enables the ETRAX general port device (major 120, minors 0 and 1). + You can use this driver to access the general port bits. It supports + these ioctl's: + #include + fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob + ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set); + ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear); + val = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READBITS), NULL); + Remember that you need to setup the port directions appropriately in + the General configuration. + +config ETRAX_PA_CHANGEABLE_DIR + hex "PA user changeable dir mask" + depends on ETRAX_GPIO + default "00" + help + This is a bitmask with information of what bits in PA that a user + can change direction on using ioctl's. + Bit set = changeable. + You probably want 00 here. + +config ETRAX_PA_CHANGEABLE_BITS + hex "PA user changeable bits mask" + depends on ETRAX_GPIO + default "FF" + help + This is a bitmask with information of what bits in PA that a user + can change the value on using ioctl's. + Bit set = changeable. + You probably want 00 here. + +config ETRAX_PB_CHANGEABLE_DIR + hex "PB user changeable dir mask" + depends on ETRAX_GPIO + default "00" + help + This is a bitmask with information of what bits in PB that a user + can change direction on using ioctl's. + Bit set = changeable. + You probably want 00 here. + +config ETRAX_PB_CHANGEABLE_BITS + hex "PB user changeable bits mask" + depends on ETRAX_GPIO + default "FF" + help + This is a bitmask with information of what bits in PB that a user + can change the value on using ioctl's. + Bit set = changeable. + You probably want 00 here. + +endif diff --git a/kernel/arch/cris/arch-v10/drivers/Makefile b/kernel/arch/cris/arch-v10/drivers/Makefile new file mode 100644 index 000000000..e5c13183b --- /dev/null +++ b/kernel/arch/cris/arch-v10/drivers/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for Etrax-specific drivers +# + +obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o +obj-$(CONFIG_ETRAX_I2C) += i2c.o +obj-$(CONFIG_ETRAX_I2C_EEPROM) += eeprom.o +obj-$(CONFIG_ETRAX_GPIO) += gpio.o +obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o + diff --git a/kernel/arch/cris/arch-v10/drivers/axisflashmap.c b/kernel/arch/cris/arch-v10/drivers/axisflashmap.c new file mode 100644 index 000000000..a4bbdfd37 --- /dev/null +++ b/kernel/arch/cris/arch-v10/drivers/axisflashmap.c @@ -0,0 +1,432 @@ +/* + * Physical mapping layer for MTD using the Axis partitiontable format + * + * Copyright (c) 2001, 2002 Axis Communications AB + * + * This file is under the GPL. + * + * First partition is always sector 0 regardless of if we find a partitiontable + * or not. In the start of the next sector, there can be a partitiontable that + * tells us what other partitions to define. If there isn't, we use a default + * partition split defined below. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_CRIS_LOW_MAP +#define FLASH_UNCACHED_ADDR KSEG_8 +#define FLASH_CACHED_ADDR KSEG_5 +#else +#define FLASH_UNCACHED_ADDR KSEG_E +#define FLASH_CACHED_ADDR KSEG_F +#endif + +#if CONFIG_ETRAX_FLASH_BUSWIDTH==1 +#define flash_data __u8 +#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2 +#define flash_data __u16 +#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4 +#define flash_data __u32 +#endif + +/* From head.S */ +extern unsigned long romfs_start, romfs_length, romfs_in_flash; + +/* The master mtd for the entire flash. */ +struct mtd_info* axisflash_mtd = NULL; + +/* Map driver functions. */ + +static map_word flash_read(struct map_info *map, unsigned long ofs) +{ + map_word tmp; + tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs); + return tmp; +} + +static void flash_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + memcpy(to, (void *)(map->map_priv_1 + from), len); +} + +static void flash_write(struct map_info *map, map_word d, unsigned long adr) +{ + *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0]; +} + +/* + * The map for chip select e0. + * + * We run into tricky coherence situations if we mix cached with uncached + * accesses to we only use the uncached version here. + * + * The size field is the total size where the flash chips may be mapped on the + * chip select. MTD probes should find all devices there and it does not matter + * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD + * probes will ignore them. + * + * The start address in map_priv_1 is in virtual memory so we cannot use + * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start + * address of cse0. + */ +static struct map_info map_cse0 = { + .name = "cse0", + .size = MEM_CSE0_SIZE, + .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, + .read = flash_read, + .copy_from = flash_copy_from, + .write = flash_write, + .map_priv_1 = FLASH_UNCACHED_ADDR +}; + +/* + * The map for chip select e1. + * + * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong + * address, but there isn't. + */ +static struct map_info map_cse1 = { + .name = "cse1", + .size = MEM_CSE1_SIZE, + .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, + .read = flash_read, + .copy_from = flash_copy_from, + .write = flash_write, + .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE +}; + +/* If no partition-table was found, we use this default-set. */ +#define MAX_PARTITIONS 7 +#define NUM_DEFAULT_PARTITIONS 3 + +/* + * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the + * size of one flash block and "filesystem"-partition needs 5 blocks to be able + * to use JFFS. + */ +static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { + { + .name = "boot firmware", + .size = CONFIG_ETRAX_PTABLE_SECTOR, + .offset = 0 + }, + { + .name = "kernel", + .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR), + .offset = CONFIG_ETRAX_PTABLE_SECTOR + }, + { + .name = "filesystem", + .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR, + .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR) + } +}; + +/* Initialize the ones normally used. */ +static struct mtd_partition axis_partitions[MAX_PARTITIONS] = { + { + .name = "part0", + .size = CONFIG_ETRAX_PTABLE_SECTOR, + .offset = 0 + }, + { + .name = "part1", + .size = 0, + .offset = 0 + }, + { + .name = "part2", + .size = 0, + .offset = 0 + }, + { + .name = "part3", + .size = 0, + .offset = 0 + }, + { + .name = "part4", + .size = 0, + .offset = 0 + }, + { + .name = "part5", + .size = 0, + .offset = 0 + }, + { + .name = "part6", + .size = 0, + .offset = 0 + }, +}; + +#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE +/* Main flash device */ +static struct mtd_partition main_partition = { + .name = "main", + .size = 0, + .offset = 0 +}; +#endif + +/* + * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash + * chips in that order (because the amd_flash-driver is faster). + */ +static struct mtd_info *probe_cs(struct map_info *map_cs) +{ + struct mtd_info *mtd_cs = NULL; + + printk(KERN_INFO + "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n", + map_cs->name, map_cs->size, map_cs->map_priv_1); + +#ifdef CONFIG_MTD_CFI + mtd_cs = do_map_probe("cfi_probe", map_cs); +#endif +#ifdef CONFIG_MTD_JEDECPROBE + if (!mtd_cs) + mtd_cs = do_map_probe("jedec_probe", map_cs); +#endif + + return mtd_cs; +} + +/* + * Probe each chip select individually for flash chips. If there are chips on + * both cse0 and cse1, the mtd_info structs will be concatenated to one struct + * so that MTD partitions can cross chip boundries. + * + * The only known restriction to how you can mount your chips is that each + * chip select must hold similar flash chips. But you need external hardware + * to do that anyway and you can put totally different chips on cse0 and cse1 + * so it isn't really much of a restriction. + */ +static struct mtd_info *flash_probe(void) +{ + struct mtd_info *mtd_cse0; + struct mtd_info *mtd_cse1; + struct mtd_info *mtd_cse; + + mtd_cse0 = probe_cs(&map_cse0); + mtd_cse1 = probe_cs(&map_cse1); + + if (!mtd_cse0 && !mtd_cse1) { + /* No chip found. */ + return NULL; + } + + if (mtd_cse0 && mtd_cse1) { + struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 }; + + /* Since the concatenation layer adds a small overhead we + * could try to figure out if the chips in cse0 and cse1 are + * identical and reprobe the whole cse0+cse1 window. But since + * flash chips are slow, the overhead is relatively small. + * So we use the MTD concatenation layer instead of further + * complicating the probing procedure. + */ + mtd_cse = mtd_concat_create(mtds, ARRAY_SIZE(mtds), + "cse0+cse1"); + if (!mtd_cse) { + printk(KERN_ERR "%s and %s: Concatenation failed!\n", + map_cse0.name, map_cse1.name); + + /* The best we can do now is to only use what we found + * at cse0. + */ + mtd_cse = mtd_cse0; + map_destroy(mtd_cse1); + } + } else { + mtd_cse = mtd_cse0? mtd_cse0 : mtd_cse1; + } + + return mtd_cse; +} + +/* + * Probe the flash chip(s) and, if it succeeds, read the partition-table + * and register the partitions with MTD. + */ +static int __init init_axis_flash(void) +{ + struct mtd_info *mymtd; + int err = 0; + int pidx = 0; + struct partitiontable_head *ptable_head = NULL; + struct partitiontable_entry *ptable; + int use_default_ptable = 1; /* Until proven otherwise. */ + const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n"; + + if (!(mymtd = flash_probe())) { + /* There's no reason to use this module if no flash chip can + * be identified. Make sure that's understood. + */ + printk(KERN_INFO "axisflashmap: Found no flash chip.\n"); + } else { + printk(KERN_INFO "%s: 0x%08x bytes of flash memory.\n", + mymtd->name, mymtd->size); + axisflash_mtd = mymtd; + } + + if (mymtd) { + mymtd->owner = THIS_MODULE; + ptable_head = (struct partitiontable_head *)(FLASH_CACHED_ADDR + + CONFIG_ETRAX_PTABLE_SECTOR + + PARTITION_TABLE_OFFSET); + } + pidx++; /* First partition is always set to the default. */ + + if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC) + && (ptable_head->size < + (MAX_PARTITIONS * sizeof(struct partitiontable_entry) + + PARTITIONTABLE_END_MARKER_SIZE)) + && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) + + ptable_head->size - + PARTITIONTABLE_END_MARKER_SIZE) + == PARTITIONTABLE_END_MARKER)) { + /* Looks like a start, sane length and end of a + * partition table, lets check csum etc. + */ + int ptable_ok = 0; + struct partitiontable_entry *max_addr = + (struct partitiontable_entry *) + ((unsigned long)ptable_head + sizeof(*ptable_head) + + ptable_head->size); + unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR; + unsigned char *p; + unsigned long csum = 0; + + ptable = (struct partitiontable_entry *) + ((unsigned long)ptable_head + sizeof(*ptable_head)); + + /* Lets be PARANOID, and check the checksum. */ + p = (unsigned char*) ptable; + + while (p <= (unsigned char*)max_addr) { + csum += *p++; + csum += *p++; + csum += *p++; + csum += *p++; + } + ptable_ok = (csum == ptable_head->checksum); + + /* Read the entries and use/show the info. */ + printk(KERN_INFO " Found a%s partition table at 0x%p-0x%p.\n", + (ptable_ok ? " valid" : "n invalid"), ptable_head, + max_addr); + + /* We have found a working bootblock. Now read the + * partition table. Scan the table. It ends when + * there is 0xffffffff, that is, empty flash. + */ + while (ptable_ok + && ptable->offset != 0xffffffff + && ptable < max_addr + && pidx < MAX_PARTITIONS) { + + axis_partitions[pidx].offset = offset + ptable->offset; + axis_partitions[pidx].size = ptable->size; + + printk(pmsg, pidx, axis_partitions[pidx].offset, + axis_partitions[pidx].size); + pidx++; + ptable++; + } + use_default_ptable = !ptable_ok; + } + + if (romfs_in_flash) { + /* Add an overlapping device for the root partition (romfs). */ + + axis_partitions[pidx].name = "romfs"; + axis_partitions[pidx].size = romfs_length; + axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; + axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; + + printk(KERN_INFO + " Adding readonly flash partition for romfs image:\n"); + printk(pmsg, pidx, axis_partitions[pidx].offset, + axis_partitions[pidx].size); + pidx++; + } + +#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE + if (mymtd) { + main_partition.size = mymtd->size; + err = mtd_device_register(mymtd, &main_partition, 1); + if (err) + panic("axisflashmap: Could not initialize " + "partition for whole main mtd device!\n"); + } +#endif + + if (mymtd) { + if (use_default_ptable) { + printk(KERN_INFO " Using default partition table.\n"); + err = mtd_device_register(mymtd, + axis_default_partitions, + NUM_DEFAULT_PARTITIONS); + } else { + err = mtd_device_register(mymtd, axis_partitions, + pidx); + } + + if (err) + panic("axisflashmap could not add MTD partitions!\n"); + } + + if (!romfs_in_flash) { + /* Create an RAM device for the root partition (romfs). */ + +#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0) + /* No use trying to boot this kernel from RAM. Panic! */ + printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " + "device due to kernel (mis)configuration!\n"); + panic("This kernel cannot boot from RAM!\n"); +#else + struct mtd_info *mtd_ram; + + mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL); + if (!mtd_ram) + panic("axisflashmap couldn't allocate memory for " + "mtd_info!\n"); + + printk(KERN_INFO " Adding RAM partition for romfs image:\n"); + printk(pmsg, pidx, (unsigned)romfs_start, + (unsigned)romfs_length); + + err = mtdram_init_device(mtd_ram, + (void *)romfs_start, + romfs_length, + "romfs"); + if (err) + panic("axisflashmap could not initialize MTD RAM " + "device!\n"); +#endif + } + return err; +} + +/* This adds the above to the kernels init-call chain. */ +module_init(init_axis_flash); + +EXPORT_SYMBOL(axisflash_mtd); diff --git a/kernel/arch/cris/arch-v10/drivers/eeprom.c b/kernel/arch/cris/arch-v10/drivers/eeprom.c new file mode 100644 index 000000000..5047a3304 --- /dev/null +++ b/kernel/arch/cris/arch-v10/drivers/eeprom.c @@ -0,0 +1,852 @@ +/*!***************************************************************************** +*! +*! Implements an interface for i2c compatible eeproms to run under Linux. +*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by +*! Johan.Adolfsson@axis.com +*! +*! Probing results: +*! 8k or not is detected (the assumes 2k or 16k) +*! 2k or 16k detected using test reads and writes. +*! +*!------------------------------------------------------------------------ +*! HISTORY +*! +*! DATE NAME CHANGES +*! ---- ---- ------- +*! Aug 28 1999 Edgar Iglesias Initial Version +*! Aug 31 1999 Edgar Iglesias Allow simultaneous users. +*! Sep 03 1999 Edgar Iglesias Updated probe. +*! Sep 03 1999 Edgar Iglesias Added bail-out stuff if we get interrupted +*! in the spin-lock. +*! +*! (c) 1999 Axis Communications AB, Lund, Sweden +*!*****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "i2c.h" + +#define D(x) + +/* If we should use adaptive timing or not: */ +/* #define EEPROM_ADAPTIVE_TIMING */ + +#define EEPROM_MAJOR_NR 122 /* use a LOCAL/EXPERIMENTAL major for now */ +#define EEPROM_MINOR_NR 0 + +/* Empirical sane initial value of the delay, the value will be adapted to + * what the chip needs when using EEPROM_ADAPTIVE_TIMING. + */ +#define INITIAL_WRITEDELAY_US 4000 +#define MAX_WRITEDELAY_US 10000 /* 10 ms according to spec for 2KB EEPROM */ + +/* This one defines how many times to try when eeprom fails. */ +#define EEPROM_RETRIES 10 + +#define EEPROM_2KB (2 * 1024) +/*#define EEPROM_4KB (4 * 1024)*/ /* Exists but not used in Axis products */ +#define EEPROM_8KB (8 * 1024 - 1 ) /* Last byte has write protection bit */ +#define EEPROM_16KB (16 * 1024) + +#define i2c_delay(x) udelay(x) + +/* + * This structure describes the attached eeprom chip. + * The values are probed for. + */ + +struct eeprom_type +{ + unsigned long size; + unsigned long sequential_write_pagesize; + unsigned char select_cmd; + unsigned long usec_delay_writecycles; /* Min time between write cycles + (up to 10ms for some models) */ + unsigned long usec_delay_step; /* For adaptive algorithm */ + int adapt_state; /* 1 = To high , 0 = Even, -1 = To low */ + + /* this one is to keep the read/write operations atomic */ + struct mutex lock; + int retry_cnt_addr; /* Used to keep track of number of retries for + adaptive timing adjustments */ + int retry_cnt_read; +}; + +static int eeprom_open(struct inode * inode, struct file * file); +static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig); +static ssize_t eeprom_read(struct file * file, char * buf, size_t count, + loff_t *off); +static ssize_t eeprom_write(struct file * file, const char * buf, size_t count, + loff_t *off); +static int eeprom_close(struct inode * inode, struct file * file); + +static int eeprom_address(unsigned long addr); +static int read_from_eeprom(char * buf, int count); +static int eeprom_write_buf(loff_t addr, const char * buf, int count); +static int eeprom_read_buf(loff_t addr, char * buf, int count); + +static void eeprom_disable_write_protect(void); + + +static const char eeprom_name[] = "eeprom"; + +/* chip description */ +static struct eeprom_type eeprom; + +/* This is the exported file-operations structure for this device. */ +const struct file_operations eeprom_fops = +{ + .llseek = eeprom_lseek, + .read = eeprom_read, + .write = eeprom_write, + .open = eeprom_open, + .release = eeprom_close +}; + +/* eeprom init call. Probes for different eeprom models. */ + +int __init eeprom_init(void) +{ + mutex_init(&eeprom.lock); + +#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE +#define EETEXT "Found" +#else +#define EETEXT "Assuming" +#endif + if (register_chrdev(EEPROM_MAJOR_NR, eeprom_name, &eeprom_fops)) + { + printk(KERN_INFO "%s: unable to get major %d for eeprom device\n", + eeprom_name, EEPROM_MAJOR_NR); + return -1; + } + + printk("EEPROM char device v0.3, (c) 2000 Axis Communications AB\n"); + + /* + * Note: Most of this probing method was taken from the printserver (5470e) + * codebase. It did not contain a way of finding the 16kB chips + * (M24128 or variants). The method used here might not work + * for all models. If you encounter problems the easiest way + * is probably to define your model within #ifdef's, and hard- + * code it. + */ + + eeprom.size = 0; + eeprom.usec_delay_writecycles = INITIAL_WRITEDELAY_US; + eeprom.usec_delay_step = 128; + eeprom.adapt_state = 0; + +#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE + i2c_start(); + i2c_outbyte(0x80); + if(!i2c_getack()) + { + /* It's not 8k.. */ + int success = 0; + unsigned char buf_2k_start[16]; + + /* Im not sure this will work... :) */ + /* assume 2kB, if failure go for 16kB */ + /* Test with 16kB settings.. */ + /* If it's a 2kB EEPROM and we address it outside it's range + * it will mirror the address space: + * 1. We read two locations (that are mirrored), + * if the content differs * it's a 16kB EEPROM. + * 2. if it doesn't differ - write different value to one of the locations, + * check the other - if content still is the same it's a 2k EEPROM, + * restore original data. + */ +#define LOC1 8 +#define LOC2 (0x1fb) /*1fb, 3ed, 5df, 7d1 */ + + /* 2k settings */ + i2c_stop(); + eeprom.size = EEPROM_2KB; + eeprom.select_cmd = 0xA0; + eeprom.sequential_write_pagesize = 16; + if( eeprom_read_buf( 0, buf_2k_start, 16 ) == 16 ) + { + D(printk("2k start: '%16.16s'\n", buf_2k_start)); + } + else + { + printk(KERN_INFO "%s: Failed to read in 2k mode!\n", eeprom_name); + } + + /* 16k settings */ + eeprom.size = EEPROM_16KB; + eeprom.select_cmd = 0xA0; + eeprom.sequential_write_pagesize = 64; + + { + unsigned char loc1[4], loc2[4], tmp[4]; + if( eeprom_read_buf(LOC2, loc2, 4) == 4) + { + if( eeprom_read_buf(LOC1, loc1, 4) == 4) + { + D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", + LOC1, loc1, LOC2, loc2)); +#if 0 + if (memcmp(loc1, loc2, 4) != 0 ) + { + /* It's 16k */ + printk(KERN_INFO "%s: 16k detected in step 1\n", eeprom_name); + eeprom.size = EEPROM_16KB; + success = 1; + } + else +#endif + { + /* Do step 2 check */ + /* Invert value */ + loc1[0] = ~loc1[0]; + if (eeprom_write_buf(LOC1, loc1, 1) == 1) + { + /* If 2k EEPROM this write will actually write 10 bytes + * from pos 0 + */ + D(printk("1 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", + LOC1, loc1, LOC2, loc2)); + if( eeprom_read_buf(LOC1, tmp, 4) == 4) + { + D(printk("2 loc1: (%i) '%4.4s' tmp '%4.4s'\n", + LOC1, loc1, tmp)); + if (memcmp(loc1, tmp, 4) != 0 ) + { + printk(KERN_INFO "%s: read and write differs! Not 16kB\n", + eeprom_name); + loc1[0] = ~loc1[0]; + + if (eeprom_write_buf(LOC1, loc1, 1) == 1) + { + success = 1; + } + else + { + printk(KERN_INFO "%s: Restore 2k failed during probe," + " EEPROM might be corrupt!\n", eeprom_name); + + } + i2c_stop(); + /* Go to 2k mode and write original data */ + eeprom.size = EEPROM_2KB; + eeprom.select_cmd = 0xA0; + eeprom.sequential_write_pagesize = 16; + if( eeprom_write_buf(0, buf_2k_start, 16) == 16) + { + } + else + { + printk(KERN_INFO "%s: Failed to write back 2k start!\n", + eeprom_name); + } + + eeprom.size = EEPROM_2KB; + } + } + + if(!success) + { + if( eeprom_read_buf(LOC2, loc2, 1) == 1) + { + D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", + LOC1, loc1, LOC2, loc2)); + if (memcmp(loc1, loc2, 4) == 0 ) + { + /* Data the same, must be mirrored -> 2k */ + /* Restore data */ + printk(KERN_INFO "%s: 2k detected in step 2\n", eeprom_name); + loc1[0] = ~loc1[0]; + if (eeprom_write_buf(LOC1, loc1, 1) == 1) + { + success = 1; + } + else + { + printk(KERN_INFO "%s: Restore 2k failed during probe," + " EEPROM might be corrupt!\n", eeprom_name); + + } + + eeprom.size = EEPROM_2KB; + } + else + { + printk(KERN_INFO "%s: 16k detected in step 2\n", + eeprom_name); + loc1[0] = ~loc1[0]; + /* Data differs, assume 16k */ + /* Restore data */ + if (eeprom_write_buf(LOC1, loc1, 1) == 1) + { + success = 1; + } + else + { + printk(KERN_INFO "%s: Restore 16k failed during probe," + " EEPROM might be corrupt!\n", eeprom_name); + } + + eeprom.size = EEPROM_16KB; + } + } + } + } + } /* read LOC1 */ + } /* address LOC1 */ + if (!success) + { + printk(KERN_INFO "%s: Probing failed!, using 2KB!\n", eeprom_name); + eeprom.size = EEPROM_2KB; + } + } /* read */ + } + } + else + { + i2c_outbyte(0x00); + if(!i2c_getack()) + { + /* No 8k */ + eeprom.size = EEPROM_2KB; + } + else + { + i2c_start(); + i2c_outbyte(0x81); + if (!i2c_getack()) + { + eeprom.size = EEPROM_2KB; + } + else + { + /* It's a 8kB */ + i2c_inbyte(); + eeprom.size = EEPROM_8KB; + } + } + } + i2c_stop(); +#elif defined(CONFIG_ETRAX_I2C_EEPROM_16KB) + eeprom.size = EEPROM_16KB; +#elif defined(CONFIG_ETRAX_I2C_EEPROM_8KB) + eeprom.size = EEPROM_8KB; +#elif defined(CONFIG_ETRAX_I2C_EEPROM_2KB) + eeprom.size = EEPROM_2KB; +#endif + + switch(eeprom.size) + { + case (EEPROM_2KB): + printk("%s: " EETEXT " i2c compatible 2kB eeprom.\n", eeprom_name); + eeprom.sequential_write_pagesize = 16; + eeprom.select_cmd = 0xA0; + break; + case (EEPROM_8KB): + printk("%s: " EETEXT " i2c compatible 8kB eeprom.\n", eeprom_name); + eeprom.sequential_write_pagesize = 16; + eeprom.select_cmd = 0x80; + break; + case (EEPROM_16KB): + printk("%s: " EETEXT " i2c compatible 16kB eeprom.\n", eeprom_name); + eeprom.sequential_write_pagesize = 64; + eeprom.select_cmd = 0xA0; + break; + default: + eeprom.size = 0; + printk("%s: Did not find a supported eeprom\n", eeprom_name); + break; + } + + + + eeprom_disable_write_protect(); + + return 0; +} + +/* Opens the device. */ +static int eeprom_open(struct inode * inode, struct file * file) +{ + if(iminor(inode) != EEPROM_MINOR_NR) + return -ENXIO; + if(imajor(inode) != EEPROM_MAJOR_NR) + return -ENXIO; + + if( eeprom.size > 0 ) + { + /* OK */ + return 0; + } + + /* No EEprom found */ + return -EFAULT; +} + +/* Changes the current file position. */ + +static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig) +{ +/* + * orig 0: position from begning of eeprom + * orig 1: relative from current position + * orig 2: position from last eeprom address + */ + + switch (orig) + { + case 0: + file->f_pos = offset; + break; + case 1: + file->f_pos += offset; + break; + case 2: + file->f_pos = eeprom.size - offset; + break; + default: + return -EINVAL; + } + + /* truncate position */ + if (file->f_pos < 0) + { + file->f_pos = 0; + return(-EOVERFLOW); + } + + if (file->f_pos >= eeprom.size) + { + file->f_pos = eeprom.size - 1; + return(-EOVERFLOW); + } + + return ( file->f_pos ); +} + +/* Reads data from eeprom. */ + +static int eeprom_read_buf(loff_t addr, char * buf, int count) +{ + return eeprom_read(NULL, buf, count, &addr); +} + + + +/* Reads data from eeprom. */ + +static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t *off) +{ + int read=0; + unsigned long p = *off; + + unsigned char page; + + if(p >= eeprom.size) /* Address i 0 - (size-1) */ + { + return -EFAULT; + } + + if (mutex_lock_interruptible(&eeprom.lock)) + return -EINTR; + + page = (unsigned char) (p >> 8); + + if(!eeprom_address(p)) + { + printk(KERN_INFO "%s: Read failed to address the eeprom: " + "0x%08X (%i) page: %i\n", eeprom_name, (int)p, (int)p, page); + i2c_stop(); + + /* don't forget to wake them up */ + mutex_unlock(&eeprom.lock); + return -EFAULT; + } + + if( (p + count) > eeprom.size) + { + /* truncate count */ + count = eeprom.size - p; + } + + /* stop dummy write op and initiate the read op */ + i2c_start(); + + /* special case for small eeproms */ + if(eeprom.size < EEPROM_16KB) + { + i2c_outbyte( eeprom.select_cmd | 1 | (page << 1) ); + } + + /* go on with the actual read */ + read = read_from_eeprom( buf, count); + + if(read > 0) + { + *off += read; + } + + mutex_unlock(&eeprom.lock); + return read; +} + +/* Writes data to eeprom. */ + +static int eeprom_write_buf(loff_t addr, const char * buf, int count) +{ + return eeprom_write(NULL, buf, count, &addr); +} + + +/* Writes data to eeprom. */ + +static ssize_t eeprom_write(struct file * file, const char * buf, size_t count, + loff_t *off) +{ + int i, written, restart=1; + unsigned long p; + + if (!access_ok(VERIFY_READ, buf, count)) + { + return -EFAULT; + } + + /* bail out if we get interrupted */ + if (mutex_lock_interruptible(&eeprom.lock)) + return -EINTR; + for(i = 0; (i < EEPROM_RETRIES) && (restart > 0); i++) + { + restart = 0; + written = 0; + p = *off; + + + while( (written < count) && (p < eeprom.size)) + { + /* address the eeprom */ + if(!eeprom_address(p)) + { + printk(KERN_INFO "%s: Write failed to address the eeprom: " + "0x%08X (%i) \n", eeprom_name, (int)p, (int)p); + i2c_stop(); + + /* don't forget to wake them up */ + mutex_unlock(&eeprom.lock); + return -EFAULT; + } +#ifdef EEPROM_ADAPTIVE_TIMING + /* Adaptive algorithm to adjust timing */ + if (eeprom.retry_cnt_addr > 0) + { + /* To Low now */ + D(printk(">D=%i d=%i\n", + eeprom.usec_delay_writecycles, eeprom.usec_delay_step)); + + if (eeprom.usec_delay_step < 4) + { + eeprom.usec_delay_step++; + eeprom.usec_delay_writecycles += eeprom.usec_delay_step; + } + else + { + + if (eeprom.adapt_state > 0) + { + /* To Low before */ + eeprom.usec_delay_step *= 2; + if (eeprom.usec_delay_step > 2) + { + eeprom.usec_delay_step--; + } + eeprom.usec_delay_writecycles += eeprom.usec_delay_step; + } + else if (eeprom.adapt_state < 0) + { + /* To High before (toggle dir) */ + eeprom.usec_delay_writecycles += eeprom.usec_delay_step; + if (eeprom.usec_delay_step > 1) + { + eeprom.usec_delay_step /= 2; + eeprom.usec_delay_step--; + } + } + } + + eeprom.adapt_state = 1; + } + else + { + /* To High (or good) now */ + D(printk(" 1) + { + eeprom.usec_delay_step *= 2; + eeprom.usec_delay_step--; + + if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step) + { + eeprom.usec_delay_writecycles -= eeprom.usec_delay_step; + } + } + } + else if (eeprom.adapt_state > 0) + { + /* To Low before (toggle dir) */ + if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step) + { + eeprom.usec_delay_writecycles -= eeprom.usec_delay_step; + } + if (eeprom.usec_delay_step > 1) + { + eeprom.usec_delay_step /= 2; + eeprom.usec_delay_step--; + } + + eeprom.adapt_state = -1; + } + + if (eeprom.adapt_state > -100) + { + eeprom.adapt_state--; + } + else + { + /* Restart adaption */ + D(printk("#Restart\n")); + eeprom.usec_delay_step++; + } + } +#endif /* EEPROM_ADAPTIVE_TIMING */ + /* write until we hit a page boundary or count */ + do + { + i2c_outbyte(buf[written]); + if(!i2c_getack()) + { + restart=1; + printk(KERN_INFO "%s: write error, retrying. %d\n", eeprom_name, i); + i2c_stop(); + break; + } + written++; + p++; + } while( written < count && ( p % eeprom.sequential_write_pagesize )); + + /* end write cycle */ + i2c_stop(); + i2c_delay(eeprom.usec_delay_writecycles); + } /* while */ + } /* for */ + + mutex_unlock(&eeprom.lock); + if (written == 0 && p >= eeprom.size){ + return -ENOSPC; + } + *off = p; + return written; +} + +/* Closes the device. */ + +static int eeprom_close(struct inode * inode, struct file * file) +{ + /* do nothing for now */ + return 0; +} + +/* Sets the current address of the eeprom. */ + +static int eeprom_address(unsigned long addr) +{ + int i; + unsigned char page, offset; + + page = (unsigned char) (addr >> 8); + offset = (unsigned char) addr; + + for(i = 0; i < EEPROM_RETRIES; i++) + { + /* start a dummy write for addressing */ + i2c_start(); + + if(eeprom.size == EEPROM_16KB) + { + i2c_outbyte( eeprom.select_cmd ); + i2c_getack(); + i2c_outbyte(page); + } + else + { + i2c_outbyte( eeprom.select_cmd | (page << 1) ); + } + if(!i2c_getack()) + { + /* retry */ + i2c_stop(); + /* Must have a delay here.. 500 works, >50, 100->works 5th time*/ + i2c_delay(MAX_WRITEDELAY_US / EEPROM_RETRIES * i); + /* The chip needs up to 10 ms from write stop to next start */ + + } + else + { + i2c_outbyte(offset); + + if(!i2c_getack()) + { + /* retry */ + i2c_stop(); + } + else + break; + } + } + + + eeprom.retry_cnt_addr = i; + D(printk("%i\n", eeprom.retry_cnt_addr)); + if(eeprom.retry_cnt_addr == EEPROM_RETRIES) + { + /* failed */ + return 0; + } + return 1; +} + +/* Reads from current address. */ + +static int read_from_eeprom(char * buf, int count) +{ + int i, read=0; + + for(i = 0; i < EEPROM_RETRIES; i++) + { + if(eeprom.size == EEPROM_16KB) + { + i2c_outbyte( eeprom.select_cmd | 1 ); + } + + if(i2c_getack()) + { + break; + } + } + + if(i == EEPROM_RETRIES) + { + printk(KERN_INFO "%s: failed to read from eeprom\n", eeprom_name); + i2c_stop(); + + return -EFAULT; + } + + while( (read < count)) + { + if (put_user(i2c_inbyte(), &buf[read++])) + { + i2c_stop(); + + return -EFAULT; + } + + /* + * make sure we don't ack last byte or you will get very strange + * results! + */ + if(read < count) + { + i2c_sendack(); + } + } + + /* stop the operation */ + i2c_stop(); + + return read; +} + +/* Disables write protection if applicable. */ + +#define DBP_SAVE(x) +#define ax_printf printk +static void eeprom_disable_write_protect(void) +{ + /* Disable write protect */ + if (eeprom.size == EEPROM_8KB) + { + /* Step 1 Set WEL = 1 (write 00000010 to address 1FFFh */ + i2c_start(); + i2c_outbyte(0xbe); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false\n")); + } + i2c_outbyte(0xFF); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false 2\n")); + } + i2c_outbyte(0x02); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false 3\n")); + } + i2c_stop(); + + i2c_delay(1000); + + /* Step 2 Set RWEL = 1 (write 00000110 to address 1FFFh */ + i2c_start(); + i2c_outbyte(0xbe); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false 55\n")); + } + i2c_outbyte(0xFF); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false 52\n")); + } + i2c_outbyte(0x06); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false 53\n")); + } + i2c_stop(); + + /* Step 3 Set BP1, BP0, and/or WPEN bits (write 00000110 to address 1FFFh */ + i2c_start(); + i2c_outbyte(0xbe); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false 56\n")); + } + i2c_outbyte(0xFF); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false 57\n")); + } + i2c_outbyte(0x06); + if(!i2c_getack()) + { + DBP_SAVE(ax_printf("Get ack returns false 58\n")); + } + i2c_stop(); + + /* Write protect disabled */ + } +} + +module_init(eeprom_init); diff --git a/kernel/arch/cris/arch-v10/drivers/gpio.c b/kernel/arch/cris/arch-v10/drivers/gpio.c new file mode 100644 index 000000000..64285e0d3 --- /dev/null +++ b/kernel/arch/cris/arch-v10/drivers/gpio.c @@ -0,0 +1,856 @@ +/* + * Etrax general port I/O device + * + * Copyright (c) 1999-2007 Axis Communications AB + * + * Authors: Bjorn Wesen (initial version) + * Ola Knutsson (LED handling) + * Johan Adolfsson (read/set directions, write, port G) + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define GPIO_MAJOR 120 /* experimental MAJOR number */ + +#define D(x) + +#if 0 +static int dp_cnt; +#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0) +#else +#define DP(x) +#endif + +static char gpio_name[] = "etrax gpio"; + +#if 0 +static wait_queue_head_t *gpio_wq; +#endif + +static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg); +static ssize_t gpio_write(struct file *file, const char __user *buf, + size_t count, loff_t *off); +static int gpio_open(struct inode *inode, struct file *filp); +static int gpio_release(struct inode *inode, struct file *filp); +static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait); + +/* private data per open() of this driver */ + +struct gpio_private { + struct gpio_private *next; + /* These fields are for PA and PB only */ + volatile unsigned char *port, *shadow; + volatile unsigned char *dir, *dir_shadow; + unsigned char changeable_dir; + unsigned char changeable_bits; + unsigned char clk_mask; + unsigned char data_mask; + unsigned char write_msb; + unsigned char pad1, pad2, pad3; + /* These fields are generic */ + unsigned long highalarm, lowalarm; + wait_queue_head_t alarm_wq; + int minor; +}; + +/* linked list of alarms to check for */ + +static struct gpio_private *alarmlist; + +static int gpio_some_alarms; /* Set if someone uses alarm */ +static unsigned long gpio_pa_irq_enabled_mask; + +static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */ + +/* Port A and B use 8 bit access, but Port G is 32 bit */ +#define NUM_PORTS (GPIO_MINOR_B+1) + +static volatile unsigned char *ports[NUM_PORTS] = { + R_PORT_PA_DATA, + R_PORT_PB_DATA, +}; +static volatile unsigned char *shads[NUM_PORTS] = { + &port_pa_data_shadow, + &port_pb_data_shadow +}; + +/* What direction bits that are user changeable 1=changeable*/ +#ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR +#define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00 +#endif +#ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR +#define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00 +#endif + +#ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS +#define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF +#endif +#ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS +#define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF +#endif + + +static unsigned char changeable_dir[NUM_PORTS] = { + CONFIG_ETRAX_PA_CHANGEABLE_DIR, + CONFIG_ETRAX_PB_CHANGEABLE_DIR +}; +static unsigned char changeable_bits[NUM_PORTS] = { + CONFIG_ETRAX_PA_CHANGEABLE_BITS, + CONFIG_ETRAX_PB_CHANGEABLE_BITS +}; + +static volatile unsigned char *dir[NUM_PORTS] = { + R_PORT_PA_DIR, + R_PORT_PB_DIR +}; + +static volatile unsigned char *dir_shadow[NUM_PORTS] = { + &port_pa_dir_shadow, + &port_pb_dir_shadow +}; + +/* All bits in port g that can change dir. */ +static const unsigned long int changeable_dir_g_mask = 0x01FFFF01; + +/* Port G is 32 bit, handle it special, some bits are both inputs + and outputs at the same time, only some of the bits can change direction + and some of them in groups of 8 bit. */ +static unsigned long changeable_dir_g; +static unsigned long dir_g_in_bits; +static unsigned long dir_g_out_bits; +static unsigned long dir_g_shadow; /* 1=output */ + +#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B) + + +static unsigned int gpio_poll(struct file *file, poll_table *wait) +{ + unsigned int mask = 0; + struct gpio_private *priv = file->private_data; + unsigned long data; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + + poll_wait(file, &priv->alarm_wq, wait); + if (priv->minor == GPIO_MINOR_A) { + unsigned long tmp; + data = *R_PORT_PA_DATA; + /* PA has support for high level interrupt - + * lets activate for those low and with highalarm set + */ + tmp = ~data & priv->highalarm & 0xFF; + tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR); + + gpio_pa_irq_enabled_mask |= tmp; + *R_IRQ_MASK1_SET = tmp; + } else if (priv->minor == GPIO_MINOR_B) + data = *R_PORT_PB_DATA; + else if (priv->minor == GPIO_MINOR_G) + data = *R_PORT_G_DATA; + else { + mask = 0; + goto out; + } + + if ((data & priv->highalarm) || + (~data & priv->lowalarm)) { + mask = POLLIN|POLLRDNORM; + } + +out: + spin_unlock_irqrestore(&gpio_lock, flags); + DP(printk("gpio_poll ready: mask 0x%08X\n", mask)); + + return mask; +} + +int etrax_gpio_wake_up_check(void) +{ + struct gpio_private *priv; + unsigned long data = 0; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + priv = alarmlist; + while (priv) { + if (USE_PORTS(priv)) + data = *priv->port; + else if (priv->minor == GPIO_MINOR_G) + data = *R_PORT_G_DATA; + + if ((data & priv->highalarm) || + (~data & priv->lowalarm)) { + DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor)); + wake_up_interruptible(&priv->alarm_wq); + ret = 1; + } + priv = priv->next; + } + spin_unlock_irqrestore(&gpio_lock, flags); + return ret; +} + +static irqreturn_t +gpio_poll_timer_interrupt(int irq, void *dev_id) +{ + if (gpio_some_alarms) { + etrax_gpio_wake_up_check(); + return IRQ_HANDLED; + } + return IRQ_NONE; +} + +static irqreturn_t +gpio_interrupt(int irq, void *dev_id) +{ + unsigned long tmp; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + + /* Find what PA interrupts are active */ + tmp = (*R_IRQ_READ1); + + /* Find those that we have enabled */ + tmp &= gpio_pa_irq_enabled_mask; + + /* Clear them.. */ + *R_IRQ_MASK1_CLR = tmp; + gpio_pa_irq_enabled_mask &= ~tmp; + + spin_unlock_irqrestore(&gpio_lock, flags); + + if (gpio_some_alarms) + return IRQ_RETVAL(etrax_gpio_wake_up_check()); + + return IRQ_NONE; +} + +static void gpio_write_bit(struct gpio_private *priv, + unsigned char data, int bit) +{ + *priv->port = *priv->shadow &= ~(priv->clk_mask); + if (data & 1 << bit) + *priv->port = *priv->shadow |= priv->data_mask; + else + *priv->port = *priv->shadow &= ~(priv->data_mask); + + /* For FPGA: min 5.0ns (DCC) before CCLK high */ + *priv->port = *priv->shadow |= priv->clk_mask; +} + +static void gpio_write_byte(struct gpio_private *priv, unsigned char data) +{ + int i; + + if (priv->write_msb) + for (i = 7; i >= 0; i--) + gpio_write_bit(priv, data, i); + else + for (i = 0; i <= 7; i++) + gpio_write_bit(priv, data, i); +} + +static ssize_t gpio_write(struct file *file, const char __user *buf, + size_t count, loff_t *off) +{ + struct gpio_private *priv = file->private_data; + unsigned long flags; + ssize_t retval = count; + + if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) + return -EFAULT; + + if (!access_ok(VERIFY_READ, buf, count)) + return -EFAULT; + + spin_lock_irqsave(&gpio_lock, flags); + + /* It must have been configured using the IO_CFG_WRITE_MODE */ + /* Perhaps a better error code? */ + if (priv->clk_mask == 0 || priv->data_mask == 0) { + retval = -EPERM; + goto out; + } + + D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X " + "clk 0x%02X msb: %i\n", + count, priv->data_mask, priv->clk_mask, priv->write_msb)); + + while (count--) + gpio_write_byte(priv, *buf++); + +out: + spin_unlock_irqrestore(&gpio_lock, flags); + return retval; +} + + + +static int +gpio_open(struct inode *inode, struct file *filp) +{ + struct gpio_private *priv; + int p = iminor(inode); + unsigned long flags; + + if (p > GPIO_MINOR_LAST) + return -EINVAL; + + priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + priv->minor = p; + + /* initialize the io/alarm struct */ + + if (USE_PORTS(priv)) { /* A and B */ + priv->port = ports[p]; + priv->shadow = shads[p]; + priv->dir = dir[p]; + priv->dir_shadow = dir_shadow[p]; + priv->changeable_dir = changeable_dir[p]; + priv->changeable_bits = changeable_bits[p]; + } else { + priv->port = NULL; + priv->shadow = NULL; + priv->dir = NULL; + priv->dir_shadow = NULL; + priv->changeable_dir = 0; + priv->changeable_bits = 0; + } + + priv->highalarm = 0; + priv->lowalarm = 0; + priv->clk_mask = 0; + priv->data_mask = 0; + init_waitqueue_head(&priv->alarm_wq); + + filp->private_data = priv; + + /* link it into our alarmlist */ + spin_lock_irqsave(&gpio_lock, flags); + priv->next = alarmlist; + alarmlist = priv; + spin_unlock_irqrestore(&gpio_lock, flags); + + return 0; +} + +static int +gpio_release(struct inode *inode, struct file *filp) +{ + struct gpio_private *p; + struct gpio_private *todel; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + + p = alarmlist; + todel = filp->private_data; + + /* unlink from alarmlist and free the private structure */ + + if (p == todel) { + alarmlist = todel->next; + } else { + while (p->next != todel) + p = p->next; + p->next = todel->next; + } + + kfree(todel); + /* Check if there are still any alarms set */ + p = alarmlist; + while (p) { + if (p->highalarm | p->lowalarm) { + gpio_some_alarms = 1; + goto out; + } + p = p->next; + } + gpio_some_alarms = 0; +out: + spin_unlock_irqrestore(&gpio_lock, flags); + return 0; +} + +/* Main device API. ioctl's to read/set/clear bits, as well as to + * set alarms to wait for using a subsequent select(). + */ +unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg) +{ + /* Set direction 0=unchanged 1=input, + * return mask with 1=input */ + if (USE_PORTS(priv)) { + *priv->dir = *priv->dir_shadow &= + ~((unsigned char)arg & priv->changeable_dir); + return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */ + } + + if (priv->minor != GPIO_MINOR_G) + return 0; + + /* We must fiddle with R_GEN_CONFIG to change dir */ + if (((arg & dir_g_in_bits) != arg) && + (arg & changeable_dir_g)) { + arg &= changeable_dir_g; + /* Clear bits in genconfig to set to input */ + if (arg & (1<<0)) { + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir); + dir_g_in_bits |= (1<<0); + dir_g_out_bits &= ~(1<<0); + } + if ((arg & 0x0000FF00) == 0x0000FF00) { + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir); + dir_g_in_bits |= 0x0000FF00; + dir_g_out_bits &= ~0x0000FF00; + } + if ((arg & 0x00FF0000) == 0x00FF0000) { + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir); + dir_g_in_bits |= 0x00FF0000; + dir_g_out_bits &= ~0x00FF0000; + } + if (arg & (1<<24)) { + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir); + dir_g_in_bits |= (1<<24); + dir_g_out_bits &= ~(1<<24); + } + D(printk(KERN_DEBUG "gpio: SETINPUT on port G set " + "genconfig to 0x%08lX " + "in_bits: 0x%08lX " + "out_bits: 0x%08lX\n", + (unsigned long)genconfig_shadow, + dir_g_in_bits, dir_g_out_bits)); + *R_GEN_CONFIG = genconfig_shadow; + /* Must be a >120 ns delay before writing this again */ + + } + return dir_g_in_bits; +} /* setget_input */ + +unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg) +{ + if (USE_PORTS(priv)) { + *priv->dir = *priv->dir_shadow |= + ((unsigned char)arg & priv->changeable_dir); + return *priv->dir_shadow; + } + if (priv->minor != GPIO_MINOR_G) + return 0; + + /* We must fiddle with R_GEN_CONFIG to change dir */ + if (((arg & dir_g_out_bits) != arg) && + (arg & changeable_dir_g)) { + /* Set bits in genconfig to set to output */ + if (arg & (1<<0)) { + genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir); + dir_g_out_bits |= (1<<0); + dir_g_in_bits &= ~(1<<0); + } + if ((arg & 0x0000FF00) == 0x0000FF00) { + genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir); + dir_g_out_bits |= 0x0000FF00; + dir_g_in_bits &= ~0x0000FF00; + } + if ((arg & 0x00FF0000) == 0x00FF0000) { + genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir); + dir_g_out_bits |= 0x00FF0000; + dir_g_in_bits &= ~0x00FF0000; + } + if (arg & (1<<24)) { + genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir); + dir_g_out_bits |= (1<<24); + dir_g_in_bits &= ~(1<<24); + } + D(printk(KERN_INFO "gpio: SETOUTPUT on port G set " + "genconfig to 0x%08lX " + "in_bits: 0x%08lX " + "out_bits: 0x%08lX\n", + (unsigned long)genconfig_shadow, + dir_g_in_bits, dir_g_out_bits)); + *R_GEN_CONFIG = genconfig_shadow; + /* Must be a >120 ns delay before writing this again */ + } + return dir_g_out_bits & 0x7FFFFFFF; +} /* setget_output */ + +static int +gpio_leds_ioctl(unsigned int cmd, unsigned long arg); + +static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + unsigned long flags; + unsigned long val; + int ret = 0; + + struct gpio_private *priv = file->private_data; + if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) + return -EINVAL; + + switch (_IOC_NR(cmd)) { + case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ + // read the port + spin_lock_irqsave(&gpio_lock, flags); + if (USE_PORTS(priv)) { + ret = *priv->port; + } else if (priv->minor == GPIO_MINOR_G) { + ret = (*R_PORT_G_DATA) & 0x7FFFFFFF; + } + spin_unlock_irqrestore(&gpio_lock, flags); + + break; + case IO_SETBITS: + // set changeable bits with a 1 in arg + spin_lock_irqsave(&gpio_lock, flags); + + if (USE_PORTS(priv)) { + *priv->port = *priv->shadow |= + ((unsigned char)arg & priv->changeable_bits); + } else if (priv->minor == GPIO_MINOR_G) { + *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits); + } + spin_unlock_irqrestore(&gpio_lock, flags); + + break; + case IO_CLRBITS: + // clear changeable bits with a 1 in arg + spin_lock_irqsave(&gpio_lock, flags); + if (USE_PORTS(priv)) { + *priv->port = *priv->shadow &= + ~((unsigned char)arg & priv->changeable_bits); + } else if (priv->minor == GPIO_MINOR_G) { + *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits); + } + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_HIGHALARM: + // set alarm when bits with 1 in arg go high + spin_lock_irqsave(&gpio_lock, flags); + priv->highalarm |= arg; + gpio_some_alarms = 1; + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_LOWALARM: + // set alarm when bits with 1 in arg go low + spin_lock_irqsave(&gpio_lock, flags); + priv->lowalarm |= arg; + gpio_some_alarms = 1; + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_CLRALARM: + /* clear alarm for bits with 1 in arg */ + spin_lock_irqsave(&gpio_lock, flags); + priv->highalarm &= ~arg; + priv->lowalarm &= ~arg; + { + /* Must update gpio_some_alarms */ + struct gpio_private *p = alarmlist; + int some_alarms; + p = alarmlist; + some_alarms = 0; + while (p) { + if (p->highalarm | p->lowalarm) { + some_alarms = 1; + break; + } + p = p->next; + } + gpio_some_alarms = some_alarms; + } + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ + /* Read direction 0=input 1=output */ + spin_lock_irqsave(&gpio_lock, flags); + if (USE_PORTS(priv)) { + ret = *priv->dir_shadow; + } else if (priv->minor == GPIO_MINOR_G) { + /* Note: Some bits are both in and out, + * Those that are dual is set here as well. + */ + ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF; + } + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */ + /* Set direction 0=unchanged 1=input, + * return mask with 1=input + */ + spin_lock_irqsave(&gpio_lock, flags); + ret = setget_input(priv, arg) & 0x7FFFFFFF; + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */ + /* Set direction 0=unchanged 1=output, + * return mask with 1=output + */ + spin_lock_irqsave(&gpio_lock, flags); + ret = setget_output(priv, arg) & 0x7FFFFFFF; + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_SHUTDOWN: + spin_lock_irqsave(&gpio_lock, flags); + SOFT_SHUTDOWN(); + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_GET_PWR_BT: + spin_lock_irqsave(&gpio_lock, flags); +#if defined (CONFIG_ETRAX_SOFT_SHUTDOWN) + ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT)); +#else + ret = 0; +#endif + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_CFG_WRITE_MODE: + spin_lock_irqsave(&gpio_lock, flags); + priv->clk_mask = arg & 0xFF; + priv->data_mask = (arg >> 8) & 0xFF; + priv->write_msb = (arg >> 16) & 0x01; + /* Check if we're allowed to change the bits and + * the direction is correct + */ + if (!((priv->clk_mask & priv->changeable_bits) && + (priv->data_mask & priv->changeable_bits) && + (priv->clk_mask & *priv->dir_shadow) && + (priv->data_mask & *priv->dir_shadow))) + { + priv->clk_mask = 0; + priv->data_mask = 0; + ret = -EPERM; + } + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_READ_INBITS: + /* *arg is result of reading the input pins */ + spin_lock_irqsave(&gpio_lock, flags); + if (USE_PORTS(priv)) { + val = *priv->port; + } else if (priv->minor == GPIO_MINOR_G) { + val = *R_PORT_G_DATA; + } + spin_unlock_irqrestore(&gpio_lock, flags); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + ret = -EFAULT; + break; + case IO_READ_OUTBITS: + /* *arg is result of reading the output shadow */ + spin_lock_irqsave(&gpio_lock, flags); + if (USE_PORTS(priv)) { + val = *priv->shadow; + } else if (priv->minor == GPIO_MINOR_G) { + val = port_g_data_shadow; + } + spin_unlock_irqrestore(&gpio_lock, flags); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + ret = -EFAULT; + break; + case IO_SETGET_INPUT: + /* bits set in *arg is set to input, + * *arg updated with current input pins. + */ + if (copy_from_user(&val, (void __user *)arg, sizeof(val))) + { + ret = -EFAULT; + break; + } + spin_lock_irqsave(&gpio_lock, flags); + val = setget_input(priv, val); + spin_unlock_irqrestore(&gpio_lock, flags); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + ret = -EFAULT; + break; + case IO_SETGET_OUTPUT: + /* bits set in *arg is set to output, + * *arg updated with current output pins. + */ + if (copy_from_user(&val, (void __user *)arg, sizeof(val))) { + ret = -EFAULT; + break; + } + spin_lock_irqsave(&gpio_lock, flags); + val = setget_output(priv, val); + spin_unlock_irqrestore(&gpio_lock, flags); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + ret = -EFAULT; + break; + default: + spin_lock_irqsave(&gpio_lock, flags); + if (priv->minor == GPIO_MINOR_LEDS) + ret = gpio_leds_ioctl(cmd, arg); + else + ret = -EINVAL; + spin_unlock_irqrestore(&gpio_lock, flags); + } /* switch */ + + return ret; +} + +static int +gpio_leds_ioctl(unsigned int cmd, unsigned long arg) +{ + unsigned char green; + unsigned char red; + + switch (_IOC_NR(cmd)) { + case IO_LEDACTIVE_SET: + green = ((unsigned char)arg) & 1; + red = (((unsigned char)arg) >> 1) & 1; + CRIS_LED_ACTIVE_SET_G(green); + CRIS_LED_ACTIVE_SET_R(red); + break; + + case IO_LED_SETBIT: + CRIS_LED_BIT_SET(arg); + break; + + case IO_LED_CLRBIT: + CRIS_LED_BIT_CLR(arg); + break; + + default: + return -EINVAL; + } /* switch */ + + return 0; +} + +static const struct file_operations gpio_fops = { + .owner = THIS_MODULE, + .poll = gpio_poll, + .unlocked_ioctl = gpio_ioctl, + .write = gpio_write, + .open = gpio_open, + .release = gpio_release, + .llseek = noop_llseek, +}; + +static void ioif_watcher(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available) +{ + unsigned long int flags; + + D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n")); + D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x " + "PA: 0x%02x PB: 0x%02x\n", + gpio_in_available, gpio_out_available, + pa_available, pb_available)); + + spin_lock_irqsave(&gpio_lock, flags); + + dir_g_in_bits = gpio_in_available; + dir_g_out_bits = gpio_out_available; + + /* Initialise the dir_g_shadow etc. depending on genconfig */ + /* 0=input 1=output */ + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out)) + dir_g_shadow |= (1 << 0); + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out)) + dir_g_shadow |= 0x0000FF00; + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out)) + dir_g_shadow |= 0x00FF0000; + if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out)) + dir_g_shadow |= (1 << 24); + + changeable_dir_g = changeable_dir_g_mask; + changeable_dir_g &= dir_g_out_bits; + changeable_dir_g &= dir_g_in_bits; + + /* Correct the bits that can change direction */ + dir_g_out_bits &= ~changeable_dir_g; + dir_g_out_bits |= dir_g_shadow; + dir_g_in_bits &= ~changeable_dir_g; + dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g); + + spin_unlock_irqrestore(&gpio_lock, flags); + + printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX " + "val: %08lX\n", + dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA); + printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n", + dir_g_shadow, changeable_dir_g); +} + +/* main driver initialization routine, called from mem.c */ + +static int __init gpio_init(void) +{ + int res; +#if defined (CONFIG_ETRAX_CSP0_LEDS) + int i; +#endif + + res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops); + if (res < 0) { + printk(KERN_ERR "gpio: couldn't get a major number.\n"); + return res; + } + + /* Clear all leds */ +#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS) + CRIS_LED_NETWORK_SET(0); + CRIS_LED_ACTIVE_SET(0); + CRIS_LED_DISK_READ(0); + CRIS_LED_DISK_WRITE(0); + +#if defined (CONFIG_ETRAX_CSP0_LEDS) + for (i = 0; i < 32; i++) + CRIS_LED_BIT_SET(i); +#endif + +#endif + /* The I/O interface allocation watcher will be called when + * registering it. */ + if (cris_io_interface_register_watcher(ioif_watcher)){ + printk(KERN_WARNING "gpio_init: Failed to install IO " + "if allocator watcher\n"); + } + + printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 " + "Axis Communications AB\n"); + /* We call etrax_gpio_wake_up_check() from timer interrupt and + * from default_idle() in kernel/process.c + * The check in default_idle() reduces latency from ~15 ms to ~6 ms + * in some tests. + */ + res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt, + IRQF_SHARED, "gpio poll", gpio_name); + if (res) { + printk(KERN_CRIT "err: timer0 irq for gpio\n"); + return res; + } + res = request_irq(PA_IRQ_NBR, gpio_interrupt, + IRQF_SHARED, "gpio PA", gpio_name); + if (res) + printk(KERN_CRIT "err: PA irq for gpio\n"); + + return res; +} + +/* this makes sure that gpio_init is called during kernel boot */ +module_init(gpio_init); + diff --git a/kernel/arch/cris/arch-v10/drivers/i2c.c b/kernel/arch/cris/arch-v10/drivers/i2c.c new file mode 100644 index 000000000..b3d1f9ed1 --- /dev/null +++ b/kernel/arch/cris/arch-v10/drivers/i2c.c @@ -0,0 +1,698 @@ +/*!*************************************************************************** +*! +*! FILE NAME : i2c.c +*! +*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other +*! kernel modules (i2c_writereg/readreg) and from userspace using +*! ioctl()'s +*! +*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN +*! +*!***************************************************************************/ + +/****************** INCLUDE FILES SECTION ***********************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include "i2c.h" + +/****************** I2C DEFINITION SECTION *************************/ + +#define D(x) + +#define I2C_MAJOR 123 /* LOCAL/EXPERIMENTAL */ +static const char i2c_name[] = "i2c"; + +#define CLOCK_LOW_TIME 8 +#define CLOCK_HIGH_TIME 8 +#define START_CONDITION_HOLD_TIME 8 +#define STOP_CONDITION_HOLD_TIME 8 +#define ENABLE_OUTPUT 0x01 +#define ENABLE_INPUT 0x00 +#define I2C_CLOCK_HIGH 1 +#define I2C_CLOCK_LOW 0 +#define I2C_DATA_HIGH 1 +#define I2C_DATA_LOW 0 + +#ifdef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C +/* Use PB and not PB_I2C */ +#ifndef CONFIG_ETRAX_I2C_DATA_PORT +#define CONFIG_ETRAX_I2C_DATA_PORT 0 +#endif +#ifndef CONFIG_ETRAX_I2C_CLK_PORT +#define CONFIG_ETRAX_I2C_CLK_PORT 1 +#endif + +#define SDABIT CONFIG_ETRAX_I2C_DATA_PORT +#define SCLBIT CONFIG_ETRAX_I2C_CLK_PORT +#define i2c_enable() +#define i2c_disable() + +/* enable or disable output-enable, to select output or input on the i2c bus */ + +#define i2c_dir_out() \ + REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 1) +#define i2c_dir_in() \ + REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 0) + +/* control the i2c clock and data signals */ + +#define i2c_clk(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SCLBIT, x) +#define i2c_data(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SDABIT, x) + +/* read a bit from the i2c interface */ + +#define i2c_getbit() (((*R_PORT_PB_READ & (1 << SDABIT))) >> SDABIT) + +#else +/* enable or disable the i2c interface */ + +#define i2c_enable() *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_en)) +#define i2c_disable() *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_en)) + +/* enable or disable output-enable, to select output or input on the i2c bus */ + +#define i2c_dir_out() \ + *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \ + REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 1); +#define i2c_dir_in() \ + *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \ + REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 0); + +/* control the i2c clock and data signals */ + +#define i2c_clk(x) \ + *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \ + ~IO_MASK(R_PORT_PB_I2C, i2c_clk)) | IO_FIELD(R_PORT_PB_I2C, i2c_clk, (x))); \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 1, x); + +#define i2c_data(x) \ + *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \ + ~IO_MASK(R_PORT_PB_I2C, i2c_d)) | IO_FIELD(R_PORT_PB_I2C, i2c_d, (x))); \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 0, x); + +/* read a bit from the i2c interface */ + +#define i2c_getbit() (*R_PORT_PB_READ & 0x1) +#endif + +/* use the kernels delay routine */ + +#define i2c_delay(usecs) udelay(usecs) + +static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */ + +/****************** FUNCTION DEFINITION SECTION *************************/ + + +/* generate i2c start condition */ + +void +i2c_start(void) +{ + /* + * SCL=1 SDA=1 + */ + i2c_dir_out(); + i2c_delay(CLOCK_HIGH_TIME/6); + i2c_data(I2C_DATA_HIGH); + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + /* + * SCL=1 SDA=0 + */ + i2c_data(I2C_DATA_LOW); + i2c_delay(START_CONDITION_HOLD_TIME); + /* + * SCL=0 SDA=0 + */ + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME); +} + +/* generate i2c stop condition */ + +void +i2c_stop(void) +{ + i2c_dir_out(); + + /* + * SCL=0 SDA=0 + */ + i2c_clk(I2C_CLOCK_LOW); + i2c_data(I2C_DATA_LOW); + i2c_delay(CLOCK_LOW_TIME*2); + /* + * SCL=1 SDA=0 + */ + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME*2); + /* + * SCL=1 SDA=1 + */ + i2c_data(I2C_DATA_HIGH); + i2c_delay(STOP_CONDITION_HOLD_TIME); + + i2c_dir_in(); +} + +/* write a byte to the i2c interface */ + +void +i2c_outbyte(unsigned char x) +{ + int i; + + i2c_dir_out(); + + for (i = 0; i < 8; i++) { + if (x & 0x80) { + i2c_data(I2C_DATA_HIGH); + } else { + i2c_data(I2C_DATA_LOW); + } + + i2c_delay(CLOCK_LOW_TIME/2); + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME/2); + x <<= 1; + } + i2c_data(I2C_DATA_LOW); + i2c_delay(CLOCK_LOW_TIME/2); + + /* + * enable input + */ + i2c_dir_in(); +} + +/* read a byte from the i2c interface */ + +unsigned char +i2c_inbyte(void) +{ + unsigned char aBitByte = 0; + int i; + + /* Switch off I2C to get bit */ + i2c_disable(); + i2c_dir_in(); + i2c_delay(CLOCK_HIGH_TIME/2); + + /* Get bit */ + aBitByte |= i2c_getbit(); + + /* Enable I2C */ + i2c_enable(); + i2c_delay(CLOCK_LOW_TIME/2); + + for (i = 1; i < 8; i++) { + aBitByte <<= 1; + /* Clock pulse */ + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME); + + /* Switch off I2C to get bit */ + i2c_disable(); + i2c_dir_in(); + i2c_delay(CLOCK_HIGH_TIME/2); + + /* Get bit */ + aBitByte |= i2c_getbit(); + + /* Enable I2C */ + i2c_enable(); + i2c_delay(CLOCK_LOW_TIME/2); + } + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + + /* + * we leave the clock low, getbyte is usually followed + * by sendack/nack, they assume the clock to be low + */ + i2c_clk(I2C_CLOCK_LOW); + return aBitByte; +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_getack +*# +*# DESCRIPTION : checks if ack was received from ic2 +*# +*#--------------------------------------------------------------------------*/ + +int +i2c_getack(void) +{ + int ack = 1; + /* + * enable output + */ + i2c_dir_out(); + /* + * Release data bus by setting + * data high + */ + i2c_data(I2C_DATA_HIGH); + /* + * enable input + */ + i2c_dir_in(); + i2c_delay(CLOCK_HIGH_TIME/4); + /* + * generate ACK clock pulse + */ + i2c_clk(I2C_CLOCK_HIGH); + /* + * Use PORT PB instead of I2C + * for input. (I2C not working) + */ + i2c_clk(1); + i2c_data(1); + /* + * switch off I2C + */ + i2c_data(1); + i2c_disable(); + i2c_dir_in(); + /* + * now wait for ack + */ + i2c_delay(CLOCK_HIGH_TIME/2); + /* + * check for ack + */ + if(i2c_getbit()) + ack = 0; + i2c_delay(CLOCK_HIGH_TIME/2); + if(!ack){ + if(!i2c_getbit()) /* receiver pulld SDA low */ + ack = 1; + i2c_delay(CLOCK_HIGH_TIME/2); + } + + /* + * our clock is high now, make sure data is low + * before we enable our output. If we keep data high + * and enable output, we would generate a stop condition. + */ + i2c_data(I2C_DATA_LOW); + + /* + * end clock pulse + */ + i2c_enable(); + i2c_dir_out(); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_HIGH_TIME/4); + /* + * enable output + */ + i2c_dir_out(); + /* + * remove ACK clock pulse + */ + i2c_data(I2C_DATA_HIGH); + i2c_delay(CLOCK_LOW_TIME/2); + return ack; +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: I2C::sendAck +*# +*# DESCRIPTION : Send ACK on received data +*# +*#--------------------------------------------------------------------------*/ +void +i2c_sendack(void) +{ + /* + * enable output + */ + i2c_delay(CLOCK_LOW_TIME); + i2c_dir_out(); + /* + * set ack pulse high + */ + i2c_data(I2C_DATA_LOW); + /* + * generate clock pulse + */ + i2c_delay(CLOCK_HIGH_TIME/6); + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME/6); + /* + * reset data out + */ + i2c_data(I2C_DATA_HIGH); + i2c_delay(CLOCK_LOW_TIME); + + i2c_dir_in(); +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_sendnack +*# +*# DESCRIPTION : Sends NACK on received data +*# +*#--------------------------------------------------------------------------*/ +void +i2c_sendnack(void) +{ + /* + * enable output + */ + i2c_delay(CLOCK_LOW_TIME); + i2c_dir_out(); + /* + * set data high + */ + i2c_data(I2C_DATA_HIGH); + /* + * generate clock pulse + */ + i2c_delay(CLOCK_HIGH_TIME/6); + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME); + + i2c_dir_in(); +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_writereg +*# +*# DESCRIPTION : Writes a value to an I2C device +*# +*#--------------------------------------------------------------------------*/ +int +i2c_writereg(unsigned char theSlave, unsigned char theReg, + unsigned char theValue) +{ + int error, cntr = 3; + unsigned long flags; + + spin_lock(&i2c_lock); + + do { + error = 0; + /* + * we don't like to be interrupted + */ + local_irq_save(flags); + + i2c_start(); + /* + * send slave address + */ + i2c_outbyte((theSlave & 0xfe)); + /* + * wait for ack + */ + if(!i2c_getack()) + error = 1; + /* + * now select register + */ + i2c_dir_out(); + i2c_outbyte(theReg); + /* + * now it's time to wait for ack + */ + if(!i2c_getack()) + error |= 2; + /* + * send register register data + */ + i2c_outbyte(theValue); + /* + * now it's time to wait for ack + */ + if(!i2c_getack()) + error |= 4; + /* + * end byte stream + */ + i2c_stop(); + /* + * enable interrupt again + */ + local_irq_restore(flags); + + } while(error && cntr--); + + i2c_delay(CLOCK_LOW_TIME); + + spin_unlock(&i2c_lock); + + return -error; +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_readreg +*# +*# DESCRIPTION : Reads a value from the decoder registers. +*# +*#--------------------------------------------------------------------------*/ +unsigned char +i2c_readreg(unsigned char theSlave, unsigned char theReg) +{ + unsigned char b = 0; + int error, cntr = 3; + unsigned long flags; + + spin_lock(&i2c_lock); + + do { + error = 0; + /* + * we don't like to be interrupted + */ + local_irq_save(flags); + /* + * generate start condition + */ + i2c_start(); + + /* + * send slave address + */ + i2c_outbyte((theSlave & 0xfe)); + /* + * wait for ack + */ + if(!i2c_getack()) + error = 1; + /* + * now select register + */ + i2c_dir_out(); + i2c_outbyte(theReg); + /* + * now it's time to wait for ack + */ + if(!i2c_getack()) + error = 1; + /* + * repeat start condition + */ + i2c_delay(CLOCK_LOW_TIME); + i2c_start(); + /* + * send slave address + */ + i2c_outbyte(theSlave | 0x01); + /* + * wait for ack + */ + if(!i2c_getack()) + error = 1; + /* + * fetch register + */ + b = i2c_inbyte(); + /* + * last received byte needs to be nacked + * instead of acked + */ + i2c_sendnack(); + /* + * end sequence + */ + i2c_stop(); + /* + * enable interrupt again + */ + local_irq_restore(flags); + + } while(error && cntr--); + + spin_unlock(&i2c_lock); + + return b; +} + +static int +i2c_open(struct inode *inode, struct file *filp) +{ + return 0; +} + +static int +i2c_release(struct inode *inode, struct file *filp) +{ + return 0; +} + +/* Main device API. ioctl's to write or read to/from i2c registers. + */ + +static long i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) { + return -EINVAL; + } + + switch (_IOC_NR(cmd)) { + case I2C_WRITEREG: + /* write to an i2c slave */ + D(printk(KERN_DEBUG "i2cw %d %d %d\n", + I2C_ARGSLAVE(arg), + I2C_ARGREG(arg), + I2C_ARGVALUE(arg))); + + return i2c_writereg(I2C_ARGSLAVE(arg), + I2C_ARGREG(arg), + I2C_ARGVALUE(arg)); + case I2C_READREG: + { + unsigned char val; + /* read from an i2c slave */ + D(printk(KERN_DEBUG "i2cr %d %d ", + I2C_ARGSLAVE(arg), + I2C_ARGREG(arg))); + val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg)); + D(printk(KERN_DEBUG "= %d\n", val)); + return val; + } + default: + return -EINVAL; + + } + return 0; +} + +static const struct file_operations i2c_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = i2c_ioctl, + .open = i2c_open, + .release = i2c_release, + .llseek = noop_llseek, +}; + +int __init +i2c_init(void) +{ + static int res = 0; + static int first = 1; + + if (!first) { + return res; + } + first = 0; + + /* Setup and enable the Port B I2C interface */ + +#ifndef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C + if ((res = cris_request_io_interface(if_i2c, "I2C"))) { + printk(KERN_CRIT "i2c_init: Failed to get IO interface\n"); + return res; + } + + *R_PORT_PB_I2C = port_pb_i2c_shadow |= + IO_STATE(R_PORT_PB_I2C, i2c_en, on) | + IO_FIELD(R_PORT_PB_I2C, i2c_d, 1) | + IO_FIELD(R_PORT_PB_I2C, i2c_clk, 1) | + IO_STATE(R_PORT_PB_I2C, i2c_oe_, enable); + + port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir0); + port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir1); + + *R_PORT_PB_DIR = (port_pb_dir_shadow |= + IO_STATE(R_PORT_PB_DIR, dir0, input) | + IO_STATE(R_PORT_PB_DIR, dir1, output)); +#else + if ((res = cris_io_interface_allocate_pins(if_i2c, + 'b', + CONFIG_ETRAX_I2C_DATA_PORT, + CONFIG_ETRAX_I2C_DATA_PORT))) { + printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C data port\n"); + return res; + } else if ((res = cris_io_interface_allocate_pins(if_i2c, + 'b', + CONFIG_ETRAX_I2C_CLK_PORT, + CONFIG_ETRAX_I2C_CLK_PORT))) { + cris_io_interface_free_pins(if_i2c, + 'b', + CONFIG_ETRAX_I2C_DATA_PORT, + CONFIG_ETRAX_I2C_DATA_PORT); + printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C clk port\n"); + } +#endif + + return res; +} + +static int __init +i2c_register(void) +{ + int res; + + res = i2c_init(); + if (res < 0) + return res; + res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops); + if(res < 0) { + printk(KERN_ERR "i2c: couldn't get a major number.\n"); + return res; + } + + printk(KERN_INFO "I2C driver v2.2, (c) 1999-2004 Axis Communications AB\n"); + + return 0; +} + +/* this makes sure that i2c_register is called during boot */ + +module_init(i2c_register); + +/****************** END OF FILE i2c.c ********************************/ diff --git a/kernel/arch/cris/arch-v10/drivers/i2c.h b/kernel/arch/cris/arch-v10/drivers/i2c.h new file mode 100644 index 000000000..e36c96276 --- /dev/null +++ b/kernel/arch/cris/arch-v10/drivers/i2c.h @@ -0,0 +1,17 @@ +/* i2c.h */ +int i2c_init(void); + +/* High level I2C actions */ +int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); +unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg); + +/* Low level I2C */ +void i2c_start(void); +void i2c_stop(void); +void i2c_outbyte(unsigned char x); +unsigned char i2c_inbyte(void); +int i2c_getack(void); +void i2c_sendack(void); + + + diff --git a/kernel/arch/cris/arch-v10/drivers/sync_serial.c b/kernel/arch/cris/arch-v10/drivers/sync_serial.c new file mode 100644 index 000000000..0f3983241 --- /dev/null +++ b/kernel/arch/cris/arch-v10/drivers/sync_serial.c @@ -0,0 +1,1462 @@ +/* + * Simple synchronous serial port driver for ETRAX 100LX. + * + * Synchronous serial ports are used for continuous streamed data like audio. + * The default setting for this driver is compatible with the STA 013 MP3 + * decoder. The driver can easily be tuned to fit other audio encoder/decoders + * and SPI + * + * Copyright (c) 2001-2008 Axis Communications AB + * + * Author: Mikael Starvik, Johan Adolfsson + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The receiver is a bit tricky because of the continuous stream of data.*/ +/* */ +/* Three DMA descriptors are linked together. Each DMA descriptor is */ +/* responsible for port->bufchunk of a common buffer. */ +/* */ +/* +---------------------------------------------+ */ +/* | +----------+ +----------+ +----------+ | */ +/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */ +/* +----------+ +----------+ +----------+ */ +/* | | | */ +/* v v v */ +/* +-------------------------------------+ */ +/* | BUFFER | */ +/* +-------------------------------------+ */ +/* |<- data_avail ->| */ +/* readp writep */ +/* */ +/* If the application keeps up the pace readp will be right after writep.*/ +/* If the application can't keep the pace we have to throw away data. */ +/* The idea is that readp should be ready with the data pointed out by */ +/* Descr[i] when the DMA has filled in Descr[i+1]. */ +/* Otherwise we will discard */ +/* the rest of the data pointed out by Descr1 and set readp to the start */ +/* of Descr2 */ + +#define SYNC_SERIAL_MAJOR 125 + +/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ +/* words can be handled */ +#define IN_BUFFER_SIZE 12288 +#define IN_DESCR_SIZE 256 +#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE) +#define OUT_BUFFER_SIZE 4096 + +#define DEFAULT_FRAME_RATE 0 +#define DEFAULT_WORD_RATE 7 + +/* NOTE: Enabling some debug will likely cause overrun or underrun, + * especially if manual mode is use. + */ +#define DEBUG(x) +#define DEBUGREAD(x) +#define DEBUGWRITE(x) +#define DEBUGPOLL(x) +#define DEBUGRXINT(x) +#define DEBUGTXINT(x) + +/* Define some macros to access ETRAX 100 registers */ +#define SETF(var, reg, field, val) \ + do { \ + var = (var & ~IO_MASK_(reg##_, field##_)) | \ + IO_FIELD_(reg##_, field##_, val); \ + } while (0) + +#define SETS(var, reg, field, val) \ + do { \ + var = (var & ~IO_MASK_(reg##_, field##_)) | \ + IO_STATE_(reg##_, field##_, _##val); \ + } while (0) + +struct sync_port { + /* Etrax registers and bits*/ + const volatile unsigned *const status; + volatile unsigned *const ctrl_data; + volatile unsigned *const output_dma_first; + volatile unsigned char *const output_dma_cmd; + volatile unsigned char *const output_dma_clr_irq; + volatile unsigned *const input_dma_first; + volatile unsigned char *const input_dma_cmd; + volatile unsigned *const input_dma_descr; + /* 8*4 */ + volatile unsigned char *const input_dma_clr_irq; + volatile unsigned *const data_out; + const volatile unsigned *const data_in; + char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ + char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ + char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */ + + char output_dma_bit; /* In R_IRQ_MASK2_RD */ + /* End of fields initialised in array */ + char started; /* 1 if port has been started */ + char port_nbr; /* Port 0 or 1 */ + char busy; /* 1 if port is busy */ + + char enabled; /* 1 if port is enabled */ + char use_dma; /* 1 if port uses dma */ + char tr_running; + + char init_irqs; + + /* Register shadow */ + unsigned int ctrl_data_shadow; + /* Remaining bytes for current transfer */ + volatile unsigned int out_count; + /* Current position in out_buffer */ + unsigned char *outp; + /* 16*4 */ + /* Next byte to be read by application */ + volatile unsigned char *volatile readp; + /* Next byte to be written by etrax */ + volatile unsigned char *volatile writep; + + unsigned int in_buffer_size; + unsigned int inbufchunk; + struct etrax_dma_descr out_descr __attribute__ ((aligned(32))); + struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32))); + unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32))); + unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32))); + unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32))); + struct etrax_dma_descr *next_rx_desc; + struct etrax_dma_descr *prev_rx_desc; + int full; + + wait_queue_head_t out_wait_q; + wait_queue_head_t in_wait_q; +}; + + +static DEFINE_MUTEX(sync_serial_mutex); +static int etrax_sync_serial_init(void); +static void initialize_port(int portnbr); +static inline int sync_data_avail(struct sync_port *port); + +static int sync_serial_open(struct inode *inode, struct file *file); +static int sync_serial_release(struct inode *inode, struct file *file); +static unsigned int sync_serial_poll(struct file *filp, poll_table *wait); + +static long sync_serial_ioctl(struct file *file, + unsigned int cmd, unsigned long arg); +static ssize_t sync_serial_write(struct file *file, const char *buf, + size_t count, loff_t *ppos); +static ssize_t sync_serial_read(struct file *file, char *buf, + size_t count, loff_t *ppos); + +#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ + defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ + (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ + defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) +#define SYNC_SER_DMA +#endif + +static void send_word(struct sync_port *port); +static void start_dma(struct sync_port *port, const char *data, int count); +static void start_dma_in(struct sync_port *port); +#ifdef SYNC_SER_DMA +static irqreturn_t tr_interrupt(int irq, void *dev_id); +static irqreturn_t rx_interrupt(int irq, void *dev_id); +#endif +#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ + !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ + (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ + !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) +#define SYNC_SER_MANUAL +#endif +#ifdef SYNC_SER_MANUAL +static irqreturn_t manual_interrupt(int irq, void *dev_id); +#endif + +/* The ports */ +static struct sync_port ports[] = { + { + .status = R_SYNC_SERIAL1_STATUS, + .ctrl_data = R_SYNC_SERIAL1_CTRL, + .output_dma_first = R_DMA_CH8_FIRST, + .output_dma_cmd = R_DMA_CH8_CMD, + .output_dma_clr_irq = R_DMA_CH8_CLR_INTR, + .input_dma_first = R_DMA_CH9_FIRST, + .input_dma_cmd = R_DMA_CH9_CMD, + .input_dma_descr = R_DMA_CH9_DESCR, + .input_dma_clr_irq = R_DMA_CH9_CLR_INTR, + .data_out = R_SYNC_SERIAL1_TR_DATA, + .data_in = R_SYNC_SERIAL1_REC_DATA, + .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data), + .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready), + .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr), + .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop), + .init_irqs = 1, +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) + .use_dma = 1, +#else + .use_dma = 0, +#endif + }, + { + .status = R_SYNC_SERIAL3_STATUS, + .ctrl_data = R_SYNC_SERIAL3_CTRL, + .output_dma_first = R_DMA_CH4_FIRST, + .output_dma_cmd = R_DMA_CH4_CMD, + .output_dma_clr_irq = R_DMA_CH4_CLR_INTR, + .input_dma_first = R_DMA_CH5_FIRST, + .input_dma_cmd = R_DMA_CH5_CMD, + .input_dma_descr = R_DMA_CH5_DESCR, + .input_dma_clr_irq = R_DMA_CH5_CLR_INTR, + .data_out = R_SYNC_SERIAL3_TR_DATA, + .data_in = R_SYNC_SERIAL3_REC_DATA, + .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data), + .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready), + .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr), + .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop), + .init_irqs = 1, +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) + .use_dma = 1, +#else + .use_dma = 0, +#endif + } +}; + +/* Register shadows */ +static unsigned sync_serial_prescale_shadow; + +#define NUMBER_OF_PORTS 2 + +static const struct file_operations sync_serial_fops = { + .owner = THIS_MODULE, + .write = sync_serial_write, + .read = sync_serial_read, + .poll = sync_serial_poll, + .unlocked_ioctl = sync_serial_ioctl, + .open = sync_serial_open, + .release = sync_serial_release, + .llseek = noop_llseek, +}; + +static int __init etrax_sync_serial_init(void) +{ + ports[0].enabled = 0; + ports[1].enabled = 0; + +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) + if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) { + printk(KERN_CRIT "ETRAX100LX sync_serial: " + "Could not allocate IO group for port %d\n", 0); + return -EBUSY; + } +#endif +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) + if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) { +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) + cris_free_io_interface(if_sync_serial_1); +#endif + printk(KERN_CRIT "ETRAX100LX sync_serial: " + "Could not allocate IO group for port %d\n", 1); + return -EBUSY; + } +#endif + + if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial", + &sync_serial_fops) < 0) { +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) + cris_free_io_interface(if_sync_serial_3); +#endif +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) + cris_free_io_interface(if_sync_serial_1); +#endif + printk("unable to get major for synchronous serial port\n"); + return -EBUSY; + } + + /* Deselect synchronous serial ports while configuring. */ + SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); + SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); + *R_GEN_CONFIG_II = gen_config_ii_shadow; + + /* Initialize Ports */ +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) + ports[0].enabled = 1; + SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra); + SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) + ports[0].use_dma = 1; +#else + ports[0].use_dma = 0; +#endif + initialize_port(0); +#endif + +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) + ports[1].enabled = 1; + SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra); + SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) + ports[1].use_dma = 1; +#else + ports[1].use_dma = 0; +#endif + initialize_port(1); +#endif + + *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */ + + /* Set up timing */ + *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = ( + IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) | + IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) | + IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) | + IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) | + IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) | + IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate, + DEFAULT_FRAME_RATE) | + IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) | + IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal)); + + /* Select synchronous ports */ + *R_GEN_CONFIG_II = gen_config_ii_shadow; + + printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n"); + return 0; +} + +static void __init initialize_port(int portnbr) +{ + struct sync_port *port = &ports[portnbr]; + + DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr)); + + port->started = 0; + port->port_nbr = portnbr; + port->busy = 0; + port->tr_running = 0; + + port->out_count = 0; + port->outp = port->out_buffer; + + port->readp = port->flip; + port->writep = port->flip; + port->in_buffer_size = IN_BUFFER_SIZE; + port->inbufchunk = IN_DESCR_SIZE; + port->next_rx_desc = &port->in_descr[0]; + port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1]; + port->prev_rx_desc->ctrl = d_eol; + + init_waitqueue_head(&port->out_wait_q); + init_waitqueue_head(&port->in_wait_q); + + port->ctrl_data_shadow = + IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) | + IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) | + IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) | + IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) | + IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) | + IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) | + IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) | + IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) | + IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) | + IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) | + IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) | + IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) | + IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) | + IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) | + IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) | + IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) | + IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)| + IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)| + IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) | + IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) | + IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)| + IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high); + + if (port->use_dma) + port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, + dma_enable, on); + else + port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, + dma_enable, off); + + *port->ctrl_data = port->ctrl_data_shadow; +} + +static inline int sync_data_avail(struct sync_port *port) +{ + int avail; + unsigned char *start; + unsigned char *end; + + start = (unsigned char *)port->readp; /* cast away volatile */ + end = (unsigned char *)port->writep; /* cast away volatile */ + /* 0123456789 0123456789 + * ----- - ----- + * ^rp ^wp ^wp ^rp + */ + if (end >= start) + avail = end - start; + else + avail = port->in_buffer_size - (start - end); + return avail; +} + +static inline int sync_data_avail_to_end(struct sync_port *port) +{ + int avail; + unsigned char *start; + unsigned char *end; + + start = (unsigned char *)port->readp; /* cast away volatile */ + end = (unsigned char *)port->writep; /* cast away volatile */ + /* 0123456789 0123456789 + * ----- ----- + * ^rp ^wp ^wp ^rp + */ + + if (end >= start) + avail = end - start; + else + avail = port->flip + port->in_buffer_size - start; + return avail; +} + + +static int sync_serial_open(struct inode *inode, struct file *file) +{ + int dev = MINOR(inode->i_rdev); + struct sync_port *port; + int mode; + int err = -EBUSY; + + mutex_lock(&sync_serial_mutex); + DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev)); + + if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { + DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); + err = -ENODEV; + goto out; + } + port = &ports[dev]; + /* Allow open this device twice (assuming one reader and one writer) */ + if (port->busy == 2) { + DEBUG(printk(KERN_DEBUG "Device is busy.. \n")); + goto out; + } + if (port->init_irqs) { + if (port->use_dma) { + if (port == &ports[0]) { +#ifdef SYNC_SER_DMA + if (request_irq(24, tr_interrupt, 0, + "synchronous serial 1 dma tr", + &ports[0])) { + printk(KERN_CRIT "Can't alloc " + "sync serial port 1 IRQ"); + goto out; + } else if (request_irq(25, rx_interrupt, 0, + "synchronous serial 1 dma rx", + &ports[0])) { + free_irq(24, &port[0]); + printk(KERN_CRIT "Can't alloc " + "sync serial port 1 IRQ"); + goto out; + } else if (cris_request_dma(8, + "synchronous serial 1 dma tr", + DMA_VERBOSE_ON_ERROR, + dma_ser1)) { + free_irq(24, &port[0]); + free_irq(25, &port[0]); + printk(KERN_CRIT "Can't alloc " + "sync serial port 1 " + "TX DMA channel"); + goto out; + } else if (cris_request_dma(9, + "synchronous serial 1 dma rec", + DMA_VERBOSE_ON_ERROR, + dma_ser1)) { + cris_free_dma(8, NULL); + free_irq(24, &port[0]); + free_irq(25, &port[0]); + printk(KERN_CRIT "Can't alloc " + "sync serial port 1 " + "RX DMA channel"); + goto out; + } +#endif + RESET_DMA(8); WAIT_DMA(8); + RESET_DMA(9); WAIT_DMA(9); + *R_DMA_CH8_CLR_INTR = + IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, + do) | + IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, + do); + *R_DMA_CH9_CLR_INTR = + IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, + do) | + IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, + do); + *R_IRQ_MASK2_SET = + IO_STATE(R_IRQ_MASK2_SET, dma8_eop, + set) | + IO_STATE(R_IRQ_MASK2_SET, dma9_descr, + set); + } else if (port == &ports[1]) { +#ifdef SYNC_SER_DMA + if (request_irq(20, tr_interrupt, 0, + "synchronous serial 3 dma tr", + &ports[1])) { + printk(KERN_CRIT "Can't alloc " + "sync serial port 3 IRQ"); + goto out; + } else if (request_irq(21, rx_interrupt, 0, + "synchronous serial 3 dma rx", + &ports[1])) { + free_irq(20, &ports[1]); + printk(KERN_CRIT "Can't alloc " + "sync serial port 3 IRQ"); + goto out; + } else if (cris_request_dma(4, + "synchronous serial 3 dma tr", + DMA_VERBOSE_ON_ERROR, + dma_ser3)) { + free_irq(21, &ports[1]); + free_irq(20, &ports[1]); + printk(KERN_CRIT "Can't alloc " + "sync serial port 3 " + "TX DMA channel"); + goto out; + } else if (cris_request_dma(5, + "synchronous serial 3 dma rec", + DMA_VERBOSE_ON_ERROR, + dma_ser3)) { + cris_free_dma(4, NULL); + free_irq(21, &ports[1]); + free_irq(20, &ports[1]); + printk(KERN_CRIT "Can't alloc " + "sync serial port 3 " + "RX DMA channel"); + goto out; + } +#endif + RESET_DMA(4); WAIT_DMA(4); + RESET_DMA(5); WAIT_DMA(5); + *R_DMA_CH4_CLR_INTR = + IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, + do) | + IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, + do); + *R_DMA_CH5_CLR_INTR = + IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, + do) | + IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, + do); + *R_IRQ_MASK2_SET = + IO_STATE(R_IRQ_MASK2_SET, dma4_eop, + set) | + IO_STATE(R_IRQ_MASK2_SET, dma5_descr, + set); + } + start_dma_in(port); + port->init_irqs = 0; + } else { /* !port->use_dma */ +#ifdef SYNC_SER_MANUAL + if (port == &ports[0]) { + if (request_irq(8, + manual_interrupt, + IRQF_SHARED, + "synchronous serial manual irq", + &ports[0])) { + printk(KERN_CRIT "Can't alloc " + "sync serial manual irq"); + goto out; + } + } else if (port == &ports[1]) { + if (request_irq(8, + manual_interrupt, + IRQF_SHARED, + "synchronous serial manual irq", + &ports[1])) { + printk(KERN_CRIT "Can't alloc " + "sync serial manual irq"); + goto out; + } + } + port->init_irqs = 0; +#else + panic("sync_serial: Manual mode not supported.\n"); +#endif /* SYNC_SER_MANUAL */ + } + } /* port->init_irqs */ + + port->busy++; + /* Start port if we use it as input */ + mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow); + if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) || + mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) || + mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) || + mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) { + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, + running); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, + enable); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, + enable); + port->started = 1; + *port->ctrl_data = port->ctrl_data_shadow; + if (!port->use_dma) + *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; + DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev)); + } + err = 0; + +out: + mutex_unlock(&sync_serial_mutex); + return err; +} + +static int sync_serial_release(struct inode *inode, struct file *file) +{ + int dev = MINOR(inode->i_rdev); + struct sync_port *port; + + if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { + DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); + return -ENODEV; + } + port = &ports[dev]; + if (port->busy) + port->busy--; + if (!port->busy) + *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) | + (1 << port->transmitter_ready_bit)); + + return 0; +} + + + +static unsigned int sync_serial_poll(struct file *file, poll_table *wait) +{ + int dev = MINOR(file_inode(file)->i_rdev); + unsigned int mask = 0; + struct sync_port *port; + DEBUGPOLL(static unsigned int prev_mask = 0); + + port = &ports[dev]; + poll_wait(file, &port->out_wait_q, wait); + poll_wait(file, &port->in_wait_q, wait); + /* Some room to write */ + if (port->out_count < OUT_BUFFER_SIZE) + mask |= POLLOUT | POLLWRNORM; + /* At least an inbufchunk of data */ + if (sync_data_avail(port) >= port->inbufchunk) + mask |= POLLIN | POLLRDNORM; + + DEBUGPOLL(if (mask != prev_mask) + printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n", + mask, + mask & POLLOUT ? "POLLOUT" : "", + mask & POLLIN ? "POLLIN" : ""); + prev_mask = mask; + ); + return mask; +} + +static int sync_serial_ioctl_unlocked(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int return_val = 0; + unsigned long flags; + + int dev = MINOR(file_inode(file)->i_rdev); + struct sync_port *port; + + if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { + DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); + return -1; + } + port = &ports[dev]; + + local_irq_save(flags); + /* Disable port while changing config */ + if (dev) { + if (port->use_dma) { + RESET_DMA(4); WAIT_DMA(4); + port->tr_running = 0; + port->out_count = 0; + port->outp = port->out_buffer; + *R_DMA_CH4_CLR_INTR = + IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) | + IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do); + } + SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); + } else { + if (port->use_dma) { + RESET_DMA(8); WAIT_DMA(8); + port->tr_running = 0; + port->out_count = 0; + port->outp = port->out_buffer; + *R_DMA_CH8_CLR_INTR = + IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) | + IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do); + } + SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); + } + *R_GEN_CONFIG_II = gen_config_ii_shadow; + local_irq_restore(flags); + + switch (cmd) { + case SSP_SPEED: + if (GET_SPEED(arg) == CODEC) { + if (dev) + SETS(sync_serial_prescale_shadow, + R_SYNC_SERIAL_PRESCALE, clk_sel_u3, + codec); + else + SETS(sync_serial_prescale_shadow, + R_SYNC_SERIAL_PRESCALE, clk_sel_u1, + codec); + + SETF(sync_serial_prescale_shadow, + R_SYNC_SERIAL_PRESCALE, prescaler, + GET_FREQ(arg)); + SETF(sync_serial_prescale_shadow, + R_SYNC_SERIAL_PRESCALE, frame_rate, + GET_FRAME_RATE(arg)); + SETF(sync_serial_prescale_shadow, + R_SYNC_SERIAL_PRESCALE, word_rate, + GET_WORD_RATE(arg)); + } else { + SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + tr_baud, GET_SPEED(arg)); + if (dev) + SETS(sync_serial_prescale_shadow, + R_SYNC_SERIAL_PRESCALE, clk_sel_u3, + baudrate); + else + SETS(sync_serial_prescale_shadow, + R_SYNC_SERIAL_PRESCALE, clk_sel_u1, + baudrate); + } + break; + case SSP_MODE: + if (arg > 5) + return -EINVAL; + if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT) + *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit; + else if (!port->use_dma) + *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; + SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg); + break; + case SSP_FRAME_SYNC: + if (arg & NORMAL_SYNC) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + f_synctype, normal); + else if (arg & EARLY_SYNC) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + f_synctype, early); + + if (arg & BIT_SYNC) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + f_syncsize, bit); + else if (arg & WORD_SYNC) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + f_syncsize, word); + else if (arg & EXTENDED_SYNC) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + f_syncsize, extended); + + if (arg & SYNC_ON) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + f_sync, on); + else if (arg & SYNC_OFF) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + f_sync, off); + + if (arg & WORD_SIZE_8) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + wordsize, size8bit); + else if (arg & WORD_SIZE_12) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + wordsize, size12bit); + else if (arg & WORD_SIZE_16) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + wordsize, size16bit); + else if (arg & WORD_SIZE_24) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + wordsize, size24bit); + else if (arg & WORD_SIZE_32) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + wordsize, size32bit); + + if (arg & BIT_ORDER_MSB) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + bitorder, msb); + else if (arg & BIT_ORDER_LSB) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + bitorder, lsb); + + if (arg & FLOW_CONTROL_ENABLE) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + flow_ctrl, enabled); + else if (arg & FLOW_CONTROL_DISABLE) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + flow_ctrl, disabled); + + if (arg & CLOCK_NOT_GATED) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + clk_mode, normal); + else if (arg & CLOCK_GATED) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + clk_mode, gated); + + break; + case SSP_IPOLARITY: + /* NOTE!! negedge is considered NORMAL */ + if (arg & CLOCK_NORMAL) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + clk_polarity, neg); + else if (arg & CLOCK_INVERT) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + clk_polarity, pos); + + if (arg & FRAME_NORMAL) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + frame_polarity, normal); + else if (arg & FRAME_INVERT) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + frame_polarity, inverted); + + if (arg & STATUS_NORMAL) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + status_polarity, normal); + else if (arg & STATUS_INVERT) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + status_polarity, inverted); + break; + case SSP_OPOLARITY: + if (arg & CLOCK_NORMAL) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + clk_driver, normal); + else if (arg & CLOCK_INVERT) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + clk_driver, inverted); + + if (arg & FRAME_NORMAL) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + frame_driver, normal); + else if (arg & FRAME_INVERT) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + frame_driver, inverted); + + if (arg & STATUS_NORMAL) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + status_driver, normal); + else if (arg & STATUS_INVERT) + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + status_driver, inverted); + break; + case SSP_SPI: + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, + disabled); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, + msb); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, + size8bit); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, + word); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, + normal); + if (arg & SPI_SLAVE) { + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + frame_polarity, inverted); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + clk_polarity, neg); + SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + mode, SLAVE_INPUT); + } else { + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + frame_driver, inverted); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + clk_driver, inverted); + SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, + mode, MASTER_OUTPUT); + } + break; + case SSP_INBUFCHUNK: +#if 0 + if (arg > port->in_buffer_size/NUM_IN_DESCR) + return -EINVAL; + port->inbufchunk = arg; + /* Make sure in_buffer_size is a multiple of inbufchunk */ + port->in_buffer_size = + (port->in_buffer_size/port->inbufchunk) * + port->inbufchunk; + DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n", + port->inbufchunk, port->in_buffer_size)); + if (port->use_dma) { + if (port->port_nbr == 0) { + RESET_DMA(9); + WAIT_DMA(9); + } else { + RESET_DMA(5); + WAIT_DMA(5); + } + start_dma_in(port); + } +#endif + break; + default: + return_val = -1; + } + /* Make sure we write the config without interruption */ + local_irq_save(flags); + /* Set config and enable port */ + *port->ctrl_data = port->ctrl_data_shadow; + nop(); nop(); nop(); nop(); + *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow; + nop(); nop(); nop(); nop(); + if (dev) + SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); + else + SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); + + *R_GEN_CONFIG_II = gen_config_ii_shadow; + /* Reset DMA. At readout from serial port the data could be shifted + * one byte if not resetting DMA. + */ + if (port->use_dma) { + if (port->port_nbr == 0) { + RESET_DMA(9); + WAIT_DMA(9); + } else { + RESET_DMA(5); + WAIT_DMA(5); + } + start_dma_in(port); + } + local_irq_restore(flags); + return return_val; +} + +static long sync_serial_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + long ret; + + mutex_lock(&sync_serial_mutex); + ret = sync_serial_ioctl_unlocked(file, cmd, arg); + mutex_unlock(&sync_serial_mutex); + + return ret; +} + + +static ssize_t sync_serial_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + int dev = MINOR(file_inode(file)->i_rdev); + DECLARE_WAITQUEUE(wait, current); + struct sync_port *port; + unsigned long flags; + unsigned long c, c1; + unsigned long free_outp; + unsigned long outp; + unsigned long out_buffer; + + if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { + DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); + return -ENODEV; + } + port = &ports[dev]; + + DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n", + port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE)); + /* Space to end of buffer */ + /* + * out_buffer 012345<- c ->OUT_BUFFER_SIZE + * outp^ +out_count + * ^free_outp + * out_buffer 45<- c ->0123OUT_BUFFER_SIZE + * +out_count outp^ + * free_outp + * + */ + + /* Read variables that may be updated by interrupts */ + local_irq_save(flags); + if (count > OUT_BUFFER_SIZE - port->out_count) + count = OUT_BUFFER_SIZE - port->out_count; + + outp = (unsigned long)port->outp; + free_outp = outp + port->out_count; + local_irq_restore(flags); + out_buffer = (unsigned long)port->out_buffer; + + /* Find out where and how much to write */ + if (free_outp >= out_buffer + OUT_BUFFER_SIZE) + free_outp -= OUT_BUFFER_SIZE; + if (free_outp >= outp) + c = out_buffer + OUT_BUFFER_SIZE - free_outp; + else + c = outp - free_outp; + if (c > count) + c = count; + + DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n", + outp, free_outp, c)); + if (copy_from_user((void *)free_outp, buf, c)) + return -EFAULT; + + if (c != count) { + buf += c; + c1 = count - c; + DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n", + free_outp-out_buffer, c, c1)); + if (copy_from_user((void *)out_buffer, buf, c1)) + return -EFAULT; + } + local_irq_save(flags); + port->out_count += count; + local_irq_restore(flags); + + /* Make sure transmitter/receiver is running */ + if (!port->started) { + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, + running); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, + enable); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, + enable); + port->started = 1; + } + + *port->ctrl_data = port->ctrl_data_shadow; + + if (file->f_flags & O_NONBLOCK) { + local_irq_save(flags); + if (!port->tr_running) { + if (!port->use_dma) { + /* Start sender by writing data */ + send_word(port); + /* and enable transmitter ready IRQ */ + *R_IRQ_MASK1_SET = 1 << + port->transmitter_ready_bit; + } else + start_dma(port, + (unsigned char *volatile)port->outp, c); + } + local_irq_restore(flags); + DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n", + port->port_nbr, count)); + return count; + } + + /* Sleep until all sent */ + add_wait_queue(&port->out_wait_q, &wait); + set_current_state(TASK_INTERRUPTIBLE); + local_irq_save(flags); + if (!port->tr_running) { + if (!port->use_dma) { + /* Start sender by writing data */ + send_word(port); + /* and enable transmitter ready IRQ */ + *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit; + } else + start_dma(port, port->outp, c); + } + local_irq_restore(flags); + schedule(); + remove_wait_queue(&port->out_wait_q, &wait); + if (signal_pending(current)) + return -EINTR; + + DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count)); + return count; +} + +static ssize_t sync_serial_read(struct file *file, char *buf, + size_t count, loff_t *ppos) +{ + int dev = MINOR(file_inode(file)->i_rdev); + int avail; + struct sync_port *port; + unsigned char *start; + unsigned char *end; + unsigned long flags; + + if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { + DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); + return -ENODEV; + } + port = &ports[dev]; + + DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n", + dev, count, port->readp - port->flip, + port->writep - port->flip, port->in_buffer_size)); + + if (!port->started) { + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, + running); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, + enable); + SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, + enable); + port->started = 1; + } + *port->ctrl_data = port->ctrl_data_shadow; + + /* Calculate number of available bytes */ + /* Save pointers to avoid that they are modified by interrupt */ + local_irq_save(flags); + start = (unsigned char *)port->readp; /* cast away volatile */ + end = (unsigned char *)port->writep; /* cast away volatile */ + local_irq_restore(flags); + while (start == end && !port->full) { + /* No data */ + if (file->f_flags & O_NONBLOCK) + return -EAGAIN; + + wait_event_interruptible(port->in_wait_q, + !(start == end && !port->full)); + if (signal_pending(current)) + return -EINTR; + + local_irq_save(flags); + start = (unsigned char *)port->readp; /* cast away volatile */ + end = (unsigned char *)port->writep; /* cast away volatile */ + local_irq_restore(flags); + } + + /* Lazy read, never return wrapped data. */ + if (port->full) + avail = port->in_buffer_size; + else if (end > start) + avail = end - start; + else + avail = port->flip + port->in_buffer_size - start; + + count = count > avail ? avail : count; + if (copy_to_user(buf, start, count)) + return -EFAULT; + /* Disable interrupts while updating readp */ + local_irq_save(flags); + port->readp += count; + if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ + port->readp = port->flip; + port->full = 0; + local_irq_restore(flags); + DEBUGREAD(printk(KERN_DEBUG "r %d\n", count)); + return count; +} + +static void send_word(struct sync_port *port) +{ + switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize, + port->ctrl_data_shadow)) { + case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): + port->out_count--; + *port->data_out = *port->outp++; + if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) + port->outp = port->out_buffer; + break; + case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): + { + int data = (*port->outp++) << 8; + data |= *port->outp++; + port->out_count -= 2; + *port->data_out = data; + if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) + port->outp = port->out_buffer; + break; + } + case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): + port->out_count -= 2; + *port->data_out = *(unsigned short *)port->outp; + port->outp += 2; + if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) + port->outp = port->out_buffer; + break; + case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): + port->out_count -= 3; + *port->data_out = *(unsigned int *)port->outp; + port->outp += 3; + if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) + port->outp = port->out_buffer; + break; + case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): + port->out_count -= 4; + *port->data_out = *(unsigned int *)port->outp; + port->outp += 4; + if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) + port->outp = port->out_buffer; + break; + } +} + + +static void start_dma(struct sync_port *port, const char *data, int count) +{ + port->tr_running = 1; + port->out_descr.hw_len = 0; + port->out_descr.next = 0; + port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */ + port->out_descr.sw_len = count; + port->out_descr.buf = virt_to_phys(data); + port->out_descr.status = 0; + + *port->output_dma_first = virt_to_phys(&port->out_descr); + *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); + DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n", + (unsigned long)data, count)); +} + +static void start_dma_in(struct sync_port *port) +{ + int i; + unsigned long buf; + port->writep = port->flip; + + if (port->writep > port->flip + port->in_buffer_size) { + panic("Offset too large in sync serial driver\n"); + return; + } + buf = virt_to_phys(port->in_buffer); + for (i = 0; i < NUM_IN_DESCR; i++) { + port->in_descr[i].sw_len = port->inbufchunk; + port->in_descr[i].ctrl = d_int; + port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]); + port->in_descr[i].buf = buf; + port->in_descr[i].hw_len = 0; + port->in_descr[i].status = 0; + port->in_descr[i].fifo_len = 0; + buf += port->inbufchunk; + prepare_rx_descriptor(&port->in_descr[i]); + } + /* Link the last descriptor to the first */ + port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]); + port->in_descr[i-1].ctrl |= d_eol; + port->next_rx_desc = &port->in_descr[0]; + port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1]; + *port->input_dma_first = virt_to_phys(port->next_rx_desc); + *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); +} + +#ifdef SYNC_SER_DMA +static irqreturn_t tr_interrupt(int irq, void *dev_id) +{ + unsigned long ireg = *R_IRQ_MASK2_RD; + struct etrax_dma_descr *descr; + unsigned int sentl; + int handled = 0; + int i; + + for (i = 0; i < NUMBER_OF_PORTS; i++) { + struct sync_port *port = &ports[i]; + if (!port->enabled || !port->use_dma) + continue; + + /* IRQ active for the port? */ + if (!(ireg & (1 << port->output_dma_bit))) + continue; + + handled = 1; + + /* Clear IRQ */ + *port->output_dma_clr_irq = + IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) | + IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do); + + descr = &port->out_descr; + if (!(descr->status & d_stop)) + sentl = descr->sw_len; + else + /* Otherwise find amount of data sent here */ + sentl = descr->hw_len; + + port->out_count -= sentl; + port->outp += sentl; + if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) + port->outp = port->out_buffer; + if (port->out_count) { + int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp; + if (c > port->out_count) + c = port->out_count; + DEBUGTXINT(printk(KERN_DEBUG + "tx_int DMAWRITE %i %i\n", sentl, c)); + start_dma(port, port->outp, c); + } else { + DEBUGTXINT(printk(KERN_DEBUG + "tx_int DMA stop %i\n", sentl)); + port->tr_running = 0; + } + /* wake up the waiting process */ + wake_up_interruptible(&port->out_wait_q); + } + return IRQ_RETVAL(handled); +} /* tr_interrupt */ + +static irqreturn_t rx_interrupt(int irq, void *dev_id) +{ + unsigned long ireg = *R_IRQ_MASK2_RD; + int i; + int handled = 0; + + for (i = 0; i < NUMBER_OF_PORTS; i++) { + struct sync_port *port = &ports[i]; + + if (!port->enabled || !port->use_dma) + continue; + + if (!(ireg & (1 << port->input_dma_descr_bit))) + continue; + + /* Descriptor interrupt */ + handled = 1; + while (*port->input_dma_descr != + virt_to_phys(port->next_rx_desc)) { + if (port->writep + port->inbufchunk > port->flip + + port->in_buffer_size) { + int first_size = port->flip + + port->in_buffer_size - port->writep; + memcpy(port->writep, + phys_to_virt(port->next_rx_desc->buf), + first_size); + memcpy(port->flip, + phys_to_virt(port->next_rx_desc->buf + + first_size), + port->inbufchunk - first_size); + port->writep = port->flip + + port->inbufchunk - first_size; + } else { + memcpy(port->writep, + phys_to_virt(port->next_rx_desc->buf), + port->inbufchunk); + port->writep += port->inbufchunk; + if (port->writep >= port->flip + + port->in_buffer_size) + port->writep = port->flip; + } + if (port->writep == port->readp) + port->full = 1; + prepare_rx_descriptor(port->next_rx_desc); + port->next_rx_desc->ctrl |= d_eol; + port->prev_rx_desc->ctrl &= ~d_eol; + port->prev_rx_desc = phys_to_virt((unsigned) + port->next_rx_desc); + port->next_rx_desc = phys_to_virt((unsigned) + port->next_rx_desc->next); + /* Wake up the waiting process */ + wake_up_interruptible(&port->in_wait_q); + *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD, + cmd, restart); + /* DMA has reached end of descriptor */ + *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR, + clr_descr, do); + } + } + return IRQ_RETVAL(handled); +} /* rx_interrupt */ +#endif /* SYNC_SER_DMA */ + +#ifdef SYNC_SER_MANUAL +static irqreturn_t manual_interrupt(int irq, void *dev_id) +{ + int i; + int handled = 0; + + for (i = 0; i < NUMBER_OF_PORTS; i++) { + struct sync_port *port = &ports[i]; + + if (!port->enabled || port->use_dma) + continue; + + /* Data received? */ + if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) { + handled = 1; + /* Read data */ + switch (port->ctrl_data_shadow & + IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) { + case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): + *port->writep++ = + *(volatile char *)port->data_in; + break; + case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): + { + int data = *(unsigned short *)port->data_in; + *port->writep = (data & 0x0ff0) >> 4; + *(port->writep + 1) = data & 0x0f; + port->writep += 2; + break; + } + case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): + *(unsigned short *)port->writep = + *(volatile unsigned short *)port->data_in; + port->writep += 2; + break; + case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): + *(unsigned int *)port->writep = *port->data_in; + port->writep += 3; + break; + case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): + *(unsigned int *)port->writep = *port->data_in; + port->writep += 4; + break; + } + + /* Wrap? */ + if (port->writep >= port->flip + port->in_buffer_size) + port->writep = port->flip; + if (port->writep == port->readp) { + /* Receive buffer overrun, discard oldest */ + port->readp++; + /* Wrap? */ + if (port->readp >= port->flip + + port->in_buffer_size) + port->readp = port->flip; + } + if (sync_data_avail(port) >= port->inbufchunk) { + /* Wake up application */ + wake_up_interruptible(&port->in_wait_q); + } + } + + /* Transmitter ready? */ + if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) { + if (port->out_count > 0) { + /* More data to send */ + send_word(port); + } else { + /* Transmission finished */ + /* Turn off IRQ */ + *R_IRQ_MASK1_CLR = 1 << + port->transmitter_ready_bit; + /* Wake up application */ + wake_up_interruptible(&port->out_wait_q); + } + } + } + return IRQ_RETVAL(handled); +} +#endif + +module_init(etrax_sync_serial_init); diff --git a/kernel/arch/cris/arch-v10/kernel/Makefile b/kernel/arch/cris/arch-v10/kernel/Makefile new file mode 100644 index 000000000..4841e822c --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/Makefile @@ -0,0 +1,17 @@ +# +# Makefile for the linux kernel. +# + +extra-y := head.o + + +obj-y := entry.o traps.o shadows.o debugport.o irq.o \ + process.o setup.o signal.o traps.o time.o ptrace.o \ + dma.o io_interface_mux.o + +obj-$(CONFIG_ETRAX_KGDB) += kgdb.o +obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o +obj-$(CONFIG_MODULES) += crisksyms.o + +clean: + diff --git a/kernel/arch/cris/arch-v10/kernel/crisksyms.c b/kernel/arch/cris/arch-v10/kernel/crisksyms.c new file mode 100644 index 000000000..1ca6fc283 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/crisksyms.c @@ -0,0 +1,16 @@ +#include +#include +#include + +/* Export shadow registers for the CPU I/O pins */ +EXPORT_SYMBOL(genconfig_shadow); +EXPORT_SYMBOL(port_pa_data_shadow); +EXPORT_SYMBOL(port_pa_dir_shadow); +EXPORT_SYMBOL(port_pb_data_shadow); +EXPORT_SYMBOL(port_pb_dir_shadow); +EXPORT_SYMBOL(port_pb_config_shadow); +EXPORT_SYMBOL(port_g_data_shadow); + +/* Cache flush functions */ +EXPORT_SYMBOL(flush_etrax_cache); +EXPORT_SYMBOL(prepare_rx_descriptor); diff --git a/kernel/arch/cris/arch-v10/kernel/debugport.c b/kernel/arch/cris/arch-v10/kernel/debugport.c new file mode 100644 index 000000000..7d307cce8 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/debugport.c @@ -0,0 +1,559 @@ +/* Serialport functions for debugging + * + * Copyright (c) 2000-2007 Axis Communications AB + * + * Authors: Bjorn Wesen + * + * Exports: + * console_print_etrax(char *buf) + * int getDebugChar() + * putDebugChar(int) + * enableDebugIRQ() + * init_etrax_debug() + * + */ + +#include +#include +#include +#include +#include +#include + +extern void reset_watchdog(void); + +struct dbg_port +{ + unsigned int index; + const volatile unsigned* read; + volatile char* write; + volatile unsigned* xoff; + volatile char* baud; + volatile char* tr_ctrl; + volatile char* rec_ctrl; + unsigned long irq; + unsigned int started; + unsigned long baudrate; + unsigned char parity; + unsigned int bits; +}; + +struct dbg_port ports[]= +{ + { + 0, + R_SERIAL0_READ, + R_SERIAL0_TR_DATA, + R_SERIAL0_XOFF, + R_SERIAL0_BAUD, + R_SERIAL0_TR_CTRL, + R_SERIAL0_REC_CTRL, + IO_STATE(R_IRQ_MASK1_SET, ser0_data, set), + 0, + 115200, + 'N', + 8 + }, + { + 1, + R_SERIAL1_READ, + R_SERIAL1_TR_DATA, + R_SERIAL1_XOFF, + R_SERIAL1_BAUD, + R_SERIAL1_TR_CTRL, + R_SERIAL1_REC_CTRL, + IO_STATE(R_IRQ_MASK1_SET, ser1_data, set), + 0, + 115200, + 'N', + 8 + }, + { + 2, + R_SERIAL2_READ, + R_SERIAL2_TR_DATA, + R_SERIAL2_XOFF, + R_SERIAL2_BAUD, + R_SERIAL2_TR_CTRL, + R_SERIAL2_REC_CTRL, + IO_STATE(R_IRQ_MASK1_SET, ser2_data, set), + 0, + 115200, + 'N', + 8 + }, + { + 3, + R_SERIAL3_READ, + R_SERIAL3_TR_DATA, + R_SERIAL3_XOFF, + R_SERIAL3_BAUD, + R_SERIAL3_TR_CTRL, + R_SERIAL3_REC_CTRL, + IO_STATE(R_IRQ_MASK1_SET, ser3_data, set), + 0, + 115200, + 'N', + 8 + } +}; + +#ifdef CONFIG_ETRAX_SERIAL +extern struct tty_driver *serial_driver; +#endif + +struct dbg_port* port = +#if defined(CONFIG_ETRAX_DEBUG_PORT0) + &ports[0]; +#elif defined(CONFIG_ETRAX_DEBUG_PORT1) + &ports[1]; +#elif defined(CONFIG_ETRAX_DEBUG_PORT2) + &ports[2]; +#elif defined(CONFIG_ETRAX_DEBUG_PORT3) + &ports[3]; +#else + NULL; +#endif + +static struct dbg_port* kgdb_port = +#if defined(CONFIG_ETRAX_KGDB_PORT0) + &ports[0]; +#elif defined(CONFIG_ETRAX_KGDB_PORT1) + &ports[1]; +#elif defined(CONFIG_ETRAX_KGDB_PORT2) + &ports[2]; +#elif defined(CONFIG_ETRAX_KGDB_PORT3) + &ports[3]; +#else + NULL; +#endif + +static void +start_port(struct dbg_port* p) +{ + unsigned long rec_ctrl = 0; + unsigned long tr_ctrl = 0; + + if (!p) + return; + + if (p->started) + return; + p->started = 1; + + if (p->index == 0) + { + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6); + genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused); + } + else if (p->index == 1) + { + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8); + genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb); + } + else if (p->index == 2) + { + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2); + genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0); + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3); + genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0); + genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser2, select); + } + else + { + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4); + genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1); + genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5); + genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1); + genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser3, select); + } + + *R_GEN_CONFIG = genconfig_shadow; + + *p->xoff = + IO_STATE(R_SERIAL0_XOFF, tx_stop, enable) | + IO_STATE(R_SERIAL0_XOFF, auto_xoff, disable) | + IO_FIELD(R_SERIAL0_XOFF, xoff_char, 0); + + switch (p->baudrate) + { + case 0: + case 115200: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); + break; + case 1200: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c1200Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c1200Hz); + break; + case 2400: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c2400Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c2400Hz); + break; + case 4800: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c4800Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c4800Hz); + break; + case 9600: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c9600Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c9600Hz); + break; + case 19200: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c19k2Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c19k2Hz); + break; + case 38400: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c38k4Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c38k4Hz); + break; + case 57600: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c57k6Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c57k6Hz); + break; + default: + *p->baud = + IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | + IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); + break; + } + + if (p->parity == 'E') { + rec_ctrl = + IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | + IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); + tr_ctrl = + IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | + IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); + } else if (p->parity == 'O') { + rec_ctrl = + IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd) | + IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); + tr_ctrl = + IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd) | + IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); + } else { + rec_ctrl = + IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | + IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, disable); + tr_ctrl = + IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | + IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, disable); + } + if (p->bits == 7) + { + rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit); + tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); + } + else + { + rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit); + tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit); + } + + *p->rec_ctrl = + IO_STATE(R_SERIAL0_REC_CTRL, dma_err, stop) | + IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable) | + IO_STATE(R_SERIAL0_REC_CTRL, rts_, active) | + IO_STATE(R_SERIAL0_REC_CTRL, sampling, middle) | + IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, normal) | + rec_ctrl; + + *p->tr_ctrl = + IO_FIELD(R_SERIAL0_TR_CTRL, txd, 0) | + IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable) | + IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, disabled) | + IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, one_bit) | + IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, normal) | + tr_ctrl; +} + +static void +console_write_direct(struct console *co, const char *buf, unsigned int len) +{ + int i; + unsigned long flags; + + if (!port) + return; + + local_irq_save(flags); + + /* Send data */ + for (i = 0; i < len; i++) { + /* LF -> CRLF */ + if (buf[i] == '\n') { + while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) + ; + *port->write = '\r'; + } + /* Wait until transmitter is ready and send.*/ + while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) + ; + *port->write = buf[i]; + } + + /* + * Feed the watchdog, otherwise it will reset the chip during boot. + * The time to send an ordinary boot message line (10-90 chars) + * varies between 1-8ms at 115200. What makes up for the additional + * 90ms that allows the watchdog to bite? + */ + reset_watchdog(); + + local_irq_restore(flags); +} + +static void +console_write(struct console *co, const char *buf, unsigned int len) +{ + if (!port) + return; + + console_write_direct(co, buf, len); +} + +/* legacy function */ + +void +console_print_etrax(const char *buf) +{ + console_write(NULL, buf, strlen(buf)); +} + +/* Use polling to get a single character FROM the debug port */ + +int +getDebugChar(void) +{ + unsigned long readval; + + if (!kgdb_port) + return 0; + + do { + readval = *kgdb_port->read; + } while (!(readval & IO_MASK(R_SERIAL0_READ, data_avail))); + + return (readval & IO_MASK(R_SERIAL0_READ, data_in)); +} + +/* Use polling to put a single character to the debug port */ + +void +putDebugChar(int val) +{ + if (!kgdb_port) + return; + + while (!(*kgdb_port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) + ; + *kgdb_port->write = val; +} + +/* Enable irq for receiving chars on the debug port, used by kgdb */ + +void +enableDebugIRQ(void) +{ + if (!kgdb_port) + return; + + *R_IRQ_MASK1_SET = kgdb_port->irq; + /* use R_VECT_MASK directly, since we really bypass Linux normal + * IRQ handling in kgdb anyway, we don't need to use enable_irq + */ + *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set); + + *kgdb_port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); +} + +static int __init +console_setup(struct console *co, char *options) +{ + char* s; + + if (options) { + port = &ports[co->index]; + port->baudrate = 115200; + port->parity = 'N'; + port->bits = 8; + port->baudrate = simple_strtoul(options, NULL, 10); + s = options; + while(*s >= '0' && *s <= '9') + s++; + if (*s) port->parity = *s++; + if (*s) port->bits = *s++ - '0'; + port->started = 0; + start_port(0); + } + return 0; +} + + +/* This is a dummy serial device that throws away anything written to it. + * This is used when no debug output is wanted. + */ +static struct tty_driver dummy_driver; + +static int dummy_open(struct tty_struct *tty, struct file * filp) +{ + return 0; +} + +static void dummy_close(struct tty_struct *tty, struct file * filp) +{ +} + +static int dummy_write(struct tty_struct * tty, + const unsigned char *buf, int count) +{ + return count; +} + +static int dummy_write_room(struct tty_struct *tty) +{ + return 8192; +} + +static const struct tty_operations dummy_ops = { + .open = dummy_open, + .close = dummy_close, + .write = dummy_write, + .write_room = dummy_write_room, +}; + +void __init +init_dummy_console(void) +{ + memset(&dummy_driver, 0, sizeof(struct tty_driver)); + dummy_driver.driver_name = "serial"; + dummy_driver.name = "ttyS"; + dummy_driver.major = TTY_MAJOR; + dummy_driver.minor_start = 68; + dummy_driver.num = 1; /* etrax100 has 4 serial ports */ + dummy_driver.type = TTY_DRIVER_TYPE_SERIAL; + dummy_driver.subtype = SERIAL_TYPE_NORMAL; + dummy_driver.init_termios = tty_std_termios; + /* Normally B9600 default... */ + dummy_driver.init_termios.c_cflag = + B115200 | CS8 | CREAD | HUPCL | CLOCAL; + dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; + dummy_driver.init_termios.c_ispeed = 115200; + dummy_driver.init_termios.c_ospeed = 115200; + + dummy_driver.ops = &dummy_ops; + if (tty_register_driver(&dummy_driver)) + panic("Couldn't register dummy serial driver\n"); +} + +static struct tty_driver* +etrax_console_device(struct console* co, int *index) +{ + if (port) + *index = port->index; + else + *index = 0; +#ifdef CONFIG_ETRAX_SERIAL + return port ? serial_driver : &dummy_driver; +#else + return &dummy_driver; +#endif +} + +static struct console sercons = { + name : "ttyS", + write: console_write, + read : NULL, + device : etrax_console_device, + unblank : NULL, + setup : console_setup, + flags : CON_PRINTBUFFER, + index : -1, + cflag : 0, + next : NULL +}; +static struct console sercons0 = { + name : "ttyS", + write: console_write, + read : NULL, + device : etrax_console_device, + unblank : NULL, + setup : console_setup, + flags : CON_PRINTBUFFER, + index : 0, + cflag : 0, + next : NULL +}; + +static struct console sercons1 = { + name : "ttyS", + write: console_write, + read : NULL, + device : etrax_console_device, + unblank : NULL, + setup : console_setup, + flags : CON_PRINTBUFFER, + index : 1, + cflag : 0, + next : NULL +}; +static struct console sercons2 = { + name : "ttyS", + write: console_write, + read : NULL, + device : etrax_console_device, + unblank : NULL, + setup : console_setup, + flags : CON_PRINTBUFFER, + index : 2, + cflag : 0, + next : NULL +}; +static struct console sercons3 = { + name : "ttyS", + write: console_write, + read : NULL, + device : etrax_console_device, + unblank : NULL, + setup : console_setup, + flags : CON_PRINTBUFFER, + index : 3, + cflag : 0, + next : NULL +}; +/* + * Register console (for printk's etc) + */ + +int __init +init_etrax_debug(void) +{ + static int first = 1; + + if (!first) { + unregister_console(&sercons); + register_console(&sercons0); + register_console(&sercons1); + register_console(&sercons2); + register_console(&sercons3); + init_dummy_console(); + return 0; + } + + first = 0; + register_console(&sercons); + start_port(port); +#ifdef CONFIG_ETRAX_KGDB + start_port(kgdb_port); +#endif + return 0; +} +__initcall(init_etrax_debug); diff --git a/kernel/arch/cris/arch-v10/kernel/dma.c b/kernel/arch/cris/arch-v10/kernel/dma.c new file mode 100644 index 000000000..579504735 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/dma.c @@ -0,0 +1,287 @@ +/* Wrapper for DMA channel allocator that updates DMA client muxing. + * Copyright 2004-2007, Axis Communications AB + */ + +#include +#include +#include + +#include +#include +#include + +/* Macro to access ETRAX 100 registers */ +#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \ + IO_STATE_(reg##_, field##_, _##val) + + +static char used_dma_channels[MAX_DMA_CHANNELS]; +static const char * used_dma_channels_users[MAX_DMA_CHANNELS]; + +int cris_request_dma(unsigned int dmanr, const char * device_id, + unsigned options, enum dma_owner owner) +{ + unsigned long flags; + unsigned long int gens; + int fail = -EINVAL; + + if (dmanr >= MAX_DMA_CHANNELS) { + printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr); + return -EINVAL; + } + + local_irq_save(flags); + if (used_dma_channels[dmanr]) { + local_irq_restore(flags); + if (options & DMA_VERBOSE_ON_ERROR) { + printk(KERN_CRIT "Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]); + } + if (options & DMA_PANIC_ON_ERROR) { + panic("request_dma error!"); + } + return -EBUSY; + } + + gens = genconfig_shadow; + + switch(owner) + { + case dma_eth: + if ((dmanr != NETWORK_TX_DMA_NBR) && + (dmanr != NETWORK_RX_DMA_NBR)) { + printk(KERN_CRIT "Invalid DMA channel for eth\n"); + goto bail; + } + break; + case dma_ser0: + if (dmanr == SER0_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma6, serial0); + } else if (dmanr == SER0_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma7, serial0); + } else { + printk(KERN_CRIT "Invalid DMA channel for ser0\n"); + goto bail; + } + break; + case dma_ser1: + if (dmanr == SER1_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma8, serial1); + } else if (dmanr == SER1_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma9, serial1); + } else { + printk(KERN_CRIT "Invalid DMA channel for ser1\n"); + goto bail; + } + break; + case dma_ser2: + if (dmanr == SER2_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma2, serial2); + } else if (dmanr == SER2_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma3, serial2); + } else { + printk(KERN_CRIT "Invalid DMA channel for ser2\n"); + goto bail; + } + break; + case dma_ser3: + if (dmanr == SER3_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma4, serial3); + } else if (dmanr == SER3_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma5, serial3); + } else { + printk(KERN_CRIT "Invalid DMA channel for ser3\n"); + goto bail; + } + break; + case dma_ata: + if (dmanr == ATA_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma2, ata); + } else if (dmanr == ATA_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma3, ata); + } else { + printk(KERN_CRIT "Invalid DMA channel for ata\n"); + goto bail; + } + break; + case dma_ext0: + if (dmanr == EXTDMA0_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma4, extdma0); + } else if (dmanr == EXTDMA0_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma5, extdma0); + } else { + printk(KERN_CRIT "Invalid DMA channel for ext0\n"); + goto bail; + } + break; + case dma_ext1: + if (dmanr == EXTDMA1_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma6, extdma1); + } else if (dmanr == EXTDMA1_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma7, extdma1); + } else { + printk(KERN_CRIT "Invalid DMA channel for ext1\n"); + goto bail; + } + break; + case dma_int6: + if (dmanr == MEM2MEM_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma7, intdma6); + } else { + printk(KERN_CRIT "Invalid DMA channel for int6\n"); + goto bail; + } + break; + case dma_int7: + if (dmanr == MEM2MEM_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma6, intdma7); + } else { + printk(KERN_CRIT "Invalid DMA channel for int7\n"); + goto bail; + } + break; + case dma_usb: + if (dmanr == USB_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma8, usb); + } else if (dmanr == USB_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma9, usb); + } else { + printk(KERN_CRIT "Invalid DMA channel for usb\n"); + goto bail; + } + break; + case dma_scsi0: + if (dmanr == SCSI0_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma2, scsi0); + } else if (dmanr == SCSI0_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma3, scsi0); + } else { + printk(KERN_CRIT "Invalid DMA channel for scsi0\n"); + goto bail; + } + break; + case dma_scsi1: + if (dmanr == SCSI1_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma4, scsi1); + } else if (dmanr == SCSI1_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma5, scsi1); + } else { + printk(KERN_CRIT "Invalid DMA channel for scsi1\n"); + goto bail; + } + break; + case dma_par0: + if (dmanr == PAR0_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma2, par0); + } else if (dmanr == PAR0_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma3, par0); + } else { + printk(KERN_CRIT "Invalid DMA channel for par0\n"); + goto bail; + } + break; + case dma_par1: + if (dmanr == PAR1_TX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma4, par1); + } else if (dmanr == PAR1_RX_DMA_NBR) { + SETS(gens, R_GEN_CONFIG, dma5, par1); + } else { + printk(KERN_CRIT "Invalid DMA channel for par1\n"); + goto bail; + } + break; + default: + printk(KERN_CRIT "Invalid DMA owner.\n"); + goto bail; + } + + used_dma_channels[dmanr] = 1; + used_dma_channels_users[dmanr] = device_id; + + { + volatile int i; + genconfig_shadow = gens; + *R_GEN_CONFIG = genconfig_shadow; + /* Wait 12 cycles before doing any DMA command */ + for(i = 6; i > 0; i--) + nop(); + } + fail = 0; + bail: + local_irq_restore(flags); + return fail; +} + +void cris_free_dma(unsigned int dmanr, const char * device_id) +{ + unsigned long flags; + if (dmanr >= MAX_DMA_CHANNELS) { + printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr); + return; + } + + local_irq_save(flags); + if (!used_dma_channels[dmanr]) { + printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated\n", dmanr); + } else if (device_id != used_dma_channels_users[dmanr]) { + printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated by device\n", dmanr); + } else { + switch(dmanr) + { + case 0: + *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH0_CMD, cmd, *R_DMA_CH0_CMD) == + IO_STATE_VALUE(R_DMA_CH0_CMD, cmd, reset)); + break; + case 1: + *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH1_CMD, cmd, *R_DMA_CH1_CMD) == + IO_STATE_VALUE(R_DMA_CH1_CMD, cmd, reset)); + break; + case 2: + *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH2_CMD, cmd, *R_DMA_CH2_CMD) == + IO_STATE_VALUE(R_DMA_CH2_CMD, cmd, reset)); + break; + case 3: + *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH3_CMD, cmd, *R_DMA_CH3_CMD) == + IO_STATE_VALUE(R_DMA_CH3_CMD, cmd, reset)); + break; + case 4: + *R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH4_CMD, cmd, *R_DMA_CH4_CMD) == + IO_STATE_VALUE(R_DMA_CH4_CMD, cmd, reset)); + break; + case 5: + *R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH5_CMD, cmd, *R_DMA_CH5_CMD) == + IO_STATE_VALUE(R_DMA_CH5_CMD, cmd, reset)); + break; + case 6: + *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *R_DMA_CH6_CMD) == + IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); + break; + case 7: + *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH7_CMD, cmd, *R_DMA_CH7_CMD) == + IO_STATE_VALUE(R_DMA_CH7_CMD, cmd, reset)); + break; + case 8: + *R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH8_CMD, cmd, *R_DMA_CH8_CMD) == + IO_STATE_VALUE(R_DMA_CH8_CMD, cmd, reset)); + break; + case 9: + *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset); + while (IO_EXTRACT(R_DMA_CH9_CMD, cmd, *R_DMA_CH9_CMD) == + IO_STATE_VALUE(R_DMA_CH9_CMD, cmd, reset)); + break; + } + used_dma_channels[dmanr] = 0; + } + local_irq_restore(flags); +} + +EXPORT_SYMBOL(cris_request_dma); +EXPORT_SYMBOL(cris_free_dma); diff --git a/kernel/arch/cris/arch-v10/kernel/entry.S b/kernel/arch/cris/arch-v10/kernel/entry.S new file mode 100644 index 000000000..81570fcd0 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/entry.S @@ -0,0 +1,969 @@ +/* + * linux/arch/cris/entry.S + * + * Copyright (C) 2000, 2001, 2002 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + */ + +/* + * entry.S contains the system-call and fault low-level handling routines. + * + * NOTE: This code handles signal-recognition, which happens every time + * after a timer-interrupt and after each system call. + * + * Stack layout in 'ret_from_system_call': + * ptrace needs to have all regs on the stack. + * if the order here is changed, it needs to be + * updated in fork.c:copy_process, signal.c:do_signal, + * ptrace.c and ptrace.h + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + ;; functions exported from this file + + .globl system_call + .globl ret_from_intr + .globl ret_from_fork + .globl ret_from_kernel_thread + .globl resume + .globl multiple_interrupt + .globl hwbreakpoint + .globl IRQ1_interrupt + .globl spurious_interrupt + .globl hw_bp_trigs + .globl mmu_bus_fault + .globl do_sigtrap + .globl gdb_handle_breakpoint + .globl sys_call_table + + ;; below are various parts of system_call which are not in the fast-path + +#ifdef CONFIG_PREEMPT + ; Check if preemptive kernel scheduling should be done +_resume_kernel: + di + ; Load current task struct + movs.w -8192, $r0 ; THREAD_SIZE = 8192 + and.d $sp, $r0 + move.d [$r0+TI_preempt_count], $r10 ; Preemption disabled? + bne _Rexit + nop +_need_resched: + move.d [$r0+TI_flags], $r10 + btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set + bpl _Rexit + nop + ; Ok, lets's do some preemptive kernel scheduling + jsr preempt_schedule_irq + ; Load new task struct + movs.w -8192, $r0 ; THREAD_SIZE = 8192 + and.d $sp, $r0 + ; One more time (with new task) + ba _need_resched + nop +#else +#define _resume_kernel _Rexit +#endif + + ; Called at exit from fork. schedule_tail must be called to drop + ; spinlock if CONFIG_PREEMPT +ret_from_fork: + jsr schedule_tail + ba ret_from_sys_call + nop + +ret_from_kernel_thread: + jsr schedule_tail + move.d $r2, $r10 ; argument is here + jsr $r1 ; call the payload + moveq 0, $r9 ; no syscall restarts, TYVM... + ba ret_from_sys_call + +ret_from_intr: + ;; check for resched if preemptive kernel or if we're going back to user-mode + ;; this test matches the user_regs(regs) macro + ;; we cannot simply test $dccr, because that does not necessarily + ;; reflect what mode we'll return into. + + move.d [$sp + PT_dccr], $r0; regs->dccr + btstq 8, $r0 ; U-flag + bpl _resume_kernel + ; Note that di below is in delay slot + +_resume_userspace: + di ; so need_resched and sigpending don't change + + movs.w -8192, $r0 ; THREAD_SIZE == 8192 + and.d $sp, $r0 + + move.d [$r0+TI_flags], $r10 ; current->work + and.d _TIF_WORK_MASK, $r10 ; is there any work to be done on return + bne _work_pending + nop + ba _Rexit + nop + + ;; The system_call is called by a BREAK instruction, which works like + ;; an interrupt call but it stores the return PC in BRP instead of IRP. + ;; Since we dont really want to have two epilogues (one for system calls + ;; and one for interrupts) we push the contents of BRP instead of IRP in the + ;; system call prologue, to make it look like an ordinary interrupt on the + ;; stackframe. + ;; + ;; Since we can't have system calls inside interrupts, it should not matter + ;; that we don't stack IRP. + ;; + ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12,r13,mof,srp + ;; + ;; This function looks on the _surface_ like spaghetti programming, but it's + ;; really designed so that the fast-path does not force cache-loading of non-used + ;; instructions. Only the non-common cases cause the outlined code to run.. + +system_call: + ;; stack-frame similar to the irq heads, which is reversed in ret_from_sys_call + move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame + push $srp + push $dccr + push $mof + subq 14*4, $sp ; make room for r0-r13 + movem $r13, [$sp] ; push r0-r13 + push $r10 ; push orig_r10 + clear.d [$sp=$sp-4] ; frametype == 0, normal stackframe + + movs.w -ENOSYS, $r0 + move.d $r0, [$sp+PT_r10] ; put the default return value in r10 in the frame + + ;; check if this process is syscall-traced + + movs.w -8192, $r0 ; THREAD_SIZE == 8192 + and.d $sp, $r0 + + move.d [$r0+TI_flags], $r0 + btstq TIF_SYSCALL_TRACE, $r0 + bmi _syscall_trace_entry + nop + +_syscall_traced: + + ;; check for sanity in the requested syscall number + + cmpu.w NR_syscalls, $r9 + bcc ret_from_sys_call + lslq 2, $r9 ; multiply by 4, in the delay slot + + ;; as a bonus 7th parameter, we give the location on the stack + ;; of the register structure itself. some syscalls need this. + + push $sp + + ;; the parameter carrying registers r10, r11, r12 and 13 are intact. + ;; the fifth and sixth parameters (if any) was in mof and srp + ;; respectively, and we need to put them on the stack. + + push $srp + push $mof + + jsr [$r9+sys_call_table] ; actually do the system call + addq 3*4, $sp ; pop the mof, srp and regs parameters + move.d $r10, [$sp+PT_r10] ; save the return value + + moveq 1, $r9 ; "parameter" to ret_from_sys_call to show it was a sys call + + ;; fall through into ret_from_sys_call to return + +ret_from_sys_call: + ;; r9 is a parameter - if >=1 we came from a syscall, if 0, from an irq + + ;; get the current task-struct pointer (see top for defs) + + movs.w -8192, $r0 ; THREAD_SIZE == 8192 + and.d $sp, $r0 + + di ; make sure need_resched and sigpending don't change + move.d [$r0+TI_flags],$r1 + and.d _TIF_ALLWORK_MASK, $r1 + bne _syscall_exit_work + nop + +_Rexit: + ;; this epilogue MUST match the prologues in multiple_interrupt, irq.h and ptregs.h + pop $r10 ; frametype + bne _RBFexit ; was not CRIS_FRAME_NORMAL, handle otherwise + addq 4, $sp ; skip orig_r10, in delayslot + movem [$sp+], $r13 ; registers r0-r13 + pop $mof ; multiply overflow register + pop $dccr ; condition codes + pop $srp ; subroutine return pointer + ;; now we have a 4-word SBFS frame which we do not want to restore + ;; using RBF since it was not stacked with SBFS. instead we would like to + ;; just get the PC value to restart it with, and skip the rest of + ;; the frame. + ;; Also notice that it's important to use instructions here that + ;; keep the interrupts disabled (since we've already popped DCCR) + move [$sp=$sp+16], $p8; pop the SBFS frame from the sp + jmpu [$sp-16] ; return through the irp field in the sbfs frame + +_RBFexit: + movem [$sp+], $r13 ; registers r0-r13, in delay slot + pop $mof ; multiply overflow register + pop $dccr ; condition codes + pop $srp ; subroutine return pointer + rbf [$sp+] ; return by popping the CPU status + + ;; We get here after doing a syscall if extra work might need to be done + ;; perform syscall exit tracing if needed + +_syscall_exit_work: + ;; $r0 contains current at this point and irq's are disabled + + move.d [$r0+TI_flags], $r1 + btstq TIF_SYSCALL_TRACE, $r1 + bpl _work_pending + nop + + ei + + move.d $r9, $r1 ; preserve r9 + jsr do_syscall_trace + move.d $r1, $r9 + + ba _resume_userspace + nop + +_work_pending: + move.d [$r0+TI_flags], $r1 + btstq TIF_NEED_RESCHED, $r1 + bpl _work_notifysig ; was neither trace nor sched, must be signal/notify + nop + +_work_resched: + move.d $r9, $r1 ; preserve r9 + jsr schedule + move.d $r1, $r9 + di + + move.d [$r0+TI_flags], $r1 + and.d _TIF_WORK_MASK, $r1; ignore the syscall trace counter + beq _Rexit + nop + btstq TIF_NEED_RESCHED, $r1 + bmi _work_resched ; current->work.need_resched + nop + +_work_notifysig: + ;; deal with pending signals and notify-resume requests + + move.d $r9, $r10 ; do_notify_resume syscall/irq param + move.d $sp, $r11 ; the regs param + move.d $r1, $r12 ; the thread_info_flags parameter + jsr do_notify_resume + + ba _Rexit + nop + + ;; We get here as a sidetrack when we've entered a syscall with the + ;; trace-bit set. We need to call do_syscall_trace and then continue + ;; with the call. + +_syscall_trace_entry: + ;; PT_r10 in the frame contains -ENOSYS as required, at this point + + jsr do_syscall_trace + + ;; now re-enter the syscall code to do the syscall itself + ;; we need to restore $r9 here to contain the wanted syscall, and + ;; the other parameter-bearing registers + + move.d [$sp+PT_r9], $r9 + move.d [$sp+PT_orig_r10], $r10 ; PT_r10 is already filled with -ENOSYS. + move.d [$sp+PT_r11], $r11 + move.d [$sp+PT_r12], $r12 + move.d [$sp+PT_r13], $r13 + move [$sp+PT_mof], $mof + move [$sp+PT_srp], $srp + + ba _syscall_traced + nop + + ;; resume performs the actual task-switching, by switching stack pointers + ;; input arguments: r10 = prev, r11 = next, r12 = thread offset in task struct + ;; returns old current in r10 + ;; + ;; TODO: see the i386 version. The switch_to which calls resume in our version + ;; could really be an inline asm of this. + +resume: + push $srp ; we keep the old/new PC on the stack + add.d $r12, $r10 ; r10 = current tasks tss + move $dccr, [$r10+THREAD_dccr]; save irq enable state + di + + move $usp, [$r10+ THREAD_usp] ; save user-mode stackpointer + + ;; See copy_thread for the reason why register R9 is saved. + subq 10*4, $sp + movem $r9, [$sp] ; save non-scratch registers and R9. + + move.d $sp, [$r10+THREAD_ksp] ; save the kernel stack pointer for the old task + move.d $sp, $r10 ; return last running task in r10 + and.d -8192, $r10 ; get thread_info from stackpointer + move.d [$r10+TI_task], $r10 ; get task + add.d $r12, $r11 ; find the new tasks tss + move.d [$r11+THREAD_ksp], $sp ; switch into the new stackframe by restoring kernel sp + + movem [$sp+], $r9 ; restore non-scratch registers and R9. + + move [$r11+THREAD_usp], $usp ; restore user-mode stackpointer + + move [$r11+THREAD_dccr], $dccr ; restore irq enable status + jump [$sp+] ; restore PC + + ;; This is the MMU bus fault handler. + ;; It needs to stack the CPU status and overall is different + ;; from the other interrupt handlers. + +mmu_bus_fault: + ;; For refills we try to do a quick page table lookup. If it is + ;; a real fault we let the mm subsystem handle it. + + ;; the first longword in the sbfs frame was the interrupted PC + ;; which fits nicely with the "IRP" slot in pt_regs normally used to + ;; contain the return address. used by Oops to print kernel errors. + sbfs [$sp=$sp-16] ; push the internal CPU status + push $dccr + di + subq 2*4, $sp + movem $r1, [$sp] + move.d [R_MMU_CAUSE], $r1 + ;; ETRAX 100LX TR89 bugfix: if the second half of an unaligned + ;; write causes a MMU-fault, it will not be restarted correctly. + ;; This could happen if a write crosses a page-boundary and the + ;; second page is not yet COW'ed or even loaded. The workaround + ;; is to clear the unaligned bit in the CPU status record, so + ;; that the CPU will rerun both the first and second halves of + ;; the instruction. This will not have any sideeffects unless + ;; the first half goes to any device or memory that can't be + ;; written twice, and which is mapped through the MMU. + ;; + ;; We only need to do this for writes. + btstq 8, $r1 ; Write access? + bpl 1f + nop + move.d [$sp+16], $r0 ; Clear unaligned bit in csrinstr + and.d ~(1<<5), $r0 + move.d $r0, [$sp+16] +1: btstq 12, $r1 ; Refill? + bpl 2f + lsrq 24, $r1 ; Get PGD index (bit 24-31) + move.d [current_pgd], $r0 ; PGD for the current process + move.d [$r0+$r1.d], $r0 ; Get PMD + beq 2f + nop + and.w PAGE_MASK, $r0 ; Remove PMD flags + move.d [R_MMU_CAUSE], $r1 + lsrq PAGE_SHIFT, $r1 + and.d 0x7ff, $r1 ; Get PTE index into PGD (bit 13-23) + move.d [$r0+$r1.d], $r1 ; Get PTE + beq 2f + nop + ;; Store in TLB + move.d $r1, [R_TLB_LO] + ;; Return + movem [$sp+], $r1 + pop $dccr + rbf [$sp+] ; return by popping the CPU status + +2: ; PMD or PTE missing, let the mm subsystem fix it up. + movem [$sp+], $r1 + pop $dccr + + ; Ok, not that easy, pass it on to the mm subsystem + ; The MMU status record is now on the stack + push $srp ; make a stackframe similar to pt_regs + push $dccr + push $mof + di + subq 14*4, $sp + movem $r13, [$sp] + push $r10 ; dummy orig_r10 + moveq 1, $r10 + push $r10 ; frametype == 1, BUSFAULT frame type + + move.d $sp, $r10 ; pt_regs argument to handle_mmu_bus_fault + + jsr handle_mmu_bus_fault ; in arch/cris/arch-v10/mm/fault.c + + ;; now we need to return through the normal path, we cannot just + ;; do the RBFexit since we might have killed off the running + ;; process due to a SEGV, scheduled due to a page blocking or + ;; whatever. + + moveq 0, $r9 ; busfault is equivalent to an irq + + ba ret_from_intr + nop + + ;; special handlers for breakpoint and NMI +hwbreakpoint: + push $dccr + di + push $r10 + push $r11 + move.d [hw_bp_trig_ptr],$r10 + move $brp,$r11 + move.d $r11,[$r10+] + move.d $r10,[hw_bp_trig_ptr] +1: pop $r11 + pop $r10 + pop $dccr + retb + nop + +IRQ1_interrupt: + ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!! + move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame + push $srp + push $dccr + push $mof + di + subq 14*4, $sp + movem $r13, [$sp] + push $r10 ; push orig_r10 + clear.d [$sp=$sp-4] ; frametype == 0, normal frame + + ;; If there is a glitch on the NMI pin shorter than ~100ns + ;; (i.e. non-active by the time we get here) then the nmi_pin bit + ;; in R_IRQ_MASK0_RD will already be cleared. The watchdog_nmi bit + ;; is cleared by us however (when feeding the watchdog), which is why + ;; we use that bit to determine what brought us here. + + move.d [R_IRQ_MASK0_RD], $r1 ; External NMI or watchdog? + and.d (1<<30), $r1 + bne wdog + move.d $sp, $r10 + jsr handle_nmi + setf m ; Enable NMI again + ba _Rexit ; Return the standard way + nop +wdog: +#if defined(CONFIG_ETRAX_WATCHDOG) +;; Check if we're waiting for reset to happen, as signalled by +;; hard_reset_now setting cause_of_death to a magic value. If so, just +;; get stuck until reset happens. + .comm cause_of_death, 4 ;; Don't declare this anywhere. + move.d [cause_of_death], $r10 + cmp.d 0xbedead, $r10 +_killed_by_death: + beq _killed_by_death + nop + +;; We'll see this in ksymoops dumps. +Watchdog_bite: + +#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY + ;; We just restart the watchdog here to be sure we dont get + ;; hit while printing the watchdogmsg below + ;; This restart is compatible with the rest of the C-code, so + ;; the C-code can keep restarting the watchdog after this point. + ;; The non-NICE_DOGGY code below though, disables the possibility + ;; to restart since it changes the watchdog key, to avoid any + ;; buggy loops etc. keeping the watchdog alive after this. + jsr reset_watchdog +#else + +;; We need to extend the 3.3ms after the NMI at watchdog bite, so we have +;; time for an oops-dump over a 115k2 serial wire. Another 100ms should do. + +;; Change the watchdog key to an arbitrary 3-bit value and restart the +;; watchdog. +#define WD_INIT 2 + moveq IO_FIELD (R_WATCHDOG, key, WD_INIT), $r10 + move.d R_WATCHDOG, $r11 + + move.d $r10, [$r11] + moveq IO_FIELD (R_WATCHDOG, key, \ + IO_EXTRACT (R_WATCHDOG, key, \ + IO_MASK (R_WATCHDOG, key)) \ + ^ WD_INIT) \ + | IO_STATE (R_WATCHDOG, enable, start), $r10 + move.d $r10, [$r11] + +#endif + +;; Note that we don't do "setf m" here (or after two necessary NOPs), +;; since *not* doing that saves us from re-entrancy checks. We don't want +;; to get here again due to possible subsequent NMIs; we want the watchdog +;; to reset us. + + move.d _watchdogmsg,$r10 + jsr printk + + move.d $sp, $r10 + jsr watchdog_bite_hook + +;; This nop is here so we see the "Watchdog_bite" label in ksymoops dumps +;; rather than "spurious_interrupt". + nop +;; At this point we drop down into spurious_interrupt, which will do a +;; hard reset. + + .section .rodata,"a" +_watchdogmsg: + .ascii "Oops: bitten by watchdog\n\0" + .previous + +#endif /* CONFIG_ETRAX_WATCHDOG */ + +spurious_interrupt: + di + jump hard_reset_now + + ;; this handles the case when multiple interrupts arrive at the same time + ;; we jump to the first set interrupt bit in a priority fashion + ;; the hardware will call the unserved interrupts after the handler finishes + +multiple_interrupt: + ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!! + move $irp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame + push $srp + push $dccr + push $mof + di + subq 14*4, $sp + movem $r13, [$sp] + push $r10 ; push orig_r10 + clear.d [$sp=$sp-4] ; frametype == 0, normal frame + + move.d $sp, $r10 + jsr do_multiple_IRQ + + jump ret_from_intr + +do_sigtrap: + ;; + ;; SIGTRAP the process that executed the break instruction. + ;; Make a frame that Rexit in entry.S expects. + ;; + move $brp, [$sp=$sp-16] ; Push BRP while faking a cpu status record. + push $srp ; Push subroutine return pointer. + push $dccr ; Push condition codes. + push $mof ; Push multiply overflow reg. + di ; Need to disable irq's at this point. + subq 14*4, $sp ; Make room for r0-r13. + movem $r13, [$sp] ; Push the r0-r13 registers. + push $r10 ; Push orig_r10. + clear.d [$sp=$sp-4] ; Frametype - this is a normal stackframe. + + movs.w -8192,$r9 ; THREAD_SIZE == 8192 + and.d $sp, $r9 + move.d [$r9+TI_task], $r10 + move.d [$r10+TASK_pid], $r10 ; current->pid as arg1. + moveq 5, $r11 ; SIGTRAP as arg2. + jsr sys_kill + jump ret_from_intr ; Use the return routine for interrupts. + +gdb_handle_breakpoint: + push $dccr + push $r0 +#ifdef CONFIG_ETRAX_KGDB + move $dccr, $r0 ; U-flag not affected by previous insns. + btstq 8, $r0 ; Test the U-flag. + bmi _ugdb_handle_breakpoint ; Go to user mode debugging. + nop ; Empty delay slot (cannot pop r0 here). + pop $r0 ; Restore r0. + ba kgdb_handle_breakpoint ; Go to kernel debugging. + pop $dccr ; Restore dccr in delay slot. +#endif + +_ugdb_handle_breakpoint: + move $brp, $r0 ; Use r0 temporarily for calculation. + subq 2, $r0 ; Set to address of previous instruction. + move $r0, $brp + pop $r0 ; Restore r0. + ba do_sigtrap ; SIGTRAP the offending process. + pop $dccr ; Restore dccr in delay slot. + + .data + +hw_bp_trigs: + .space 64*4 +hw_bp_trig_ptr: + .dword hw_bp_trigs + + .section .rodata,"a" +sys_call_table: + .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */ + .long sys_exit + .long sys_fork + .long sys_read + .long sys_write + .long sys_open /* 5 */ + .long sys_close + .long sys_waitpid + .long sys_creat + .long sys_link + .long sys_unlink /* 10 */ + .long sys_execve + .long sys_chdir + .long sys_time + .long sys_mknod + .long sys_chmod /* 15 */ + .long sys_lchown16 + .long sys_ni_syscall /* old break syscall holder */ + .long sys_stat + .long sys_lseek + .long sys_getpid /* 20 */ + .long sys_mount + .long sys_oldumount + .long sys_setuid16 + .long sys_getuid16 + .long sys_stime /* 25 */ + .long sys_ptrace + .long sys_alarm + .long sys_fstat + .long sys_pause + .long sys_utime /* 30 */ + .long sys_ni_syscall /* old stty syscall holder */ + .long sys_ni_syscall /* old gtty syscall holder */ + .long sys_access + .long sys_nice + .long sys_ni_syscall /* 35 old ftime syscall holder */ + .long sys_sync + .long sys_kill + .long sys_rename + .long sys_mkdir + .long sys_rmdir /* 40 */ + .long sys_dup + .long sys_pipe + .long sys_times + .long sys_ni_syscall /* old prof syscall holder */ + .long sys_brk /* 45 */ + .long sys_setgid16 + .long sys_getgid16 + .long sys_signal + .long sys_geteuid16 + .long sys_getegid16 /* 50 */ + .long sys_acct + .long sys_umount /* recycled never used phys( */ + .long sys_ni_syscall /* old lock syscall holder */ + .long sys_ioctl + .long sys_fcntl /* 55 */ + .long sys_ni_syscall /* old mpx syscall holder */ + .long sys_setpgid + .long sys_ni_syscall /* old ulimit syscall holder */ + .long sys_ni_syscall /* old sys_olduname holder */ + .long sys_umask /* 60 */ + .long sys_chroot + .long sys_ustat + .long sys_dup2 + .long sys_getppid + .long sys_getpgrp /* 65 */ + .long sys_setsid + .long sys_sigaction + .long sys_sgetmask + .long sys_ssetmask + .long sys_setreuid16 /* 70 */ + .long sys_setregid16 + .long sys_sigsuspend + .long sys_sigpending + .long sys_sethostname + .long sys_setrlimit /* 75 */ + .long sys_old_getrlimit + .long sys_getrusage + .long sys_gettimeofday + .long sys_settimeofday + .long sys_getgroups16 /* 80 */ + .long sys_setgroups16 + .long sys_select /* was old_select in Linux/E100 */ + .long sys_symlink + .long sys_lstat + .long sys_readlink /* 85 */ + .long sys_uselib + .long sys_swapon + .long sys_reboot + .long sys_old_readdir + .long sys_old_mmap /* 90 */ + .long sys_munmap + .long sys_truncate + .long sys_ftruncate + .long sys_fchmod + .long sys_fchown16 /* 95 */ + .long sys_getpriority + .long sys_setpriority + .long sys_ni_syscall /* old profil syscall holder */ + .long sys_statfs + .long sys_fstatfs /* 100 */ + .long sys_ni_syscall /* sys_ioperm in i386 */ + .long sys_socketcall + .long sys_syslog + .long sys_setitimer + .long sys_getitimer /* 105 */ + .long sys_newstat + .long sys_newlstat + .long sys_newfstat + .long sys_ni_syscall /* old sys_uname holder */ + .long sys_ni_syscall /* 110 */ /* sys_iopl in i386 */ + .long sys_vhangup + .long sys_ni_syscall /* old "idle" system call */ + .long sys_ni_syscall /* vm86old in i386 */ + .long sys_wait4 + .long sys_swapoff /* 115 */ + .long sys_sysinfo + .long sys_ipc + .long sys_fsync + .long sys_sigreturn + .long sys_clone /* 120 */ + .long sys_setdomainname + .long sys_newuname + .long sys_ni_syscall /* sys_modify_ldt */ + .long sys_adjtimex + .long sys_mprotect /* 125 */ + .long sys_sigprocmask + .long sys_ni_syscall /* old "create_module" */ + .long sys_init_module + .long sys_delete_module + .long sys_ni_syscall /* 130: old "get_kernel_syms" */ + .long sys_quotactl + .long sys_getpgid + .long sys_fchdir + .long sys_bdflush + .long sys_sysfs /* 135 */ + .long sys_personality + .long sys_ni_syscall /* for afs_syscall */ + .long sys_setfsuid16 + .long sys_setfsgid16 + .long sys_llseek /* 140 */ + .long sys_getdents + .long sys_select + .long sys_flock + .long sys_msync + .long sys_readv /* 145 */ + .long sys_writev + .long sys_getsid + .long sys_fdatasync + .long sys_sysctl + .long sys_mlock /* 150 */ + .long sys_munlock + .long sys_mlockall + .long sys_munlockall + .long sys_sched_setparam + .long sys_sched_getparam /* 155 */ + .long sys_sched_setscheduler + .long sys_sched_getscheduler + .long sys_sched_yield + .long sys_sched_get_priority_max + .long sys_sched_get_priority_min /* 160 */ + .long sys_sched_rr_get_interval + .long sys_nanosleep + .long sys_mremap + .long sys_setresuid16 + .long sys_getresuid16 /* 165 */ + .long sys_ni_syscall /* sys_vm86 */ + .long sys_ni_syscall /* Old sys_query_module */ + .long sys_poll + .long sys_ni_syscall /* old nfsservctl */ + .long sys_setresgid16 /* 170 */ + .long sys_getresgid16 + .long sys_prctl + .long sys_rt_sigreturn + .long sys_rt_sigaction + .long sys_rt_sigprocmask /* 175 */ + .long sys_rt_sigpending + .long sys_rt_sigtimedwait + .long sys_rt_sigqueueinfo + .long sys_rt_sigsuspend + .long sys_pread64 /* 180 */ + .long sys_pwrite64 + .long sys_chown16 + .long sys_getcwd + .long sys_capget + .long sys_capset /* 185 */ + .long sys_sigaltstack + .long sys_sendfile + .long sys_ni_syscall /* streams1 */ + .long sys_ni_syscall /* streams2 */ + .long sys_vfork /* 190 */ + .long sys_getrlimit + .long sys_mmap2 /* mmap_pgoff */ + .long sys_truncate64 + .long sys_ftruncate64 + .long sys_stat64 /* 195 */ + .long sys_lstat64 + .long sys_fstat64 + .long sys_lchown + .long sys_getuid + .long sys_getgid /* 200 */ + .long sys_geteuid + .long sys_getegid + .long sys_setreuid + .long sys_setregid + .long sys_getgroups /* 205 */ + .long sys_setgroups + .long sys_fchown + .long sys_setresuid + .long sys_getresuid + .long sys_setresgid /* 210 */ + .long sys_getresgid + .long sys_chown + .long sys_setuid + .long sys_setgid + .long sys_setfsuid /* 215 */ + .long sys_setfsgid + .long sys_pivot_root + .long sys_mincore + .long sys_madvise + .long sys_getdents64 /* 220 */ + .long sys_fcntl64 + .long sys_ni_syscall /* reserved for TUX */ + .long sys_ni_syscall + .long sys_gettid + .long sys_readahead /* 225 */ + .long sys_setxattr + .long sys_lsetxattr + .long sys_fsetxattr + .long sys_getxattr + .long sys_lgetxattr /* 230 */ + .long sys_fgetxattr + .long sys_listxattr + .long sys_llistxattr + .long sys_flistxattr + .long sys_removexattr /* 235 */ + .long sys_lremovexattr + .long sys_fremovexattr + .long sys_tkill + .long sys_sendfile64 + .long sys_futex /* 240 */ + .long sys_sched_setaffinity + .long sys_sched_getaffinity + .long sys_ni_syscall /* sys_set_thread_area */ + .long sys_ni_syscall /* sys_get_thread_area */ + .long sys_io_setup /* 245 */ + .long sys_io_destroy + .long sys_io_getevents + .long sys_io_submit + .long sys_io_cancel + .long sys_fadvise64 /* 250 */ + .long sys_ni_syscall + .long sys_exit_group + .long sys_lookup_dcookie + .long sys_epoll_create + .long sys_epoll_ctl /* 255 */ + .long sys_epoll_wait + .long sys_remap_file_pages + .long sys_set_tid_address + .long sys_timer_create + .long sys_timer_settime /* 260 */ + .long sys_timer_gettime + .long sys_timer_getoverrun + .long sys_timer_delete + .long sys_clock_settime + .long sys_clock_gettime /* 265 */ + .long sys_clock_getres + .long sys_clock_nanosleep + .long sys_statfs64 + .long sys_fstatfs64 + .long sys_tgkill /* 270 */ + .long sys_utimes + .long sys_fadvise64_64 + .long sys_ni_syscall /* sys_vserver */ + .long sys_ni_syscall /* sys_mbind */ + .long sys_ni_syscall /* 275 sys_get_mempolicy */ + .long sys_ni_syscall /* sys_set_mempolicy */ + .long sys_mq_open + .long sys_mq_unlink + .long sys_mq_timedsend + .long sys_mq_timedreceive /* 280 */ + .long sys_mq_notify + .long sys_mq_getsetattr + .long sys_ni_syscall + .long sys_waitid + .long sys_ni_syscall /* 285 */ /* available */ + .long sys_add_key + .long sys_request_key + .long sys_keyctl + .long sys_ioprio_set + .long sys_ioprio_get /* 290 */ + .long sys_inotify_init + .long sys_inotify_add_watch + .long sys_inotify_rm_watch + .long sys_migrate_pages + .long sys_openat /* 295 */ + .long sys_mkdirat + .long sys_mknodat + .long sys_fchownat + .long sys_futimesat + .long sys_fstatat64 /* 300 */ + .long sys_unlinkat + .long sys_renameat + .long sys_linkat + .long sys_symlinkat + .long sys_readlinkat /* 305 */ + .long sys_fchmodat + .long sys_faccessat + .long sys_pselect6 + .long sys_ppoll + .long sys_unshare /* 310 */ + .long sys_set_robust_list + .long sys_get_robust_list + .long sys_splice + .long sys_sync_file_range + .long sys_tee /* 315 */ + .long sys_vmsplice + .long sys_move_pages + .long sys_getcpu + .long sys_epoll_pwait + .long sys_utimensat /* 320 */ + .long sys_signalfd + .long sys_timerfd_create + .long sys_eventfd + .long sys_fallocate + .long sys_timerfd_settime /* 325 */ + .long sys_timerfd_gettime + .long sys_signalfd4 + .long sys_eventfd2 + .long sys_epoll_create1 + .long sys_dup3 /* 330 */ + .long sys_pipe2 + .long sys_inotify_init1 + .long sys_preadv + .long sys_pwritev + .long sys_setns /* 335 */ + .long sys_name_to_handle_at + .long sys_open_by_handle_at + .long sys_rt_tgsigqueueinfo + .long sys_perf_event_open + .long sys_recvmmsg /* 340 */ + .long sys_accept4 + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 + .long sys_clock_adjtime /* 345 */ + .long sys_syncfs + .long sys_sendmmsg + .long sys_process_vm_readv + .long sys_process_vm_writev + .long sys_kcmp /* 350 */ + .long sys_finit_module + + /* + * NOTE!! This doesn't have to be exact - we just have + * to make sure we have _enough_ of the "sys_ni_syscall" + * entries. Don't panic if you notice that this hasn't + * been shrunk every time we add a new system call. + */ + + .rept NR_syscalls-(.-sys_call_table)/4 + .long sys_ni_syscall + .endr + diff --git a/kernel/arch/cris/arch-v10/kernel/fasttimer.c b/kernel/arch/cris/arch-v10/kernel/fasttimer.c new file mode 100644 index 000000000..e9298739d --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/fasttimer.c @@ -0,0 +1,834 @@ +/* + * linux/arch/cris/kernel/fasttimer.c + * + * Fast timers for ETRAX100/ETRAX100LX + * + * Copyright (C) 2000-2007 Axis Communications AB, Lund, Sweden + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + + +#define DEBUG_LOG_INCLUDED +#define FAST_TIMER_LOG +/* #define FAST_TIMER_TEST */ + +#define FAST_TIMER_SANITY_CHECKS + +#ifdef FAST_TIMER_SANITY_CHECKS +static int sanity_failed; +#endif + +#define D1(x) +#define D2(x) +#define DP(x) + +static unsigned int fast_timer_running; +static unsigned int fast_timers_added; +static unsigned int fast_timers_started; +static unsigned int fast_timers_expired; +static unsigned int fast_timers_deleted; +static unsigned int fast_timer_is_init; +static unsigned int fast_timer_ints; + +struct fast_timer *fast_timer_list = NULL; + +#ifdef DEBUG_LOG_INCLUDED +#define DEBUG_LOG_MAX 128 +static const char * debug_log_string[DEBUG_LOG_MAX]; +static unsigned long debug_log_value[DEBUG_LOG_MAX]; +static unsigned int debug_log_cnt; +static unsigned int debug_log_cnt_wrapped; + +#define DEBUG_LOG(string, value) \ +{ \ + unsigned long log_flags; \ + local_irq_save(log_flags); \ + debug_log_string[debug_log_cnt] = (string); \ + debug_log_value[debug_log_cnt] = (unsigned long)(value); \ + if (++debug_log_cnt >= DEBUG_LOG_MAX) \ + { \ + debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \ + debug_log_cnt_wrapped = 1; \ + } \ + local_irq_restore(log_flags); \ +} +#else +#define DEBUG_LOG(string, value) +#endif + + +/* The frequencies for index = clkselx number in R_TIMER_CTRL */ +#define NUM_TIMER_FREQ 15 +#define MAX_USABLE_TIMER_FREQ 7 +#define MAX_DELAY_US 853333L +const unsigned long timer_freq_100[NUM_TIMER_FREQ] = +{ + 3, /* 0 3333 - 853333 us */ + 6, /* 1 1666 - 426666 us */ + 12, /* 2 833 - 213333 us */ + 24, /* 3 416 - 106666 us */ + 48, /* 4 208 - 53333 us */ + 96, /* 5 104 - 26666 us */ + 192, /* 6 52 - 13333 us */ + 384, /* 7 26 - 6666 us */ + 576, + 1152, + 2304, + 4608, + 9216, + 18432, + 62500, + /* 15 = cascade */ +}; +#define NUM_TIMER_STATS 16 +#ifdef FAST_TIMER_LOG +struct fast_timer timer_added_log[NUM_TIMER_STATS]; +struct fast_timer timer_started_log[NUM_TIMER_STATS]; +struct fast_timer timer_expired_log[NUM_TIMER_STATS]; +#endif + +int timer_div_settings[NUM_TIMER_STATS]; +int timer_freq_settings[NUM_TIMER_STATS]; +int timer_delay_settings[NUM_TIMER_STATS]; + +/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */ +inline void do_gettimeofday_fast(struct fasttime_t *tv) +{ + tv->tv_jiff = jiffies; + tv->tv_usec = GET_JIFFIES_USEC(); +} + +inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1) +{ + /* Compare jiffies. Takes care of wrapping */ + if (time_before(t0->tv_jiff, t1->tv_jiff)) + return -1; + else if (time_after(t0->tv_jiff, t1->tv_jiff)) + return 1; + + /* Compare us */ + if (t0->tv_usec < t1->tv_usec) + return -1; + else if (t0->tv_usec > t1->tv_usec) + return 1; + return 0; +} + +inline void start_timer1(unsigned long delay_us) +{ + int freq_index = 0; /* This is the lowest resolution */ + unsigned long upper_limit = MAX_DELAY_US; + + unsigned long div; + /* Start/Restart the timer to the new shorter value */ + /* t = 1/freq = 1/19200 = 53us + * T=div*t, div = T/t = delay_us*freq/1000000 + */ +#if 1 /* Adaptive timer settings */ + while (delay_us < upper_limit && freq_index < MAX_USABLE_TIMER_FREQ) + { + freq_index++; + upper_limit >>= 1; /* Divide by 2 using shift */ + } + if (freq_index > 0) + { + freq_index--; + } +#else + freq_index = 6; +#endif + div = delay_us * timer_freq_100[freq_index]/10000; + if (div < 2) + { + /* Maybe increase timer freq? */ + div = 2; + } + if (div > 255) + { + div = 0; /* This means 256, the max the timer takes */ + /* If a longer timeout than the timer can handle is used, + * then we must restart it when it goes off. + */ + } + + timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = div; + timer_freq_settings[fast_timers_started % NUM_TIMER_STATS] = freq_index; + timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us; + + D1(printk(KERN_DEBUG "start_timer1 : %d us freq: %i div: %i\n", + delay_us, freq_index, div)); + /* Clear timer1 irq */ + *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr); + + /* Set timer values */ + *R_TIMER_CTRL = r_timer_ctrl_shadow = + (r_timer_ctrl_shadow & + ~IO_MASK(R_TIMER_CTRL, timerdiv1) & + ~IO_MASK(R_TIMER_CTRL, tm1) & + ~IO_MASK(R_TIMER_CTRL, clksel1)) | + IO_FIELD(R_TIMER_CTRL, timerdiv1, div) | + IO_STATE(R_TIMER_CTRL, tm1, stop_ld) | + IO_FIELD(R_TIMER_CTRL, clksel1, freq_index ); /* 6=c19k2Hz */ + + /* Ack interrupt */ + *R_TIMER_CTRL = r_timer_ctrl_shadow | + IO_STATE(R_TIMER_CTRL, i1, clr); + + /* Start timer */ + *R_TIMER_CTRL = r_timer_ctrl_shadow = + (r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) | + IO_STATE(R_TIMER_CTRL, tm1, run); + + /* Enable timer1 irq */ + *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer1, set); + fast_timers_started++; + fast_timer_running = 1; +} + +/* In version 1.4 this function takes 27 - 50 us */ +void start_one_shot_timer(struct fast_timer *t, + fast_timer_function_type *function, + unsigned long data, + unsigned long delay_us, + const char *name) +{ + unsigned long flags; + struct fast_timer *tmp; + + D1(printk("sft %s %d us\n", name, delay_us)); + + local_irq_save(flags); + + do_gettimeofday_fast(&t->tv_set); + tmp = fast_timer_list; + +#ifdef FAST_TIMER_SANITY_CHECKS + /* Check so this is not in the list already... */ + while (tmp != NULL) { + if (tmp == t) { + printk(KERN_WARNING "timer name: %s data: " + "0x%08lX already in list!\n", name, data); + sanity_failed++; + goto done; + } else + tmp = tmp->next; + } + tmp = fast_timer_list; +#endif + + t->delay_us = delay_us; + t->function = function; + t->data = data; + t->name = name; + + t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000; + t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ; + if (t->tv_expires.tv_usec > 1000000) + { + t->tv_expires.tv_usec -= 1000000; + t->tv_expires.tv_jiff += HZ; + } +#ifdef FAST_TIMER_LOG + timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t; +#endif + fast_timers_added++; + + /* Check if this should timeout before anything else */ + if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0) + { + /* Put first in list and modify the timer value */ + t->prev = NULL; + t->next = fast_timer_list; + if (fast_timer_list) + { + fast_timer_list->prev = t; + } + fast_timer_list = t; +#ifdef FAST_TIMER_LOG + timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; +#endif + start_timer1(delay_us); + } else { + /* Put in correct place in list */ + while (tmp->next && fasttime_cmp(&t->tv_expires, + &tmp->next->tv_expires) > 0) + { + tmp = tmp->next; + } + /* Insert t after tmp */ + t->prev = tmp; + t->next = tmp->next; + if (tmp->next) + { + tmp->next->prev = t; + } + tmp->next = t; + } + + D2(printk("start_one_shot_timer: %d us done\n", delay_us)); + +done: + local_irq_restore(flags); +} /* start_one_shot_timer */ + +static inline int fast_timer_pending (const struct fast_timer * t) +{ + return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list); +} + +static inline int detach_fast_timer (struct fast_timer *t) +{ + struct fast_timer *next, *prev; + if (!fast_timer_pending(t)) + return 0; + next = t->next; + prev = t->prev; + if (next) + next->prev = prev; + if (prev) + prev->next = next; + else + fast_timer_list = next; + fast_timers_deleted++; + return 1; +} + +int del_fast_timer(struct fast_timer * t) +{ + unsigned long flags; + int ret; + + local_irq_save(flags); + ret = detach_fast_timer(t); + t->next = t->prev = NULL; + local_irq_restore(flags); + return ret; +} /* del_fast_timer */ + + +/* Interrupt routines or functions called in interrupt context */ + +/* Timer 1 interrupt handler */ + +static irqreturn_t +timer1_handler(int irq, void *dev_id) +{ + struct fast_timer *t; + unsigned long flags; + + /* We keep interrupts disabled not only when we modify the + * fast timer list, but any time we hold a reference to a + * timer in the list, since del_fast_timer may be called + * from (another) interrupt context. Thus, the only time + * when interrupts are enabled is when calling the timer + * callback function. + */ + local_irq_save(flags); + + /* Clear timer1 irq */ + *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr); + + /* First stop timer, then ack interrupt */ + /* Stop timer */ + *R_TIMER_CTRL = r_timer_ctrl_shadow = + (r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) | + IO_STATE(R_TIMER_CTRL, tm1, stop_ld); + + /* Ack interrupt */ + *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i1, clr); + + fast_timer_running = 0; + fast_timer_ints++; + + t = fast_timer_list; + while (t) + { + struct fasttime_t tv; + fast_timer_function_type *f; + unsigned long d; + + /* Has it really expired? */ + do_gettimeofday_fast(&tv); + D1(printk(KERN_DEBUG "t: %is %06ius\n", + tv.tv_jiff, tv.tv_usec)); + + if (fasttime_cmp(&t->tv_expires, &tv) <= 0) + { + /* Yes it has expired */ +#ifdef FAST_TIMER_LOG + timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t; +#endif + fast_timers_expired++; + + /* Remove this timer before call, since it may reuse the timer */ + if (t->prev) + { + t->prev->next = t->next; + } + else + { + fast_timer_list = t->next; + } + if (t->next) + { + t->next->prev = t->prev; + } + t->prev = NULL; + t->next = NULL; + + /* Save function callback data before enabling + * interrupts, since the timer may be removed and + * we don't know how it was allocated + * (e.g. ->function and ->data may become overwritten + * after deletion if the timer was stack-allocated). + */ + f = t->function; + d = t->data; + + if (f != NULL) { + /* Run callback with interrupts enabled. */ + local_irq_restore(flags); + f(d); + local_irq_save(flags); + } else + DEBUG_LOG("!timer1 %i function==NULL!\n", fast_timer_ints); + } + else + { + /* Timer is to early, let's set it again using the normal routines */ + D1(printk(".\n")); + } + + if ((t = fast_timer_list) != NULL) + { + /* Start next timer.. */ + long us = 0; + struct fasttime_t tv; + + do_gettimeofday_fast(&tv); + + /* time_after_eq takes care of wrapping */ + if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff)) + us = ((t->tv_expires.tv_jiff - tv.tv_jiff) * + 1000000 / HZ + t->tv_expires.tv_usec - + tv.tv_usec); + + if (us > 0) + { + if (!fast_timer_running) + { +#ifdef FAST_TIMER_LOG + timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; +#endif + start_timer1(us); + } + break; + } + else + { + /* Timer already expired, let's handle it better late than never. + * The normal loop handles it + */ + D1(printk("e! %d\n", us)); + } + } + } + + local_irq_restore(flags); + + if (!t) + { + D1(printk("t1 stop!\n")); + } + + return IRQ_HANDLED; +} + +static void wake_up_func(unsigned long data) +{ + wait_queue_head_t *sleep_wait_p = (wait_queue_head_t *)data; + wake_up(sleep_wait_p); +} + + +/* Useful API */ + +void schedule_usleep(unsigned long us) +{ + struct fast_timer t; + wait_queue_head_t sleep_wait; + init_waitqueue_head(&sleep_wait); + + D1(printk("schedule_usleep(%d)\n", us)); + start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us, + "usleep"); + /* Uninterruptible sleep on the fast timer. (The condition is somewhat + * redundant since the timer is what wakes us up.) */ + wait_event(sleep_wait, !fast_timer_pending(&t)); + + D1(printk("done schedule_usleep(%d)\n", us)); +} + +#ifdef CONFIG_PROC_FS +/* This value is very much based on testing */ +#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300) + +static int proc_fasttimer_show(struct seq_file *m, void *v) +{ + unsigned long flags; + int i = 0; + int num_to_show; + struct fasttime_t tv; + struct fast_timer *t, *nextt; + + do_gettimeofday_fast(&tv); + + seq_printf(m, "Fast timers added: %i\n", fast_timers_added); + seq_printf(m, "Fast timers started: %i\n", fast_timers_started); + seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints); + seq_printf(m, "Fast timers expired: %i\n", fast_timers_expired); + seq_printf(m, "Fast timers deleted: %i\n", fast_timers_deleted); + seq_printf(m, "Fast timer running: %s\n", + fast_timer_running ? "yes" : "no"); + seq_printf(m, "Current time: %lu.%06lu\n", + (unsigned long)tv.tv_jiff, + (unsigned long)tv.tv_usec); +#ifdef FAST_TIMER_SANITY_CHECKS + seq_printf(m, "Sanity failed: %i\n", sanity_failed); +#endif + seq_putc(m, '\n'); + +#ifdef DEBUG_LOG_INCLUDED + { + int end_i = debug_log_cnt; + i = 0; + + if (debug_log_cnt_wrapped) + i = debug_log_cnt; + + while (i != end_i || debug_log_cnt_wrapped) { + seq_printf(m, debug_log_string[i], debug_log_value[i]); + if (seq_has_overflowed(m)) + return 0; + i = (i+1) % DEBUG_LOG_MAX; + } + } + seq_putc(m, '\n'); +#endif + + num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started: + NUM_TIMER_STATS); + seq_printf(m, "Timers started: %i\n", fast_timers_started); + for (i = 0; i < num_to_show; i++) { + int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS; + +#if 1 //ndef FAST_TIMER_LOG + seq_printf(m, "div: %i freq: %i delay: %i\n", + timer_div_settings[cur], + timer_freq_settings[cur], + timer_delay_settings[cur]); +#endif +#ifdef FAST_TIMER_LOG + t = &timer_started_log[cur]; + seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", + t->name, + (unsigned long)t->tv_set.tv_jiff, + (unsigned long)t->tv_set.tv_usec, + (unsigned long)t->tv_expires.tv_jiff, + (unsigned long)t->tv_expires.tv_usec, + t->delay_us, + t->data); + if (seq_has_overflowed(m)) + return 0; +#endif + } + seq_putc(m, '\n'); + +#ifdef FAST_TIMER_LOG + num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added: + NUM_TIMER_STATS); + seq_printf(m, "Timers added: %i\n", fast_timers_added); + for (i = 0; i < num_to_show; i++) { + t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS]; + seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", + t->name, + (unsigned long)t->tv_set.tv_jiff, + (unsigned long)t->tv_set.tv_usec, + (unsigned long)t->tv_expires.tv_jiff, + (unsigned long)t->tv_expires.tv_usec, + t->delay_us, + t->data); + if (seq_has_overflowed(m)) + return 0; + } + seq_putc(m, '\n'); + + num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired: + NUM_TIMER_STATS); + seq_printf(m, "Timers expired: %i\n", fast_timers_expired); + for (i = 0; i < num_to_show; i++) { + t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS]; + seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", + t->name, + (unsigned long)t->tv_set.tv_jiff, + (unsigned long)t->tv_set.tv_usec, + (unsigned long)t->tv_expires.tv_jiff, + (unsigned long)t->tv_expires.tv_usec, + t->delay_us, + t->data); + if (seq_has_overflowed(m)) + return 0; + } + seq_putc(m, '\n'); +#endif + + seq_puts(m, "Active timers:\n"); + local_irq_save(flags); + t = fast_timer_list; + while (t) { + nextt = t->next; + local_irq_restore(flags); + seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", + t->name, + (unsigned long)t->tv_set.tv_jiff, + (unsigned long)t->tv_set.tv_usec, + (unsigned long)t->tv_expires.tv_jiff, + (unsigned long)t->tv_expires.tv_usec, + t->delay_us, + t->data); + if (seq_has_overflowed(m)) + return 0; + local_irq_save(flags); + if (t->next != nextt) + printk(KERN_WARNING "timer removed!\n"); + t = nextt; + } + local_irq_restore(flags); + + return 0; +} + +static int proc_fasttimer_open(struct inode *inode, struct file *file) +{ + return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE); +} + +static const struct file_operations proc_fasttimer_fops = { + .open = proc_fasttimer_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +#endif /* PROC_FS */ + +#ifdef FAST_TIMER_TEST +static volatile unsigned long i = 0; +static volatile int num_test_timeout = 0; +static struct fast_timer tr[10]; +static int exp_num[10]; + +static struct fasttime_t tv_exp[100]; + +static void test_timeout(unsigned long data) +{ + do_gettimeofday_fast(&tv_exp[data]); + exp_num[data] = num_test_timeout; + + num_test_timeout++; +} + +static void test_timeout1(unsigned long data) +{ + do_gettimeofday_fast(&tv_exp[data]); + exp_num[data] = num_test_timeout; + if (data < 7) + { + start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1"); + i++; + } + num_test_timeout++; +} + +DP( +static char buf0[2000]; +static char buf1[2000]; +static char buf2[2000]; +static char buf3[2000]; +static char buf4[2000]; +); + +static char buf5[6000]; +static int j_u[1000]; + +static void fast_timer_test(void) +{ + int prev_num; + int j; + + struct fasttime_t tv, tv0, tv1, tv2; + + printk("fast_timer_test() start\n"); + do_gettimeofday_fast(&tv); + + for (j = 0; j < 1000; j++) + { + j_u[j] = GET_JIFFIES_USEC(); + } + for (j = 0; j < 100; j++) + { + do_gettimeofday_fast(&tv_exp[j]); + } + printk(KERN_DEBUG "fast_timer_test() %is %06i\n", + tv.tv_jiff, tv.tv_usec); + + for (j = 0; j < 1000; j++) + { + printk("%i %i %i %i %i\n",j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]); + j += 4; + } + for (j = 0; j < 100; j++) + { + printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n", + tv_exp[j].tv_jiff, tv_exp[j].tv_usec, + tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec, + tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec, + tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec, + tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec); + j += 4; + } + do_gettimeofday_fast(&tv0); + start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0"); + DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0)); + i++; + start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1"); + DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0)); + i++; + start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2"); + DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0)); + i++; + start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3"); + DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0)); + i++; + start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx"); + DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0)); + i++; + do_gettimeofday_fast(&tv1); + + proc_fasttimer_read(buf5, NULL, 0, 0, 0); + + prev_num = num_test_timeout; + while (num_test_timeout < i) + { + if (num_test_timeout != prev_num) + { + prev_num = num_test_timeout; + } + } + do_gettimeofday_fast(&tv2); + printk(KERN_DEBUG "Timers started %is %06i\n", + tv0.tv_jiff, tv0.tv_usec); + printk(KERN_DEBUG "Timers started at %is %06i\n", + tv1.tv_jiff, tv1.tv_usec); + printk(KERN_DEBUG "Timers done %is %06i\n", + tv2.tv_jiff, tv2.tv_usec); + DP(printk("buf0:\n"); + printk(buf0); + printk("buf1:\n"); + printk(buf1); + printk("buf2:\n"); + printk(buf2); + printk("buf3:\n"); + printk(buf3); + printk("buf4:\n"); + printk(buf4); + ); + printk("buf5:\n"); + printk(buf5); + + printk("timers set:\n"); + for(j = 0; jname, + t->tv_set.tv_jiff, + t->tv_set.tv_usec, + t->tv_expires.tv_jiff, + t->tv_expires.tv_usec, + t->data, + t->function + ); + + printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n", + t->delay_us, + tv_exp[j].tv_jiff, + tv_exp[j].tv_usec, + exp_num[j], + (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) * + 1000000 + tv_exp[j].tv_usec - + t->tv_expires.tv_usec); + } + proc_fasttimer_read(buf5, NULL, 0, 0, 0); + printk("buf5 after all done:\n"); + printk(buf5); + printk("fast_timer_test() done\n"); +} +#endif + + +int fast_timer_init(void) +{ + /* For some reason, request_irq() hangs when called froom time_init() */ + if (!fast_timer_is_init) + { +#if 0 && defined(FAST_TIMER_TEST) + int i; +#endif + + printk(KERN_INFO "fast_timer_init()\n"); + +#if 0 && defined(FAST_TIMER_TEST) + for (i = 0; i <= TIMER0_DIV; i++) + { + /* We must be careful not to get overflow... */ + printk("%3i %6u\n", i, timer0_value_us[i]); + } +#endif +#ifdef CONFIG_PROC_FS + proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops); +#endif /* PROC_FS */ + if(request_irq(TIMER1_IRQ_NBR, timer1_handler, 0, + "fast timer int", NULL)) + { + printk("err: timer1 irq\n"); + } + fast_timer_is_init = 1; +#ifdef FAST_TIMER_TEST + printk("do test\n"); + fast_timer_test(); +#endif + } + return 0; +} +__initcall(fast_timer_init); diff --git a/kernel/arch/cris/arch-v10/kernel/head.S b/kernel/arch/cris/arch-v10/kernel/head.S new file mode 100644 index 000000000..4a146e174 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/head.S @@ -0,0 +1,723 @@ +/* + * Head of the kernel - alter with care + * + * Copyright (C) 2000, 2001, 2010 Axis Communications AB + * + */ + +#define ASSEMBLER_MACROS_ONLY +/* The IO_* macros use the ## token concatenation operator, so + -traditional must not be used when assembling this file. */ +#include + +#define CRAMFS_MAGIC 0x28cd3d45 +#define RAM_INIT_MAGIC 0x56902387 +#define COMMAND_LINE_MAGIC 0x87109563 + +#define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\ + IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk) + + ;; exported symbols + + .globl etrax_irv + .globl romfs_start + .globl romfs_length + .globl romfs_in_flash + .globl swapper_pg_dir + + .text + + ;; This is the entry point of the kernel. We are in supervisor mode. + ;; 0x00000000 if Flash, 0x40004000 if DRAM + ;; since etrax actually starts at address 2 when booting from flash, we + ;; put a nop (2 bytes) here first so we dont accidentally skip the di + ;; + ;; NOTICE! The registers r8 and r9 are used as parameters carrying + ;; information from the decompressor (if the kernel was compressed). + ;; They should not be used in the code below until read. + + nop + di + + ;; First setup the kseg_c mapping from where the kernel is linked + ;; to 0x40000000 (where the actual DRAM resides) otherwise + ;; we cannot do very much! See arch/cris/README.mm + ;; + ;; Notice that since we're potentially running at 0x00 or 0x40 right now, + ;; we will get a fault as soon as we enable the MMU if we dont + ;; temporarily map those segments linearily. + ;; + ;; Due to a bug in Etrax-100 LX version 1 we need to map the memory + ;; slightly different. The bug is that you can't remap bit 31 of + ;; an address. Though we can check the version register for + ;; whether the bug is present, some constants would then have to + ;; be variables, so we don't. The drawback is that you can "only" map + ;; 1G per process with CONFIG_CRIS_LOW_MAP. + +#ifdef CONFIG_CRIS_LOW_MAP + ; kseg mappings, temporary map of 0xc0->0x40 + move.d IO_FIELD (R_MMU_KBASE_HI, base_c, 4) \ + | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb) \ + | IO_FIELD (R_MMU_KBASE_HI, base_9, 9) \ + | IO_FIELD (R_MMU_KBASE_HI, base_8, 8), $r0 + move.d $r0, [R_MMU_KBASE_HI] + + ; temporary map of 0x40->0x40 and 0x60->0x40 + move.d IO_FIELD (R_MMU_KBASE_LO, base_6, 4) \ + | IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0 + move.d $r0, [R_MMU_KBASE_LO] + + ; mmu enable, segs e,c,b,a,6,5,4,0 segment mapped + move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \ + | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \ + | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \ + | IO_STATE (R_MMU_CONFIG, we_excp, enable) \ + | IO_STATE (R_MMU_CONFIG, seg_f, page) \ + | IO_STATE (R_MMU_CONFIG, seg_e, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_d, page) \ + | IO_STATE (R_MMU_CONFIG, seg_c, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_b, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_a, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_9, page) \ + | IO_STATE (R_MMU_CONFIG, seg_8, page) \ + | IO_STATE (R_MMU_CONFIG, seg_7, page) \ + | IO_STATE (R_MMU_CONFIG, seg_6, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_5, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_4, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_3, page) \ + | IO_STATE (R_MMU_CONFIG, seg_2, page) \ + | IO_STATE (R_MMU_CONFIG, seg_1, page) \ + | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0 + move.d $r0, [R_MMU_CONFIG] +#else + ; kseg mappings + move.d IO_FIELD (R_MMU_KBASE_HI, base_e, 8) \ + | IO_FIELD (R_MMU_KBASE_HI, base_c, 4) \ + | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb), $r0 + move.d $r0, [R_MMU_KBASE_HI] + + ; temporary map of 0x40->0x40 and 0x00->0x00 + move.d IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0 + move.d $r0, [R_MMU_KBASE_LO] + + ; mmu enable, segs f,e,c,b,4,0 segment mapped + move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \ + | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \ + | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \ + | IO_STATE (R_MMU_CONFIG, we_excp, enable) \ + | IO_STATE (R_MMU_CONFIG, seg_f, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_e, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_d, page) \ + | IO_STATE (R_MMU_CONFIG, seg_c, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_b, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_a, page) \ + | IO_STATE (R_MMU_CONFIG, seg_9, page) \ + | IO_STATE (R_MMU_CONFIG, seg_8, page) \ + | IO_STATE (R_MMU_CONFIG, seg_7, page) \ + | IO_STATE (R_MMU_CONFIG, seg_6, page) \ + | IO_STATE (R_MMU_CONFIG, seg_5, page) \ + | IO_STATE (R_MMU_CONFIG, seg_4, seg) \ + | IO_STATE (R_MMU_CONFIG, seg_3, page) \ + | IO_STATE (R_MMU_CONFIG, seg_2, page) \ + | IO_STATE (R_MMU_CONFIG, seg_1, page) \ + | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0 + move.d $r0, [R_MMU_CONFIG] +#endif + + ;; Now we need to sort out the segments and their locations in RAM or + ;; Flash. The image in the Flash (or in DRAM) consists of 3 pieces: + ;; 1) kernel text, 2) kernel data, 3) ROM filesystem image + ;; But the linker has linked the kernel to expect this layout in + ;; DRAM memory: + ;; 1) kernel text, 2) kernel data, 3) kernel BSS + ;; (the location of the ROM filesystem is determined by the krom driver) + ;; If we boot this from Flash, we want to keep the ROM filesystem in + ;; the flash, we want to copy the text and need to copy the data to DRAM. + ;; But if we boot from DRAM, we need to move the ROMFS image + ;; from its position after kernel data, to after kernel BSS, BEFORE the + ;; kernel starts using the BSS area (since its "overlayed" with the ROMFS) + ;; + ;; In both cases, we start in un-cached mode, and need to jump into a + ;; cached PC after we're done fiddling around with the segments. + ;; + ;; arch/etrax100/etrax100.ld sets some symbols that define the start + ;; and end of each segment. + + ;; Check if we start from DRAM or FLASH by testing PC + + move.d $pc,$r0 + and.d 0x7fffffff,$r0 ; get rid of the non-cache bit + cmp.d 0x10000,$r0 ; arbitrary... just something above this code + blo _inflash0 + nop + + jump _inram ; enter cached ram + + ;; Jumpgate for branches. +_inflash0: + jump _inflash + + ;; Put this in a suitable section where we can reclaim storage + ;; after init. + .section ".init.text", "ax" +_inflash: +#ifdef CONFIG_ETRAX_ETHERNET + ;; Start MII clock to make sure it is running when tranceiver is reset + move.d START_ETHERNET_CLOCK, $r0 + move.d $r0, [R_NETWORK_GEN_CONFIG] +#endif + + ;; Set up waitstates etc according to kernel configuration. + move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0 + move.d $r0, [R_WAITSTATES] + + move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0 + move.d $r0, [R_BUS_CONFIG] + + ;; We need to initialze DRAM registers before we start using the DRAM + + cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? + beq _dram_init_finished + nop + +#include "../lib/dram_init.S" + +_dram_init_finished: + ;; Copy text+data to DRAM + ;; This is fragile - the calculation of r4 as the image size depends + ;; on that the labels below actually are the first and last positions + ;; in the linker-script. + ;; + ;; Then the locating of the cramfs image depends on the aforementioned + ;; image being located in the flash at 0. This is most often not true, + ;; thus the following does not work (normally there is a rescue-block + ;; between the physical start of the flash and the flash-image start, + ;; and when run with compression, the kernel is actually unpacked to + ;; DRAM and we never get here in the first place :)) + + moveq 0, $r0 ; source + move.d text_start, $r1 ; destination + move.d __vmlinux_end, $r2 ; end destination + move.d $r2, $r4 + sub.d $r1, $r4 ; r4=__vmlinux_end in flash, used below +1: move.w [$r0+], $r3 + move.w $r3, [$r1+] + cmp.d $r2, $r1 + blo 1b + nop + + ;; We keep the cramfs in the flash. + ;; There might be none, but that does not matter because + ;; we don't do anything than read some bytes here. + + moveq 0, $r0 + move.d $r0, [romfs_length] ; default if there is no cramfs + + move.d [$r4], $r0 ; cramfs_super.magic + cmp.d CRAMFS_MAGIC, $r0 + bne 1f + nop + move.d [$r4 + 4], $r0 ; cramfs_super.size + move.d $r0, [romfs_length] +#ifdef CONFIG_CRIS_LOW_MAP + add.d 0x50000000, $r4 ; add flash start in virtual memory (cached) +#else + add.d 0xf0000000, $r4 ; add flash start in virtual memory (cached) +#endif + move.d $r4, [romfs_start] +1: + moveq 1, $r0 + move.d $r0, [romfs_in_flash] + + jump _start_it ; enter code, cached this time + +_inram: + ;; Move the ROM fs to after BSS end. This assumes that the cramfs + ;; second longword contains the length of the cramfs + + moveq 0, $r0 + move.d $r0, [romfs_length] ; default if there is no cramfs + + ;; The kernel could have been unpacked to DRAM by the loader, but + ;; the cramfs image could still be in the Flash directly after the + ;; compressed kernel image. The loader passes the address of the + ;; byte succeeding the last compressed byte in the flash in the + ;; register r9 when starting the kernel. Check if r9 points to a + ;; decent cramfs image! + ;; (Notice that if this is not booted from the loader, r9 will be + ;; garbage but we do sanity checks on it, the chance that it points + ;; to a cramfs magic is small.. ) + + cmp.d 0x0ffffff8, $r9 + bhs _no_romfs_in_flash ; r9 points outside the flash area + nop + move.d [$r9], $r0 ; cramfs_super.magic + cmp.d CRAMFS_MAGIC, $r0 + bne _no_romfs_in_flash + nop + move.d [$r9+4], $r0 ; cramfs_super.length + move.d $r0, [romfs_length] +#ifdef CONFIG_CRIS_LOW_MAP + add.d 0x50000000, $r9 ; add flash start in virtual memory (cached) +#else + add.d 0xf0000000, $r9 ; add flash start in virtual memory (cached) +#endif + move.d $r9, [romfs_start] + + moveq 1, $r0 + move.d $r0, [romfs_in_flash] + + jump _start_it ; enter code, cached this time + +_no_romfs_in_flash: + + ;; Check if there is a cramfs (magic value). + ;; Notice that we check for cramfs magic value - which is + ;; the "rom fs" we'll possibly use in 2.4 if not JFFS (which does + ;; not need this mechanism anyway) + + move.d __init_end, $r0; the image will be after the end of init + move.d [$r0], $r1 ; cramfs assumes same endian on host/target + cmp.d CRAMFS_MAGIC, $r1; magic value in cramfs superblock + bne 2f + nop + + ;; Ok. What is its size ? + + move.d [$r0 + 4], $r2 ; cramfs_super.size (again, no need to swapwb) + + ;; We want to copy it to the end of the BSS + + move.d _end, $r1 + + ;; Remember values so cramfs and setup can find this info + + move.d $r1, [romfs_start] ; new romfs location + move.d $r2, [romfs_length] + + ;; We need to copy it backwards, since they can be overlapping + + add.d $r2, $r0 + add.d $r2, $r1 + + ;; Go ahead. Make my loop. + + lsrq 1, $r2 ; size is in bytes, we copy words + +1: move.w [$r0=$r0-2],$r3 + move.w $r3,[$r1=$r1-2] + subq 1, $r2 + bne 1b + nop + +2: + ;; Dont worry that the BSS is tainted. It will be cleared later. + + moveq 0, $r0 + move.d $r0, [romfs_in_flash] + + jump _start_it ; better skip the additional cramfs check below + +_start_it: + + ;; Check if kernel command line is supplied + cmp.d COMMAND_LINE_MAGIC, $r10 + bne no_command_line + nop + + move.d 256, $r13 + move.d cris_command_line, $r10 + or.d 0x80000000, $r11 ; Make it virtual +1: + move.b [$r11+], $r12 + move.b $r12, [$r10+] + subq 1, $r13 + bne 1b + nop + +no_command_line: + + ;; the kernel stack is overlayed with the task structure for each + ;; task. thus the initial kernel stack is in the same page as the + ;; init_task (but starts in the top of the page, size 8192) + move.d init_thread_union + 8192, $sp + move.d ibr_start,$r0 ; this symbol is set by the linker script + move $r0,$ibr + move.d $r0,[etrax_irv] ; set the interrupt base register and pointer + + ;; Clear BSS region, from _bss_start to _end + + move.d __bss_start, $r0 + move.d _end, $r1 +1: clear.d [$r0+] + cmp.d $r1, $r0 + blo 1b + nop + +#ifdef CONFIG_BLK_DEV_ETRAXIDE + ;; disable ATA before enabling it in genconfig below + moveq 0,$r0 + move.d $r0,[R_ATA_CTRL_DATA] + move.d $r0,[R_ATA_TRANSFER_CNT] + move.d $r0,[R_ATA_CONFIG] +#if 0 + move.d R_PORT_G_DATA, $r1 + move.d $r0, [$r1]; assert ATA bus-reset + nop + nop + nop + nop + nop + nop + move.d 0x08000000,$r0 + move.d $r0,[$r1] +#endif +#endif + +#ifdef CONFIG_JULIETTE + ;; configure external DMA channel 0 before enabling it in genconfig + + moveq 0,$r0 + move.d $r0,[R_EXT_DMA_0_ADDR] + ; cnt enable, word size, output, stop, size 0 + move.d IO_STATE (R_EXT_DMA_0_CMD, cnt, enable) \ + | IO_STATE (R_EXT_DMA_0_CMD, rqpol, ahigh) \ + | IO_STATE (R_EXT_DMA_0_CMD, apol, ahigh) \ + | IO_STATE (R_EXT_DMA_0_CMD, rq_ack, burst) \ + | IO_STATE (R_EXT_DMA_0_CMD, wid, word) \ + | IO_STATE (R_EXT_DMA_0_CMD, dir, output) \ + | IO_STATE (R_EXT_DMA_0_CMD, run, stop) \ + | IO_FIELD (R_EXT_DMA_0_CMD, trf_count, 0),$r0 + move.d $r0,[R_EXT_DMA_0_CMD] + + ;; reset dma4 and wait for completion + + moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0 + move.b $r0,[R_DMA_CH4_CMD] +1: move.b [R_DMA_CH4_CMD],$r0 + and.b IO_MASK (R_DMA_CH4_CMD, cmd),$r0 + cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0 + beq 1b + nop + + ;; reset dma5 and wait for completion + + moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0 + move.b $r0,[R_DMA_CH5_CMD] +1: move.b [R_DMA_CH5_CMD],$r0 + and.b IO_MASK (R_DMA_CH5_CMD, cmd),$r0 + cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0 + beq 1b + nop +#endif + + ;; Etrax product HW genconfig setup + + moveq 0,$r0 + + ;; Select or disable serial port 2 +#ifdef CONFIG_ETRAX_SERIAL_PORT2 + or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0 +#else + or.d IO_STATE (R_GEN_CONFIG, ser2, disable),$r0 +#endif + + ;; Init interfaces (disable them). + or.d IO_STATE (R_GEN_CONFIG, scsi0, disable) \ + | IO_STATE (R_GEN_CONFIG, ata, disable) \ + | IO_STATE (R_GEN_CONFIG, par0, disable) \ + | IO_STATE (R_GEN_CONFIG, mio, disable) \ + | IO_STATE (R_GEN_CONFIG, scsi1, disable) \ + | IO_STATE (R_GEN_CONFIG, scsi0w, disable) \ + | IO_STATE (R_GEN_CONFIG, par1, disable) \ + | IO_STATE (R_GEN_CONFIG, ser3, disable) \ + | IO_STATE (R_GEN_CONFIG, mio_w, disable) \ + | IO_STATE (R_GEN_CONFIG, usb1, disable) \ + | IO_STATE (R_GEN_CONFIG, usb2, disable) \ + | IO_STATE (R_GEN_CONFIG, par_w, disable),$r0 + + ;; Init DMA channel muxing (set to unused clients). + or.d IO_STATE (R_GEN_CONFIG, dma2, ata) \ + | IO_STATE (R_GEN_CONFIG, dma3, ata) \ + | IO_STATE (R_GEN_CONFIG, dma4, scsi1) \ + | IO_STATE (R_GEN_CONFIG, dma5, scsi1) \ + | IO_STATE (R_GEN_CONFIG, dma6, unused) \ + | IO_STATE (R_GEN_CONFIG, dma7, unused) \ + | IO_STATE (R_GEN_CONFIG, dma8, usb) \ + | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0 + + +#if defined(CONFIG_ETRAX_DEF_R_PORT_G0_DIR_OUT) + or.d IO_STATE (R_GEN_CONFIG, g0dir, out),$r0 +#endif + +#if defined(CONFIG_ETRAX_DEF_R_PORT_G8_15_DIR_OUT) + or.d IO_STATE (R_GEN_CONFIG, g8_15dir, out),$r0 +#endif +#if defined(CONFIG_ETRAX_DEF_R_PORT_G16_23_DIR_OUT) + or.d IO_STATE (R_GEN_CONFIG, g16_23dir, out),$r0 +#endif + +#if defined(CONFIG_ETRAX_DEF_R_PORT_G24_DIR_OUT) + or.d IO_STATE (R_GEN_CONFIG, g24dir, out),$r0 +#endif + + move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG + + move.d $r0,[R_GEN_CONFIG] + +#if 0 + moveq 4,$r0 + move.b $r0,[R_DMA_CH6_CMD] ; reset (ser0 dma out) + move.b $r0,[R_DMA_CH7_CMD] ; reset (ser0 dma in) +1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish + and.b 7,$r0 + cmp.b 4,$r0 + beq 1b + nop +1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish + and.b 7,$r0 + cmp.b 4,$r0 + beq 1b + nop +#endif + + moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0 + move.b $r0,[R_DMA_CH8_CMD] ; reset (ser1 dma out) + move.b $r0,[R_DMA_CH9_CMD] ; reset (ser1 dma in) +1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish + andq IO_MASK (R_DMA_CH8_CMD, cmd),$r0 + cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0 + beq 1b + nop +1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish + andq IO_MASK (R_DMA_CH9_CMD, cmd),$r0 + cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0 + beq 1b + nop + + ;; setup port PA and PB default initial directions and data + ;; including their shadow registers + + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0 +#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7) + or.b IO_STATE (R_PORT_PA_DIR, dir7, output),$r0 +#endif + move.b $r0,[port_pa_dir_shadow] + move.b $r0,[R_PORT_PA_DIR] + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0 +#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7) +#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH) + and.b ~(1 << 7),$r0 +#else + or.b (1 << 7),$r0 +#endif +#endif + move.b $r0,[port_pa_data_shadow] + move.b $r0,[R_PORT_PA_DATA] + + move.b CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG,$r0 + move.b $r0,[port_pb_config_shadow] + move.b $r0,[R_PORT_PB_CONFIG] + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0 +#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5) + or.b IO_STATE (R_PORT_PB_DIR, dir5, output),$r0 +#endif + move.b $r0,[port_pb_dir_shadow] + move.b $r0,[R_PORT_PB_DIR] + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0 +#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5) +#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH) + and.b ~(1 << 5),$r0 +#else + or.b (1 << 5),$r0 +#endif +#endif + move.b $r0,[port_pb_data_shadow] + move.b $r0,[R_PORT_PB_DATA] + + moveq 0, $r0 + move.d $r0,[port_pb_i2c_shadow] + move.d $r0, [R_PORT_PB_I2C] + + moveq 0,$r0 +#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G10) +#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH) + and.d ~(1 << 10),$r0 +#else + or.d (1 << 10),$r0 +#endif +#endif +#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G11) +#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH) + and.d ~(1 << 11),$r0 +#else + or.d (1 << 11),$r0 +#endif +#endif + move.d $r0,[port_g_data_shadow] + move.d $r0,[R_PORT_G_DATA] + + ;; setup the serial port 0 at 115200 baud for debug purposes + + moveq IO_STATE (R_SERIAL0_XOFF, tx_stop, enable) \ + | IO_STATE (R_SERIAL0_XOFF, auto_xoff, disable) \ + | IO_FIELD (R_SERIAL0_XOFF, xoff_char, 0),$r0 + move.d $r0,[R_SERIAL0_XOFF] + + ; 115.2kbaud for both transmit and receive + move.b IO_STATE (R_SERIAL0_BAUD, tr_baud, c115k2Hz) \ + | IO_STATE (R_SERIAL0_BAUD, rec_baud, c115k2Hz),$r0 + move.b $r0,[R_SERIAL0_BAUD] + + ; Set up and enable the serial0 receiver. + move.b IO_STATE (R_SERIAL0_REC_CTRL, dma_err, stop) \ + | IO_STATE (R_SERIAL0_REC_CTRL, rec_enable, enable) \ + | IO_STATE (R_SERIAL0_REC_CTRL, rts_, active) \ + | IO_STATE (R_SERIAL0_REC_CTRL, sampling, middle) \ + | IO_STATE (R_SERIAL0_REC_CTRL, rec_stick_par, normal) \ + | IO_STATE (R_SERIAL0_REC_CTRL, rec_par, even) \ + | IO_STATE (R_SERIAL0_REC_CTRL, rec_par_en, disable) \ + | IO_STATE (R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit),$r0 + move.b $r0,[R_SERIAL0_REC_CTRL] + + ; Set up and enable the serial0 transmitter. + move.b IO_FIELD (R_SERIAL0_TR_CTRL, txd, 0) \ + | IO_STATE (R_SERIAL0_TR_CTRL, tr_enable, enable) \ + | IO_STATE (R_SERIAL0_TR_CTRL, auto_cts, disabled) \ + | IO_STATE (R_SERIAL0_TR_CTRL, stop_bits, one_bit) \ + | IO_STATE (R_SERIAL0_TR_CTRL, tr_stick_par, normal) \ + | IO_STATE (R_SERIAL0_TR_CTRL, tr_par, even) \ + | IO_STATE (R_SERIAL0_TR_CTRL, tr_par_en, disable) \ + | IO_STATE (R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit),$r0 + move.b $r0,[R_SERIAL0_TR_CTRL] + + ;; setup the serial port 1 at 115200 baud for debug purposes + + moveq IO_STATE (R_SERIAL1_XOFF, tx_stop, enable) \ + | IO_STATE (R_SERIAL1_XOFF, auto_xoff, disable) \ + | IO_FIELD (R_SERIAL1_XOFF, xoff_char, 0),$r0 + move.d $r0,[R_SERIAL1_XOFF] + + ; 115.2kbaud for both transmit and receive + move.b IO_STATE (R_SERIAL1_BAUD, tr_baud, c115k2Hz) \ + | IO_STATE (R_SERIAL1_BAUD, rec_baud, c115k2Hz),$r0 + move.b $r0,[R_SERIAL1_BAUD] + + ; Set up and enable the serial1 receiver. + move.b IO_STATE (R_SERIAL1_REC_CTRL, dma_err, stop) \ + | IO_STATE (R_SERIAL1_REC_CTRL, rec_enable, enable) \ + | IO_STATE (R_SERIAL1_REC_CTRL, rts_, active) \ + | IO_STATE (R_SERIAL1_REC_CTRL, sampling, middle) \ + | IO_STATE (R_SERIAL1_REC_CTRL, rec_stick_par, normal) \ + | IO_STATE (R_SERIAL1_REC_CTRL, rec_par, even) \ + | IO_STATE (R_SERIAL1_REC_CTRL, rec_par_en, disable) \ + | IO_STATE (R_SERIAL1_REC_CTRL, rec_bitnr, rec_8bit),$r0 + move.b $r0,[R_SERIAL1_REC_CTRL] + + ; Set up and enable the serial1 transmitter. + move.b IO_FIELD (R_SERIAL1_TR_CTRL, txd, 0) \ + | IO_STATE (R_SERIAL1_TR_CTRL, tr_enable, enable) \ + | IO_STATE (R_SERIAL1_TR_CTRL, auto_cts, disabled) \ + | IO_STATE (R_SERIAL1_TR_CTRL, stop_bits, one_bit) \ + | IO_STATE (R_SERIAL1_TR_CTRL, tr_stick_par, normal) \ + | IO_STATE (R_SERIAL1_TR_CTRL, tr_par, even) \ + | IO_STATE (R_SERIAL1_TR_CTRL, tr_par_en, disable) \ + | IO_STATE (R_SERIAL1_TR_CTRL, tr_bitnr, tr_8bit),$r0 + move.b $r0,[R_SERIAL1_TR_CTRL] + +#ifdef CONFIG_ETRAX_SERIAL_PORT2 + ;; setup the serial port 2 at 115200 baud for debug purposes + + moveq IO_STATE (R_SERIAL2_XOFF, tx_stop, enable) \ + | IO_STATE (R_SERIAL2_XOFF, auto_xoff, disable) \ + | IO_FIELD (R_SERIAL2_XOFF, xoff_char, 0),$r0 + move.d $r0,[R_SERIAL2_XOFF] + + ; 115.2kbaud for both transmit and receive + move.b IO_STATE (R_SERIAL2_BAUD, tr_baud, c115k2Hz) \ + | IO_STATE (R_SERIAL2_BAUD, rec_baud, c115k2Hz),$r0 + move.b $r0,[R_SERIAL2_BAUD] + + ; Set up and enable the serial2 receiver. + move.b IO_STATE (R_SERIAL2_REC_CTRL, dma_err, stop) \ + | IO_STATE (R_SERIAL2_REC_CTRL, rec_enable, enable) \ + | IO_STATE (R_SERIAL2_REC_CTRL, rts_, active) \ + | IO_STATE (R_SERIAL2_REC_CTRL, sampling, middle) \ + | IO_STATE (R_SERIAL2_REC_CTRL, rec_stick_par, normal) \ + | IO_STATE (R_SERIAL2_REC_CTRL, rec_par, even) \ + | IO_STATE (R_SERIAL2_REC_CTRL, rec_par_en, disable) \ + | IO_STATE (R_SERIAL2_REC_CTRL, rec_bitnr, rec_8bit),$r0 + move.b $r0,[R_SERIAL2_REC_CTRL] + + ; Set up and enable the serial2 transmitter. + move.b IO_FIELD (R_SERIAL2_TR_CTRL, txd, 0) \ + | IO_STATE (R_SERIAL2_TR_CTRL, tr_enable, enable) \ + | IO_STATE (R_SERIAL2_TR_CTRL, auto_cts, disabled) \ + | IO_STATE (R_SERIAL2_TR_CTRL, stop_bits, one_bit) \ + | IO_STATE (R_SERIAL2_TR_CTRL, tr_stick_par, normal) \ + | IO_STATE (R_SERIAL2_TR_CTRL, tr_par, even) \ + | IO_STATE (R_SERIAL2_TR_CTRL, tr_par_en, disable) \ + | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0 + move.b $r0,[R_SERIAL2_TR_CTRL] +#endif + +#ifdef CONFIG_ETRAX_SERIAL_PORT3 + ;; setup the serial port 3 at 115200 baud for debug purposes + + moveq IO_STATE (R_SERIAL3_XOFF, tx_stop, enable) \ + | IO_STATE (R_SERIAL3_XOFF, auto_xoff, disable) \ + | IO_FIELD (R_SERIAL3_XOFF, xoff_char, 0),$r0 + move.d $r0,[R_SERIAL3_XOFF] + + ; 115.2kbaud for both transmit and receive + move.b IO_STATE (R_SERIAL3_BAUD, tr_baud, c115k2Hz) \ + | IO_STATE (R_SERIAL3_BAUD, rec_baud, c115k2Hz),$r0 + move.b $r0,[R_SERIAL3_BAUD] + + ; Set up and enable the serial3 receiver. + move.b IO_STATE (R_SERIAL3_REC_CTRL, dma_err, stop) \ + | IO_STATE (R_SERIAL3_REC_CTRL, rec_enable, enable) \ + | IO_STATE (R_SERIAL3_REC_CTRL, rts_, active) \ + | IO_STATE (R_SERIAL3_REC_CTRL, sampling, middle) \ + | IO_STATE (R_SERIAL3_REC_CTRL, rec_stick_par, normal) \ + | IO_STATE (R_SERIAL3_REC_CTRL, rec_par, even) \ + | IO_STATE (R_SERIAL3_REC_CTRL, rec_par_en, disable) \ + | IO_STATE (R_SERIAL3_REC_CTRL, rec_bitnr, rec_8bit),$r0 + move.b $r0,[R_SERIAL3_REC_CTRL] + + ; Set up and enable the serial3 transmitter. + move.b IO_FIELD (R_SERIAL3_TR_CTRL, txd, 0) \ + | IO_STATE (R_SERIAL3_TR_CTRL, tr_enable, enable) \ + | IO_STATE (R_SERIAL3_TR_CTRL, auto_cts, disabled) \ + | IO_STATE (R_SERIAL3_TR_CTRL, stop_bits, one_bit) \ + | IO_STATE (R_SERIAL3_TR_CTRL, tr_stick_par, normal) \ + | IO_STATE (R_SERIAL3_TR_CTRL, tr_par, even) \ + | IO_STATE (R_SERIAL3_TR_CTRL, tr_par_en, disable) \ + | IO_STATE (R_SERIAL3_TR_CTRL, tr_bitnr, tr_8bit),$r0 + move.b $r0,[R_SERIAL3_TR_CTRL] +#endif + + jump start_kernel ; jump into the C-function start_kernel in init/main.c + + .data +etrax_irv: + .dword 0 +romfs_start: + .dword 0 +romfs_length: + .dword 0 +romfs_in_flash: + .dword 0 + + ;; put some special pages at the beginning of the kernel aligned + ;; to page boundaries - the kernel cannot start until after this + +#ifdef CONFIG_CRIS_LOW_MAP +swapper_pg_dir = 0x60002000 +#else +swapper_pg_dir = 0xc0002000 +#endif + + .section ".init.data", "aw" +#include "../lib/hw_settings.S" diff --git a/kernel/arch/cris/arch-v10/kernel/io_interface_mux.c b/kernel/arch/cris/arch-v10/kernel/io_interface_mux.c new file mode 100644 index 000000000..ad64cd1c8 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/io_interface_mux.c @@ -0,0 +1,1182 @@ +/* IO interface mux allocator for ETRAX100LX. + * Copyright 2004-2007, Axis Communications AB + */ + + +/* C.f. ETRAX100LX Designer's Reference chapter 19.9 */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +#define DBG(s) + +/* Macro to access ETRAX 100 registers */ +#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \ + IO_STATE_(reg##_, field##_, _##val) + +enum io_if_group { + group_a = (1<<0), + group_b = (1<<1), + group_c = (1<<2), + group_d = (1<<3), + group_e = (1<<4), + group_f = (1<<5) +}; + +struct watcher +{ + void (*notify)(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available); + struct watcher *next; +}; + + +struct if_group +{ + enum io_if_group group; + /* name - the name of the group 'A' to 'F' */ + char *name; + /* used - a bit mask of all pins in the group in the order listed + * in the tables in 19.9.1 to 19.9.6. Note that no + * distinction is made between in, out and in/out pins. */ + unsigned int used; +}; + + +struct interface +{ + enum cris_io_interface ioif; + /* name - the name of the interface */ + char *name; + /* groups - OR'ed together io_if_group flags describing what pin groups + * the interface uses pins in. */ + unsigned char groups; + /* used - set when the interface is allocated. */ + unsigned char used; + char *owner; + /* group_a through group_f - bit masks describing what pins in the + * pin groups the interface uses. */ + unsigned int group_a; + unsigned int group_b; + unsigned int group_c; + unsigned int group_d; + unsigned int group_e; + unsigned int group_f; + + /* gpio_g_in, gpio_g_out, gpio_b - bit masks telling what pins in the + * GPIO ports the interface uses. This could be reconstucted using + * the group_X masks and a table of what pins the GPIO ports use, + * but that would be messy. */ + unsigned int gpio_g_in; + unsigned int gpio_g_out; + unsigned char gpio_b; +}; + +static struct if_group if_groups[6] = { + { + .group = group_a, + .name = "A", + .used = 0, + }, + { + .group = group_b, + .name = "B", + .used = 0, + }, + { + .group = group_c, + .name = "C", + .used = 0, + }, + { + .group = group_d, + .name = "D", + .used = 0, + }, + { + .group = group_e, + .name = "E", + .used = 0, + }, + { + .group = group_f, + .name = "F", + .used = 0, + } +}; + +/* The order in the array must match the order of enum + * cris_io_interface in io_interface_mux.h */ +static struct interface interfaces[] = { + /* Begin Non-multiplexed interfaces */ + { + .ioif = if_eth, + .name = "ethernet", + .groups = 0, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0, + .gpio_g_out = 0, + .gpio_b = 0 + }, + { + .ioif = if_serial_0, + .name = "serial_0", + .groups = 0, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0, + .gpio_g_out = 0, + .gpio_b = 0 + }, + /* End Non-multiplexed interfaces */ + { + .ioif = if_serial_1, + .name = "serial_1", + .groups = group_e, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0x0f, + .group_f = 0, + + .gpio_g_in = 0x00000000, + .gpio_g_out = 0x00000000, + .gpio_b = 0x00 + }, + { + .ioif = if_serial_2, + .name = "serial_2", + .groups = group_b, + + .group_a = 0, + .group_b = 0x0f, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x000000c0, + .gpio_g_out = 0x000000c0, + .gpio_b = 0x00 + }, + { + .ioif = if_serial_3, + .name = "serial_3", + .groups = group_c, + + .group_a = 0, + .group_b = 0, + .group_c = 0x0f, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0xc0000000, + .gpio_g_out = 0xc0000000, + .gpio_b = 0x00 + }, + { + .ioif = if_sync_serial_1, + .name = "sync_serial_1", + .groups = group_e | group_f, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0x0f, + .group_f = 0x10, + + .gpio_g_in = 0x00000000, + .gpio_g_out = 0x00000000, + .gpio_b = 0x10 + }, + { + .ioif = if_sync_serial_3, + .name = "sync_serial_3", + .groups = group_c | group_f, + + .group_a = 0, + .group_b = 0, + .group_c = 0x0f, + .group_d = 0, + .group_e = 0, + .group_f = 0x80, + + .gpio_g_in = 0xc0000000, + .gpio_g_out = 0xc0000000, + .gpio_b = 0x80 + }, + { + .ioif = if_shared_ram, + .name = "shared_ram", + .groups = group_a, + + .group_a = 0x7f8ff, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x0000ff3e, + .gpio_g_out = 0x0000ff38, + .gpio_b = 0x00 + }, + { + .ioif = if_shared_ram_w, + .name = "shared_ram_w", + .groups = group_a | group_d, + + .group_a = 0x7f8ff, + .group_b = 0, + .group_c = 0, + .group_d = 0xff, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x00ffff3e, + .gpio_g_out = 0x00ffff38, + .gpio_b = 0x00 + }, + { + .ioif = if_par_0, + .name = "par_0", + .groups = group_a, + + .group_a = 0x7fbff, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x0000ff3e, + .gpio_g_out = 0x0000ff3e, + .gpio_b = 0x00 + }, + { + .ioif = if_par_1, + .name = "par_1", + .groups = group_d, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0x7feff, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x3eff0000, + .gpio_g_out = 0x3eff0000, + .gpio_b = 0x00 + }, + { + .ioif = if_par_w, + .name = "par_w", + .groups = group_a | group_d, + + .group_a = 0x7fbff, + .group_b = 0, + .group_c = 0, + .group_d = 0xff, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x00ffff3e, + .gpio_g_out = 0x00ffff3e, + .gpio_b = 0x00 + }, + { + .ioif = if_scsi8_0, + .name = "scsi8_0", + .groups = group_a | group_b | group_f, + + .group_a = 0x7ffff, + .group_b = 0x0f, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0x10, + + .gpio_g_in = 0x0000ffff, + .gpio_g_out = 0x0000ffff, + .gpio_b = 0x10 + }, + { + .ioif = if_scsi8_1, + .name = "scsi8_1", + .groups = group_c | group_d | group_f, + + .group_a = 0, + .group_b = 0, + .group_c = 0x0f, + .group_d = 0x7ffff, + .group_e = 0, + .group_f = 0x80, + + .gpio_g_in = 0xffff0000, + .gpio_g_out = 0xffff0000, + .gpio_b = 0x80 + }, + { + .ioif = if_scsi_w, + .name = "scsi_w", + .groups = group_a | group_b | group_d | group_f, + + .group_a = 0x7ffff, + .group_b = 0x0f, + .group_c = 0, + .group_d = 0x601ff, + .group_e = 0, + .group_f = 0x90, + + .gpio_g_in = 0x01ffffff, + .gpio_g_out = 0x07ffffff, + .gpio_b = 0x80 + }, + { + .ioif = if_ata, + .name = "ata", + .groups = group_a | group_b | group_c | group_d, + + .group_a = 0x7ffff, + .group_b = 0x0f, + .group_c = 0x0f, + .group_d = 0x7cfff, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0xf9ffffff, + .gpio_g_out = 0xffffffff, + .gpio_b = 0x80 + }, + { + .ioif = if_csp, + .name = "csp", + .groups = group_f, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0xfc, + + .gpio_g_in = 0x00000000, + .gpio_g_out = 0x00000000, + .gpio_b = 0xfc + }, + { + .ioif = if_i2c, + .name = "i2c", + .groups = group_f, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0x03, + + .gpio_g_in = 0x00000000, + .gpio_g_out = 0x00000000, + .gpio_b = 0x03 + }, + { + .ioif = if_usb_1, + .name = "usb_1", + .groups = group_e | group_f, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0x0f, + .group_f = 0x2c, + + .gpio_g_in = 0x00000000, + .gpio_g_out = 0x00000000, + .gpio_b = 0x2c + }, + { + .ioif = if_usb_2, + .name = "usb_2", + .groups = group_d, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0x33e00, + .group_f = 0, + + .gpio_g_in = 0x3e000000, + .gpio_g_out = 0x0c000000, + .gpio_b = 0x00 + }, + /* GPIO pins */ + { + .ioif = if_gpio_grp_a, + .name = "gpio_a", + .groups = group_a, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x0000ff3f, + .gpio_g_out = 0x0000ff3f, + .gpio_b = 0x00 + }, + { + .ioif = if_gpio_grp_b, + .name = "gpio_b", + .groups = group_b, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x000000c0, + .gpio_g_out = 0x000000c0, + .gpio_b = 0x00 + }, + { + .ioif = if_gpio_grp_c, + .name = "gpio_c", + .groups = group_c, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0xc0000000, + .gpio_g_out = 0xc0000000, + .gpio_b = 0x00 + }, + { + .ioif = if_gpio_grp_d, + .name = "gpio_d", + .groups = group_d, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x3fff0000, + .gpio_g_out = 0x3fff0000, + .gpio_b = 0x00 + }, + { + .ioif = if_gpio_grp_e, + .name = "gpio_e", + .groups = group_e, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x00000000, + .gpio_g_out = 0x00000000, + .gpio_b = 0x00 + }, + { + .ioif = if_gpio_grp_f, + .name = "gpio_f", + .groups = group_f, + + .group_a = 0, + .group_b = 0, + .group_c = 0, + .group_d = 0, + .group_e = 0, + .group_f = 0, + + .gpio_g_in = 0x00000000, + .gpio_g_out = 0x00000000, + .gpio_b = 0xff + } + /* Array end */ +}; + +static struct watcher *watchers = NULL; + +/* The pins that are free to use in the GPIO ports. */ +static unsigned int gpio_in_pins = 0xffffffff; +static unsigned int gpio_out_pins = 0xffffffff; +static unsigned char gpio_pb_pins = 0xff; +static unsigned char gpio_pa_pins = 0xff; + +/* Identifiers for the owners of the GPIO pins. */ +static enum cris_io_interface gpio_pa_owners[8]; +static enum cris_io_interface gpio_pb_owners[8]; +static enum cris_io_interface gpio_pg_owners[32]; + +static int cris_io_interface_init(void); + +static unsigned char clear_group_from_set(const unsigned char groups, struct if_group *group) +{ + return (groups & ~group->group); +} + + +static struct if_group *get_group(const unsigned char groups) +{ + int i; + for (i = 0; i < ARRAY_SIZE(if_groups); i++) { + if (groups & if_groups[i].group) { + return &if_groups[i]; + } + } + return NULL; +} + + +static void notify_watchers(void) +{ + struct watcher *w = watchers; + + DBG(printk("io_interface_mux: notifying watchers\n")); + + while (NULL != w) { + w->notify((const unsigned int)gpio_in_pins, + (const unsigned int)gpio_out_pins, + (const unsigned char)gpio_pa_pins, + (const unsigned char)gpio_pb_pins); + w = w->next; + } +} + + +int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id) +{ + int set_gen_config = 0; + int set_gen_config_ii = 0; + unsigned long int gens; + unsigned long int gens_ii; + struct if_group *grp; + unsigned char group_set; + unsigned long flags; + int res = 0; + + (void)cris_io_interface_init(); + + DBG(printk("cris_request_io_interface(%d, \"%s\")\n", ioif, device_id)); + + if ((ioif >= if_max_interfaces) || (ioif < 0)) { + printk(KERN_CRIT "cris_request_io_interface: Bad interface " + "%u submitted for %s\n", + ioif, + device_id); + return -EINVAL; + } + + local_irq_save(flags); + + if (interfaces[ioif].used) { + printk(KERN_CRIT "cris_io_interface: Cannot allocate interface " + "%s for %s, in use by %s\n", + interfaces[ioif].name, + device_id, + interfaces[ioif].owner); + res = -EBUSY; + goto exit; + } + + /* Check that all required pins in the used groups are free + * before allocating. */ + group_set = interfaces[ioif].groups; + while (NULL != (grp = get_group(group_set))) { + unsigned int if_group_use = 0; + + switch (grp->group) { + case group_a: + if_group_use = interfaces[ioif].group_a; + break; + case group_b: + if_group_use = interfaces[ioif].group_b; + break; + case group_c: + if_group_use = interfaces[ioif].group_c; + break; + case group_d: + if_group_use = interfaces[ioif].group_d; + break; + case group_e: + if_group_use = interfaces[ioif].group_e; + break; + case group_f: + if_group_use = interfaces[ioif].group_f; + break; + default: + BUG_ON(1); + } + + if (if_group_use & grp->used) { + printk(KERN_INFO "cris_request_io_interface: group " + "%s needed by %s not available\n", + grp->name, interfaces[ioif].name); + res = -EBUSY; + goto exit; + } + + group_set = clear_group_from_set(group_set, grp); + } + + /* Are the required GPIO pins available too? */ + if (((interfaces[ioif].gpio_g_in & gpio_in_pins) != + interfaces[ioif].gpio_g_in) || + ((interfaces[ioif].gpio_g_out & gpio_out_pins) != + interfaces[ioif].gpio_g_out) || + ((interfaces[ioif].gpio_b & gpio_pb_pins) != + interfaces[ioif].gpio_b)) { + printk(KERN_CRIT "cris_request_io_interface: Could not get " + "required pins for interface %u\n", ioif); + res = -EBUSY; + goto exit; + } + + /* Check which registers need to be reconfigured. */ + gens = genconfig_shadow; + gens_ii = gen_config_ii_shadow; + + set_gen_config = 1; + switch (ioif) + { + /* Begin Non-multiplexed interfaces */ + case if_eth: + /* fall through */ + case if_serial_0: + set_gen_config = 0; + break; + /* End Non-multiplexed interfaces */ + case if_serial_1: + set_gen_config_ii = 1; + SETS(gens_ii, R_GEN_CONFIG_II, sermode1, async); + break; + case if_serial_2: + SETS(gens, R_GEN_CONFIG, ser2, select); + break; + case if_serial_3: + SETS(gens, R_GEN_CONFIG, ser3, select); + set_gen_config_ii = 1; + SETS(gens_ii, R_GEN_CONFIG_II, sermode3, async); + break; + case if_sync_serial_1: + set_gen_config_ii = 1; + SETS(gens_ii, R_GEN_CONFIG_II, sermode1, sync); + break; + case if_sync_serial_3: + SETS(gens, R_GEN_CONFIG, ser3, select); + set_gen_config_ii = 1; + SETS(gens_ii, R_GEN_CONFIG_II, sermode3, sync); + break; + case if_shared_ram: + SETS(gens, R_GEN_CONFIG, mio, select); + break; + case if_shared_ram_w: + SETS(gens, R_GEN_CONFIG, mio_w, select); + break; + case if_par_0: + SETS(gens, R_GEN_CONFIG, par0, select); + break; + case if_par_1: + SETS(gens, R_GEN_CONFIG, par1, select); + break; + case if_par_w: + SETS(gens, R_GEN_CONFIG, par0, select); + SETS(gens, R_GEN_CONFIG, par_w, select); + break; + case if_scsi8_0: + SETS(gens, R_GEN_CONFIG, scsi0, select); + break; + case if_scsi8_1: + SETS(gens, R_GEN_CONFIG, scsi1, select); + break; + case if_scsi_w: + SETS(gens, R_GEN_CONFIG, scsi0, select); + SETS(gens, R_GEN_CONFIG, scsi0w, select); + break; + case if_ata: + SETS(gens, R_GEN_CONFIG, ata, select); + break; + case if_csp: + /* fall through */ + case if_i2c: + set_gen_config = 0; + break; + case if_usb_1: + SETS(gens, R_GEN_CONFIG, usb1, select); + break; + case if_usb_2: + SETS(gens, R_GEN_CONFIG, usb2, select); + break; + case if_gpio_grp_a: + /* GPIO groups are only accounted, don't do configuration changes. */ + /* fall through */ + case if_gpio_grp_b: + /* fall through */ + case if_gpio_grp_c: + /* fall through */ + case if_gpio_grp_d: + /* fall through */ + case if_gpio_grp_e: + /* fall through */ + case if_gpio_grp_f: + set_gen_config = 0; + break; + default: + printk(KERN_INFO "cris_request_io_interface: Bad interface " + "%u submitted for %s\n", + ioif, device_id); + res = -EBUSY; + goto exit; + } + + /* All needed I/O pins and pin groups are free, allocate. */ + group_set = interfaces[ioif].groups; + while (NULL != (grp = get_group(group_set))) { + unsigned int if_group_use = 0; + + switch (grp->group) { + case group_a: + if_group_use = interfaces[ioif].group_a; + break; + case group_b: + if_group_use = interfaces[ioif].group_b; + break; + case group_c: + if_group_use = interfaces[ioif].group_c; + break; + case group_d: + if_group_use = interfaces[ioif].group_d; + break; + case group_e: + if_group_use = interfaces[ioif].group_e; + break; + case group_f: + if_group_use = interfaces[ioif].group_f; + break; + default: + BUG_ON(1); + } + grp->used |= if_group_use; + + group_set = clear_group_from_set(group_set, grp); + } + + interfaces[ioif].used = 1; + interfaces[ioif].owner = (char*)device_id; + + if (set_gen_config) { + volatile int i; + genconfig_shadow = gens; + *R_GEN_CONFIG = genconfig_shadow; + /* Wait 12 cycles before doing any DMA command */ + for(i = 6; i > 0; i--) + nop(); + } + if (set_gen_config_ii) { + gen_config_ii_shadow = gens_ii; + *R_GEN_CONFIG_II = gen_config_ii_shadow; + } + + DBG(printk(KERN_DEBUG "GPIO pins: available before: " + "g_in=0x%08x g_out=0x%08x pb=0x%02x\n", + gpio_in_pins, gpio_out_pins, gpio_pb_pins)); + DBG(printk(KERN_DEBUG + "grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", + interfaces[ioif].gpio_g_in, + interfaces[ioif].gpio_g_out, + interfaces[ioif].gpio_b)); + + gpio_in_pins &= ~interfaces[ioif].gpio_g_in; + gpio_out_pins &= ~interfaces[ioif].gpio_g_out; + gpio_pb_pins &= ~interfaces[ioif].gpio_b; + + DBG(printk(KERN_DEBUG "GPIO pins: available after: " + "g_in=0x%08x g_out=0x%08x pb=0x%02x\n", + gpio_in_pins, gpio_out_pins, gpio_pb_pins)); + +exit: + local_irq_restore(flags); + if (res == 0) + notify_watchers(); + return res; +} + + +void cris_free_io_interface(enum cris_io_interface ioif) +{ + struct if_group *grp; + unsigned char group_set; + unsigned long flags; + + (void)cris_io_interface_init(); + + if ((ioif >= if_max_interfaces) || (ioif < 0)) { + printk(KERN_CRIT "cris_free_io_interface: Bad interface %u\n", + ioif); + return; + } + local_irq_save(flags); + if (!interfaces[ioif].used) { + printk(KERN_CRIT "cris_free_io_interface: Freeing free interface %u\n", + ioif); + local_irq_restore(flags); + return; + } + group_set = interfaces[ioif].groups; + while (NULL != (grp = get_group(group_set))) { + unsigned int if_group_use = 0; + + switch (grp->group) { + case group_a: + if_group_use = interfaces[ioif].group_a; + break; + case group_b: + if_group_use = interfaces[ioif].group_b; + break; + case group_c: + if_group_use = interfaces[ioif].group_c; + break; + case group_d: + if_group_use = interfaces[ioif].group_d; + break; + case group_e: + if_group_use = interfaces[ioif].group_e; + break; + case group_f: + if_group_use = interfaces[ioif].group_f; + break; + default: + BUG_ON(1); + } + + if ((grp->used & if_group_use) != if_group_use) + BUG_ON(1); + grp->used = grp->used & ~if_group_use; + + group_set = clear_group_from_set(group_set, grp); + } + interfaces[ioif].used = 0; + interfaces[ioif].owner = NULL; + + DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", + gpio_in_pins, gpio_out_pins, gpio_pb_pins)); + DBG(printk("freeing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", + interfaces[ioif].gpio_g_in, + interfaces[ioif].gpio_g_out, + interfaces[ioif].gpio_b)); + + gpio_in_pins |= interfaces[ioif].gpio_g_in; + gpio_out_pins |= interfaces[ioif].gpio_g_out; + gpio_pb_pins |= interfaces[ioif].gpio_b; + + DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", + gpio_in_pins, gpio_out_pins, gpio_pb_pins)); + + local_irq_restore(flags); + + notify_watchers(); +} + +/* Create a bitmask from bit 0 (inclusive) to bit stop_bit + (non-inclusive). stop_bit == 0 returns 0x0 */ +static inline unsigned int create_mask(const unsigned stop_bit) +{ + /* Avoid overflow */ + if (stop_bit >= 32) { + return 0xffffffff; + } + return (1<notify = notify; + w->next = watchers; + watchers = w; + + w->notify((const unsigned int)gpio_in_pins, + (const unsigned int)gpio_out_pins, + (const unsigned char)gpio_pa_pins, + (const unsigned char)gpio_pb_pins); + + return 0; +} + +void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available)) +{ + struct watcher *w = watchers, *prev = NULL; + + (void)cris_io_interface_init(); + + while ((NULL != w) && (w->notify != notify)){ + prev = w; + w = w->next; + } + if (NULL != w) { + if (NULL != prev) { + prev->next = w->next; + } else { + watchers = w->next; + } + kfree(w); + return; + } + printk(KERN_WARNING "cris_io_interface_delete_watcher: Deleting unknown watcher 0x%p\n", notify); +} + + +static int cris_io_interface_init(void) +{ + static int first = 1; + int i; + + if (!first) { + return 0; + } + first = 0; + + for (i = 0; i<8; i++) { + gpio_pa_owners[i] = if_unclaimed; + gpio_pb_owners[i] = if_unclaimed; + gpio_pg_owners[i] = if_unclaimed; + } + for (; i<32; i++) { + gpio_pg_owners[i] = if_unclaimed; + } + return 0; +} + + +module_init(cris_io_interface_init); + + +EXPORT_SYMBOL(cris_request_io_interface); +EXPORT_SYMBOL(cris_free_io_interface); +EXPORT_SYMBOL(cris_io_interface_allocate_pins); +EXPORT_SYMBOL(cris_io_interface_free_pins); +EXPORT_SYMBOL(cris_io_interface_register_watcher); +EXPORT_SYMBOL(cris_io_interface_delete_watcher); diff --git a/kernel/arch/cris/arch-v10/kernel/irq.c b/kernel/arch/cris/arch-v10/kernel/irq.c new file mode 100644 index 000000000..09cae80a8 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/irq.c @@ -0,0 +1,235 @@ +/* + * linux/arch/cris/kernel/irq.c + * + * Copyright (c) 2000-2002 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * + * This file contains the interrupt vectors and some + * helper functions + * + */ + +#include +#include +#include +#include +#include +#include + +#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); +#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); + +extern void kgdb_init(void); +extern void breakpoint(void); + +/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is + * global just so that the kernel gdb can use it. + */ + +void +set_int_vector(int n, irqvectptr addr) +{ + etrax_irv->v[n + 0x20] = (irqvectptr)addr; +} + +/* the breakpoint vector is obviously not made just like the normal irq handlers + * but needs to contain _code_ to jump to addr. + * + * the BREAK n instruction jumps to IBR + n * 8 + */ + +void +set_break_vector(int n, irqvectptr addr) +{ + unsigned short *jinstr = (unsigned short *)&etrax_irv->v[n*2]; + unsigned long *jaddr = (unsigned long *)(jinstr + 1); + + /* if you don't know what this does, do not touch it! */ + + *jinstr = 0x0d3f; + *jaddr = (unsigned long)addr; + + /* 00000026 3f0d82000000 jump 0x82 */ +} + +/* + * This builds up the IRQ handler stubs using some ugly macros in irq.h + * + * These macros create the low-level assembly IRQ routines that do all + * the operations that are needed. They are also written to be fast - and to + * disable interrupts as little as humanly possible. + * + */ + +/* IRQ0 and 1 are special traps */ +void hwbreakpoint(void); +void IRQ1_interrupt(void); +BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */ +BUILD_IRQ(3, 0x08) +BUILD_IRQ(4, 0x10) +BUILD_IRQ(5, 0x20) +BUILD_IRQ(6, 0x40) +BUILD_IRQ(7, 0x80) +BUILD_IRQ(8, 0x100) +BUILD_IRQ(9, 0x200) +BUILD_IRQ(10, 0x400) +BUILD_IRQ(11, 0x800) +BUILD_IRQ(12, 0x1000) +BUILD_IRQ(13, 0x2000) +void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */ +void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */ +BUILD_IRQ(16, 0x10000 | 0x20000) /* ethernet tx interrupt needs to block rx */ +BUILD_IRQ(17, 0x20000 | 0x10000) /* ...and vice versa */ +BUILD_IRQ(18, 0x40000) +BUILD_IRQ(19, 0x80000) +BUILD_IRQ(20, 0x100000) +BUILD_IRQ(21, 0x200000) +BUILD_IRQ(22, 0x400000) +BUILD_IRQ(23, 0x800000) +BUILD_IRQ(24, 0x1000000) +BUILD_IRQ(25, 0x2000000) +/* IRQ 26-30 are reserved */ +BUILD_IRQ(31, 0x80000000) + +/* + * Pointers to the low-level handlers + */ + +static void (*interrupt[NR_IRQS])(void) = { + NULL, NULL, IRQ2_interrupt, IRQ3_interrupt, + IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt, + IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt, + IRQ12_interrupt, IRQ13_interrupt, NULL, NULL, + IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt, + IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt, + IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL, + IRQ31_interrupt +}; + +static void enable_crisv10_irq(struct irq_data *data) +{ + crisv10_unmask_irq(data->irq); +} + +static void disable_crisv10_irq(struct irq_data *data) +{ + crisv10_mask_irq(data->irq); +} + +static struct irq_chip crisv10_irq_type = { + .name = "CRISv10", + .irq_shutdown = disable_crisv10_irq, + .irq_enable = enable_crisv10_irq, + .irq_disable = disable_crisv10_irq, +}; + +void weird_irq(void); +void system_call(void); /* from entry.S */ +void do_sigtrap(void); /* from entry.S */ +void gdb_handle_breakpoint(void); /* from entry.S */ + +extern void do_IRQ(int irq, struct pt_regs * regs); + +/* Handle multiple IRQs */ +void do_multiple_IRQ(struct pt_regs* regs) +{ + int bit; + unsigned masked; + unsigned mask; + unsigned ethmask = 0; + + /* Get interrupts to mask and handle */ + mask = masked = *R_VECT_MASK_RD; + + /* Never mask timer IRQ */ + mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0)); + + /* + * If either ethernet interrupt (rx or tx) is active then block + * the other one too. Unblock afterwards also. + */ + if (mask & + (IO_STATE(R_VECT_MASK_RD, dma0, active) | + IO_STATE(R_VECT_MASK_RD, dma1, active))) { + ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) | + IO_MASK(R_VECT_MASK_RD, dma1)); + } + + /* Block them */ + *R_VECT_MASK_CLR = (mask | ethmask); + + /* An extra irq_enter here to prevent softIRQs to run after + * each do_IRQ. This will decrease the interrupt latency. + */ + irq_enter(); + + /* Handle all IRQs */ + for (bit = 2; bit < 32; bit++) { + if (masked & (1 << bit)) { + do_IRQ(bit, regs); + } + } + + /* This irq_exit() will trigger the soft IRQs. */ + irq_exit(); + + /* Unblock the IRQs again */ + *R_VECT_MASK_SET = (masked | ethmask); +} + +/* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and + setting the irq vector table. +*/ + +void __init init_IRQ(void) +{ + int i; + + /* clear all interrupt masks */ + *R_IRQ_MASK0_CLR = 0xffffffff; + *R_IRQ_MASK1_CLR = 0xffffffff; + *R_IRQ_MASK2_CLR = 0xffffffff; + *R_VECT_MASK_CLR = 0xffffffff; + + for (i = 0; i < 256; i++) + etrax_irv->v[i] = weird_irq; + + /* Initialize IRQ handler descriptors. */ + for(i = 2; i < NR_IRQS; i++) { + irq_set_chip_and_handler(i, &crisv10_irq_type, + handle_simple_irq); + set_int_vector(i, interrupt[i]); + } + + /* the entries in the break vector contain actual code to be + executed by the associated break handler, rather than just a jump + address. therefore we need to setup a default breakpoint handler + for all breakpoints */ + for (i = 0; i < 16; i++) + set_break_vector(i, do_sigtrap); + + /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */ + set_int_vector(15, multiple_interrupt); + + /* 0 and 1 which are special breakpoint/NMI traps */ + set_int_vector(0, hwbreakpoint); + set_int_vector(1, IRQ1_interrupt); + + /* and irq 14 which is the mmu bus fault handler */ + set_int_vector(14, mmu_bus_fault); + + /* setup the system-call trap, which is reached by BREAK 13 */ + set_break_vector(13, system_call); + + /* setup a breakpoint handler for debugging used for both user and + kernel mode debugging (which is why it is not inside an ifdef + CONFIG_ETRAX_KGDB) */ + set_break_vector(8, gdb_handle_breakpoint); + +#ifdef CONFIG_ETRAX_KGDB + /* setup kgdb if its enabled, and break into the debugger */ + kgdb_init(); + breakpoint(); +#endif +} diff --git a/kernel/arch/cris/arch-v10/kernel/kgdb.c b/kernel/arch/cris/arch-v10/kernel/kgdb.c new file mode 100644 index 000000000..22d846bfc --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/kgdb.c @@ -0,0 +1,1144 @@ +/*!************************************************************************** +*! +*! FILE NAME : kgdb.c +*! +*! DESCRIPTION: Implementation of the gdb stub with respect to ETRAX 100. +*! It is a mix of arch/m68k/kernel/kgdb.c and cris_stub.c. +*! +*!--------------------------------------------------------------------------- +*! HISTORY +*! +*! DATE NAME CHANGES +*! ---- ---- ------- +*! Apr 26 1999 Hendrik Ruijter Initial version. +*! May 6 1999 Hendrik Ruijter Removed call to strlen in libc and removed +*! struct assignment as it generates calls to +*! memcpy in libc. +*! Jun 17 1999 Hendrik Ruijter Added gdb 4.18 support. 'X', 'qC' and 'qL'. +*! Jul 21 1999 Bjorn Wesen eLinux port +*! +*!--------------------------------------------------------------------------- +*! +*! (C) Copyright 1999, Axis Communications AB, LUND, SWEDEN +*! +*!**************************************************************************/ +/* @(#) cris_stub.c 1.3 06/17/99 */ + +/* + * kgdb usage notes: + * ----------------- + * + * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be + * built with different gcc flags: "-g" is added to get debug infos, and + * "-fomit-frame-pointer" is omitted to make debugging easier. Since the + * resulting kernel will be quite big (approx. > 7 MB), it will be stripped + * before compresion. Such a kernel will behave just as usually, except if + * given a "debug=" command line option. (Only serial devices are + * allowed for , i.e. no printers or the like; possible values are + * machine depedend and are the same as for the usual debug device, the one + * for logging kernel messages.) If that option is given and the device can be + * initialized, the kernel will connect to the remote gdb in trap_init(). The + * serial parameters are fixed to 8N1 and 115200 bps, for easyness of + * implementation. + * + * To start a debugging session, start that gdb with the debugging kernel + * image (the one with the symbols, vmlinux.debug) named on the command line. + * This file will be used by gdb to get symbol and debugging infos about the + * kernel. Next, select remote debug mode by + * target remote + * where is the name of the serial device over which the debugged + * machine is connected. Maybe you have to adjust the baud rate by + * set remotebaud + * or also other parameters with stty: + * shell stty ... #. + * + * where + * :: + * :: < two hex digits computed as modulo 256 sum of > + * + * When a packet is received, it is first acknowledged with either '+' or '-'. + * '+' indicates a successful transfer. '-' indicates a failed transfer. + * + * Example: + * + * Host: Reply: + * $m0,10#2a +$00010203040506070809101112131415#42 + * + */ + + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +static int kgdb_started = 0; + +/********************************* Register image ****************************/ +/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's + Reference", p. 1-1, with the additional register definitions of the + ETRAX 100LX in cris-opc.h. + There are 16 general 32-bit registers, R0-R15, where R14 is the stack + pointer, SP, and R15 is the program counter, PC. + There are 16 special registers, P0-P15, where three of the unimplemented + registers, P0, P4 and P8, are reserved as zero-registers. A read from + any of these registers returns zero and a write has no effect. */ + +typedef +struct register_image +{ + /* Offset */ + unsigned int r0; /* 0x00 */ + unsigned int r1; /* 0x04 */ + unsigned int r2; /* 0x08 */ + unsigned int r3; /* 0x0C */ + unsigned int r4; /* 0x10 */ + unsigned int r5; /* 0x14 */ + unsigned int r6; /* 0x18 */ + unsigned int r7; /* 0x1C */ + unsigned int r8; /* 0x20 Frame pointer */ + unsigned int r9; /* 0x24 */ + unsigned int r10; /* 0x28 */ + unsigned int r11; /* 0x2C */ + unsigned int r12; /* 0x30 */ + unsigned int r13; /* 0x34 */ + unsigned int sp; /* 0x38 Stack pointer */ + unsigned int pc; /* 0x3C Program counter */ + + unsigned char p0; /* 0x40 8-bit zero-register */ + unsigned char vr; /* 0x41 Version register */ + + unsigned short p4; /* 0x42 16-bit zero-register */ + unsigned short ccr; /* 0x44 Condition code register */ + + unsigned int mof; /* 0x46 Multiply overflow register */ + + unsigned int p8; /* 0x4A 32-bit zero-register */ + unsigned int ibr; /* 0x4E Interrupt base register */ + unsigned int irp; /* 0x52 Interrupt return pointer */ + unsigned int srp; /* 0x56 Subroutine return pointer */ + unsigned int bar; /* 0x5A Breakpoint address register */ + unsigned int dccr; /* 0x5E Double condition code register */ + unsigned int brp; /* 0x62 Breakpoint return pointer (pc in caller) */ + unsigned int usp; /* 0x66 User mode stack pointer */ +} registers; + +/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */ +int getDebugChar (void); + +/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */ +void putDebugChar (int val); + +void enableDebugIRQ (void); + +/******************** Prototypes for global functions. ***********************/ + +/* The string str is prepended with the GDB printout token and sent. */ +void putDebugString (const unsigned char *str, int length); /* used by etrax100ser.c */ + +/* The hook for both static (compiled) and dynamic breakpoints set by GDB. + ETRAX 100 specific. */ +void handle_breakpoint (void); /* used by irq.c */ + +/* The hook for an interrupt generated by GDB. ETRAX 100 specific. */ +void handle_interrupt (void); /* used by irq.c */ + +/* A static breakpoint to be used at startup. */ +void breakpoint (void); /* called by init/main.c */ + +/* From osys_int.c, executing_task contains the number of the current + executing task in osys. Does not know of object-oriented threads. */ +extern unsigned char executing_task; + +/* The number of characters used for a 64 bit thread identifier. */ +#define HEXCHARS_IN_THREAD_ID 16 + +/********************************** Packet I/O ******************************/ +/* BUFMAX defines the maximum number of characters in + inbound/outbound buffers */ +#define BUFMAX 512 + +/* Run-length encoding maximum length. Send 64 at most. */ +#define RUNLENMAX 64 + +/* The inbound/outbound buffers used in packet I/O */ +static char remcomInBuffer[BUFMAX]; +static char remcomOutBuffer[BUFMAX]; + +/* Error and warning messages. */ +enum error_type +{ + SUCCESS, E01, E02, E03, E04, E05, E06, E07 +}; +static char *error_message[] = +{ + "", + "E01 Set current or general thread - H[c,g] - internal error.", + "E02 Change register content - P - cannot change read-only register.", + "E03 Thread is not alive.", /* T, not used. */ + "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.", + "E05 Change register content - P - the register is not implemented..", + "E06 Change memory content - M - internal error.", + "E07 Change register content - P - the register is not stored on the stack" +}; +/********************************* Register image ****************************/ +/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's + Reference", p. 1-1, with the additional register definitions of the + ETRAX 100LX in cris-opc.h. + There are 16 general 32-bit registers, R0-R15, where R14 is the stack + pointer, SP, and R15 is the program counter, PC. + There are 16 special registers, P0-P15, where three of the unimplemented + registers, P0, P4 and P8, are reserved as zero-registers. A read from + any of these registers returns zero and a write has no effect. */ +enum register_name +{ + R0, R1, R2, R3, + R4, R5, R6, R7, + R8, R9, R10, R11, + R12, R13, SP, PC, + P0, VR, P2, P3, + P4, CCR, P6, MOF, + P8, IBR, IRP, SRP, + BAR, DCCR, BRP, USP +}; + +/* The register sizes of the registers in register_name. An unimplemented register + is designated by size 0 in this array. */ +static int register_size[] = +{ + 4, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4, 4, + 1, 1, 0, 0, + 2, 2, 0, 4, + 4, 4, 4, 4, + 4, 4, 4, 4 +}; + +/* Contains the register image of the executing thread in the assembler + part of the code in order to avoid horrible addressing modes. */ +registers cris_reg; + +/* FIXME: Should this be used? Delete otherwise. */ +/* Contains the assumed consistency state of the register image. Uses the + enum error_type for state information. */ +static int consistency_status = SUCCESS; + +/********************************** Handle exceptions ************************/ +/* The variable cris_reg contains the register image associated with the + current_thread_c variable. It is a complete register image created at + entry. The reg_g contains a register image of a task where the general + registers are taken from the stack and all special registers are taken + from the executing task. It is associated with current_thread_g and used + in order to provide access mainly for 'g', 'G' and 'P'. +*/ + +/********************************** Breakpoint *******************************/ +/* Use an internal stack in the breakpoint and interrupt response routines */ +#define INTERNAL_STACK_SIZE 1024 +char internal_stack[INTERNAL_STACK_SIZE]; + +/* Due to the breakpoint return pointer, a state variable is needed to keep + track of whether it is a static (compiled) or dynamic (gdb-invoked) + breakpoint to be handled. A static breakpoint uses the content of register + BRP as it is whereas a dynamic breakpoint requires subtraction with 2 + in order to execute the instruction. The first breakpoint is static. */ +static unsigned char is_dyn_brkp = 0; + +/********************************* String library ****************************/ +/* Single-step over library functions creates trap loops. */ + +/* Copy char s2[] to s1[]. */ +static char* +gdb_cris_strcpy (char *s1, const char *s2) +{ + char *s = s1; + + for (s = s1; (*s++ = *s2++) != '\0'; ) + ; + return (s1); +} + +/* Find length of s[]. */ +static int +gdb_cris_strlen (const char *s) +{ + const char *sc; + + for (sc = s; *sc != '\0'; sc++) + ; + return (sc - s); +} + +/* Find first occurrence of c in s[n]. */ +static void* +gdb_cris_memchr (const void *s, int c, int n) +{ + const unsigned char uc = c; + const unsigned char *su; + + for (su = s; 0 < n; ++su, --n) + if (*su == uc) + return ((void *)su); + return (NULL); +} +/******************************* Standard library ****************************/ +/* Single-step over library functions creates trap loops. */ +/* Convert string to long. */ +static int +gdb_cris_strtol (const char *s, char **endptr, int base) +{ + char *s1; + char *sd; + int x = 0; + + for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1) + x = x * base + (sd - hex_asc); + + if (endptr) + { + /* Unconverted suffix is stored in endptr unless endptr is NULL. */ + *endptr = s1; + } + + return x; +} + +/********************************** Packet I/O ******************************/ +/* Returns the integer equivalent of a hexadecimal character. */ +static int +hex (char ch) +{ + if ((ch >= 'a') && (ch <= 'f')) + return (ch - 'a' + 10); + if ((ch >= '0') && (ch <= '9')) + return (ch - '0'); + if ((ch >= 'A') && (ch <= 'F')) + return (ch - 'A' + 10); + return (-1); +} + +/* Convert the memory, pointed to by mem into hexadecimal representation. + Put the result in buf, and return a pointer to the last character + in buf (null). */ + +static char * +mem2hex(char *buf, unsigned char *mem, int count) +{ + int i; + int ch; + + if (mem == NULL) { + /* Bogus read from m0. FIXME: What constitutes a valid address? */ + for (i = 0; i < count; i++) { + *buf++ = '0'; + *buf++ = '0'; + } + } else { + /* Valid mem address. */ + for (i = 0; i < count; i++) { + ch = *mem++; + buf = hex_byte_pack(buf, ch); + } + } + + /* Terminate properly. */ + *buf = '\0'; + return (buf); +} + +/* Convert the array, in hexadecimal representation, pointed to by buf into + binary representation. Put the result in mem, and return a pointer to + the character after the last byte written. */ +static unsigned char* +hex2mem (unsigned char *mem, char *buf, int count) +{ + int i; + unsigned char ch; + for (i = 0; i < count; i++) { + ch = hex (*buf++) << 4; + ch = ch + hex (*buf++); + *mem++ = ch; + } + return (mem); +} + +/* Put the content of the array, in binary representation, pointed to by buf + into memory pointed to by mem, and return a pointer to the character after + the last byte written. + Gdb will escape $, #, and the escape char (0x7d). */ +static unsigned char* +bin2mem (unsigned char *mem, unsigned char *buf, int count) +{ + int i; + unsigned char *next; + for (i = 0; i < count; i++) { + /* Check for any escaped characters. Be paranoid and + only unescape chars that should be escaped. */ + if (*buf == 0x7d) { + next = buf + 1; + if (*next == 0x3 || *next == 0x4 || *next == 0x5D) /* #, $, ESC */ + { + buf++; + *buf += 0x20; + } + } + *mem++ = *buf++; + } + return (mem); +} + +/* Await the sequence $# and store in the array buffer + returned. */ +static void +getpacket (char *buffer) +{ + unsigned char checksum; + unsigned char xmitcsum; + int i; + int count; + char ch; + do { + while ((ch = getDebugChar ()) != '$') + /* Wait for the start character $ and ignore all other characters */; + checksum = 0; + xmitcsum = -1; + count = 0; + /* Read until a # or the end of the buffer is reached */ + while (count < BUFMAX - 1) { + ch = getDebugChar (); + if (ch == '#') + break; + checksum = checksum + ch; + buffer[count] = ch; + count = count + 1; + } + buffer[count] = '\0'; + + if (ch == '#') { + xmitcsum = hex (getDebugChar ()) << 4; + xmitcsum += hex (getDebugChar ()); + if (checksum != xmitcsum) { + /* Wrong checksum */ + putDebugChar ('-'); + } + else { + /* Correct checksum */ + putDebugChar ('+'); + /* If sequence characters are received, reply with them */ + if (buffer[2] == ':') { + putDebugChar (buffer[0]); + putDebugChar (buffer[1]); + /* Remove the sequence characters from the buffer */ + count = gdb_cris_strlen (buffer); + for (i = 3; i <= count; i++) + buffer[i - 3] = buffer[i]; + } + } + } + } while (checksum != xmitcsum); +} + +/* Send $# from the in the array buffer. */ + +static void +putpacket(char *buffer) +{ + int checksum; + int runlen; + int encode; + + do { + char *src = buffer; + putDebugChar ('$'); + checksum = 0; + while (*src) { + /* Do run length encoding */ + putDebugChar (*src); + checksum += *src; + runlen = 0; + while (runlen < RUNLENMAX && *src == src[runlen]) { + runlen++; + } + if (runlen > 3) { + /* Got a useful amount */ + putDebugChar ('*'); + checksum += '*'; + encode = runlen + ' ' - 4; + putDebugChar (encode); + checksum += encode; + src += runlen; + } + else { + src++; + } + } + putDebugChar('#'); + putDebugChar(hex_asc_hi(checksum)); + putDebugChar(hex_asc_lo(checksum)); + } while(kgdb_started && (getDebugChar() != '+')); +} + +/* The string str is prepended with the GDB printout token and sent. Required + in traditional implementations. */ +void +putDebugString (const unsigned char *str, int length) +{ + remcomOutBuffer[0] = 'O'; + mem2hex(&remcomOutBuffer[1], (unsigned char *)str, length); + putpacket(remcomOutBuffer); +} + +/********************************* Register image ****************************/ +/* Write a value to a specified register in the register image of the current + thread. Returns status code SUCCESS, E02 or E05. */ +static int +write_register (int regno, char *val) +{ + int status = SUCCESS; + registers *current_reg = &cris_reg; + + if (regno >= R0 && regno <= PC) { + /* 32-bit register with simple offset. */ + hex2mem ((unsigned char *)current_reg + regno * sizeof(unsigned int), + val, sizeof(unsigned int)); + } + else if (regno == P0 || regno == VR || regno == P4 || regno == P8) { + /* Do not support read-only registers. */ + status = E02; + } + else if (regno == CCR) { + /* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented, + and P7 (MOF) is 32 bits in ETRAX 100LX. */ + hex2mem ((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short), + val, sizeof(unsigned short)); + } + else if (regno >= MOF && regno <= USP) { + /* 32 bit register with complex offset. (P8 has been taken care of.) */ + hex2mem ((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int), + val, sizeof(unsigned int)); + } + else { + /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */ + status = E05; + } + return status; +} + +/* Read a value from a specified register in the register image. Returns the + value in the register or -1 for non-implemented registers. + Should check consistency_status after a call which may be E05 after changes + in the implementation. */ +static int +read_register (char regno, unsigned int *valptr) +{ + registers *current_reg = &cris_reg; + + if (regno >= R0 && regno <= PC) { + /* 32-bit register with simple offset. */ + *valptr = *(unsigned int *)((char *)current_reg + regno * sizeof(unsigned int)); + return SUCCESS; + } + else if (regno == P0 || regno == VR) { + /* 8 bit register with complex offset. */ + *valptr = (unsigned int)(*(unsigned char *) + ((char *)&(current_reg->p0) + (regno-P0) * sizeof(char))); + return SUCCESS; + } + else if (regno == P4 || regno == CCR) { + /* 16 bit register with complex offset. */ + *valptr = (unsigned int)(*(unsigned short *) + ((char *)&(current_reg->p4) + (regno-P4) * sizeof(unsigned short))); + return SUCCESS; + } + else if (regno >= MOF && regno <= USP) { + /* 32 bit register with complex offset. */ + *valptr = *(unsigned int *)((char *)&(current_reg->p8) + + (regno-P8) * sizeof(unsigned int)); + return SUCCESS; + } + else { + /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */ + consistency_status = E05; + return E05; + } +} + +/********************************** Handle exceptions ************************/ +/* Build and send a response packet in order to inform the host the + stub is stopped. TAAn...:r...;n...:r...;n...:r...; + AA = signal number + n... = register number (hex) + r... = register contents + n... = `thread' + r... = thread process ID. This is a hex integer. + n... = other string not starting with valid hex digit. + gdb should ignore this n,r pair and go on to the next. + This way we can extend the protocol. */ +static void +stub_is_stopped(int sigval) +{ + char *ptr = remcomOutBuffer; + int regno; + + unsigned int reg_cont; + int status; + + /* Send trap type (converted to signal) */ + + *ptr++ = 'T'; + ptr = hex_byte_pack(ptr, sigval); + + /* Send register contents. We probably only need to send the + * PC, frame pointer and stack pointer here. Other registers will be + * explicitly asked for. But for now, send all. + */ + + for (regno = R0; regno <= USP; regno++) { + /* Store n...:r...; for the registers in the buffer. */ + + status = read_register (regno, ®_cont); + + if (status == SUCCESS) { + ptr = hex_byte_pack(ptr, regno); + *ptr++ = ':'; + + ptr = mem2hex(ptr, (unsigned char *)®_cont, + register_size[regno]); + *ptr++ = ';'; + } + + } + + /* null-terminate and send it off */ + + *ptr = 0; + + putpacket (remcomOutBuffer); +} + +/* Performs a complete re-start from scratch. */ +static void +kill_restart (void) +{ + machine_restart(""); +} + +/* All expected commands are sent from remote.c. Send a response according + to the description in remote.c. */ +void +handle_exception (int sigval) +{ + /* Send response. */ + + stub_is_stopped (sigval); + + for (;;) { + remcomOutBuffer[0] = '\0'; + getpacket (remcomInBuffer); + switch (remcomInBuffer[0]) { + case 'g': + /* Read registers: g + Success: Each byte of register data is described by two hex digits. + Registers are in the internal order for GDB, and the bytes + in a register are in the same order the machine uses. + Failure: void. */ + + mem2hex(remcomOutBuffer, (char *)&cris_reg, sizeof(registers)); + break; + + case 'G': + /* Write registers. GXX..XX + Each byte of register data is described by two hex digits. + Success: OK + Failure: void. */ + hex2mem((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers)); + gdb_cris_strcpy (remcomOutBuffer, "OK"); + break; + + case 'P': + /* Write register. Pn...=r... + Write register n..., hex value without 0x, with value r..., + which contains a hex value without 0x and two hex digits + for each byte in the register (target byte order). P1f=11223344 means + set register 31 to 44332211. + Success: OK + Failure: E02, E05 */ + { + char *suffix; + int regno = gdb_cris_strtol (&remcomInBuffer[1], &suffix, 16); + int status; + status = write_register (regno, suffix+1); + + switch (status) { + case E02: + /* Do not support read-only registers. */ + gdb_cris_strcpy (remcomOutBuffer, error_message[E02]); + break; + case E05: + /* Do not support non-existing registers. */ + gdb_cris_strcpy (remcomOutBuffer, error_message[E05]); + break; + case E07: + /* Do not support non-existing registers on the stack. */ + gdb_cris_strcpy (remcomOutBuffer, error_message[E07]); + break; + default: + /* Valid register number. */ + gdb_cris_strcpy (remcomOutBuffer, "OK"); + break; + } + } + break; + + case 'm': + /* Read from memory. mAA..AA,LLLL + AA..AA is the address and LLLL is the length. + Success: XX..XX is the memory content. Can be fewer bytes than + requested if only part of the data may be read. m6000120a,6c means + retrieve 108 byte from base address 6000120a. + Failure: void. */ + { + char *suffix; + unsigned char *addr = (unsigned char *)gdb_cris_strtol(&remcomInBuffer[1], + &suffix, 16); int length = gdb_cris_strtol(suffix+1, 0, 16); + + mem2hex(remcomOutBuffer, addr, length); + } + break; + + case 'X': + /* Write to memory. XAA..AA,LLLL:XX..XX + AA..AA is the start address, LLLL is the number of bytes, and + XX..XX is the binary data. + Success: OK + Failure: void. */ + case 'M': + /* Write to memory. MAA..AA,LLLL:XX..XX + AA..AA is the start address, LLLL is the number of bytes, and + XX..XX is the hexadecimal data. + Success: OK + Failure: void. */ + { + char *lenptr; + char *dataptr; + unsigned char *addr = (unsigned char *)gdb_cris_strtol(&remcomInBuffer[1], + &lenptr, 16); + int length = gdb_cris_strtol(lenptr+1, &dataptr, 16); + if (*lenptr == ',' && *dataptr == ':') { + if (remcomInBuffer[0] == 'M') { + hex2mem(addr, dataptr + 1, length); + } + else /* X */ { + bin2mem(addr, dataptr + 1, length); + } + gdb_cris_strcpy (remcomOutBuffer, "OK"); + } + else { + gdb_cris_strcpy (remcomOutBuffer, error_message[E06]); + } + } + break; + + case 'c': + /* Continue execution. cAA..AA + AA..AA is the address where execution is resumed. If AA..AA is + omitted, resume at the present address. + Success: return to the executing thread. + Failure: will never know. */ + if (remcomInBuffer[1] != '\0') { + cris_reg.pc = gdb_cris_strtol (&remcomInBuffer[1], 0, 16); + } + enableDebugIRQ(); + return; + + case 's': + /* Step. sAA..AA + AA..AA is the address where execution is resumed. If AA..AA is + omitted, resume at the present address. Success: return to the + executing thread. Failure: will never know. + + Should never be invoked. The single-step is implemented on + the host side. If ever invoked, it is an internal error E04. */ + gdb_cris_strcpy (remcomOutBuffer, error_message[E04]); + putpacket (remcomOutBuffer); + return; + + case '?': + /* The last signal which caused a stop. ? + Success: SAA, where AA is the signal number. + Failure: void. */ + remcomOutBuffer[0] = 'S'; + remcomOutBuffer[1] = hex_asc_hi(sigval); + remcomOutBuffer[2] = hex_asc_lo(sigval); + remcomOutBuffer[3] = 0; + break; + + case 'D': + /* Detach from host. D + Success: OK, and return to the executing thread. + Failure: will never know */ + putpacket ("OK"); + return; + + case 'k': + case 'r': + /* kill request or reset request. + Success: restart of target. + Failure: will never know. */ + kill_restart (); + break; + + case 'C': + case 'S': + case '!': + case 'R': + case 'd': + /* Continue with signal sig. Csig;AA..AA + Step with signal sig. Ssig;AA..AA + Use the extended remote protocol. ! + Restart the target system. R0 + Toggle debug flag. d + Search backwards. tAA:PP,MM + Not supported: E04 */ + gdb_cris_strcpy (remcomOutBuffer, error_message[E04]); + break; + + default: + /* The stub should ignore other request and send an empty + response ($#). This way we can extend the protocol and GDB + can tell whether the stub it is talking to uses the old or the new. */ + remcomOutBuffer[0] = 0; + break; + } + putpacket(remcomOutBuffer); + } +} + +/********************************** Breakpoint *******************************/ +/* The hook for both a static (compiled) and a dynamic breakpoint set by GDB. + An internal stack is used by the stub. The register image of the caller is + stored in the structure register_image. + Interactive communication with the host is handled by handle_exception and + finally the register image is restored. */ + +void kgdb_handle_breakpoint(void); + +asm ("\n" +" .global kgdb_handle_breakpoint\n" +"kgdb_handle_breakpoint:\n" +";;\n" +";; Response to the break-instruction\n" +";;\n" +";; Create a register image of the caller\n" +";;\n" +" move $dccr,[cris_reg+0x5E] ; Save the flags in DCCR before disable interrupts\n" +" di ; Disable interrupts\n" +" move.d $r0,[cris_reg] ; Save R0\n" +" move.d $r1,[cris_reg+0x04] ; Save R1\n" +" move.d $r2,[cris_reg+0x08] ; Save R2\n" +" move.d $r3,[cris_reg+0x0C] ; Save R3\n" +" move.d $r4,[cris_reg+0x10] ; Save R4\n" +" move.d $r5,[cris_reg+0x14] ; Save R5\n" +" move.d $r6,[cris_reg+0x18] ; Save R6\n" +" move.d $r7,[cris_reg+0x1C] ; Save R7\n" +" move.d $r8,[cris_reg+0x20] ; Save R8\n" +" move.d $r9,[cris_reg+0x24] ; Save R9\n" +" move.d $r10,[cris_reg+0x28] ; Save R10\n" +" move.d $r11,[cris_reg+0x2C] ; Save R11\n" +" move.d $r12,[cris_reg+0x30] ; Save R12\n" +" move.d $r13,[cris_reg+0x34] ; Save R13\n" +" move.d $sp,[cris_reg+0x38] ; Save SP (R14)\n" +";; Due to the old assembler-versions BRP might not be recognized\n" +" .word 0xE670 ; move brp,$r0\n" +" subq 2,$r0 ; Set to address of previous instruction.\n" +" move.d $r0,[cris_reg+0x3c] ; Save the address in PC (R15)\n" +" clear.b [cris_reg+0x40] ; Clear P0\n" +" move $vr,[cris_reg+0x41] ; Save special register P1\n" +" clear.w [cris_reg+0x42] ; Clear P4\n" +" move $ccr,[cris_reg+0x44] ; Save special register CCR\n" +" move $mof,[cris_reg+0x46] ; P7\n" +" clear.d [cris_reg+0x4A] ; Clear P8\n" +" move $ibr,[cris_reg+0x4E] ; P9,\n" +" move $irp,[cris_reg+0x52] ; P10,\n" +" move $srp,[cris_reg+0x56] ; P11,\n" +" move $dtp0,[cris_reg+0x5A] ; P12, register BAR, assembler might not know BAR\n" +" ; P13, register DCCR already saved\n" +";; Due to the old assembler-versions BRP might not be recognized\n" +" .word 0xE670 ; move brp,r0\n" +";; Static (compiled) breakpoints must return to the next instruction in order\n" +";; to avoid infinite loops. Dynamic (gdb-invoked) must restore the instruction\n" +";; in order to execute it when execution is continued.\n" +" test.b [is_dyn_brkp] ; Is this a dynamic breakpoint?\n" +" beq is_static ; No, a static breakpoint\n" +" nop\n" +" subq 2,$r0 ; rerun the instruction the break replaced\n" +"is_static:\n" +" moveq 1,$r1\n" +" move.b $r1,[is_dyn_brkp] ; Set the state variable to dynamic breakpoint\n" +" move.d $r0,[cris_reg+0x62] ; Save the return address in BRP\n" +" move $usp,[cris_reg+0x66] ; USP\n" +";;\n" +";; Handle the communication\n" +";;\n" +" move.d internal_stack+1020,$sp ; Use the internal stack which grows upward\n" +" moveq 5,$r10 ; SIGTRAP\n" +" jsr handle_exception ; Interactive routine\n" +";;\n" +";; Return to the caller\n" +";;\n" +" move.d [cris_reg],$r0 ; Restore R0\n" +" move.d [cris_reg+0x04],$r1 ; Restore R1\n" +" move.d [cris_reg+0x08],$r2 ; Restore R2\n" +" move.d [cris_reg+0x0C],$r3 ; Restore R3\n" +" move.d [cris_reg+0x10],$r4 ; Restore R4\n" +" move.d [cris_reg+0x14],$r5 ; Restore R5\n" +" move.d [cris_reg+0x18],$r6 ; Restore R6\n" +" move.d [cris_reg+0x1C],$r7 ; Restore R7\n" +" move.d [cris_reg+0x20],$r8 ; Restore R8\n" +" move.d [cris_reg+0x24],$r9 ; Restore R9\n" +" move.d [cris_reg+0x28],$r10 ; Restore R10\n" +" move.d [cris_reg+0x2C],$r11 ; Restore R11\n" +" move.d [cris_reg+0x30],$r12 ; Restore R12\n" +" move.d [cris_reg+0x34],$r13 ; Restore R13\n" +";;\n" +";; FIXME: Which registers should be restored?\n" +";;\n" +" move.d [cris_reg+0x38],$sp ; Restore SP (R14)\n" +" move [cris_reg+0x56],$srp ; Restore the subroutine return pointer.\n" +" move [cris_reg+0x5E],$dccr ; Restore DCCR\n" +" move [cris_reg+0x66],$usp ; Restore USP\n" +" jump [cris_reg+0x62] ; A jump to the content in register BRP works.\n" +" nop ;\n" +"\n"); + +/* The hook for an interrupt generated by GDB. An internal stack is used + by the stub. The register image of the caller is stored in the structure + register_image. Interactive communication with the host is handled by + handle_exception and finally the register image is restored. Due to the + old assembler which does not recognise the break instruction and the + breakpoint return pointer hex-code is used. */ + +void kgdb_handle_serial(void); + +asm ("\n" +" .global kgdb_handle_serial\n" +"kgdb_handle_serial:\n" +";;\n" +";; Response to a serial interrupt\n" +";;\n" +"\n" +" move $dccr,[cris_reg+0x5E] ; Save the flags in DCCR\n" +" di ; Disable interrupts\n" +" move.d $r0,[cris_reg] ; Save R0\n" +" move.d $r1,[cris_reg+0x04] ; Save R1\n" +" move.d $r2,[cris_reg+0x08] ; Save R2\n" +" move.d $r3,[cris_reg+0x0C] ; Save R3\n" +" move.d $r4,[cris_reg+0x10] ; Save R4\n" +" move.d $r5,[cris_reg+0x14] ; Save R5\n" +" move.d $r6,[cris_reg+0x18] ; Save R6\n" +" move.d $r7,[cris_reg+0x1C] ; Save R7\n" +" move.d $r8,[cris_reg+0x20] ; Save R8\n" +" move.d $r9,[cris_reg+0x24] ; Save R9\n" +" move.d $r10,[cris_reg+0x28] ; Save R10\n" +" move.d $r11,[cris_reg+0x2C] ; Save R11\n" +" move.d $r12,[cris_reg+0x30] ; Save R12\n" +" move.d $r13,[cris_reg+0x34] ; Save R13\n" +" move.d $sp,[cris_reg+0x38] ; Save SP (R14)\n" +" move $irp,[cris_reg+0x3c] ; Save the address in PC (R15)\n" +" clear.b [cris_reg+0x40] ; Clear P0\n" +" move $vr,[cris_reg+0x41] ; Save special register P1,\n" +" clear.w [cris_reg+0x42] ; Clear P4\n" +" move $ccr,[cris_reg+0x44] ; Save special register CCR\n" +" move $mof,[cris_reg+0x46] ; P7\n" +" clear.d [cris_reg+0x4A] ; Clear P8\n" +" move $ibr,[cris_reg+0x4E] ; P9,\n" +" move $irp,[cris_reg+0x52] ; P10,\n" +" move $srp,[cris_reg+0x56] ; P11,\n" +" move $dtp0,[cris_reg+0x5A] ; P12, register BAR, assembler might not know BAR\n" +" ; P13, register DCCR already saved\n" +";; Due to the old assembler-versions BRP might not be recognized\n" +" .word 0xE670 ; move brp,r0\n" +" move.d $r0,[cris_reg+0x62] ; Save the return address in BRP\n" +" move $usp,[cris_reg+0x66] ; USP\n" +"\n" +";; get the serial character (from debugport.c) and check if it is a ctrl-c\n" +"\n" +" jsr getDebugChar\n" +" cmp.b 3, $r10\n" +" bne goback\n" +" nop\n" +"\n" +" move.d [cris_reg+0x5E], $r10 ; Get DCCR\n" +" btstq 8, $r10 ; Test the U-flag.\n" +" bmi goback\n" +" nop\n" +"\n" +";;\n" +";; Handle the communication\n" +";;\n" +" move.d internal_stack+1020,$sp ; Use the internal stack\n" +" moveq 2,$r10 ; SIGINT\n" +" jsr handle_exception ; Interactive routine\n" +"\n" +"goback:\n" +";;\n" +";; Return to the caller\n" +";;\n" +" move.d [cris_reg],$r0 ; Restore R0\n" +" move.d [cris_reg+0x04],$r1 ; Restore R1\n" +" move.d [cris_reg+0x08],$r2 ; Restore R2\n" +" move.d [cris_reg+0x0C],$r3 ; Restore R3\n" +" move.d [cris_reg+0x10],$r4 ; Restore R4\n" +" move.d [cris_reg+0x14],$r5 ; Restore R5\n" +" move.d [cris_reg+0x18],$r6 ; Restore R6\n" +" move.d [cris_reg+0x1C],$r7 ; Restore R7\n" +" move.d [cris_reg+0x20],$r8 ; Restore R8\n" +" move.d [cris_reg+0x24],$r9 ; Restore R9\n" +" move.d [cris_reg+0x28],$r10 ; Restore R10\n" +" move.d [cris_reg+0x2C],$r11 ; Restore R11\n" +" move.d [cris_reg+0x30],$r12 ; Restore R12\n" +" move.d [cris_reg+0x34],$r13 ; Restore R13\n" +";;\n" +";; FIXME: Which registers should be restored?\n" +";;\n" +" move.d [cris_reg+0x38],$sp ; Restore SP (R14)\n" +" move [cris_reg+0x56],$srp ; Restore the subroutine return pointer.\n" +" move [cris_reg+0x5E],$dccr ; Restore DCCR\n" +" move [cris_reg+0x66],$usp ; Restore USP\n" +" reti ; Return from the interrupt routine\n" +" nop\n" +"\n"); + +/* Use this static breakpoint in the start-up only. */ + +void +breakpoint(void) +{ + kgdb_started = 1; + is_dyn_brkp = 0; /* This is a static, not a dynamic breakpoint. */ + __asm__ volatile ("break 8"); /* Jump to handle_breakpoint. */ +} + +/* initialize kgdb. doesn't break into the debugger, but sets up irq and ports */ + +void +kgdb_init(void) +{ + /* could initialize debug port as well but it's done in head.S already... */ + + /* breakpoint handler is now set in irq.c */ + set_int_vector(8, kgdb_handle_serial); + + enableDebugIRQ(); +} + +/****************************** End of file **********************************/ diff --git a/kernel/arch/cris/arch-v10/kernel/process.c b/kernel/arch/cris/arch-v10/kernel/process.c new file mode 100644 index 000000000..02b783457 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/process.c @@ -0,0 +1,193 @@ +/* + * linux/arch/cris/kernel/process.c + * + * Copyright (C) 1995 Linus Torvalds + * Copyright (C) 2000-2002 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * Mikael Starvik (starvik@axis.com) + * + * This file handles the architecture-dependent parts of process handling.. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ETRAX_GPIO +void etrax_gpio_wake_up_check(void); /* drivers/gpio.c */ +#endif + +/* + * We use this if we don't have any better + * idle routine.. + */ +void default_idle(void) +{ +#ifdef CONFIG_ETRAX_GPIO + etrax_gpio_wake_up_check(); +#endif + local_irq_enable(); +} + +/* + * Free current thread data structures etc.. + */ + +void exit_thread(void) +{ + /* Nothing needs to be done. */ +} + +/* if the watchdog is enabled, we can simply disable interrupts and go + * into an eternal loop, and the watchdog will reset the CPU after 0.1s + * if on the other hand the watchdog wasn't enabled, we just enable it and wait + */ + +void hard_reset_now (void) +{ + /* + * Don't declare this variable elsewhere. We don't want any other + * code to know about it than the watchdog handler in entry.S and + * this code, implementing hard reset through the watchdog. + */ +#if defined(CONFIG_ETRAX_WATCHDOG) + extern int cause_of_death; +#endif + + printk("*** HARD RESET ***\n"); + local_irq_disable(); + +#if defined(CONFIG_ETRAX_WATCHDOG) + cause_of_death = 0xbedead; +#else + /* Since we dont plan to keep on resetting the watchdog, + the key can be arbitrary hence three */ + *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, 3) | + IO_STATE(R_WATCHDOG, enable, start); +#endif + + while(1) /* waiting for RETRIBUTION! */ ; +} + +/* + * Return saved PC of a blocked thread. + */ +unsigned long thread_saved_pc(struct task_struct *t) +{ + return task_pt_regs(t)->irp; +} + +/* setup the child's kernel stack with a pt_regs and switch_stack on it. + * it will be un-nested during _resume and _ret_from_sys_call when the + * new thread is scheduled. + * + * also setup the thread switching structure which is used to keep + * thread-specific data during _resumes. + * + */ +asmlinkage void ret_from_fork(void); +asmlinkage void ret_from_kernel_thread(void); + +int copy_thread(unsigned long clone_flags, unsigned long usp, + unsigned long arg, struct task_struct *p) +{ + struct pt_regs *childregs = task_pt_regs(p); + struct switch_stack *swstack = ((struct switch_stack *)childregs) - 1; + + /* put the pt_regs structure at the end of the new kernel stack page and fix it up + * remember that the task_struct doubles as the kernel stack for the task + */ + + if (unlikely(p->flags & PF_KTHREAD)) { + memset(swstack, 0, + sizeof(struct switch_stack) + sizeof(struct pt_regs)); + swstack->r1 = usp; + swstack->r2 = arg; + childregs->dccr = 1 << I_DCCR_BITNR; + swstack->return_ip = (unsigned long) ret_from_kernel_thread; + p->thread.ksp = (unsigned long) swstack; + p->thread.usp = 0; + return 0; + } + *childregs = *current_pt_regs(); /* struct copy of pt_regs */ + + childregs->r10 = 0; /* child returns 0 after a fork/clone */ + + /* put the switch stack right below the pt_regs */ + + swstack->r9 = 0; /* parameter to ret_from_sys_call, 0 == dont restart the syscall */ + + /* we want to return into ret_from_sys_call after the _resume */ + + swstack->return_ip = (unsigned long) ret_from_fork; /* Will call ret_from_sys_call */ + + /* fix the user-mode stackpointer */ + + p->thread.usp = usp ?: rdusp(); + + /* and the kernel-mode one */ + + p->thread.ksp = (unsigned long) swstack; + +#ifdef DEBUG + printk("copy_thread: new regs at 0x%p, as shown below:\n", childregs); + show_registers(childregs); +#endif + + return 0; +} + +unsigned long get_wchan(struct task_struct *p) +{ +#if 0 + /* YURGH. TODO. */ + + unsigned long ebp, esp, eip; + unsigned long stack_page; + int count = 0; + if (!p || p == current || p->state == TASK_RUNNING) + return 0; + stack_page = (unsigned long)p; + esp = p->thread.esp; + if (!stack_page || esp < stack_page || esp > 8188+stack_page) + return 0; + /* include/asm-i386/system.h:switch_to() pushes ebp last. */ + ebp = *(unsigned long *) esp; + do { + if (ebp < stack_page || ebp > 8184+stack_page) + return 0; + eip = *(unsigned long *) (ebp+4); + if (!in_sched_functions(eip)) + return eip; + ebp = *(unsigned long *) ebp; + } while (count++ < 16); +#endif + return 0; +} +#undef last_sched +#undef first_sched + +void show_regs(struct pt_regs * regs) +{ + unsigned long usp = rdusp(); + + show_regs_print_info(KERN_DEFAULT); + + printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n", + regs->irp, regs->srp, regs->dccr, usp, regs->mof ); + printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", + regs->r0, regs->r1, regs->r2, regs->r3); + printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", + regs->r4, regs->r5, regs->r6, regs->r7); + printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", + regs->r8, regs->r9, regs->r10, regs->r11); + printk("r12: %08lx r13: %08lx oR10: %08lx\n", + regs->r12, regs->r13, regs->orig_r10); +} + diff --git a/kernel/arch/cris/arch-v10/kernel/ptrace.c b/kernel/arch/cris/arch-v10/kernel/ptrace.c new file mode 100644 index 000000000..bfddfb994 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/ptrace.c @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2000-2003, Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* + * Determines which bits in DCCR the user has access to. + * 1 = access, 0 = no access. + */ +#define DCCR_MASK 0x0000001f /* XNZVC */ + +/* + * Get contents of register REGNO in task TASK. + */ +inline long get_reg(struct task_struct *task, unsigned int regno) +{ + /* USP is a special case, it's not in the pt_regs struct but + * in the tasks thread struct + */ + + if (regno == PT_USP) + return task->thread.usp; + else if (regno < PT_MAX) + return ((unsigned long *)task_pt_regs(task))[regno]; + else + return 0; +} + +/* + * Write contents of register REGNO in task TASK. + */ +inline int put_reg(struct task_struct *task, unsigned int regno, + unsigned long data) +{ + if (regno == PT_USP) + task->thread.usp = data; + else if (regno < PT_MAX) + ((unsigned long *)task_pt_regs(task))[regno] = data; + else + return -1; + return 0; +} + +/* + * Called by kernel/ptrace.c when detaching. + * + * Make sure the single step bit is not set. + */ +void +ptrace_disable(struct task_struct *child) +{ + /* Todo - pending singlesteps? */ + clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); +} + +/* + * Note that this implementation of ptrace behaves differently from vanilla + * ptrace. Contrary to what the man page says, in the PTRACE_PEEKTEXT, + * PTRACE_PEEKDATA, and PTRACE_PEEKUSER requests the data variable is not + * ignored. Instead, the data variable is expected to point at a location + * (in user space) where the result of the ptrace call is written (instead of + * being returned). + */ +long arch_ptrace(struct task_struct *child, long request, + unsigned long addr, unsigned long data) +{ + int ret; + unsigned int regno = addr >> 2; + unsigned long __user *datap = (unsigned long __user *)data; + + switch (request) { + /* Read word at location address. */ + case PTRACE_PEEKTEXT: + case PTRACE_PEEKDATA: + ret = generic_ptrace_peekdata(child, addr, data); + break; + + /* Read the word at location address in the USER area. */ + case PTRACE_PEEKUSR: { + unsigned long tmp; + + ret = -EIO; + if ((addr & 3) || regno > PT_MAX) + break; + + tmp = get_reg(child, regno); + ret = put_user(tmp, datap); + break; + } + + /* Write the word at location address. */ + case PTRACE_POKETEXT: + case PTRACE_POKEDATA: + ret = generic_ptrace_pokedata(child, addr, data); + break; + + /* Write the word at location address in the USER area. */ + case PTRACE_POKEUSR: + ret = -EIO; + if ((addr & 3) || regno > PT_MAX) + break; + + if (regno == PT_DCCR) { + /* don't allow the tracing process to change stuff like + * interrupt enable, kernel/user bit, dma enables etc. + */ + data &= DCCR_MASK; + data |= get_reg(child, PT_DCCR) & ~DCCR_MASK; + } + if (put_reg(child, regno, data)) + break; + ret = 0; + break; + + /* Get all GP registers from the child. */ + case PTRACE_GETREGS: { + int i; + unsigned long tmp; + + ret = 0; + for (i = 0; i <= PT_MAX; i++) { + tmp = get_reg(child, i); + + if (put_user(tmp, datap)) { + ret = -EFAULT; + break; + } + + datap++; + } + + break; + } + + /* Set all GP registers in the child. */ + case PTRACE_SETREGS: { + int i; + unsigned long tmp; + + ret = 0; + for (i = 0; i <= PT_MAX; i++) { + if (get_user(tmp, datap)) { + ret = -EFAULT; + break; + } + + if (i == PT_DCCR) { + tmp &= DCCR_MASK; + tmp |= get_reg(child, PT_DCCR) & ~DCCR_MASK; + } + + put_reg(child, i, tmp); + datap++; + } + + break; + } + + default: + ret = ptrace_request(child, request, addr, data); + break; + } + + return ret; +} + +void do_syscall_trace(void) +{ + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + return; + + if (!(current->ptrace & PT_PTRACED)) + return; + + /* the 0x80 provides a way for the tracing parent to distinguish + between a syscall stop and SIGTRAP delivery */ + ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) + ? 0x80 : 0)); + + /* + * This isn't the same as continuing with a signal, but it will do for + * normal use. + */ + if (current->exit_code) { + send_sig(current->exit_code, current, 1); + current->exit_code = 0; + } +} diff --git a/kernel/arch/cris/arch-v10/kernel/setup.c b/kernel/arch/cris/arch-v10/kernel/setup.c new file mode 100644 index 000000000..7ab31f1c7 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/setup.c @@ -0,0 +1,106 @@ +/* + * + * linux/arch/cris/arch-v10/kernel/setup.c + * + * Copyright (C) 1995 Linus Torvalds + * Copyright (c) 2001-2002 Axis Communications AB + */ + +/* + * This file handles the architecture-dependent parts of initialization + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_PROC_FS +#define HAS_FPU 0x0001 +#define HAS_MMU 0x0002 +#define HAS_ETHERNET100 0x0004 +#define HAS_TOKENRING 0x0008 +#define HAS_SCSI 0x0010 +#define HAS_ATA 0x0020 +#define HAS_USB 0x0040 +#define HAS_IRQ_BUG 0x0080 +#define HAS_MMU_BUG 0x0100 + +static struct cpu_info { + char *model; + unsigned short cache; + unsigned short flags; +} cpu_info[] = { + /* The first four models will never ever run this code and are + only here for display. */ + { "ETRAX 1", 0, 0 }, + { "ETRAX 2", 0, 0 }, + { "ETRAX 3", 0, HAS_TOKENRING }, + { "ETRAX 4", 0, HAS_TOKENRING | HAS_SCSI }, + { "Unknown", 0, 0 }, + { "Unknown", 0, 0 }, + { "Unknown", 0, 0 }, + { "Simulator", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA }, + { "ETRAX 100", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG }, + { "ETRAX 100", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA }, + { "ETRAX 100LX", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB | HAS_MMU | HAS_MMU_BUG }, + { "ETRAX 100LX v2", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB | HAS_MMU }, + { "Unknown", 0, 0 } /* This entry MUST be the last */ +}; + +int show_cpuinfo(struct seq_file *m, void *v) +{ + unsigned long revision; + struct cpu_info *info; + + /* read the version register in the CPU and print some stuff */ + + revision = rdvr(); + + if (revision >= ARRAY_SIZE(cpu_info)) + info = &cpu_info[ARRAY_SIZE(cpu_info) - 1]; + else + info = &cpu_info[revision]; + + seq_printf(m, + "processor\t: 0\n" + "cpu\t\t: CRIS\n" + "cpu revision\t: %lu\n" + "cpu model\t: %s\n" + "cache size\t: %d kB\n" + "fpu\t\t: %s\n" + "mmu\t\t: %s\n" + "mmu DMA bug\t: %s\n" + "ethernet\t: %s Mbps\n" + "token ring\t: %s\n" + "scsi\t\t: %s\n" + "ata\t\t: %s\n" + "usb\t\t: %s\n" + "bogomips\t: %lu.%02lu\n", + + revision, + info->model, + info->cache, + info->flags & HAS_FPU ? "yes" : "no", + info->flags & HAS_MMU ? "yes" : "no", + info->flags & HAS_MMU_BUG ? "yes" : "no", + info->flags & HAS_ETHERNET100 ? "10/100" : "10", + info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no", + info->flags & HAS_SCSI ? "yes" : "no", + info->flags & HAS_ATA ? "yes" : "no", + info->flags & HAS_USB ? "yes" : "no", + (loops_per_jiffy * HZ + 500) / 500000, + ((loops_per_jiffy * HZ + 500) / 5000) % 100); + + return 0; +} + +#endif /* CONFIG_PROC_FS */ + +void +show_etrax_copyright(void) +{ + printk(KERN_INFO + "Linux/CRIS port on ETRAX 100LX (c) 2001 Axis Communications AB\n"); +} diff --git a/kernel/arch/cris/arch-v10/kernel/shadows.c b/kernel/arch/cris/arch-v10/kernel/shadows.c new file mode 100644 index 000000000..2454a0b02 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/shadows.c @@ -0,0 +1,36 @@ +/* + * Various shadow registers. Defines for these are in include/asm-etrax100/io.h + */ + +/* Shadows for internal Etrax-registers */ + +unsigned long genconfig_shadow; +unsigned long gen_config_ii_shadow; +unsigned long port_g_data_shadow; +unsigned char port_pa_dir_shadow; +unsigned char port_pa_data_shadow; +unsigned char port_pb_i2c_shadow; +unsigned char port_pb_config_shadow; +unsigned char port_pb_dir_shadow; +unsigned char port_pb_data_shadow; +unsigned long r_timer_ctrl_shadow; + +/* Shadows for external I/O port registers. + * These are only usable if there actually IS a latch connected + * to the corresponding external chip-select pin. + * + * A common usage is that CSP0 controls LEDs and CSP4 video chips. + */ + +unsigned long port_cse1_shadow; +unsigned long port_csp0_shadow; +unsigned long port_csp4_shadow; + +/* Corresponding addresses for the ports. + * These are initialized in arch/cris/mm/init.c using ioremap. + */ + +volatile unsigned long *port_cse1_addr; +volatile unsigned long *port_csp0_addr; +volatile unsigned long *port_csp4_addr; + diff --git a/kernel/arch/cris/arch-v10/kernel/signal.c b/kernel/arch/cris/arch-v10/kernel/signal.c new file mode 100644 index 000000000..7122d9773 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/signal.c @@ -0,0 +1,438 @@ +/* + * linux/arch/cris/kernel/signal.c + * + * Based on arch/i386/kernel/signal.c by + * Copyright (C) 1991, 1992 Linus Torvalds + * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson * + * + * Ideas also taken from arch/arm. + * + * Copyright (C) 2000-2007 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define DEBUG_SIG 0 + +/* a syscall in Linux/CRIS is a break 13 instruction which is 2 bytes */ +/* manipulate regs so that upon return, it will be re-executed */ + +/* We rely on that pc points to the instruction after "break 13", so the + * library must never do strange things like putting it in a delay slot. + */ +#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->irp -= 2; + +void do_signal(int canrestart, struct pt_regs *regs); + +/* + * Do a signal return; undo the signal stack. + */ + +struct sigframe { + struct sigcontext sc; + unsigned long extramask[_NSIG_WORDS-1]; + unsigned char retcode[8]; /* trampoline code */ +}; + +struct rt_sigframe { + struct siginfo *pinfo; + void *puc; + struct siginfo info; + struct ucontext uc; + unsigned char retcode[8]; /* trampoline code */ +}; + + +static int +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) +{ + unsigned int err = 0; + unsigned long old_usp; + + /* Always make any pending restarted system calls return -EINTR */ + current->restart_block.fn = do_no_restart_syscall; + + /* restore the regs from &sc->regs (same as sc, since regs is first) + * (sc is already checked for VERIFY_READ since the sigframe was + * checked in sys_sigreturn previously) + */ + + if (__copy_from_user(regs, sc, sizeof(struct pt_regs))) + goto badframe; + + /* make sure the U-flag is set so user-mode cannot fool us */ + + regs->dccr |= 1 << 8; + + /* restore the old USP as it was before we stacked the sc etc. + * (we cannot just pop the sigcontext since we aligned the sp and + * stuff after pushing it) + */ + + err |= __get_user(old_usp, &sc->usp); + + wrusp(old_usp); + + /* TODO: the other ports use regs->orig_XX to disable syscall checks + * after this completes, but we don't use that mechanism. maybe we can + * use it now ? + */ + + return err; + +badframe: + return 1; +} + +asmlinkage int sys_sigreturn(void) +{ + struct pt_regs *regs = current_pt_regs(); + struct sigframe __user *frame = (struct sigframe *)rdusp(); + sigset_t set; + + /* + * Since we stacked the signal on a dword boundary, + * then frame should be dword aligned here. If it's + * not, then the user is trying to mess with us. + */ + if (((long)frame) & 3) + goto badframe; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__get_user(set.sig[0], &frame->sc.oldmask) + || (_NSIG_WORDS > 1 + && __copy_from_user(&set.sig[1], frame->extramask, + sizeof(frame->extramask)))) + goto badframe; + + set_current_blocked(&set); + + if (restore_sigcontext(regs, &frame->sc)) + goto badframe; + + /* TODO: SIGTRAP when single-stepping as in arm ? */ + + return regs->r10; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +asmlinkage int sys_rt_sigreturn(void) +{ + struct pt_regs *regs = current_pt_regs(); + struct rt_sigframe __user *frame = (struct rt_sigframe *)rdusp(); + sigset_t set; + + /* + * Since we stacked the signal on a dword boundary, + * then frame should be dword aligned here. If it's + * not, then the user is trying to mess with us. + */ + if (((long)frame) & 3) + goto badframe; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) + goto badframe; + + set_current_blocked(&set); + + if (restore_sigcontext(regs, &frame->uc.uc_mcontext)) + goto badframe; + + if (restore_altstack(&frame->uc.uc_stack)) + goto badframe; + + return regs->r10; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +/* + * Set up a signal frame. + */ + +static int setup_sigcontext(struct sigcontext __user *sc, + struct pt_regs *regs, unsigned long mask) +{ + int err = 0; + unsigned long usp = rdusp(); + + /* copy the regs. they are first in sc so we can use sc directly */ + + err |= __copy_to_user(sc, regs, sizeof(struct pt_regs)); + + /* Set the frametype to CRIS_FRAME_NORMAL for the execution of + the signal handler. The frametype will be restored to its previous + value in restore_sigcontext. */ + regs->frametype = CRIS_FRAME_NORMAL; + + /* then some other stuff */ + + err |= __put_user(mask, &sc->oldmask); + + err |= __put_user(usp, &sc->usp); + + return err; +} + +/* Figure out where we want to put the new signal frame + * - usually on the stack. */ + +static inline void __user * +get_sigframe(struct ksignal *ksig, size_t frame_size) +{ + unsigned long sp = sigsp(rdusp(), ksig); + + /* make sure the frame is dword-aligned */ + + sp &= ~3; + + return (void __user*)(sp - frame_size); +} + +/* grab and setup a signal frame. + * + * basically we stack a lot of state info, and arrange for the + * user-mode program to return to the kernel using either a + * trampoline which performs the syscall sigreturn, or a provided + * user-mode trampoline. + */ + +static int setup_frame(struct ksignal *ksig, sigset_t *set, + struct pt_regs *regs) +{ + struct sigframe __user *frame; + unsigned long return_ip; + int err = 0; + + frame = get_sigframe(ksig, sizeof(*frame)); + + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + return -EFAULT; + + err |= setup_sigcontext(&frame->sc, regs, set->sig[0]); + if (err) + return -EFAULT; + + if (_NSIG_WORDS > 1) { + err |= __copy_to_user(frame->extramask, &set->sig[1], + sizeof(frame->extramask)); + } + if (err) + return -EFAULT; + + /* Set up to return from userspace. If provided, use a stub + already in userspace. */ + if (ksig->ka.sa.sa_flags & SA_RESTORER) { + return_ip = (unsigned long)ksig->ka.sa.sa_restorer; + } else { + /* trampoline - the desired return ip is the retcode itself */ + return_ip = (unsigned long)&frame->retcode; + /* This is movu.w __NR_sigreturn, r9; break 13; */ + err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0)); + err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2)); + err |= __put_user(0xe93d, (short __user*)(frame->retcode+4)); + } + + if (err) + return -EFAULT; + + /* Set up registers for signal handler */ + + regs->irp = (unsigned long) ksig->ka.sa.sa_handler; /* what we enter NOW */ + regs->srp = return_ip; /* what we enter LATER */ + regs->r10 = ksig->sig; /* first argument is signo */ + + /* actually move the usp to reflect the stacked frame */ + + wrusp((unsigned long)frame); + + return 0; +} + +static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, + struct pt_regs *regs) +{ + struct rt_sigframe __user *frame; + unsigned long return_ip; + int err = 0; + + frame = get_sigframe(ksig, sizeof(*frame)); + + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + return -EFAULT; + + err |= __put_user(&frame->info, &frame->pinfo); + err |= __put_user(&frame->uc, &frame->puc); + err |= copy_siginfo_to_user(&frame->info, &ksig->info); + if (err) + return -EFAULT; + + /* Clear all the bits of the ucontext we don't use. */ + err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext)); + + err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]); + + err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); + + err |= __save_altstack(&frame->uc.uc_stack, rdusp()); + + if (err) + return -EFAULT; + + /* Set up to return from userspace. If provided, use a stub + already in userspace. */ + if (ksig->ka.sa.sa_flags & SA_RESTORER) { + return_ip = (unsigned long)ksig->ka.sa.sa_restorer; + } else { + /* trampoline - the desired return ip is the retcode itself */ + return_ip = (unsigned long)&frame->retcode; + /* This is movu.w __NR_rt_sigreturn, r9; break 13; */ + err |= __put_user(0x9c5f, (short __user *)(frame->retcode+0)); + err |= __put_user(__NR_rt_sigreturn, + (short __user *)(frame->retcode+2)); + err |= __put_user(0xe93d, (short __user *)(frame->retcode+4)); + } + + if (err) + return -EFAULT; + + /* Set up registers for signal handler */ + + /* What we enter NOW */ + regs->irp = (unsigned long) ksig->ka.sa.sa_handler; + /* What we enter LATER */ + regs->srp = return_ip; + /* First argument is signo */ + regs->r10 = ksig->sig; + /* Second argument is (siginfo_t *) */ + regs->r11 = (unsigned long)&frame->info; + /* Third argument is unused */ + regs->r12 = 0; + + /* Actually move the usp to reflect the stacked frame */ + wrusp((unsigned long)frame); + + return 0; +} + +/* + * OK, we're invoking a handler + */ + +static inline void handle_signal(int canrestart, struct ksignal *ksig, + struct pt_regs *regs) +{ + sigset_t *oldset = sigmask_to_save(); + int ret; + + /* Are we from a system call? */ + if (canrestart) { + /* If so, check system call restarting.. */ + switch (regs->r10) { + case -ERESTART_RESTARTBLOCK: + case -ERESTARTNOHAND: + /* ERESTARTNOHAND means that the syscall should + * only be restarted if there was no handler for + * the signal, and since we only get here if there + * is a handler, we don't restart */ + regs->r10 = -EINTR; + break; + case -ERESTARTSYS: + /* ERESTARTSYS means to restart the syscall if + * there is no handler or the handler was + * registered with SA_RESTART */ + if (!(ksig->ka.sa.sa_flags & SA_RESTART)) { + regs->r10 = -EINTR; + break; + } + /* fallthrough */ + case -ERESTARTNOINTR: + /* ERESTARTNOINTR means that the syscall should + * be called again after the signal handler returns. */ + RESTART_CRIS_SYS(regs); + } + } + + /* Set up the stack frame */ + if (ksig->ka.sa.sa_flags & SA_SIGINFO) + ret = setup_rt_frame(ksig, oldset, regs); + else + ret = setup_frame(ksig, oldset, regs); + + signal_setup_done(ret, ksig, 0); +} + +/* + * Note that 'init' is a special process: it doesn't get signals it doesn't + * want to handle. Thus you cannot kill init even with a SIGKILL even by + * mistake. + * + * Also note that the regs structure given here as an argument, is the latest + * pushed pt_regs. It may or may not be the same as the first pushed registers + * when the initial usermode->kernelmode transition took place. Therefore + * we can use user_mode(regs) to see if we came directly from kernel or user + * mode below. + */ + +void do_signal(int canrestart, struct pt_regs *regs) +{ + struct ksignal ksig; + + /* + * We want the common case to go fast, which + * is why we may in certain cases get here from + * kernel mode. Just return without doing anything + * if so. + */ + if (!user_mode(regs)) + return; + + if (get_signal(&ksig)) { + /* Whee! Actually deliver the signal. */ + handle_signal(canrestart, &ksig, regs); + return; + } + + /* Did we come from a system call? */ + if (canrestart) { + /* Restart the system call - no handlers present */ + if (regs->r10 == -ERESTARTNOHAND || + regs->r10 == -ERESTARTSYS || + regs->r10 == -ERESTARTNOINTR) { + RESTART_CRIS_SYS(regs); + } + if (regs->r10 == -ERESTART_RESTARTBLOCK) { + regs->r9 = __NR_restart_syscall; + regs->irp -= 2; + } + } + + /* if there's no signal to deliver, we just put the saved sigmask + * back */ + restore_saved_sigmask(); +} diff --git a/kernel/arch/cris/arch-v10/kernel/time.c b/kernel/arch/cris/arch-v10/kernel/time.c new file mode 100644 index 000000000..b5eb5cd2f --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/time.c @@ -0,0 +1,267 @@ +/* + * linux/arch/cris/arch-v10/kernel/time.c + * + * Copyright (C) 1991, 1992, 1995 Linus Torvalds + * Copyright (C) 1999-2002 Axis Communications AB + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* define this if you need to use print_timestamp */ +/* it will make jiffies at 96 hz instead of 100 hz though */ +#undef USE_CASCADE_TIMERS + +unsigned long get_ns_in_jiffie(void) +{ + unsigned char timer_count, t1; + unsigned short presc_count; + unsigned long ns; + unsigned long flags; + + local_irq_save(flags); + timer_count = *R_TIMER0_DATA; + presc_count = *R_TIM_PRESC_STATUS; + /* presc_count might be wrapped */ + t1 = *R_TIMER0_DATA; + + if (timer_count != t1){ + /* it wrapped, read prescaler again... */ + presc_count = *R_TIM_PRESC_STATUS; + timer_count = t1; + } + local_irq_restore(flags); + if (presc_count >= PRESCALE_VALUE/2 ){ + presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2; + } else { + presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2; + } + + ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + + ( (presc_count) * (1000000000/PRESCALE_FREQ)); + return ns; +} + +static u32 cris_v10_gettimeoffset(void) +{ + u32 count; + + /* The timer interrupt comes from Etrax timer 0. In order to get + * better precision, we check the current value. It might have + * underflowed already though. + */ + count = *R_TIMER0_DATA; + + /* Convert timer value to nsec */ + return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV; +} + +/* Excerpt from the Etrax100 HSDD about the built-in watchdog: + * + * 3.10.4 Watchdog timer + + * When the watchdog timer is started, it generates an NMI if the watchdog + * isn't restarted or stopped within 0.1 s. If it still isn't restarted or + * stopped after an additional 3.3 ms, the watchdog resets the chip. + * The watchdog timer is stopped after reset. The watchdog timer is controlled + * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit + * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is + * described in the table below: + * + * Watchdog Value written: + * state: To enable: To key: Operation: + * -------- ---------- ------- ---------- + * stopped 0 X No effect. + * stopped 1 key_val Start watchdog with key = key_val. + * started 0 ~key Stop watchdog + * started 1 ~key Restart watchdog with key = ~key. + * started X new_key_val Change key to new_key_val. + * + * Note: '~' is the bitwise NOT operator. + * + */ + +/* right now, starting the watchdog is the same as resetting it */ +#define start_watchdog reset_watchdog + +#ifdef CONFIG_ETRAX_WATCHDOG +static int watchdog_key = 0; /* arbitrary number */ +#endif + +/* number of pages to consider "out of memory". it is normal that the memory + * is used though, so put this really low. + */ + +#define WATCHDOG_MIN_FREE_PAGES 8 + +void reset_watchdog(void) +{ +#if defined(CONFIG_ETRAX_WATCHDOG) + /* only keep watchdog happy as long as we have memory left! */ + if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { + /* reset the watchdog with the inverse of the old key */ + watchdog_key ^= 0x7; /* invert key, which is 3 bits */ + *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) | + IO_STATE(R_WATCHDOG, enable, start); + } +#endif +} + +/* stop the watchdog - we still need the correct key */ + +void stop_watchdog(void) +{ +#ifdef CONFIG_ETRAX_WATCHDOG + watchdog_key ^= 0x7; /* invert key, which is 3 bits */ + *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) | + IO_STATE(R_WATCHDOG, enable, stop); +#endif +} + + +extern void cris_do_profile(struct pt_regs *regs); + +/* + * timer_interrupt() needs to keep up the real-time clock, + * as well as call the "xtime_update()" routine every clocktick + */ +static inline irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + struct pt_regs *regs = get_irq_regs(); + /* acknowledge the timer irq */ + +#ifdef USE_CASCADE_TIMERS + *R_TIMER_CTRL = + IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | + IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | + IO_STATE( R_TIMER_CTRL, i1, clr) | + IO_STATE( R_TIMER_CTRL, tm1, run) | + IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | + IO_STATE( R_TIMER_CTRL, i0, clr) | + IO_STATE( R_TIMER_CTRL, tm0, run) | + IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); +#else + *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr); +#endif + + /* reset watchdog otherwise it resets us! */ + reset_watchdog(); + + /* Update statistics. */ + update_process_times(user_mode(regs)); + + /* call the real timer interrupt handler */ + xtime_update(1); + + cris_do_profile(regs); /* Save profiling information */ + return IRQ_HANDLED; +} + +/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */ + +static struct irqaction irq2 = { + .handler = timer_interrupt, + .flags = IRQF_SHARED, + .name = "timer", +}; + +void __init time_init(void) +{ + arch_gettimeoffset = cris_v10_gettimeoffset; + + /* probe for the RTC and read it if it exists + * Before the RTC can be probed the loops_per_usec variable needs + * to be initialized to make usleep work. A better value for + * loops_per_usec is calculated by the kernel later once the + * clock has started. + */ + loops_per_usec = 50; + + /* Setup the etrax timers + * Base frequency is 25000 hz, divider 250 -> 100 HZ + * In normal mode, we use timer0, so timer1 is free. In cascade + * mode (which we sometimes use for debugging) both timers are used. + * Remember that linux/timex.h contains #defines that rely on the + * timer settings below (hz and divide factor) !!! + */ + +#ifdef USE_CASCADE_TIMERS + *R_TIMER_CTRL = + IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | + IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | + IO_STATE( R_TIMER_CTRL, i1, nop) | + IO_STATE( R_TIMER_CTRL, tm1, stop_ld) | + IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | + IO_STATE( R_TIMER_CTRL, i0, nop) | + IO_STATE( R_TIMER_CTRL, tm0, stop_ld) | + IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); + + *R_TIMER_CTRL = r_timer_ctrl_shadow = + IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | + IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | + IO_STATE( R_TIMER_CTRL, i1, nop) | + IO_STATE( R_TIMER_CTRL, tm1, run) | + IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | + IO_STATE( R_TIMER_CTRL, i0, nop) | + IO_STATE( R_TIMER_CTRL, tm0, run) | + IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); +#else + *R_TIMER_CTRL = + IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | + IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) | + IO_STATE(R_TIMER_CTRL, i1, nop) | + IO_STATE(R_TIMER_CTRL, tm1, stop_ld) | + IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | + IO_STATE(R_TIMER_CTRL, i0, nop) | + IO_STATE(R_TIMER_CTRL, tm0, stop_ld) | + IO_STATE(R_TIMER_CTRL, clksel0, flexible); + + *R_TIMER_CTRL = r_timer_ctrl_shadow = + IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | + IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) | + IO_STATE(R_TIMER_CTRL, i1, nop) | + IO_STATE(R_TIMER_CTRL, tm1, run) | + IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | + IO_STATE(R_TIMER_CTRL, i0, nop) | + IO_STATE(R_TIMER_CTRL, tm0, run) | + IO_STATE(R_TIMER_CTRL, clksel0, flexible); + + *R_TIMER_PRESCALE = PRESCALE_VALUE; +#endif + + /* unmask the timer irq */ + *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set); + + /* now actually register the irq handler that calls timer_interrupt() */ + setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */ + + /* enable watchdog if we should use one */ +#if defined(CONFIG_ETRAX_WATCHDOG) + printk("Enabling watchdog...\n"); + start_watchdog(); + + /* If we use the hardware watchdog, we want to trap it as an NMI + and dump registers before it resets us. For this to happen, we + must set the "m" NMI enable flag (which once set, is unset only + when an NMI is taken). + + The same goes for the external NMI, but that doesn't have any + driver or infrastructure support yet. */ + asm ("setf m"); + + *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set); + *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set); +#endif +} diff --git a/kernel/arch/cris/arch-v10/kernel/traps.c b/kernel/arch/cris/arch-v10/kernel/traps.c new file mode 100644 index 000000000..7001beda7 --- /dev/null +++ b/kernel/arch/cris/arch-v10/kernel/traps.c @@ -0,0 +1,131 @@ +/* + * Helper functions for trap handlers + * + * Copyright (C) 2000-2007, Axis Communications AB. + * + * Authors: Bjorn Wesen + * Hans-Peter Nilsson + * + */ + +#include +#include +#include +#include + +void +show_registers(struct pt_regs *regs) +{ + /* + * It's possible to use either the USP register or current->thread.usp. + * USP might not correspond to the current process for all cases this + * function is called, and current->thread.usp isn't up to date for the + * current process. Experience shows that using USP is the way to go. + */ + unsigned long usp = rdusp(); + + printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n", + regs->irp, regs->srp, regs->dccr, usp, regs->mof); + + printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", + regs->r0, regs->r1, regs->r2, regs->r3); + + printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", + regs->r4, regs->r5, regs->r6, regs->r7); + + printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", + regs->r8, regs->r9, regs->r10, regs->r11); + + printk("r12: %08lx r13: %08lx oR10: %08lx sp: %08lx\n", + regs->r12, regs->r13, regs->orig_r10, (long unsigned)regs); + + printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE); + + printk("Process %s (pid: %d, stackpage=%08lx)\n", + current->comm, current->pid, (unsigned long)current); + + /* + * When in-kernel, we also print out the stack and code at the + * time of the fault.. + */ + if (!user_mode(regs)) { + int i; + + show_stack(NULL, (unsigned long *)usp); + + /* + * If the previous stack-dump wasn't a kernel one, dump the + * kernel stack now. + */ + if (usp != 0) + show_stack(NULL, NULL); + + printk("\nCode: "); + + if (regs->irp < PAGE_OFFSET) + goto bad_value; + + /* + * Quite often the value at regs->irp doesn't point to the + * interesting instruction, which often is the previous + * instruction. So dump at an offset large enough that the + * instruction decoding should be in sync at the interesting + * point, but small enough to fit on a row. The regs->irp + * location is pointed out in a ksymoops-friendly way by + * wrapping the byte for that address in parenthesises. + */ + for (i = -12; i < 12; i++) { + unsigned char c; + + if (__get_user(c, &((unsigned char *)regs->irp)[i])) { +bad_value: + printk(" Bad IP value."); + break; + } + + if (i == 0) + printk("(%02x) ", c); + else + printk("%02x ", c); + } + printk("\n"); + } +} + +void +arch_enable_nmi(void) +{ + asm volatile ("setf m"); +} + +extern void (*nmi_handler)(struct pt_regs *); +void handle_nmi(struct pt_regs *regs) +{ + if (nmi_handler) + nmi_handler(regs); + + /* Wait until nmi is no longer active. (We enable NMI immediately after + returning from this function, and we don't want it happening while + exiting from the NMI interrupt handler.) */ + while (*R_IRQ_MASK0_RD & IO_STATE(R_IRQ_MASK0_RD, nmi_pin, active)) + ; +} + +#ifdef CONFIG_DEBUG_BUGVERBOSE +void +handle_BUG(struct pt_regs *regs) +{ + struct bug_frame f; + unsigned char c; + unsigned long irp = regs->irp; + + if (__copy_from_user(&f, (const void __user *)(irp - 8), sizeof f)) + return; + if (f.prefix != BUG_PREFIX || f.magic != BUG_MAGIC) + return; + if (__get_user(c, f.filename)) + f.filename = ""; + + printk("kernel BUG at %s:%d!\n", f.filename, f.line); +} +#endif diff --git a/kernel/arch/cris/arch-v10/lib/Makefile b/kernel/arch/cris/arch-v10/lib/Makefile new file mode 100644 index 000000000..725153edb --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for Etrax-specific library files.. +# + +lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o csumcpfruser.o + diff --git a/kernel/arch/cris/arch-v10/lib/checksum.S b/kernel/arch/cris/arch-v10/lib/checksum.S new file mode 100644 index 000000000..7d552f4bd --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/checksum.S @@ -0,0 +1,118 @@ +/* + * A fast checksum routine using movem + * Copyright (c) 1998-2001 Axis Communications AB + * + * csum_partial(const unsigned char * buff, int len, unsigned int sum) + */ + + .globl csum_partial +csum_partial: + + ;; r10 - src + ;; r11 - length + ;; r12 - checksum + + ;; check for breakeven length between movem and normal word looping versions + ;; we also do _NOT_ want to compute a checksum over more than the + ;; actual length when length < 40 + + cmpu.w 80,$r11 + blo _word_loop + nop + + ;; need to save the registers we use below in the movem loop + ;; this overhead is why we have a check above for breakeven length + ;; only r0 - r8 have to be saved, the other ones are clobber-able + ;; according to the ABI + + subq 9*4,$sp + movem $r8,[$sp] + + ;; do a movem checksum + + subq 10*4,$r11 ; update length for the first loop + +_mloop: movem [$r10+],$r9 ; read 10 longwords + + ;; perform dword checksumming on the 10 longwords + + add.d $r0,$r12 + ax + add.d $r1,$r12 + ax + add.d $r2,$r12 + ax + add.d $r3,$r12 + ax + add.d $r4,$r12 + ax + add.d $r5,$r12 + ax + add.d $r6,$r12 + ax + add.d $r7,$r12 + ax + add.d $r8,$r12 + ax + add.d $r9,$r12 + + ;; fold the carry into the checksum, to avoid having to loop the carry + ;; back into the top + + ax + addq 0,$r12 + + subq 10*4,$r11 + bge _mloop + nop + + addq 10*4,$r11 ; compensate for last loop underflowing length + + movem [$sp+],$r8 ; restore regs + +_word_loop: + ;; only fold if there is anything to fold. + + cmpq 0,$r12 + beq _no_fold + + ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below. + ;; r9 and r13 can be used as temporaries. + + moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9 + lsrq 16,$r9 + + move.d $r12,$r13 + lsrq 16,$r13 ; r13 = checksum >> 16 + and.d $r9,$r12 ; checksum = checksum & 0xffff + add.d $r13,$r12 ; checksum += r13 + +_no_fold: + cmpq 2,$r11 + blt _no_words + nop + + ;; checksum the rest of the words + + subq 2,$r11 + +_wloop: subq 2,$r11 + bge _wloop + addu.w [$r10+],$r12 + + addq 2,$r11 + +_no_words: + ;; see if we have one odd byte more + cmpq 1,$r11 + beq _do_byte + nop + ret + move.d $r12, $r10 + +_do_byte: + ;; copy and checksum the last byte + addu.b [$r10],$r12 + ret + move.d $r12, $r10 + diff --git a/kernel/arch/cris/arch-v10/lib/checksumcopy.S b/kernel/arch/cris/arch-v10/lib/checksumcopy.S new file mode 100644 index 000000000..540db8a5f --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/checksumcopy.S @@ -0,0 +1,126 @@ +/* + * A fast checksum+copy routine using movem + * Copyright (c) 1998, 2001 Axis Communications AB + * + * Authors: Bjorn Wesen + * + * csum_partial_copy_nocheck(const char *src, char *dst, + * int len, unsigned int sum) + */ + + .globl csum_partial_copy_nocheck +csum_partial_copy_nocheck: + + ;; r10 - src + ;; r11 - dst + ;; r12 - length + ;; r13 - checksum + + ;; check for breakeven length between movem and normal word looping versions + ;; we also do _NOT_ want to compute a checksum over more than the + ;; actual length when length < 40 + + cmpu.w 80, $r12 + blo _word_loop + nop + + ;; need to save the registers we use below in the movem loop + ;; this overhead is why we have a check above for breakeven length + ;; only r0 - r8 have to be saved, the other ones are clobber-able + ;; according to the ABI + + subq 9*4, $sp + movem $r8, [$sp] + + ;; do a movem copy and checksum + + subq 10*4, $r12 ; update length for the first loop + +_mloop: movem [$r10+],$r9 ; read 10 longwords +1: ;; A failing userspace access will have this as PC. + movem $r9,[$r11+] ; write 10 longwords + + ;; perform dword checksumming on the 10 longwords + + add.d $r0,$r13 + ax + add.d $r1,$r13 + ax + add.d $r2,$r13 + ax + add.d $r3,$r13 + ax + add.d $r4,$r13 + ax + add.d $r5,$r13 + ax + add.d $r6,$r13 + ax + add.d $r7,$r13 + ax + add.d $r8,$r13 + ax + add.d $r9,$r13 + + ;; fold the carry into the checksum, to avoid having to loop the carry + ;; back into the top + + ax + addq 0,$r13 + + subq 10*4,$r12 + bge _mloop + nop + + addq 10*4,$r12 ; compensate for last loop underflowing length + + movem [$sp+],$r8 ; restore regs + +_word_loop: + ;; only fold if there is anything to fold. + + cmpq 0,$r13 + beq _no_fold + + ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below + ;; r9 can be used as temporary. + + move.d $r13,$r9 + lsrq 16,$r9 ; r0 = checksum >> 16 + and.d 0xffff,$r13 ; checksum = checksum & 0xffff + add.d $r9,$r13 ; checksum += r0 + +_no_fold: + cmpq 2,$r12 + blt _no_words + nop + + ;; copy and checksum the rest of the words + + subq 2,$r12 + +_wloop: move.w [$r10+],$r9 +2: ;; A failing userspace access will have this as PC. + addu.w $r9,$r13 + subq 2,$r12 + bge _wloop + move.w $r9,[$r11+] + + addq 2,$r12 + +_no_words: + ;; see if we have one odd byte more + cmpq 1,$r12 + beq _do_byte + nop + ret + move.d $r13, $r10 + +_do_byte: + ;; copy and checksum the last byte + move.b [$r10],$r9 +3: ;; A failing userspace access will have this as PC. + addu.b $r9,$r13 + move.b $r9,[$r11] + ret + move.d $r13, $r10 diff --git a/kernel/arch/cris/arch-v10/lib/csumcpfruser.S b/kernel/arch/cris/arch-v10/lib/csumcpfruser.S new file mode 100644 index 000000000..5f41ccd62 --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/csumcpfruser.S @@ -0,0 +1,64 @@ +/* + * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into + * csum_partial_copy_from_user by adding exception records. + * + * Copyright (C) 2001 Axis Communications AB. + * + * Author: Hans-Peter Nilsson. + */ + +#include + +/* Same function body, but a different name. If we just added exception + records to _csum_partial_copy_nocheck and made it generic, we wouldn't + know a user fault from a kernel fault and we would have overhead in + each kernel caller for the error-pointer argument. + + unsigned int csum_partial_copy_from_user + (const char *src, char *dst, int len, unsigned int sum, int *errptr); + + Note that the errptr argument is only set if we encounter an error. + It is conveniently located on the stack, so the normal function body + does not have to handle it. */ + +#define csum_partial_copy_nocheck csum_partial_copy_from_user + +/* There are local labels numbered 1, 2 and 3 present to mark the + different from-user accesses. */ +#include "checksumcopy.S" + + .section .fixup,"ax" + +;; Here from the movem loop; restore stack. +4: + movem [$sp+],$r8 +;; r12 is already decremented. Add back chunk_size-2. + addq 40-2,$r12 + +;; Here from the word loop; r12 is off by 2; add it back. +5: + addq 2,$r12 + +;; Here from a failing single byte. +6: + +;; Signal in *errptr that we had a failing access. + moveq -EFAULT,$r9 + move.d $r9,[[$sp]] + +;; Clear the rest of the destination area using memset. Preserve the +;; checksum for the readable bytes. + push $srp + push $r13 + move.d $r11,$r10 + clear.d $r11 + jsr memset + pop $r10 + jump [$sp+] + + .previous + .section __ex_table,"a" + .dword 1b,4b + .dword 2b,5b + .dword 3b,6b + .previous diff --git a/kernel/arch/cris/arch-v10/lib/dmacopy.c b/kernel/arch/cris/arch-v10/lib/dmacopy.c new file mode 100644 index 000000000..49f5b8ca5 --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/dmacopy.c @@ -0,0 +1,42 @@ +/* + * memcpy for large blocks, using memory-memory DMA channels 6 and 7 in Etrax + */ + +#include +#include + +#define D(x) + +void *dma_memcpy(void *pdst, + const void *psrc, + unsigned int pn) +{ + static etrax_dma_descr indma, outdma; + + D(printk(KERN_DEBUG "dma_memcpy %d bytes... ", pn)); + +#if 0 + *R_GEN_CONFIG = genconfig_shadow = + (genconfig_shadow & ~0x3c0000) | + IO_STATE(R_GEN_CONFIG, dma6, intdma7) | + IO_STATE(R_GEN_CONFIG, dma7, intdma6); +#endif + indma.sw_len = outdma.sw_len = pn; + indma.ctrl = d_eol | d_eop; + outdma.ctrl = d_eol; + indma.buf = psrc; + outdma.buf = pdst; + + *R_DMA_CH6_FIRST = &indma; + *R_DMA_CH7_FIRST = &outdma; + *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, start); + *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, start); + + while (*R_DMA_CH7_CMD == 1) + /* wait for completion */; + + D(printk(KERN_DEBUG "done\n")); +} + + + diff --git a/kernel/arch/cris/arch-v10/lib/dram_init.S b/kernel/arch/cris/arch-v10/lib/dram_init.S new file mode 100644 index 000000000..e541d3d8f --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/dram_init.S @@ -0,0 +1,146 @@ +/* + * DRAM/SDRAM initialization - alter with care + * This file is intended to be included from other assembler files + * + * Note: This file may not modify r9 because r9 is used to carry + * information from the decompresser to the kernel + * + * Copyright (C) 2000-2012 Axis Communications AB + * + */ + +/* Just to be certain the config file is included, we include it here + * explicitly instead of depending on it being included in the file that + * uses this code. + */ + + + ;; WARNING! The registers r8 and r9 are used as parameters carrying + ;; information from the decompressor (if the kernel was compressed). + ;; They should not be used in the code below. + + move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0 + move.d $r0, [R_WAITSTATES] + + move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0 + move.d $r0, [R_BUS_CONFIG] + +#ifndef CONFIG_ETRAX_SDRAM + move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0 + move.d $r0, [R_DRAM_CONFIG] + + move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0 + move.d $r0, [R_DRAM_TIMING] +#else + ;; Samsung SDRAMs seem to require to be initialized twice to work properly. + moveq 2, $r6 +_sdram_init: + + ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization + + ; Bank configuration + move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0 + move.d $r0, [R_SDRAM_CONFIG] + + ; Calculate value of mrs_data + ; CAS latency = 2 && bus_width = 32 => 0x40 + ; CAS latency = 3 && bus_width = 32 => 0x60 + ; CAS latency = 2 && bus_width = 16 => 0x20 + ; CAS latency = 3 && bus_width = 16 => 0x30 + + ; Check if value is already supplied in kernel config + move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2 + and.d 0x00ff0000, $r2 + bne _set_timing + lsrq 16, $r2 + + move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2 + move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1 + move.d $r1, $r3 + and.d 0x03, $r1 ; Get CAS latency + and.d 0x1000, $r3 ; 50 or 100 MHz? + beq _speed_50 + nop +_speed_100: + cmp.d 0x00, $r1 ; CAS latency = 2? + beq _bw_check + nop + or.d 0x20, $r2 ; CAS latency = 3 + ba _bw_check + nop +_speed_50: + cmp.d 0x01, $r1 ; CAS latency = 2? + beq _bw_check + nop + or.d 0x20, $r2 ; CAS latency = 3 +_bw_check: + move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1 + and.d 0x800000, $r1 ; DRAM width is bit 23 + bne _set_timing + nop + lsrq 1, $r2 ; 16 bits. Shift down value. + + ; Set timing parameters. Starts master clock +_set_timing: + move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1 + and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0 + or.d 0x80000000, $r1 ; Make sure sdram enable bit is set + move.d $r1, $r5 + or.d 0x0000c000, $r1 ; ref = disable + lslq 16, $r2 ; mrs data starts at bit 16 + or.d $r2, $r1 + move.d $r1, [R_SDRAM_TIMING] + + ; Wait 200us + move.d 10000, $r2 +1: bne 1b + subq 1, $r2 + + ; Issue initialization command sequence + move.d _sdram_commands_start, $r2 + and.d 0x000fffff, $r2 ; Make sure commands are read from flash + move.d _sdram_commands_end, $r3 + and.d 0x000fffff, $r3 +1: clear.d $r4 + move.b [$r2+], $r4 + lslq 9, $r4 ; Command starts at bit 9 + or.d $r1, $r4 + move.d $r4, [R_SDRAM_TIMING] + nop ; Wait five nop cycles between each command + nop + nop + nop + nop + cmp.d $r2, $r3 + bne 1b + nop + move.d $r5, [R_SDRAM_TIMING] + subq 1, $r6 + bne _sdram_init + nop + ba _sdram_commands_end + nop + +_sdram_commands_start: + .byte 3 ; Precharge + .byte 0 ; nop + .byte 2 ; refresh + .byte 0 ; nop + .byte 2 ; refresh + .byte 0 ; nop + .byte 2 ; refresh + .byte 0 ; nop + .byte 2 ; refresh + .byte 0 ; nop + .byte 2 ; refresh + .byte 0 ; nop + .byte 2 ; refresh + .byte 0 ; nop + .byte 2 ; refresh + .byte 0 ; nop + .byte 2 ; refresh + .byte 0 ; nop + .byte 1 ; mrs + .byte 0 ; nop +_sdram_commands_end: +#endif diff --git a/kernel/arch/cris/arch-v10/lib/hw_settings.S b/kernel/arch/cris/arch-v10/lib/hw_settings.S new file mode 100644 index 000000000..c09f19f47 --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/hw_settings.S @@ -0,0 +1,60 @@ +/* + * This table is used by some tools to extract hardware parameters. + * The table should be included in the kernel and the decompressor. + * Don't forget to update the tools if you change this table. + * + * Copyright (C) 2001 Axis Communications AB + * + * Authors: Mikael Starvik (starvik@axis.com) + */ + +#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \ + (CONFIG_ETRAX_DEF_R_PORT_PA_DATA)) +#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \ + (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \ + (CONFIG_ETRAX_DEF_R_PORT_PB_DATA)) + + .ascii "HW_PARAM_MAGIC" ; Magic number + .dword 0xc0004000 ; Kernel start address + + ; Debug port +#ifdef CONFIG_ETRAX_DEBUG_PORT0 + .dword 0 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1) + .dword 1 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2) + .dword 2 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3) + .dword 3 +#else + .dword 4 ; No debug +#endif + + ; SDRAM or EDO DRAM? +#ifdef CONFIG_ETRAX_SDRAM + .dword 1 +#else + .dword 0 +#endif + + ; Register values + .dword R_WAITSTATES + .dword CONFIG_ETRAX_DEF_R_WAITSTATES + .dword R_BUS_CONFIG + .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG +#ifdef CONFIG_ETRAX_SDRAM + .dword R_SDRAM_CONFIG + .dword CONFIG_ETRAX_DEF_R_SDRAM_CONFIG + .dword R_SDRAM_TIMING + .dword CONFIG_ETRAX_DEF_R_SDRAM_TIMING +#else + .dword R_DRAM_CONFIG + .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG + .dword R_DRAM_TIMING + .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING +#endif + .dword R_PORT_PA_SET + .dword PA_SET_VALUE + .dword R_PORT_PB_SET + .dword PB_SET_VALUE + .dword 0 ; No more register values diff --git a/kernel/arch/cris/arch-v10/lib/memset.c b/kernel/arch/cris/arch-v10/lib/memset.c new file mode 100644 index 000000000..c94ea9b3e --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/memset.c @@ -0,0 +1,259 @@ +/* A memset for CRIS. + Copyright (C) 1999-2005 Axis Communications. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Neither the name of Axis Communications nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS + ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS + COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* FIXME: This file should really only be used for reference, as the + result is somewhat depending on gcc generating what we expect rather + than what we describe. An assembly file should be used instead. */ + +/* Note the multiple occurrence of the expression "12*4", including the + asm. It is hard to get it into the asm in a good way. Thus better to + expose the problem everywhere: no macro. */ + +/* Assuming one cycle per dword written or read (ok, not really true; the + world is not ideal), and one cycle per instruction, then 43+3*(n/48-1) + <= 24+24*(n/48-1) so n >= 45.7; n >= 0.9; we win on the first full + 48-byte block to set. */ + +#define MEMSET_BY_BLOCK_THRESHOLD (1 * 48) + +/* No name ambiguities in this file. */ +__asm__ (".syntax no_register_prefix"); + +void *memset(void *pdst, int c, unsigned int plen) +{ + /* Now we want the parameters in special registers. Make sure the + compiler does something usable with this. */ + + register char *return_dst __asm__ ("r10") = pdst; + register int n __asm__ ("r12") = plen; + register int lc __asm__ ("r11") = c; + + /* Most apps use memset sanely. Memsetting about 3..4 bytes or less get + penalized here compared to the generic implementation. */ + + /* This is fragile performancewise at best. Check with newer GCC + releases, if they compile cascaded "x |= x << 8" to sane code. */ + __asm__("movu.b %0,r13 \n\ + lslq 8,r13 \n\ + move.b %0,r13 \n\ + move.d r13,%0 \n\ + lslq 16,r13 \n\ + or.d r13,%0" + : "=r" (lc) /* Inputs. */ + : "0" (lc) /* Outputs. */ + : "r13"); /* Trash. */ + + { + register char *dst __asm__ ("r13") = pdst; + + if (((unsigned long) pdst & 3) != 0 + /* Oops! n = 0 must be a valid call, regardless of alignment. */ + && n >= 3) + { + if ((unsigned long) dst & 1) + { + *dst = (char) lc; + n--; + dst++; + } + + if ((unsigned long) dst & 2) + { + *(short *) dst = lc; + n -= 2; + dst += 2; + } + } + + /* Decide which setting method to use. */ + if (n >= MEMSET_BY_BLOCK_THRESHOLD) + { + /* It is not optimal to tell the compiler about clobbering any + registers; that will move the saving/restoring of those registers + to the function prologue/epilogue, and make non-block sizes + suboptimal. */ + __asm__ volatile + ("\ + ;; GCC does promise correct register allocations, but let's \n\ + ;; make sure it keeps its promises. \n\ + .ifnc %0-%1-%4,$r13-$r12-$r11 \n\ + .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\ + .endif \n\ + \n\ + ;; Save the registers we'll clobber in the movem process \n\ + ;; on the stack. Don't mention them to gcc, it will only be \n\ + ;; upset. \n\ + subq 11*4,sp \n\ + movem r10,[sp] \n\ + \n\ + move.d r11,r0 \n\ + move.d r11,r1 \n\ + move.d r11,r2 \n\ + move.d r11,r3 \n\ + move.d r11,r4 \n\ + move.d r11,r5 \n\ + move.d r11,r6 \n\ + move.d r11,r7 \n\ + move.d r11,r8 \n\ + move.d r11,r9 \n\ + move.d r11,r10 \n\ + \n\ + ;; Now we've got this: \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop \n\ + subq 12*4,r12 \n\ +0: \n\ +" +#ifdef __arch_common_v10_v32 + /* Cater to branch offset difference between v32 and v10. We + assume the branch below has an 8-bit offset. */ +" setf\n" +#endif +" subq 12*4,r12 \n\ + bge 0b \n\ + movem r11,[r13+] \n\ + \n\ + ;; Compensate for last loop underflowing n. \n\ + addq 12*4,r12 \n\ + \n\ + ;; Restore registers from stack. \n\ + movem [sp+],r10" + + /* Outputs. */ + : "=r" (dst), "=r" (n) + + /* Inputs. */ + : "0" (dst), "1" (n), "r" (lc)); + } + + /* An ad-hoc unroll, used for 4*12-1..16 bytes. */ + while (n >= 16) + { + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + n -= 16; + } + + switch (n) + { + case 0: + break; + + case 1: + *dst = (char) lc; + break; + + case 2: + *(short *) dst = (short) lc; + break; + + case 3: + *(short *) dst = (short) lc; dst += 2; + *dst = (char) lc; + break; + + case 4: + *(long *) dst = lc; + break; + + case 5: + *(long *) dst = lc; dst += 4; + *dst = (char) lc; + break; + + case 6: + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; + break; + + case 7: + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; dst += 2; + *dst = (char) lc; + break; + + case 8: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; + break; + + case 9: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *dst = (char) lc; + break; + + case 10: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; + break; + + case 11: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; dst += 2; + *dst = (char) lc; + break; + + case 12: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; + break; + + case 13: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *dst = (char) lc; + break; + + case 14: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; + break; + + case 15: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; dst += 2; + *dst = (char) lc; + break; + } + } + + return return_dst; +} diff --git a/kernel/arch/cris/arch-v10/lib/old_checksum.c b/kernel/arch/cris/arch-v10/lib/old_checksum.c new file mode 100644 index 000000000..8f79163f1 --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/old_checksum.c @@ -0,0 +1,86 @@ +/* + * INET An implementation of the TCP/IP protocol suite for the LINUX + * operating system. INET is implemented using the BSD Socket + * interface as the means of communication with the user level. + * + * IP/TCP/UDP checksumming routines + * + * Authors: Jorge Cwik, + * Arnt Gulbrandsen, + * Tom May, + * Lots of code moved from tcp.c and ip.c; see those files + * for more names. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include + +#undef PROFILE_CHECKSUM + +#ifdef PROFILE_CHECKSUM +/* these are just for profiling the checksum code with an oscillioscope.. uh */ +#if 0 +#define BITOFF *((unsigned char *)0xb0000030) = 0xff +#define BITON *((unsigned char *)0xb0000030) = 0x0 +#endif +#include +#define CBITON LED_ACTIVE_SET(1) +#define CBITOFF LED_ACTIVE_SET(0) +#define BITOFF +#define BITON +#else +#define BITOFF +#define BITON +#define CBITOFF +#define CBITON +#endif + +/* + * computes a partial checksum, e.g. for TCP/UDP fragments + */ + +#include + +__wsum csum_partial(const void *p, int len, __wsum __sum) +{ + u32 sum = (__force u32)__sum; + const u16 *buff = p; + /* + * Experiments with ethernet and slip connections show that buff + * is aligned on either a 2-byte or 4-byte boundary. + */ + const void *endMarker = p + len; + const void *marker = endMarker - (len % 16); +#if 0 + if((int)buff & 0x3) + printk("unaligned buff %p\n", buff); + __delay(900); /* extra delay of 90 us to test performance hit */ +#endif + BITON; + while (buff < marker) { + sum += *buff++; + sum += *buff++; + sum += *buff++; + sum += *buff++; + sum += *buff++; + sum += *buff++; + sum += *buff++; + sum += *buff++; + } + marker = endMarker - (len % 2); + while (buff < marker) + sum += *buff++; + + if (endMarker > buff) + sum += *(const u8 *)buff; /* add extra byte separately */ + + BITOFF; + return (__force __wsum)sum; +} + +EXPORT_SYMBOL(csum_partial); diff --git a/kernel/arch/cris/arch-v10/lib/string.c b/kernel/arch/cris/arch-v10/lib/string.c new file mode 100644 index 000000000..c7bd6ebdc --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/string.c @@ -0,0 +1,236 @@ +/* A memcpy for CRIS. + Copyright (C) 1994-2005 Axis Communications. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Neither the name of Axis Communications nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS + ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS + COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* FIXME: This file should really only be used for reference, as the + result is somewhat depending on gcc generating what we expect rather + than what we describe. An assembly file should be used instead. */ + +#include + +/* Break even between movem and move16 is really at 38.7 * 2, but + modulo 44, so up to the next multiple of 44, we use ordinary code. */ +#define MEMCPY_BY_BLOCK_THRESHOLD (44 * 2) + +/* No name ambiguities in this file. */ +__asm__ (".syntax no_register_prefix"); + +void * +memcpy(void *pdst, const void *psrc, size_t pn) +{ + /* Now we want the parameters put in special registers. + Make sure the compiler is able to make something useful of this. + As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). + + If gcc was allright, it really would need no temporaries, and no + stack space to save stuff on. */ + + register void *return_dst __asm__ ("r10") = pdst; + register unsigned char *dst __asm__ ("r13") = pdst; + register unsigned const char *src __asm__ ("r11") = psrc; + register int n __asm__ ("r12") = pn; + + /* When src is aligned but not dst, this makes a few extra needless + cycles. I believe it would take as many to check that the + re-alignment was unnecessary. */ + if (((unsigned long) dst & 3) != 0 + /* Don't align if we wouldn't copy more than a few bytes; so we + don't have to check further for overflows. */ + && n >= 3) + { + if ((unsigned long) dst & 1) + { + n--; + *dst = *src; + src++; + dst++; + } + + if ((unsigned long) dst & 2) + { + n -= 2; + *(short *) dst = *(short *) src; + src += 2; + dst += 2; + } + } + + /* Decide which copying method to use. */ + if (n >= MEMCPY_BY_BLOCK_THRESHOLD) + { + /* It is not optimal to tell the compiler about clobbering any + registers; that will move the saving/restoring of those registers + to the function prologue/epilogue, and make non-movem sizes + suboptimal. */ + __asm__ volatile + ("\ + ;; GCC does promise correct register allocations, but let's \n\ + ;; make sure it keeps its promises. \n\ + .ifnc %0-%1-%2,$r13-$r11-$r12 \n\ + .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\ + .endif \n\ + \n\ + ;; Save the registers we'll use in the movem process \n\ + ;; on the stack. \n\ + subq 11*4,sp \n\ + movem r10,[sp] \n\ + \n\ + ;; Now we've got this: \n\ + ;; r11 - src \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop. \n\ + subq 44,r12 \n\ +0: \n\ +" +#ifdef __arch_common_v10_v32 + /* Cater to branch offset difference between v32 and v10. We + assume the branch below has an 8-bit offset. */ +" setf\n" +#endif +" movem [r11+],r10 \n\ + subq 44,r12 \n\ + bge 0b \n\ + movem r10,[r13+] \n\ + \n\ + ;; Compensate for last loop underflowing n. \n\ + addq 44,r12 \n\ + \n\ + ;; Restore registers from stack. \n\ + movem [sp+],r10" + + /* Outputs. */ + : "=r" (dst), "=r" (src), "=r" (n) + + /* Inputs. */ + : "0" (dst), "1" (src), "2" (n)); + } + + while (n >= 16) + { + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + + n -= 16; + } + + switch (n) + { + case 0: + break; + + case 1: + *dst = *src; + break; + + case 2: + *(short *) dst = *(short *) src; + break; + + case 3: + *(short *) dst = *(short *) src; dst += 2; src += 2; + *dst = *src; + break; + + case 4: + *(long *) dst = *(long *) src; + break; + + case 5: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *dst = *src; + break; + + case 6: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; + break; + + case 7: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; dst += 2; src += 2; + *dst = *src; + break; + + case 8: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; + break; + + case 9: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *dst = *src; + break; + + case 10: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; + break; + + case 11: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; dst += 2; src += 2; + *dst = *src; + break; + + case 12: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; + break; + + case 13: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *dst = *src; + break; + + case 14: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; + break; + + case 15: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; dst += 2; src += 2; + *dst = *src; + break; + } + + return return_dst; +} diff --git a/kernel/arch/cris/arch-v10/lib/usercopy.c b/kernel/arch/cris/arch-v10/lib/usercopy.c new file mode 100644 index 000000000..b964c667a --- /dev/null +++ b/kernel/arch/cris/arch-v10/lib/usercopy.c @@ -0,0 +1,523 @@ +/* + * User address space access functions. + * The non-inlined parts of asm-cris/uaccess.h are here. + * + * Copyright (C) 2000, Axis Communications AB. + * + * Written by Hans-Peter Nilsson. + * Pieces used from memcpy, originally by Kenny Ranerup long time ago. + */ + +#include + +/* Asm:s have been tweaked (within the domain of correctness) to give + satisfactory results for "gcc version 2.96 20000427 (experimental)". + + Check regularly... + + Note that the PC saved at a bus-fault is the address *after* the + faulting instruction, which means the branch-target for instructions in + delay-slots for taken branches. Note also that the postincrement in + the instruction is performed regardless of bus-fault; the register is + seen updated in fault handlers. + + Oh, and on the code formatting issue, to whomever feels like "fixing + it" to Conformity: I'm too "lazy", but why don't you go ahead and "fix" + string.c too. I just don't think too many people will hack this file + for the code format to be an issue. */ + + +/* Copy to userspace. This is based on the memcpy used for + kernel-to-kernel copying; see "string.c". */ + +unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn) +{ + /* We want the parameters put in special registers. + Make sure the compiler is able to make something useful of this. + As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). + + FIXME: Comment for old gcc version. Check. + If gcc was alright, it really would need no temporaries, and no + stack space to save stuff on. */ + + register char *dst __asm__ ("r13") = pdst; + register const char *src __asm__ ("r11") = psrc; + register int n __asm__ ("r12") = pn; + register int retn __asm__ ("r10") = 0; + + + /* When src is aligned but not dst, this makes a few extra needless + cycles. I believe it would take as many to check that the + re-alignment was unnecessary. */ + if (((unsigned long) dst & 3) != 0 + /* Don't align if we wouldn't copy more than a few bytes; so we + don't have to check further for overflows. */ + && n >= 3) + { + if ((unsigned long) dst & 1) + { + __asm_copy_to_user_1 (dst, src, retn); + n--; + } + + if ((unsigned long) dst & 2) + { + __asm_copy_to_user_2 (dst, src, retn); + n -= 2; + } + } + + /* Decide which copying method to use. */ + if (n >= 44*2) /* Break even between movem and + move16 is at 38.7*2, but modulo 44. */ + { + /* For large copies we use 'movem'. */ + + /* It is not optimal to tell the compiler about clobbering any + registers; that will move the saving/restoring of those registers + to the function prologue/epilogue, and make non-movem sizes + suboptimal. + + This method is not foolproof; it assumes that the "asm reg" + declarations at the beginning of the function really are used + here (beware: they may be moved to temporary registers). + This way, we do not have to save/move the registers around into + temporaries; we can safely use them straight away. + + If you want to check that the allocation was right; then + check the equalities in the first comment. It should say + "r13=r13, r11=r11, r12=r12". */ + __asm__ volatile ("\ + .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ + .err \n\ + .endif \n\ + \n\ + ;; Save the registers we'll use in the movem process \n\ + ;; on the stack. \n\ + subq 11*4,$sp \n\ + movem $r10,[$sp] \n\ + \n\ + ;; Now we've got this: \n\ + ;; r11 - src \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop \n\ + subq 44,$r12 \n\ + \n\ +; Since the noted PC of a faulting instruction in a delay-slot of a taken \n\ +; branch, is that of the branch target, we actually point at the from-movem \n\ +; for this case. There is no ambiguity here; if there was a fault in that \n\ +; instruction (meaning a kernel oops), the faulted PC would be the address \n\ +; after *that* movem. \n\ + \n\ +0: \n\ + movem [$r11+],$r10 \n\ + subq 44,$r12 \n\ + bge 0b \n\ + movem $r10,[$r13+] \n\ +1: \n\ + addq 44,$r12 ;; compensate for last loop underflowing n \n\ + \n\ + ;; Restore registers from stack \n\ + movem [$sp+],$r10 \n\ +2: \n\ + .section .fixup,\"ax\" \n\ + \n\ +; To provide a correct count in r10 of bytes that failed to be copied, \n\ +; we jump back into the loop if the loop-branch was taken. There is no \n\ +; performance penalty for sany use; the program will segfault soon enough.\n\ + \n\ +3: \n\ + move.d [$sp],$r10 \n\ + addq 44,$r10 \n\ + move.d $r10,[$sp] \n\ + jump 0b \n\ +4: \n\ + movem [$sp+],$r10 \n\ + addq 44,$r10 \n\ + addq 44,$r12 \n\ + jump 2b \n\ + \n\ + .previous \n\ + .section __ex_table,\"a\" \n\ + .dword 0b,3b \n\ + .dword 1b,4b \n\ + .previous" + + /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) + /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); + + } + + /* Either we directly start copying, using dword copying in a loop, or + we copy as much as possible with 'movem' and then the last block (<44 + bytes) is copied here. This will work since 'movem' will have + updated SRC, DST and N. */ + + while (n >= 16) + { + __asm_copy_to_user_16 (dst, src, retn); + n -= 16; + } + + /* Having a separate by-four loops cuts down on cache footprint. + FIXME: Test with and without; increasing switch to be 0..15. */ + while (n >= 4) + { + __asm_copy_to_user_4 (dst, src, retn); + n -= 4; + } + + switch (n) + { + case 0: + break; + case 1: + __asm_copy_to_user_1 (dst, src, retn); + break; + case 2: + __asm_copy_to_user_2 (dst, src, retn); + break; + case 3: + __asm_copy_to_user_3 (dst, src, retn); + break; + } + + return retn; +} +EXPORT_SYMBOL(__copy_user); + +/* Copy from user to kernel, zeroing the bytes that were inaccessible in + userland. The return-value is the number of bytes that were + inaccessible. */ + +unsigned long __copy_user_zeroing(void *pdst, const void __user *psrc, + unsigned long pn) +{ + /* We want the parameters put in special registers. + Make sure the compiler is able to make something useful of this. + As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). + + FIXME: Comment for old gcc version. Check. + If gcc was alright, it really would need no temporaries, and no + stack space to save stuff on. */ + + register char *dst __asm__ ("r13") = pdst; + register const char *src __asm__ ("r11") = psrc; + register int n __asm__ ("r12") = pn; + register int retn __asm__ ("r10") = 0; + + /* The best reason to align src is that we then know that a read-fault + was for aligned bytes; there's no 1..3 remaining good bytes to + pickle. */ + if (((unsigned long) src & 3) != 0) + { + if (((unsigned long) src & 1) && n != 0) + { + __asm_copy_from_user_1 (dst, src, retn); + n--; + } + + if (((unsigned long) src & 2) && n >= 2) + { + __asm_copy_from_user_2 (dst, src, retn); + n -= 2; + } + + /* We only need one check after the unalignment-adjustments, because + if both adjustments were done, either both or neither reference + had an exception. */ + if (retn != 0) + goto copy_exception_bytes; + } + + /* Decide which copying method to use. */ + if (n >= 44*2) /* Break even between movem and + move16 is at 38.7*2, but modulo 44. + FIXME: We use move4 now. */ + { + /* For large copies we use 'movem' */ + + /* It is not optimal to tell the compiler about clobbering any + registers; that will move the saving/restoring of those registers + to the function prologue/epilogue, and make non-movem sizes + suboptimal. + + This method is not foolproof; it assumes that the "asm reg" + declarations at the beginning of the function really are used + here (beware: they may be moved to temporary registers). + This way, we do not have to save/move the registers around into + temporaries; we can safely use them straight away. + + If you want to check that the allocation was right; then + check the equalities in the first comment. It should say + "r13=r13, r11=r11, r12=r12" */ + __asm__ volatile ("\n\ + .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ + .err \n\ + .endif \n\ + \n\ + ;; Save the registers we'll use in the movem process \n\ + ;; on the stack. \n\ + subq 11*4,$sp \n\ + movem $r10,[$sp] \n\ + \n\ + ;; Now we've got this: \n\ + ;; r11 - src \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop \n\ + subq 44,$r12 \n\ +0: \n\ + movem [$r11+],$r10 \n\ +1: \n\ + subq 44,$r12 \n\ + bge 0b \n\ + movem $r10,[$r13+] \n\ + \n\ + addq 44,$r12 ;; compensate for last loop underflowing n \n\ + \n\ + ;; Restore registers from stack \n\ + movem [$sp+],$r10 \n\ +4: \n\ + .section .fixup,\"ax\" \n\ + \n\ +;; Do not jump back into the loop if we fail. For some uses, we get a \n\ +;; page fault somewhere on the line. Without checking for page limits, \n\ +;; we don't know where, but we need to copy accurately and keep an \n\ +;; accurate count; not just clear the whole line. To do that, we fall \n\ +;; down in the code below, proceeding with smaller amounts. It should \n\ +;; be kept in mind that we have to cater to code like what at one time \n\ +;; was in fs/super.c: \n\ +;; i = size - copy_from_user((void *)page, data, size); \n\ +;; which would cause repeated faults while clearing the remainder of \n\ +;; the SIZE bytes at PAGE after the first fault. \n\ +;; A caveat here is that we must not fall through from a failing page \n\ +;; to a valid page. \n\ + \n\ +3: \n\ + movem [$sp+],$r10 \n\ + addq 44,$r12 ;; Get back count before faulting point. \n\ + subq 44,$r11 ;; Get back pointer to faulting movem-line. \n\ + jump 4b ;; Fall through, pretending the fault didn't happen.\n\ + \n\ + .previous \n\ + .section __ex_table,\"a\" \n\ + .dword 1b,3b \n\ + .previous" + + /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) + /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); + + } + + /* Either we directly start copying here, using dword copying in a loop, + or we copy as much as possible with 'movem' and then the last block + (<44 bytes) is copied here. This will work since 'movem' will have + updated src, dst and n. (Except with failing src.) + + Since we want to keep src accurate, we can't use + __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and + retn, but not src (by design; it's value is ignored elsewhere). */ + + while (n >= 4) + { + __asm_copy_from_user_4 (dst, src, retn); + n -= 4; + + if (retn) + goto copy_exception_bytes; + } + + /* If we get here, there were no memory read faults. */ + switch (n) + { + /* These copies are at least "naturally aligned" (so we don't have + to check each byte), due to the src alignment code before the + movem loop. The *_3 case *will* get the correct count for retn. */ + case 0: + /* This case deliberately left in (if you have doubts check the + generated assembly code). */ + break; + case 1: + __asm_copy_from_user_1 (dst, src, retn); + break; + case 2: + __asm_copy_from_user_2 (dst, src, retn); + break; + case 3: + __asm_copy_from_user_3 (dst, src, retn); + break; + } + + /* If we get here, retn correctly reflects the number of failing + bytes. */ + return retn; + +copy_exception_bytes: + /* We already have "retn" bytes cleared, and need to clear the + remaining "n" bytes. A non-optimized simple byte-for-byte in-line + memset is preferred here, since this isn't speed-critical code and + we'd rather have this a leaf-function than calling memset. */ + { + char *endp; + for (endp = dst + n; dst < endp; dst++) + *dst = 0; + } + + return retn + n; +} +EXPORT_SYMBOL(__copy_user_zeroing); + +/* Zero userspace. */ +unsigned long __do_clear_user(void __user *pto, unsigned long pn) +{ + /* We want the parameters put in special registers. + Make sure the compiler is able to make something useful of this. + As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). + + FIXME: Comment for old gcc version. Check. + If gcc was alright, it really would need no temporaries, and no + stack space to save stuff on. */ + + register char *dst __asm__ ("r13") = pto; + register int n __asm__ ("r12") = pn; + register int retn __asm__ ("r10") = 0; + + + if (((unsigned long) dst & 3) != 0 + /* Don't align if we wouldn't copy more than a few bytes. */ + && n >= 3) + { + if ((unsigned long) dst & 1) + { + __asm_clear_1 (dst, retn); + n--; + } + + if ((unsigned long) dst & 2) + { + __asm_clear_2 (dst, retn); + n -= 2; + } + } + + /* Decide which copying method to use. + FIXME: This number is from the "ordinary" kernel memset. */ + if (n >= (1*48)) + { + /* For large clears we use 'movem' */ + + /* It is not optimal to tell the compiler about clobbering any + call-saved registers; that will move the saving/restoring of + those registers to the function prologue/epilogue, and make + non-movem sizes suboptimal. + + This method is not foolproof; it assumes that the "asm reg" + declarations at the beginning of the function really are used + here (beware: they may be moved to temporary registers). + This way, we do not have to save/move the registers around into + temporaries; we can safely use them straight away. + + If you want to check that the allocation was right; then + check the equalities in the first comment. It should say + something like "r13=r13, r11=r11, r12=r12". */ + __asm__ volatile ("\n\ + .ifnc %0%1%2,$r13$r12$r10 \n\ + .err \n\ + .endif \n\ + \n\ + ;; Save the registers we'll clobber in the movem process \n\ + ;; on the stack. Don't mention them to gcc, it will only be \n\ + ;; upset. \n\ + subq 11*4,$sp \n\ + movem $r10,[$sp] \n\ + \n\ + clear.d $r0 \n\ + clear.d $r1 \n\ + clear.d $r2 \n\ + clear.d $r3 \n\ + clear.d $r4 \n\ + clear.d $r5 \n\ + clear.d $r6 \n\ + clear.d $r7 \n\ + clear.d $r8 \n\ + clear.d $r9 \n\ + clear.d $r10 \n\ + clear.d $r11 \n\ + \n\ + ;; Now we've got this: \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop \n\ + subq 12*4,$r12 \n\ +0: \n\ + subq 12*4,$r12 \n\ + bge 0b \n\ + movem $r11,[$r13+] \n\ +1: \n\ + addq 12*4,$r12 ;; compensate for last loop underflowing n\n\ + \n\ + ;; Restore registers from stack \n\ + movem [$sp+],$r10 \n\ +2: \n\ + .section .fixup,\"ax\" \n\ +3: \n\ + move.d [$sp],$r10 \n\ + addq 12*4,$r10 \n\ + move.d $r10,[$sp] \n\ + clear.d $r10 \n\ + jump 0b \n\ + \n\ +4: \n\ + movem [$sp+],$r10 \n\ + addq 12*4,$r10 \n\ + addq 12*4,$r12 \n\ + jump 2b \n\ + \n\ + .previous \n\ + .section __ex_table,\"a\" \n\ + .dword 0b,3b \n\ + .dword 1b,4b \n\ + .previous" + + /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn) + /* Inputs */ : "0" (dst), "1" (n), "2" (retn) + /* Clobber */ : "r11"); + } + + while (n >= 16) + { + __asm_clear_16 (dst, retn); + n -= 16; + } + + /* Having a separate by-four loops cuts down on cache footprint. + FIXME: Test with and without; increasing switch to be 0..15. */ + while (n >= 4) + { + __asm_clear_4 (dst, retn); + n -= 4; + } + + switch (n) + { + case 0: + break; + case 1: + __asm_clear_1 (dst, retn); + break; + case 2: + __asm_clear_2 (dst, retn); + break; + case 3: + __asm_clear_3 (dst, retn); + break; + } + + return retn; +} +EXPORT_SYMBOL(__do_clear_user); diff --git a/kernel/arch/cris/arch-v10/mm/Makefile b/kernel/arch/cris/arch-v10/mm/Makefile new file mode 100644 index 000000000..588b4baee --- /dev/null +++ b/kernel/arch/cris/arch-v10/mm/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the linux cris-specific parts of the memory manager. +# + +obj-y := fault.o init.o tlb.o + diff --git a/kernel/arch/cris/arch-v10/mm/fault.c b/kernel/arch/cris/arch-v10/mm/fault.c new file mode 100644 index 000000000..ed60588f8 --- /dev/null +++ b/kernel/arch/cris/arch-v10/mm/fault.c @@ -0,0 +1,95 @@ +/* + * linux/arch/cris/mm/fault.c + * + * Low level bus fault handler + * + * + * Copyright (C) 2000-2007 Axis Communications AB + * + * Authors: Bjorn Wesen + * + */ + +#include +#include +#include +#include +#include + +/* debug of low-level TLB reload */ +#undef DEBUG + +#ifdef DEBUG +#define D(x) x +#else +#define D(x) +#endif + +extern const struct exception_table_entry + *search_exception_tables(unsigned long addr); + +asmlinkage void do_page_fault(unsigned long address, struct pt_regs *regs, + int protection, int writeaccess); + +/* fast TLB-fill fault handler + * this is called from entry.S with interrupts disabled + */ + +void +handle_mmu_bus_fault(struct pt_regs *regs) +{ + int cause; + int select; +#ifdef DEBUG + int index; + int page_id; + int acc, inv; +#endif + pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id()); + pmd_t *pmd; + pte_t pte; + int miss, we, writeac; + unsigned long address; + unsigned long flags; + + cause = *R_MMU_CAUSE; + + address = cause & PAGE_MASK; /* get faulting address */ + select = *R_TLB_SELECT; + +#ifdef DEBUG + page_id = IO_EXTRACT(R_MMU_CAUSE, page_id, cause); + acc = IO_EXTRACT(R_MMU_CAUSE, acc_excp, cause); + inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause); + index = IO_EXTRACT(R_TLB_SELECT, index, select); +#endif + miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause); + we = IO_EXTRACT(R_MMU_CAUSE, we_excp, cause); + writeac = IO_EXTRACT(R_MMU_CAUSE, wr_rd, cause); + + D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n", + regs->irp, address, miss, inv, we, acc, index, page_id)); + + /* leave it to the MM system fault handler */ + if (miss) + do_page_fault(address, regs, 0, writeac); + else + do_page_fault(address, regs, 1, we); + + /* Reload TLB with new entry to avoid an extra miss exception. + * do_page_fault may have flushed the TLB so we have to restore + * the MMU registers. + */ + local_irq_save(flags); + pmd = (pmd_t *)(pgd + pgd_index(address)); + if (pmd_none(*pmd)) + goto exit; + pte = *pte_offset_kernel(pmd, address); + if (!pte_present(pte)) + goto exit; + *R_TLB_SELECT = select; + *R_TLB_HI = cause; + *R_TLB_LO = pte_val(pte); +exit: + local_irq_restore(flags); +} diff --git a/kernel/arch/cris/arch-v10/mm/init.c b/kernel/arch/cris/arch-v10/mm/init.c new file mode 100644 index 000000000..e7f806610 --- /dev/null +++ b/kernel/arch/cris/arch-v10/mm/init.c @@ -0,0 +1,263 @@ +/* + * linux/arch/cris/arch-v10/mm/init.c + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void tlb_init(void); + +/* + * The kernel is already mapped with a kernel segment at kseg_c so + * we don't need to map it with a page table. However head.S also + * temporarily mapped it at kseg_4 so we should set up the ksegs again, + * clear the TLB and do some other paging setup stuff. + */ + +void __init +paging_init(void) +{ + int i; + unsigned long zones_size[MAX_NR_ZONES]; + + printk("Setting up paging and the MMU.\n"); + + /* clear out the init_mm.pgd that will contain the kernel's mappings */ + + for(i = 0; i < PTRS_PER_PGD; i++) + swapper_pg_dir[i] = __pgd(0); + + /* make sure the current pgd table points to something sane + * (even if it is most probably not used until the next + * switch_mm) + */ + + per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd; + + /* initialise the TLB (tlb.c) */ + + tlb_init(); + + /* see README.mm for details on the KSEG setup */ + +#ifdef CONFIG_CRIS_LOW_MAP + /* Etrax-100 LX version 1 has a bug so that we cannot map anything + * across the 0x80000000 boundary, so we need to shrink the user-virtual + * area to 0x50000000 instead of 0xb0000000 and map things slightly + * different. The unused areas are marked as paged so that we can catch + * freak kernel accesses there. + * + * The ARTPEC chip is mapped at 0xa so we pass that segment straight + * through. We cannot vremap it because the vmalloc area is below 0x8 + * and Juliette needs an uncached area above 0x8. + * + * Same thing with 0xc and 0x9, which is memory-mapped I/O on some boards. + * We map them straight over in LOW_MAP, but use vremap in LX version 2. + */ + +#define CACHED_BOOTROM (KSEG_F | 0x08000000UL) + + *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */ + IO_STATE(R_MMU_KSEG, seg_e, page ) | + IO_STATE(R_MMU_KSEG, seg_d, page ) | + IO_STATE(R_MMU_KSEG, seg_c, page ) | + IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */ +#ifdef CONFIG_JULIETTE + IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */ +#else + IO_STATE(R_MMU_KSEG, seg_a, page ) | +#endif + IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */ + IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */ + IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */ + IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */ + IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */ + IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */ + IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */ + IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */ + IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */ + IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */ + + *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) | + IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) | + IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) | + IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) | + IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) | +#ifdef CONFIG_JULIETTE + IO_FIELD(R_MMU_KBASE_HI, base_a, 0xa ) | +#else + IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) | +#endif + IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) | + IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) ); + + *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) | + IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) ); +#else + /* This code is for the corrected Etrax-100 LX version 2... */ + +#define CACHED_BOOTROM (KSEG_A | 0x08000000UL) + + *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */ + IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */ + IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */ + IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */ + IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */ + IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */ + IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */ + IO_STATE(R_MMU_KSEG, seg_8, page ) | + IO_STATE(R_MMU_KSEG, seg_7, page ) | + IO_STATE(R_MMU_KSEG, seg_6, page ) | + IO_STATE(R_MMU_KSEG, seg_5, page ) | + IO_STATE(R_MMU_KSEG, seg_4, page ) | + IO_STATE(R_MMU_KSEG, seg_3, page ) | + IO_STATE(R_MMU_KSEG, seg_2, page ) | + IO_STATE(R_MMU_KSEG, seg_1, page ) | + IO_STATE(R_MMU_KSEG, seg_0, page ) ); + + *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) | + IO_FIELD(R_MMU_KBASE_HI, base_e, 0x8 ) | + IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) | + IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) | + IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) | + IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) | + IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) | + IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) ); + + *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_6, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) | + IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) ); +#endif + + *R_MMU_CONTEXT = ( IO_FIELD(R_MMU_CONTEXT, page_id, 0 ) ); + + /* The MMU has been enabled ever since head.S but just to make + * it totally obvious we do it here as well. + */ + + *R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) | + IO_STATE(R_MMU_CTRL, acc_excp, enable ) | + IO_STATE(R_MMU_CTRL, we_excp, enable ) ); + + *R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable); + + /* + * initialize the bad page table and bad page to point + * to a couple of allocated pages + */ + + empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); + memset((void *)empty_zero_page, 0, PAGE_SIZE); + + /* All pages are DMA'able in Etrax, so put all in the DMA'able zone */ + + zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT; + + for (i = 1; i < MAX_NR_ZONES; i++) + zones_size[i] = 0; + + /* Use free_area_init_node instead of free_area_init, because the former + * is designed for systems where the DRAM starts at an address substantially + * higher than 0, like us (we start at PAGE_OFFSET). This saves space in the + * mem_map page array. + */ + + free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); +} + +/* Initialize remaps of some I/O-ports. It is important that this + * is called before any driver is initialized. + */ + +static int +__init init_ioremap(void) +{ + + /* Give the external I/O-port addresses their values */ + +#ifdef CONFIG_CRIS_LOW_MAP + /* Simply a linear map (see the KSEG map above in paging_init) */ + port_cse1_addr = (volatile unsigned long *)(MEM_CSE1_START | + MEM_NON_CACHEABLE); + port_csp0_addr = (volatile unsigned long *)(MEM_CSP0_START | + MEM_NON_CACHEABLE); + port_csp4_addr = (volatile unsigned long *)(MEM_CSP4_START | + MEM_NON_CACHEABLE); +#else + /* Note that nothing blows up just because we do this remapping + * it's ok even if the ports are not used or connected + * to anything (or connected to a non-I/O thing) */ + port_cse1_addr = (volatile unsigned long *) + ioremap((unsigned long)(MEM_CSE1_START | MEM_NON_CACHEABLE), 16); + port_csp0_addr = (volatile unsigned long *) + ioremap((unsigned long)(MEM_CSP0_START | MEM_NON_CACHEABLE), 16); + port_csp4_addr = (volatile unsigned long *) + ioremap((unsigned long)(MEM_CSP4_START | MEM_NON_CACHEABLE), 16); +#endif + return 0; +} + +__initcall(init_ioremap); + +/* Helper function for the two below */ + +static inline void +flush_etrax_cacherange(void *startadr, int length) +{ + /* CACHED_BOOTROM is mapped to the boot-rom area (cached) which + * we can use to get fast dummy-reads of cachelines + */ + + volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) | + CACHED_BOOTROM); + + length = length > 8192 ? 8192 : length; /* No need to flush more than cache size */ + + while(length > 0) { + *flushadr; /* dummy read to flush */ + flushadr += (32/sizeof(short)); /* a cacheline is 32 bytes */ + length -= 32; + } +} + +/* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers + * will occasionally corrupt certain CPU writes if the DMA buffers + * happen to be hot in the cache. + * + * As a workaround, we have to flush the relevant parts of the cache + * before (re) inserting any receiving descriptor into the DMA HW. + */ + +void +prepare_rx_descriptor(struct etrax_dma_descr *desc) +{ + flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536); +} + +/* Do the same thing but flush the entire cache */ + +void +flush_etrax_cache(void) +{ + flush_etrax_cacherange(0, 8192); +} diff --git a/kernel/arch/cris/arch-v10/mm/tlb.c b/kernel/arch/cris/arch-v10/mm/tlb.c new file mode 100644 index 000000000..21d78c599 --- /dev/null +++ b/kernel/arch/cris/arch-v10/mm/tlb.c @@ -0,0 +1,176 @@ +/* + * linux/arch/cris/arch-v10/mm/tlb.c + * + * Low level TLB handling + * + * + * Copyright (C) 2000-2007 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * + */ + +#include +#include +#include + +#define D(x) + +/* The TLB can host up to 64 different mm contexts at the same time. + * The running context is R_MMU_CONTEXT, and each TLB entry contains a + * page_id that has to match to give a hit. In page_id_map, we keep track + * of which mm's we have assigned which page_id's, so that we know when + * to invalidate TLB entries. + * + * The last page_id is never running - it is used as an invalid page_id + * so we can make TLB entries that will never match. + * + * Notice that we need to make the flushes atomic, otherwise an interrupt + * handler that uses vmalloced memory might cause a TLB load in the middle + * of a flush causing. + */ + +/* invalidate all TLB entries */ + +void +flush_tlb_all(void) +{ + int i; + unsigned long flags; + + /* the vpn of i & 0xf is so we dont write similar TLB entries + * in the same 4-way entry group. details... + */ + + local_irq_save(flags); + for(i = 0; i < NUM_TLB_ENTRIES; i++) { + *R_TLB_SELECT = ( IO_FIELD(R_TLB_SELECT, index, i) ); + *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) | + IO_FIELD(R_TLB_HI, vpn, i & 0xf ) ); + + *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | + IO_STATE(R_TLB_LO, valid, no ) | + IO_STATE(R_TLB_LO, kernel,no ) | + IO_STATE(R_TLB_LO, we, no ) | + IO_FIELD(R_TLB_LO, pfn, 0 ) ); + } + local_irq_restore(flags); + D(printk("tlb: flushed all\n")); +} + +/* invalidate the selected mm context only */ + +void +flush_tlb_mm(struct mm_struct *mm) +{ + int i; + int page_id = mm->context.page_id; + unsigned long flags; + + D(printk("tlb: flush mm context %d (%p)\n", page_id, mm)); + + if(page_id == NO_CONTEXT) + return; + + /* mark the TLB entries that match the page_id as invalid. + * here we could also check the _PAGE_GLOBAL bit and NOT flush + * global pages. is it worth the extra I/O ? + */ + + local_irq_save(flags); + for(i = 0; i < NUM_TLB_ENTRIES; i++) { + *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i); + if (IO_EXTRACT(R_TLB_HI, page_id, *R_TLB_HI) == page_id) { + *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) | + IO_FIELD(R_TLB_HI, vpn, i & 0xf ) ); + + *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | + IO_STATE(R_TLB_LO, valid, no ) | + IO_STATE(R_TLB_LO, kernel,no ) | + IO_STATE(R_TLB_LO, we, no ) | + IO_FIELD(R_TLB_LO, pfn, 0 ) ); + } + } + local_irq_restore(flags); +} + +/* invalidate a single page */ + +void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) +{ + struct mm_struct *mm = vma->vm_mm; + int page_id = mm->context.page_id; + int i; + unsigned long flags; + + D(printk("tlb: flush page %p in context %d (%p)\n", addr, page_id, mm)); + + if(page_id == NO_CONTEXT) + return; + + addr &= PAGE_MASK; /* perhaps not necessary */ + + /* invalidate those TLB entries that match both the mm context + * and the virtual address requested + */ + + local_irq_save(flags); + for(i = 0; i < NUM_TLB_ENTRIES; i++) { + unsigned long tlb_hi; + *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i); + tlb_hi = *R_TLB_HI; + if (IO_EXTRACT(R_TLB_HI, page_id, tlb_hi) == page_id && + (tlb_hi & PAGE_MASK) == addr) { + *R_TLB_HI = IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) | + addr; /* same addr as before works. */ + + *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | + IO_STATE(R_TLB_LO, valid, no ) | + IO_STATE(R_TLB_LO, kernel,no ) | + IO_STATE(R_TLB_LO, we, no ) | + IO_FIELD(R_TLB_LO, pfn, 0 ) ); + } + } + local_irq_restore(flags); +} + +/* + * Initialize the context related info for a new mm_struct + * instance. + */ + +int +init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ + mm->context.page_id = NO_CONTEXT; + return 0; +} + +/* called in schedule() just before actually doing the switch_to */ + +void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + if (prev != next) { + /* make sure we have a context */ + get_mmu_context(next); + + /* remember the pgd for the fault handlers + * this is similar to the pgd register in some other CPU's. + * we need our own copy of it because current and active_mm + * might be invalid at points where we still need to derefer + * the pgd. + */ + + per_cpu(current_pgd, smp_processor_id()) = next->pgd; + + /* switch context in the MMU */ + + D(printk(KERN_DEBUG "switching mmu_context to %d (%p)\n", + next->context, next)); + + *R_MMU_CONTEXT = IO_FIELD(R_MMU_CONTEXT, + page_id, next->context.page_id); + } +} + diff --git a/kernel/arch/cris/arch-v10/output_arch.ld b/kernel/arch/cris/arch-v10/output_arch.ld new file mode 100644 index 000000000..2f3288006 --- /dev/null +++ b/kernel/arch/cris/arch-v10/output_arch.ld @@ -0,0 +1,2 @@ +/* At the time of this writing, there's no equivalent ld option. */ +OUTPUT_ARCH (cris) diff --git a/kernel/arch/cris/arch-v32/Kconfig b/kernel/arch/cris/arch-v32/Kconfig new file mode 100644 index 000000000..21bbd93be --- /dev/null +++ b/kernel/arch/cris/arch-v32/Kconfig @@ -0,0 +1,299 @@ +if ETRAX_ARCH_V32 + +source arch/cris/arch-v32/mach-fs/Kconfig +source arch/cris/arch-v32/mach-a3/Kconfig + +source drivers/cpufreq/Kconfig + +config ETRAX_DRAM_VIRTUAL_BASE + hex + depends on ETRAX_ARCH_V32 + default "c0000000" + +choice + prompt "Nbr of Ethernet LED groups" + depends on ETRAX_ARCH_V32 + default ETRAX_NBR_LED_GRP_ONE + help + Select how many Ethernet LED groups that can be used. Usually one per Ethernet + interface is a good choice. + +config ETRAX_NBR_LED_GRP_ZERO + bool "Use zero LED groups" + help + Select this if you do not want any Ethernet LEDs. + +config ETRAX_NBR_LED_GRP_ONE + bool "Use one LED group" + help + Select this if you want one Ethernet LED group. This LED group + can be used for one or more Ethernet interfaces. However, it is + recommended that each Ethernet interface use a dedicated LED group. + +config ETRAX_NBR_LED_GRP_TWO + bool "Use two LED groups" + help + Select this if you want two Ethernet LED groups. This is the + best choice if you have more than one Ethernet interface and + would like to have separate LEDs for the interfaces. + +endchoice + +config ETRAX_LED_G_NET0 + string "Ethernet LED group 0 green LED bit" + depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO) + default "PA3" + help + Bit to use for the green LED in Ethernet LED group 0. + +config ETRAX_LED_R_NET0 + string "Ethernet LED group 0 red LED bit" + depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO) + default "PA4" + help + Bit to use for the red LED in Ethernet LED group 0. + +config ETRAX_LED_G_NET1 + string "Ethernet group 1 green LED bit" + depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO + default "" + help + Bit to use for the green LED in Ethernet LED group 1. + +config ETRAX_LED_R_NET1 + string "Ethernet group 1 red LED bit" + depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO + default "" + help + Bit to use for the red LED in Ethernet LED group 1. + +config ETRAX_V32_LED2G + string "Second green LED bit" + depends on ETRAX_ARCH_V32 + default "PA5" + help + Bit to use for the first green LED (status LED). + Most Axis products use bit A5 here. + +config ETRAX_V32_LED2R + string "Second red LED bit" + depends on ETRAX_ARCH_V32 + default "PA6" + help + Bit to use for the first red LED (network LED). + Most Axis products use bit A6 here. + +config ETRAX_V32_LED3G + string "Third green LED bit" + depends on ETRAX_ARCH_V32 + default "PA7" + help + Bit to use for the first green LED (drive/power LED). + Most Axis products use bit A7 here. + +config ETRAX_V32_LED3R + string "Third red LED bit" + depends on ETRAX_ARCH_V32 + default "PA7" + help + Bit to use for the first red LED (drive/power LED). + Most Axis products use bit A7 here. + +choice + prompt "Kernel GDB port" + depends on ETRAX_KGDB + default ETRAX_KGDB_PORT0 + help + Choose a serial port for kernel debugging. NOTE: This port should + not be enabled under Drivers for built-in interfaces (as it has its + own initialization code) and should not be the same as the debug port. + +config ETRAX_KGDB_PORT4 + bool "Serial-4" + depends on ETRAX_SERIAL_PORTS = 5 + help + Use serial port 4 for kernel debugging. + +endchoice + +config ETRAX_MEM_GRP1_CONFIG + hex "MEM_GRP1_CONFIG" + depends on ETRAX_ARCH_V32 + default "4044a" + help + Waitstates for flash. The default value is suitable for the + standard flashes used in axis products (120 ns). + +config ETRAX_MEM_GRP2_CONFIG + hex "MEM_GRP2_CONFIG" + depends on ETRAX_ARCH_V32 + default "0" + help + Waitstates for SRAM. 0 is a good choice for most Axis products. + +config ETRAX_MEM_GRP3_CONFIG + hex "MEM_GRP3_CONFIG" + depends on ETRAX_ARCH_V32 + default "0" + help + Waitstates for CSP0-3. 0 is a good choice for most Axis products. + It may need to be changed if external devices such as extra + register-mapped LEDs are used. + +config ETRAX_MEM_GRP4_CONFIG + hex "MEM_GRP4_CONFIG" + depends on ETRAX_ARCH_V32 + default "0" + help + Waitstates for CSP4-6. 0 is a good choice for most Axis products. + +config ETRAX_SDRAM_GRP0_CONFIG + hex "SDRAM_GRP0_CONFIG" + depends on ETRAX_ARCH_V32 + default "336" + help + SDRAM configuration for group 0. The value depends on the + hardware configuration. The default value is suitable + for 32 MB organized as two 16 bits chips (e.g. Axis + part number 18550) connected as one 32 bit device (i.e. in + the same group). + +config ETRAX_SDRAM_GRP1_CONFIG + hex "SDRAM_GRP1_CONFIG" + depends on ETRAX_ARCH_V32 + default "0" + help + SDRAM configuration for group 1. The default value is 0 + because group 1 is not used in the default configuration, + described in the help for SDRAM_GRP0_CONFIG. + +config ETRAX_SDRAM_TIMING + hex "SDRAM_TIMING" + depends on ETRAX_ARCH_V32 + default "104a" + help + SDRAM timing parameters. The default value is ok for + most hardwares but large SDRAMs may require a faster + refresh (a.k.a 8K refresh). The default value implies + 100MHz clock and SDR mode. + +config ETRAX_SDRAM_COMMAND + hex "SDRAM_COMMAND" + depends on ETRAX_ARCH_V32 + default "0" + help + SDRAM command. Should be 0 unless you really know what + you are doing (may be != 0 for unusual address line + mappings such as in a MCM).. + +config ETRAX_DEF_GIO_PA_OE + hex "GIO_PA_OE" + depends on ETRAX_ARCH_V32 + default "1c" + help + Configures the direction of general port A bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PA_OUT + hex "GIO_PA_OUT" + depends on ETRAX_ARCH_V32 + default "00" + help + Configures the initial data for the general port A bits. Most + products should use 00 here. + +config ETRAX_DEF_GIO_PB_OE + hex "GIO_PB_OE" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the direction of general port B bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PB_OUT + hex "GIO_PB_OUT" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the initial data for the general port B bits. Most + products should use 00000 here. + +config ETRAX_DEF_GIO_PC_OE + hex "GIO_PC_OE" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the direction of general port C bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PC_OUT + hex "GIO_PC_OUT" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the initial data for the general port C bits. Most + products should use 00000 here. + +config ETRAX_DEF_GIO_PD_OE + hex "GIO_PD_OE" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the direction of general port D bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PD_OUT + hex "GIO_PD_OUT" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the initial data for the general port D bits. Most + products should use 00000 here. + +config ETRAX_DEF_GIO_PE_OE + hex "GIO_PE_OE" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the direction of general port E bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PE_OUT + hex "GIO_PE_OUT" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the initial data for the general port E bits. Most + products should use 00000 here. + +endif diff --git a/kernel/arch/cris/arch-v32/drivers/Kconfig b/kernel/arch/cris/arch-v32/drivers/Kconfig new file mode 100644 index 000000000..4fc16b44f --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/Kconfig @@ -0,0 +1,430 @@ +if ETRAX_ARCH_V32 + +config ETRAX_ETHERNET + bool "Ethernet support" + depends on ETRAX_ARCH_V32 && NETDEVICES + select MII + help + This option enables the ETRAX FS built-in 10/100Mbit Ethernet + controller. + +config ETRAX_NO_PHY + bool "PHY not present" + depends on ETRAX_ETHERNET + help + This option disables all MDIO communication with an ethernet + transceiver connected to the MII interface. This option shall + typically be enabled if the MII interface is connected to a + switch. This option should normally be disabled. If enabled, + speed and duplex will be locked to 100 Mbit and full duplex. + +config ETRAXFS_SERIAL + bool "Serial-port support" + depends on ETRAX_ARCH_V32 + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + help + Enables the ETRAX FS serial driver for ser0 (ttyS0) + You probably want this enabled. + +config ETRAX_RS485 + bool "RS-485 support" + depends on ETRAXFS_SERIAL + help + Enables support for RS-485 serial communication. + +config ETRAX_RS485_DISABLE_RECEIVER + bool "Disable serial receiver" + depends on ETRAX_RS485 + help + It is necessary to disable the serial receiver to avoid serial + loopback. Not all products are able to do this in software only. + +config ETRAX_SERIAL_PORT0 + bool "Serial port 0 enabled" + depends on ETRAXFS_SERIAL + help + Enables the ETRAX FS serial driver for ser0 (ttyS0) + Normally you want this on. You can control what DMA channels to use + if you do not need DMA to something else. + ser0 can use dma4 or dma6 for output and dma5 or dma7 for input. + +config ETRAX_SERIAL_PORT1 + bool "Serial port 1 enabled" + depends on ETRAXFS_SERIAL + help + Enables the ETRAX FS serial driver for ser1 (ttyS1). + +config ETRAX_SERIAL_PORT2 + bool "Serial port 2 enabled" + depends on ETRAXFS_SERIAL + help + Enables the ETRAX FS serial driver for ser2 (ttyS2). + +config ETRAX_SERIAL_PORT3 + bool "Serial port 3 enabled" + depends on ETRAXFS_SERIAL + help + Enables the ETRAX FS serial driver for ser3 (ttyS3). + +config ETRAX_SYNCHRONOUS_SERIAL + bool "Synchronous serial-port support" + depends on ETRAX_ARCH_V32 + help + Enables the ETRAX FS synchronous serial driver. + +config ETRAX_SYNCHRONOUS_SERIAL_PORT0 + bool "Synchronous serial port 0 enabled" + depends on ETRAX_SYNCHRONOUS_SERIAL + help + Enabled synchronous serial port 0. + +config ETRAX_SYNCHRONOUS_SERIAL0_DMA + bool "Enable DMA on synchronous serial port 0." + depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0 + help + A synchronous serial port can run in manual or DMA mode. + Selecting this option will make it run in DMA mode. + +config ETRAX_SYNCHRONOUS_SERIAL_PORT1 + bool "Synchronous serial port 1 enabled" + depends on ETRAX_SYNCHRONOUS_SERIAL && ETRAXFS + help + Enabled synchronous serial port 1. + +config ETRAX_SYNCHRONOUS_SERIAL1_DMA + bool "Enable DMA on synchronous serial port 1." + depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1 + help + A synchronous serial port can run in manual or DMA mode. + Selecting this option will make it run in DMA mode. + +config ETRAX_AXISFLASHMAP + bool "Axis flash-map support" + depends on ETRAX_ARCH_V32 + select MTD + select MTD_CFI + select MTD_CFI_AMDSTD + select MTD_JEDECPROBE + select MTD_BLOCK + select MTD_COMPLEX_MAPPINGS + select MTD_MTDRAM + help + This option enables MTD mapping of flash devices. Needed to use + flash memories. If unsure, say Y. + +config ETRAX_AXISFLASHMAP_MTD0WHOLE + bool "MTD0 is whole boot flash device" + depends on ETRAX_AXISFLASHMAP + help + When this option is not set, mtd0 refers to the first partition + on the boot flash device. When set, mtd0 refers to the whole + device, with mtd1 referring to the first partition etc. + +config ETRAX_PTABLE_SECTOR + int "Byte-offset of partition table sector" + depends on ETRAX_AXISFLASHMAP + default "65536" + help + Byte-offset of the partition table in the first flash chip. + The default value is 64kB and should not be changed unless + you know exactly what you are doing. The only valid reason + for changing this is when the flash block size is bigger + than 64kB (e.g. when using two parallel 16 bit flashes). + +config ETRAX_NANDFLASH + bool "NAND flash support" + depends on ETRAX_ARCH_V32 + select MTD_NAND + select MTD_NAND_IDS + help + This option enables MTD mapping of NAND flash devices. Needed to use + NAND flash memories. If unsure, say Y. + +config ETRAX_NANDBOOT + bool "Boot from NAND flash" + depends on ETRAX_NANDFLASH + help + This options enables booting from NAND flash devices. + Say Y if your boot code, kernel and root file system is in + NAND flash. Say N if they are in NOR flash. + +config ETRAX_I2C + bool "I2C driver" + depends on ETRAX_ARCH_V32 + help + This option enables the I2C driver used by e.g. the RTC driver. + +config ETRAX_V32_I2C_DATA_PORT + string "I2C data pin" + depends on ETRAX_I2C + help + The pin to use for I2C data. + +config ETRAX_V32_I2C_CLK_PORT + string "I2C clock pin" + depends on ETRAX_I2C + help + The pin to use for I2C clock. + +config ETRAX_GPIO + bool "GPIO support" + depends on ETRAX_ARCH_V32 + ---help--- + Enables the ETRAX general port device (major 120, minors 0-4). + You can use this driver to access the general port bits. It supports + these ioctl's: + #include + fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob + ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set); + ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear); + err = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READ_INBITS), &val); + Remember that you need to setup the port directions appropriately in + the General configuration. + +config ETRAX_VIRTUAL_GPIO + bool "Virtual GPIO support" + depends on ETRAX_GPIO + help + Enables the virtual Etrax general port device (major 120, minor 6). + It uses an I/O expander for the I2C-bus. + +config ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN + int "Virtual GPIO interrupt pin on PA pin" + range 0 7 + depends on ETRAX_VIRTUAL_GPIO + help + The pin to use on PA for virtual gpio interrupt. + +config ETRAX_PA_CHANGEABLE_DIR + hex "PA user changeable dir mask" + depends on ETRAX_GPIO + default "0x00" if ETRAXFS + default "0x00000000" if !ETRAXFS + help + This is a bitmask (8 bits) with information of what bits in PA that a + user can change direction on using ioctl's. + Bit set = changeable. + You probably want 0 here, but it depends on your hardware. + +config ETRAX_PA_CHANGEABLE_BITS + hex "PA user changeable bits mask" + depends on ETRAX_GPIO + default "0x00" if ETRAXFS + default "0x00000000" if !ETRAXFS + help + This is a bitmask (8 bits) with information of what bits in PA + that a user can change the value on using ioctl's. + Bit set = changeable. + +config ETRAX_PB_CHANGEABLE_DIR + hex "PB user changeable dir mask" + depends on ETRAX_GPIO + default "0x00000" if ETRAXFS + default "0x00000000" if !ETRAXFS + help + This is a bitmask (18 bits) with information of what bits in PB + that a user can change direction on using ioctl's. + Bit set = changeable. + You probably want 0 here, but it depends on your hardware. + +config ETRAX_PB_CHANGEABLE_BITS + hex "PB user changeable bits mask" + depends on ETRAX_GPIO + default "0x00000" if ETRAXFS + default "0x00000000" if !ETRAXFS + help + This is a bitmask (18 bits) with information of what bits in PB + that a user can change the value on using ioctl's. + Bit set = changeable. + +config ETRAX_PC_CHANGEABLE_DIR + hex "PC user changeable dir mask" + depends on ETRAX_GPIO + default "0x00000" if ETRAXFS + default "0x00000000" if !ETRAXFS + help + This is a bitmask (18 bits) with information of what bits in PC + that a user can change direction on using ioctl's. + Bit set = changeable. + You probably want 0 here, but it depends on your hardware. + +config ETRAX_PC_CHANGEABLE_BITS + hex "PC user changeable bits mask" + depends on ETRAX_GPIO + default "0x00000" if ETRAXFS + default "0x00000000" if ETRAXFS + help + This is a bitmask (18 bits) with information of what bits in PC + that a user can change the value on using ioctl's. + Bit set = changeable. + +config ETRAX_PD_CHANGEABLE_DIR + hex "PD user changeable dir mask" + depends on ETRAX_GPIO && ETRAXFS + default "0x00000" + help + This is a bitmask (18 bits) with information of what bits in PD + that a user can change direction on using ioctl's. + Bit set = changeable. + You probably want 0x00000 here, but it depends on your hardware. + +config ETRAX_PD_CHANGEABLE_BITS + hex "PD user changeable bits mask" + depends on ETRAX_GPIO && ETRAXFS + default "0x00000" + help + This is a bitmask (18 bits) with information of what bits in PD + that a user can change the value on using ioctl's. + Bit set = changeable. + +config ETRAX_PE_CHANGEABLE_DIR + hex "PE user changeable dir mask" + depends on ETRAX_GPIO && ETRAXFS + default "0x00000" + help + This is a bitmask (18 bits) with information of what bits in PE + that a user can change direction on using ioctl's. + Bit set = changeable. + You probably want 0x00000 here, but it depends on your hardware. + +config ETRAX_PE_CHANGEABLE_BITS + hex "PE user changeable bits mask" + depends on ETRAX_GPIO && ETRAXFS + default "0x00000" + help + This is a bitmask (18 bits) with information of what bits in PE + that a user can change the value on using ioctl's. + Bit set = changeable. + +config ETRAX_PV_CHANGEABLE_DIR + hex "PV user changeable dir mask" + depends on ETRAX_VIRTUAL_GPIO + default "0x0000" + help + This is a bitmask (16 bits) with information of what bits in PV + that a user can change direction on using ioctl's. + Bit set = changeable. + You probably want 0x0000 here, but it depends on your hardware. + +config ETRAX_PV_CHANGEABLE_BITS + hex "PV user changeable bits mask" + depends on ETRAX_VIRTUAL_GPIO + default "0x0000" + help + This is a bitmask (16 bits) with information of what bits in PV + that a user can change the value on using ioctl's. + Bit set = changeable. + +config ETRAX_CARDBUS + bool "Cardbus support" + depends on ETRAX_ARCH_V32 + help + Enabled the ETRAX Cardbus driver. + +config PCI + bool + depends on ETRAX_CARDBUS + default y + select HAVE_GENERIC_DMA_COHERENT + +config ETRAX_IOP_FW_LOAD + tristate "IO-processor hotplug firmware loading support" + depends on ETRAX_ARCH_V32 + select FW_LOADER + help + Enables IO-processor hotplug firmware loading support. + +config ETRAX_STREAMCOPROC + tristate "Stream co-processor driver enabled" + depends on ETRAX_ARCH_V32 + help + This option enables a driver for the stream co-processor + for cryptographic operations. + +config ETRAX_MMC_IOP + tristate "MMC/SD host driver using IO-processor" + depends on ETRAX_ARCH_V32 && MMC + help + This option enables the SD/MMC host controller interface. + The host controller is implemented using the built in + IO-Processor. Only the SPU is used in this implementation. + +config ETRAX_SPI_MMC +# Make this one of several "choices" (possible simultaneously but +# suggested uniquely) when an IOP driver emerges for "real" MMC/SD +# protocol support. + tristate + depends on !ETRAX_MMC_IOP + default MMC + select SPI + select MMC_SPI + +# While the board info is MMC_SPI only, the drivers are written to be +# independent of MMC_SPI, so we'll keep SPI non-dependent on the +# MMC_SPI config choices (well, except for a single depends-on-line +# for the board-info file until a separate non-MMC SPI board file +# emerges). +# FIXME: When that happens, we'll need to be able to ask for and +# configure non-MMC SPI ports together with MMC_SPI ports (if multiple +# SPI ports are enabled). + +config SPI_ETRAX_SSER + tristate + depends on SPI_MASTER && ETRAX_ARCH_V32 + select SPI_BITBANG + help + This enables using an synchronous serial (sser) port as a + SPI master controller on Axis ETRAX FS and later. The + driver can be configured to use any sser port. + +config SPI_ETRAX_GPIO + tristate + depends on SPI_MASTER && ETRAX_ARCH_V32 + select SPI_BITBANG + help + This enables using GPIO pins port as a SPI master controller + on Axis ETRAX FS and later. The driver can be configured to + use any GPIO pins. + +config ETRAX_SPI_SSER0 + tristate "SPI using synchronous serial port 0 (sser0)" + depends on ETRAX_SPI_MMC + default m if MMC_SPI=m + default y if MMC_SPI=y + default y if MMC_SPI=n + select SPI_ETRAX_SSER + help + Say Y for an MMC/SD socket connected to synchronous serial port 0, + or for devices using the SPI protocol on that port. Say m if you + want to build it as a module, which will be named spi_crisv32_sser. + (You need to select MMC separately.) + +config ETRAX_SPI_SSER1 + tristate "SPI using synchronous serial port 1 (sser1)" + depends on ETRAX_SPI_MMC + default m if MMC_SPI=m && ETRAX_SPI_SSER0=n + default y if MMC_SPI=y && ETRAX_SPI_SSER0=n + default y if MMC_SPI=n && ETRAX_SPI_SSER0=n + select SPI_ETRAX_SSER + help + Say Y for an MMC/SD socket connected to synchronous serial port 1, + or for devices using the SPI protocol on that port. Say m if you + want to build it as a module, which will be named spi_crisv32_sser. + (You need to select MMC separately.) + +config ETRAX_SPI_GPIO + tristate "Bitbanged SPI using gpio pins" + depends on ETRAX_SPI_MMC + select SPI_ETRAX_GPIO + default m if MMC_SPI=m && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n + default y if MMC_SPI=y && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n + default y if MMC_SPI=n && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n + help + Say Y for an MMC/SD socket connected to general I/O pins (but not + a complete synchronous serial ports), or for devices using the SPI + protocol on general I/O pins. Slow and slows down the system. + Say m to build it as a module, which will be called spi_crisv32_gpio. + (You need to select MMC separately.) + +endif diff --git a/kernel/arch/cris/arch-v32/drivers/Makefile b/kernel/arch/cris/arch-v32/drivers/Makefile new file mode 100644 index 000000000..15fbfefce --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/Makefile @@ -0,0 +1,12 @@ +# +# Makefile for Etrax-specific drivers +# + +obj-$(CONFIG_ETRAX_STREAMCOPROC) += cryptocop.o +obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o +obj-$(CONFIG_ETRAXFS) += mach-fs/ +obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/ +obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o +obj-$(CONFIG_ETRAX_I2C) += i2c.o +obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o +obj-$(CONFIG_PCI) += pci/ diff --git a/kernel/arch/cris/arch-v32/drivers/axisflashmap.c b/kernel/arch/cris/arch-v32/drivers/axisflashmap.c new file mode 100644 index 000000000..28dd77144 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/axisflashmap.c @@ -0,0 +1,619 @@ +/* + * Physical mapping layer for MTD using the Axis partitiontable format + * + * Copyright (c) 2001-2007 Axis Communications AB + * + * This file is under the GPL. + * + * First partition is always sector 0 regardless of if we find a partitiontable + * or not. In the start of the next sector, there can be a partitiontable that + * tells us what other partitions to define. If there isn't, we use a default + * partition split defined below. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) + +#define FLASH_UNCACHED_ADDR KSEG_E +#define FLASH_CACHED_ADDR KSEG_F + +#define PAGESIZE (512) + +#if CONFIG_ETRAX_FLASH_BUSWIDTH==1 +#define flash_data __u8 +#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2 +#define flash_data __u16 +#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4 +#define flash_data __u32 +#endif + +/* From head.S */ +extern unsigned long romfs_in_flash; /* 1 when romfs_start, _length in flash */ +extern unsigned long romfs_start, romfs_length; +extern unsigned long nand_boot; /* 1 when booted from nand flash */ + +struct partition_name { + char name[6]; +}; + +/* The master mtd for the entire flash. */ +struct mtd_info* axisflash_mtd = NULL; + +/* Map driver functions. */ + +static map_word flash_read(struct map_info *map, unsigned long ofs) +{ + map_word tmp; + tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs); + return tmp; +} + +static void flash_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + memcpy(to, (void *)(map->map_priv_1 + from), len); +} + +static void flash_write(struct map_info *map, map_word d, unsigned long adr) +{ + *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0]; +} + +/* + * The map for chip select e0. + * + * We run into tricky coherence situations if we mix cached with uncached + * accesses to we only use the uncached version here. + * + * The size field is the total size where the flash chips may be mapped on the + * chip select. MTD probes should find all devices there and it does not matter + * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD + * probes will ignore them. + * + * The start address in map_priv_1 is in virtual memory so we cannot use + * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start + * address of cse0. + */ +static struct map_info map_cse0 = { + .name = "cse0", + .size = MEM_CSE0_SIZE, + .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, + .read = flash_read, + .copy_from = flash_copy_from, + .write = flash_write, + .map_priv_1 = FLASH_UNCACHED_ADDR +}; + +/* + * The map for chip select e1. + * + * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong + * address, but there isn't. + */ +static struct map_info map_cse1 = { + .name = "cse1", + .size = MEM_CSE1_SIZE, + .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, + .read = flash_read, + .copy_from = flash_copy_from, + .write = flash_write, + .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE +}; + +#define MAX_PARTITIONS 7 +#ifdef CONFIG_ETRAX_NANDBOOT +#define NUM_DEFAULT_PARTITIONS 4 +#define DEFAULT_ROOTFS_PARTITION_NO 2 +#define DEFAULT_MEDIA_SIZE 0x2000000 /* 32 megs */ +#else +#define NUM_DEFAULT_PARTITIONS 3 +#define DEFAULT_ROOTFS_PARTITION_NO (-1) +#define DEFAULT_MEDIA_SIZE 0x800000 /* 8 megs */ +#endif + +#if (MAX_PARTITIONS < NUM_DEFAULT_PARTITIONS) +#error MAX_PARTITIONS must be >= than NUM_DEFAULT_PARTITIONS +#endif + +/* Initialize the ones normally used. */ +static struct mtd_partition axis_partitions[MAX_PARTITIONS] = { + { + .name = "part0", + .size = CONFIG_ETRAX_PTABLE_SECTOR, + .offset = 0 + }, + { + .name = "part1", + .size = 0, + .offset = 0 + }, + { + .name = "part2", + .size = 0, + .offset = 0 + }, + { + .name = "part3", + .size = 0, + .offset = 0 + }, + { + .name = "part4", + .size = 0, + .offset = 0 + }, + { + .name = "part5", + .size = 0, + .offset = 0 + }, + { + .name = "part6", + .size = 0, + .offset = 0 + }, +}; + + +/* If no partition-table was found, we use this default-set. + * Default flash size is 8MB (NOR). CONFIG_ETRAX_PTABLE_SECTOR is most + * likely the size of one flash block and "filesystem"-partition needs + * to be >=5 blocks to be able to use JFFS. + */ +static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { + { + .name = "boot firmware", + .size = CONFIG_ETRAX_PTABLE_SECTOR, + .offset = 0 + }, + { + .name = "kernel", + .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR, + .offset = CONFIG_ETRAX_PTABLE_SECTOR + }, +#define FILESYSTEM_SECTOR (11 * CONFIG_ETRAX_PTABLE_SECTOR) +#ifdef CONFIG_ETRAX_NANDBOOT + { + .name = "rootfs", + .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR, + .offset = FILESYSTEM_SECTOR + }, +#undef FILESYSTEM_SECTOR +#define FILESYSTEM_SECTOR (21 * CONFIG_ETRAX_PTABLE_SECTOR) +#endif + { + .name = "rwfs", + .size = DEFAULT_MEDIA_SIZE - FILESYSTEM_SECTOR, + .offset = FILESYSTEM_SECTOR + } +}; + +#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE +/* Main flash device */ +static struct mtd_partition main_partition = { + .name = "main", + .size = 0, + .offset = 0 +}; +#endif + +/* Auxiliary partition if we find another flash */ +static struct mtd_partition aux_partition = { + .name = "aux", + .size = 0, + .offset = 0 +}; + +/* + * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash + * chips in that order (because the amd_flash-driver is faster). + */ +static struct mtd_info *probe_cs(struct map_info *map_cs) +{ + struct mtd_info *mtd_cs = NULL; + + printk(KERN_INFO + "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n", + map_cs->name, map_cs->size, map_cs->map_priv_1); + +#ifdef CONFIG_MTD_CFI + mtd_cs = do_map_probe("cfi_probe", map_cs); +#endif +#ifdef CONFIG_MTD_JEDECPROBE + if (!mtd_cs) + mtd_cs = do_map_probe("jedec_probe", map_cs); +#endif + + return mtd_cs; +} + +/* + * Probe each chip select individually for flash chips. If there are chips on + * both cse0 and cse1, the mtd_info structs will be concatenated to one struct + * so that MTD partitions can cross chip boundries. + * + * The only known restriction to how you can mount your chips is that each + * chip select must hold similar flash chips. But you need external hardware + * to do that anyway and you can put totally different chips on cse0 and cse1 + * so it isn't really much of a restriction. + */ +extern struct mtd_info* __init crisv32_nand_flash_probe (void); +static struct mtd_info *flash_probe(void) +{ + struct mtd_info *mtd_cse0; + struct mtd_info *mtd_cse1; + struct mtd_info *mtd_total; + struct mtd_info *mtds[2]; + int count = 0; + + if ((mtd_cse0 = probe_cs(&map_cse0)) != NULL) + mtds[count++] = mtd_cse0; + if ((mtd_cse1 = probe_cs(&map_cse1)) != NULL) + mtds[count++] = mtd_cse1; + + if (!mtd_cse0 && !mtd_cse1) { + /* No chip found. */ + return NULL; + } + + if (count > 1) { + /* Since the concatenation layer adds a small overhead we + * could try to figure out if the chips in cse0 and cse1 are + * identical and reprobe the whole cse0+cse1 window. But since + * flash chips are slow, the overhead is relatively small. + * So we use the MTD concatenation layer instead of further + * complicating the probing procedure. + */ + mtd_total = mtd_concat_create(mtds, count, "cse0+cse1"); + if (!mtd_total) { + printk(KERN_ERR "%s and %s: Concatenation failed!\n", + map_cse0.name, map_cse1.name); + + /* The best we can do now is to only use what we found + * at cse0. */ + mtd_total = mtd_cse0; + map_destroy(mtd_cse1); + } + } else + mtd_total = mtd_cse0 ? mtd_cse0 : mtd_cse1; + + return mtd_total; +} + +/* + * Probe the flash chip(s) and, if it succeeds, read the partition-table + * and register the partitions with MTD. + */ +static int __init init_axis_flash(void) +{ + struct mtd_info *main_mtd; + struct mtd_info *aux_mtd = NULL; + int err = 0; + int pidx = 0; + struct partitiontable_head *ptable_head = NULL; + struct partitiontable_entry *ptable; + int ptable_ok = 0; + static char page[PAGESIZE]; + size_t len; + int ram_rootfs_partition = -1; /* -1 => no RAM rootfs partition */ + int part; + + /* We need a root fs. If it resides in RAM, we need to use an + * MTDRAM device, so it must be enabled in the kernel config, + * but its size must be configured as 0 so as not to conflict + * with our usage. + */ +#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0) + if (!romfs_in_flash && !nand_boot) { + printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " + "device; configure CONFIG_MTD_MTDRAM with size = 0!\n"); + panic("This kernel cannot boot from RAM!\n"); + } +#endif + + main_mtd = flash_probe(); + if (main_mtd) + printk(KERN_INFO "%s: 0x%08x bytes of NOR flash memory.\n", + main_mtd->name, main_mtd->size); + +#ifdef CONFIG_ETRAX_NANDFLASH + aux_mtd = crisv32_nand_flash_probe(); + if (aux_mtd) + printk(KERN_INFO "%s: 0x%08x bytes of NAND flash memory.\n", + aux_mtd->name, aux_mtd->size); + +#ifdef CONFIG_ETRAX_NANDBOOT + { + struct mtd_info *tmp_mtd; + + printk(KERN_INFO "axisflashmap: Set to boot from NAND flash, " + "making NAND flash primary device.\n"); + tmp_mtd = main_mtd; + main_mtd = aux_mtd; + aux_mtd = tmp_mtd; + } +#endif /* CONFIG_ETRAX_NANDBOOT */ +#endif /* CONFIG_ETRAX_NANDFLASH */ + + if (!main_mtd && !aux_mtd) { + /* There's no reason to use this module if no flash chip can + * be identified. Make sure that's understood. + */ + printk(KERN_INFO "axisflashmap: Found no flash chip.\n"); + } + +#if 0 /* Dump flash memory so we can see what is going on */ + if (main_mtd) { + int sectoraddr, i; + for (sectoraddr = 0; sectoraddr < 2*65536+4096; + sectoraddr += PAGESIZE) { + main_mtd->read(main_mtd, sectoraddr, PAGESIZE, &len, + page); + printk(KERN_INFO + "Sector at %d (length %d):\n", + sectoraddr, len); + for (i = 0; i < PAGESIZE; i += 16) { + printk(KERN_INFO + "%02x %02x %02x %02x " + "%02x %02x %02x %02x " + "%02x %02x %02x %02x " + "%02x %02x %02x %02x\n", + page[i] & 255, page[i+1] & 255, + page[i+2] & 255, page[i+3] & 255, + page[i+4] & 255, page[i+5] & 255, + page[i+6] & 255, page[i+7] & 255, + page[i+8] & 255, page[i+9] & 255, + page[i+10] & 255, page[i+11] & 255, + page[i+12] & 255, page[i+13] & 255, + page[i+14] & 255, page[i+15] & 255); + } + } + } +#endif + + if (main_mtd) { + main_mtd->owner = THIS_MODULE; + axisflash_mtd = main_mtd; + + loff_t ptable_sector = CONFIG_ETRAX_PTABLE_SECTOR; + + /* First partition (rescue) is always set to the default. */ + pidx++; +#ifdef CONFIG_ETRAX_NANDBOOT + /* We know where the partition table should be located, + * it will be in first good block after that. + */ + int blockstat; + do { + blockstat = mtd_block_isbad(main_mtd, ptable_sector); + if (blockstat < 0) + ptable_sector = 0; /* read error */ + else if (blockstat) + ptable_sector += main_mtd->erasesize; + } while (blockstat && ptable_sector); +#endif + if (ptable_sector) { + mtd_read(main_mtd, ptable_sector, PAGESIZE, &len, + page); + ptable_head = &((struct partitiontable *) page)->head; + } + +#if 0 /* Dump partition table so we can see what is going on */ + printk(KERN_INFO + "axisflashmap: flash read %d bytes at 0x%08x, data: " + "%02x %02x %02x %02x %02x %02x %02x %02x\n", + len, CONFIG_ETRAX_PTABLE_SECTOR, + page[0] & 255, page[1] & 255, + page[2] & 255, page[3] & 255, + page[4] & 255, page[5] & 255, + page[6] & 255, page[7] & 255); + printk(KERN_INFO + "axisflashmap: partition table offset %d, data: " + "%02x %02x %02x %02x %02x %02x %02x %02x\n", + PARTITION_TABLE_OFFSET, + page[PARTITION_TABLE_OFFSET+0] & 255, + page[PARTITION_TABLE_OFFSET+1] & 255, + page[PARTITION_TABLE_OFFSET+2] & 255, + page[PARTITION_TABLE_OFFSET+3] & 255, + page[PARTITION_TABLE_OFFSET+4] & 255, + page[PARTITION_TABLE_OFFSET+5] & 255, + page[PARTITION_TABLE_OFFSET+6] & 255, + page[PARTITION_TABLE_OFFSET+7] & 255); +#endif + } + + if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC) + && (ptable_head->size < + (MAX_PARTITIONS * sizeof(struct partitiontable_entry) + + PARTITIONTABLE_END_MARKER_SIZE)) + && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) + + ptable_head->size - + PARTITIONTABLE_END_MARKER_SIZE) + == PARTITIONTABLE_END_MARKER)) { + /* Looks like a start, sane length and end of a + * partition table, lets check csum etc. + */ + struct partitiontable_entry *max_addr = + (struct partitiontable_entry *) + ((unsigned long)ptable_head + sizeof(*ptable_head) + + ptable_head->size); + unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR; + unsigned char *p; + unsigned long csum = 0; + + ptable = (struct partitiontable_entry *) + ((unsigned long)ptable_head + sizeof(*ptable_head)); + + /* Lets be PARANOID, and check the checksum. */ + p = (unsigned char*) ptable; + + while (p <= (unsigned char*)max_addr) { + csum += *p++; + csum += *p++; + csum += *p++; + csum += *p++; + } + ptable_ok = (csum == ptable_head->checksum); + + /* Read the entries and use/show the info. */ + printk(KERN_INFO "axisflashmap: " + "Found a%s partition table at 0x%p-0x%p.\n", + (ptable_ok ? " valid" : "n invalid"), ptable_head, + max_addr); + + /* We have found a working bootblock. Now read the + * partition table. Scan the table. It ends with 0xffffffff. + */ + while (ptable_ok + && ptable->offset != PARTITIONTABLE_END_MARKER + && ptable < max_addr + && pidx < MAX_PARTITIONS - 1) { + + axis_partitions[pidx].offset = offset + ptable->offset; +#ifdef CONFIG_ETRAX_NANDFLASH + if (main_mtd->type == MTD_NANDFLASH) { + axis_partitions[pidx].size = + (((ptable+1)->offset == + PARTITIONTABLE_END_MARKER) ? + main_mtd->size : + ((ptable+1)->offset + offset)) - + (ptable->offset + offset); + + } else +#endif /* CONFIG_ETRAX_NANDFLASH */ + axis_partitions[pidx].size = ptable->size; +#ifdef CONFIG_ETRAX_NANDBOOT + /* Save partition number of jffs2 ro partition. + * Needed if RAM booting or root file system in RAM. + */ + if (!nand_boot && + ram_rootfs_partition < 0 && /* not already set */ + ptable->type == PARTITION_TYPE_JFFS2 && + (ptable->flags & PARTITION_FLAGS_READONLY_MASK) == + PARTITION_FLAGS_READONLY) + ram_rootfs_partition = pidx; +#endif /* CONFIG_ETRAX_NANDBOOT */ + pidx++; + ptable++; + } + } + + /* Decide whether to use default partition table. */ + /* Only use default table if we actually have a device (main_mtd) */ + + struct mtd_partition *partition = &axis_partitions[0]; + if (main_mtd && !ptable_ok) { + memcpy(axis_partitions, axis_default_partitions, + sizeof(axis_default_partitions)); + pidx = NUM_DEFAULT_PARTITIONS; + ram_rootfs_partition = DEFAULT_ROOTFS_PARTITION_NO; + } + + /* Add artificial partitions for rootfs if necessary */ + if (romfs_in_flash) { + /* rootfs is in directly accessible flash memory = NOR flash. + Add an overlapping device for the rootfs partition. */ + printk(KERN_INFO "axisflashmap: Adding partition for " + "overlapping root file system image\n"); + axis_partitions[pidx].size = romfs_length; + axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; + axis_partitions[pidx].name = "romfs"; + axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; + ram_rootfs_partition = -1; + pidx++; + } else if (romfs_length && !nand_boot) { + /* romfs exists in memory, but not in flash, so must be in RAM. + * Configure an MTDRAM partition. */ + if (ram_rootfs_partition < 0) { + /* None set yet, put it at the end */ + ram_rootfs_partition = pidx; + pidx++; + } + printk(KERN_INFO "axisflashmap: Adding partition for " + "root file system image in RAM\n"); + axis_partitions[ram_rootfs_partition].size = romfs_length; + axis_partitions[ram_rootfs_partition].offset = romfs_start; + axis_partitions[ram_rootfs_partition].name = "romfs"; + axis_partitions[ram_rootfs_partition].mask_flags |= + MTD_WRITEABLE; + } + +#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE + if (main_mtd) { + main_partition.size = main_mtd->size; + err = mtd_device_register(main_mtd, &main_partition, 1); + if (err) + panic("axisflashmap: Could not initialize " + "partition for whole main mtd device!\n"); + } +#endif + + /* Now, register all partitions with mtd. + * We do this one at a time so we can slip in an MTDRAM device + * in the proper place if required. */ + + for (part = 0; part < pidx; part++) { + if (part == ram_rootfs_partition) { + /* add MTDRAM partition here */ + struct mtd_info *mtd_ram; + + mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL); + if (!mtd_ram) + panic("axisflashmap: Couldn't allocate memory " + "for mtd_info!\n"); + printk(KERN_INFO "axisflashmap: Adding RAM partition " + "for rootfs image.\n"); + err = mtdram_init_device(mtd_ram, + (void *)partition[part].offset, + partition[part].size, + partition[part].name); + if (err) + panic("axisflashmap: Could not initialize " + "MTD RAM device!\n"); + /* JFFS2 likes to have an erasesize. Keep potential + * JFFS2 rootfs happy by providing one. Since image + * was most likely created for main mtd, use that + * erasesize, if available. Otherwise, make a guess. */ + mtd_ram->erasesize = (main_mtd ? main_mtd->erasesize : + CONFIG_ETRAX_PTABLE_SECTOR); + } else { + err = mtd_device_register(main_mtd, &partition[part], + 1); + if (err) + panic("axisflashmap: Could not add mtd " + "partition %d\n", part); + } + } + + if (aux_mtd) { + aux_partition.size = aux_mtd->size; + err = mtd_device_register(aux_mtd, &aux_partition, 1); + if (err) + panic("axisflashmap: Could not initialize " + "aux mtd device!\n"); + + } + + return err; +} + +/* This adds the above to the kernels init-call chain. */ +module_init(init_axis_flash); + +EXPORT_SYMBOL(axisflash_mtd); diff --git a/kernel/arch/cris/arch-v32/drivers/cryptocop.c b/kernel/arch/cris/arch-v32/drivers/cryptocop.c new file mode 100644 index 000000000..877da1908 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/cryptocop.c @@ -0,0 +1,3536 @@ +/* + * Stream co-processor driver for the ETRAX FS + * + * Copyright (C) 2003-2007 Axis Communications AB + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_ETRAXFS +#define IN_DMA 9 +#define OUT_DMA 8 +#define IN_DMA_INST regi_dma9 +#define OUT_DMA_INST regi_dma8 +#define DMA_IRQ DMA9_INTR_VECT +#else +#define IN_DMA 3 +#define OUT_DMA 2 +#define IN_DMA_INST regi_dma3 +#define OUT_DMA_INST regi_dma2 +#define DMA_IRQ DMA3_INTR_VECT +#endif + +#define DESCR_ALLOC_PAD (31) + +struct cryptocop_dma_desc { + char *free_buf; /* If non-null will be kfreed in free_cdesc() */ + dma_descr_data *dma_descr; + + unsigned char dma_descr_buf[sizeof(dma_descr_data) + DESCR_ALLOC_PAD]; + + unsigned int from_pool:1; /* If 1 'allocated' from the descriptor pool. */ + struct cryptocop_dma_desc *next; +}; + + +struct cryptocop_int_operation{ + void *alloc_ptr; + cryptocop_session_id sid; + + dma_descr_context ctx_out; + dma_descr_context ctx_in; + + /* DMA descriptors allocated by driver. */ + struct cryptocop_dma_desc *cdesc_out; + struct cryptocop_dma_desc *cdesc_in; + + /* Strcop config to use. */ + cryptocop_3des_mode tdes_mode; + cryptocop_csum_type csum_mode; + + /* DMA descrs provided by consumer. */ + dma_descr_data *ddesc_out; + dma_descr_data *ddesc_in; +}; + + +struct cryptocop_tfrm_ctx { + cryptocop_tfrm_id tid; + unsigned int blocklength; + + unsigned int start_ix; + + struct cryptocop_tfrm_cfg *tcfg; + struct cryptocop_transform_ctx *tctx; + + unsigned char previous_src; + unsigned char current_src; + + /* Values to use in metadata out. */ + unsigned char hash_conf; + unsigned char hash_mode; + unsigned char ciph_conf; + unsigned char cbcmode; + unsigned char decrypt; + + unsigned int requires_padding:1; + unsigned int strict_block_length:1; + unsigned int active:1; + unsigned int done:1; + size_t consumed; + size_t produced; + + /* Pad (input) descriptors to put in the DMA out list when the transform + * output is put on the DMA in list. */ + struct cryptocop_dma_desc *pad_descs; + + struct cryptocop_tfrm_ctx *prev_src; + struct cryptocop_tfrm_ctx *curr_src; + + /* Mapping to HW. */ + unsigned char unit_no; +}; + + +struct cryptocop_private{ + cryptocop_session_id sid; + struct cryptocop_private *next; +}; + +/* Session list. */ + +struct cryptocop_transform_ctx{ + struct cryptocop_transform_init init; + unsigned char dec_key[CRYPTOCOP_MAX_KEY_LENGTH]; + unsigned int dec_key_set:1; + + struct cryptocop_transform_ctx *next; +}; + + +struct cryptocop_session{ + cryptocop_session_id sid; + + struct cryptocop_transform_ctx *tfrm_ctx; + + struct cryptocop_session *next; +}; + +/* Priority levels for jobs sent to the cryptocop. Checksum operations from + kernel have highest priority since TCPIP stack processing must not + be a bottleneck. */ +typedef enum { + cryptocop_prio_kernel_csum = 0, + cryptocop_prio_kernel = 1, + cryptocop_prio_user = 2, + cryptocop_prio_no_prios = 3 +} cryptocop_queue_priority; + +struct cryptocop_prio_queue{ + struct list_head jobs; + cryptocop_queue_priority prio; +}; + +struct cryptocop_prio_job{ + struct list_head node; + cryptocop_queue_priority prio; + + struct cryptocop_operation *oper; + struct cryptocop_int_operation *iop; +}; + +struct ioctl_job_cb_ctx { + unsigned int processed:1; +}; + + +static struct cryptocop_session *cryptocop_sessions = NULL; +spinlock_t cryptocop_sessions_lock; + +/* Next Session ID to assign. */ +static cryptocop_session_id next_sid = 1; + +/* Pad for checksum. */ +static const char csum_zero_pad[1] = {0x00}; + +/* Trash buffer for mem2mem operations. */ +#define MEM2MEM_DISCARD_BUF_LENGTH (512) +static unsigned char mem2mem_discard_buf[MEM2MEM_DISCARD_BUF_LENGTH]; + +/* Descriptor pool. */ +/* FIXME Tweak this value. */ +#define CRYPTOCOP_DESCRIPTOR_POOL_SIZE (100) +static struct cryptocop_dma_desc descr_pool[CRYPTOCOP_DESCRIPTOR_POOL_SIZE]; +static struct cryptocop_dma_desc *descr_pool_free_list; +static int descr_pool_no_free; +static spinlock_t descr_pool_lock; + +/* Lock to stop cryptocop to start processing of a new operation. The holder + of this lock MUST call cryptocop_start_job() after it is unlocked. */ +spinlock_t cryptocop_process_lock; + +static struct cryptocop_prio_queue cryptocop_job_queues[cryptocop_prio_no_prios]; +static spinlock_t cryptocop_job_queue_lock; +static struct cryptocop_prio_job *cryptocop_running_job = NULL; +static spinlock_t running_job_lock; + +/* The interrupt handler appends completed jobs to this list. The scehduled + * tasklet removes them upon sending the response to the crypto consumer. */ +static struct list_head cryptocop_completed_jobs; +static spinlock_t cryptocop_completed_jobs_lock; + +DECLARE_WAIT_QUEUE_HEAD(cryptocop_ioc_process_wq); + + +/** Local functions. **/ + +static int cryptocop_open(struct inode *, struct file *); + +static int cryptocop_release(struct inode *, struct file *); + +static long cryptocop_ioctl(struct file *file, + unsigned int cmd, unsigned long arg); + +static void cryptocop_start_job(void); + +static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation); +static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation); + +static int cryptocop_job_queue_init(void); +static void cryptocop_job_queue_close(void); + +static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length); + +static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length); + +static int transform_ok(struct cryptocop_transform_init *tinit); + +static struct cryptocop_session *get_session(cryptocop_session_id sid); + +static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid); + +static void delete_internal_operation(struct cryptocop_int_operation *iop); + +static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength); + +static int init_stream_coprocessor(void); + +static void __exit exit_stream_coprocessor(void); + +/*#define LDEBUG*/ +#ifdef LDEBUG +#define DEBUG(s) s +#define DEBUG_API(s) s +static void print_cryptocop_operation(struct cryptocop_operation *cop); +static void print_dma_descriptors(struct cryptocop_int_operation *iop); +static void print_strcop_crypto_op(struct strcop_crypto_op *cop); +static void print_lock_status(void); +static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op); +#define assert(s) do{if (!(s)) panic(#s);} while(0); +#else +#define DEBUG(s) +#define DEBUG_API(s) +#define assert(s) +#endif + + +/* Transform constants. */ +#define DES_BLOCK_LENGTH (8) +#define AES_BLOCK_LENGTH (16) +#define MD5_BLOCK_LENGTH (64) +#define SHA1_BLOCK_LENGTH (64) +#define CSUM_BLOCK_LENGTH (2) +#define MD5_STATE_LENGTH (16) +#define SHA1_STATE_LENGTH (20) + +/* The device number. */ +#define CRYPTOCOP_MAJOR (254) +#define CRYPTOCOP_MINOR (0) + + + +const struct file_operations cryptocop_fops = { + .owner = THIS_MODULE, + .open = cryptocop_open, + .release = cryptocop_release, + .unlocked_ioctl = cryptocop_ioctl, + .llseek = noop_llseek, +}; + + +static void free_cdesc(struct cryptocop_dma_desc *cdesc) +{ + DEBUG(printk("free_cdesc: cdesc 0x%p, from_pool=%d\n", cdesc, cdesc->from_pool)); + kfree(cdesc->free_buf); + + if (cdesc->from_pool) { + unsigned long int flags; + spin_lock_irqsave(&descr_pool_lock, flags); + cdesc->next = descr_pool_free_list; + descr_pool_free_list = cdesc; + ++descr_pool_no_free; + spin_unlock_irqrestore(&descr_pool_lock, flags); + } else { + kfree(cdesc); + } +} + + +static struct cryptocop_dma_desc *alloc_cdesc(int alloc_flag) +{ + int use_pool = (alloc_flag & GFP_ATOMIC) ? 1 : 0; + struct cryptocop_dma_desc *cdesc; + + if (use_pool) { + unsigned long int flags; + spin_lock_irqsave(&descr_pool_lock, flags); + if (!descr_pool_free_list) { + spin_unlock_irqrestore(&descr_pool_lock, flags); + DEBUG_API(printk("alloc_cdesc: pool is empty\n")); + return NULL; + } + cdesc = descr_pool_free_list; + descr_pool_free_list = descr_pool_free_list->next; + --descr_pool_no_free; + spin_unlock_irqrestore(&descr_pool_lock, flags); + cdesc->from_pool = 1; + } else { + cdesc = kmalloc(sizeof(struct cryptocop_dma_desc), alloc_flag); + if (!cdesc) { + DEBUG_API(printk("alloc_cdesc: kmalloc\n")); + return NULL; + } + cdesc->from_pool = 0; + } + cdesc->dma_descr = (dma_descr_data*)(((unsigned long int)cdesc + offsetof(struct cryptocop_dma_desc, dma_descr_buf) + DESCR_ALLOC_PAD) & ~0x0000001F); + + cdesc->next = NULL; + + cdesc->free_buf = NULL; + cdesc->dma_descr->out_eop = 0; + cdesc->dma_descr->in_eop = 0; + cdesc->dma_descr->intr = 0; + cdesc->dma_descr->eol = 0; + cdesc->dma_descr->wait = 0; + cdesc->dma_descr->buf = NULL; + cdesc->dma_descr->after = NULL; + + DEBUG_API(printk("alloc_cdesc: return 0x%p, cdesc->dma_descr=0x%p, from_pool=%d\n", cdesc, cdesc->dma_descr, cdesc->from_pool)); + return cdesc; +} + + +static void setup_descr_chain(struct cryptocop_dma_desc *cd) +{ + DEBUG(printk("setup_descr_chain: entering\n")); + while (cd) { + if (cd->next) { + cd->dma_descr->next = (dma_descr_data*)virt_to_phys(cd->next->dma_descr); + } else { + cd->dma_descr->next = NULL; + } + cd = cd->next; + } + DEBUG(printk("setup_descr_chain: exit\n")); +} + + +/* Create a pad descriptor for the transform. + * Return -1 for error, 0 if pad created. */ +static int create_pad_descriptor(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **pad_desc, int alloc_flag) +{ + struct cryptocop_dma_desc *cdesc = NULL; + int error = 0; + struct strcop_meta_out mo = { + .ciphsel = src_none, + .hashsel = src_none, + .csumsel = src_none + }; + char *pad; + size_t plen; + + DEBUG(printk("create_pad_descriptor: start.\n")); + /* Setup pad descriptor. */ + + DEBUG(printk("create_pad_descriptor: setting up padding.\n")); + cdesc = alloc_cdesc(alloc_flag); + if (!cdesc){ + DEBUG_API(printk("create_pad_descriptor: alloc pad desc\n")); + goto error_cleanup; + } + switch (tc->unit_no) { + case src_md5: + error = create_md5_pad(alloc_flag, tc->consumed, &pad, &plen); + if (error){ + DEBUG_API(printk("create_pad_descriptor: create_md5_pad_failed\n")); + goto error_cleanup; + } + cdesc->free_buf = pad; + mo.hashsel = src_dma; + mo.hashconf = tc->hash_conf; + mo.hashmode = tc->hash_mode; + break; + case src_sha1: + error = create_sha1_pad(alloc_flag, tc->consumed, &pad, &plen); + if (error){ + DEBUG_API(printk("create_pad_descriptor: create_sha1_pad_failed\n")); + goto error_cleanup; + } + cdesc->free_buf = pad; + mo.hashsel = src_dma; + mo.hashconf = tc->hash_conf; + mo.hashmode = tc->hash_mode; + break; + case src_csum: + if (tc->consumed % tc->blocklength){ + pad = (char*)csum_zero_pad; + plen = 1; + } else { + pad = (char*)cdesc; /* Use any pointer. */ + plen = 0; + } + mo.csumsel = src_dma; + break; + } + cdesc->dma_descr->wait = 1; + cdesc->dma_descr->out_eop = 1; /* Since this is a pad output is pushed. EOP is ok here since the padded unit is the only one active. */ + cdesc->dma_descr->buf = (char*)virt_to_phys((char*)pad); + cdesc->dma_descr->after = cdesc->dma_descr->buf + plen; + + cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); + *pad_desc = cdesc; + + return 0; + + error_cleanup: + if (cdesc) free_cdesc(cdesc); + return -1; +} + + +static int setup_key_dl_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **kd, int alloc_flag) +{ + struct cryptocop_dma_desc *key_desc = alloc_cdesc(alloc_flag); + struct strcop_meta_out mo = {0}; + + DEBUG(printk("setup_key_dl_desc\n")); + + if (!key_desc) { + DEBUG_API(printk("setup_key_dl_desc: failed descriptor allocation.\n")); + return -ENOMEM; + } + + /* Download key. */ + if ((tc->tctx->init.alg == cryptocop_alg_aes) && (tc->tcfg->flags & CRYPTOCOP_DECRYPT)) { + /* Precook the AES decrypt key. */ + if (!tc->tctx->dec_key_set){ + get_aes_decrypt_key(tc->tctx->dec_key, tc->tctx->init.key, tc->tctx->init.keylen); + tc->tctx->dec_key_set = 1; + } + key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->dec_key); + key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8; + } else { + key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->init.key); + key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8; + } + /* Setup metadata. */ + mo.dlkey = 1; + switch (tc->tctx->init.keylen) { + case 64: + mo.decrypt = 0; + mo.hashmode = 0; + break; + case 128: + mo.decrypt = 0; + mo.hashmode = 1; + break; + case 192: + mo.decrypt = 1; + mo.hashmode = 0; + break; + case 256: + mo.decrypt = 1; + mo.hashmode = 1; + break; + default: + break; + } + mo.ciphsel = mo.hashsel = mo.csumsel = src_none; + key_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); + + key_desc->dma_descr->out_eop = 1; + key_desc->dma_descr->wait = 1; + key_desc->dma_descr->intr = 0; + + *kd = key_desc; + return 0; +} + +static int setup_cipher_iv_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag) +{ + struct cryptocop_dma_desc *iv_desc = alloc_cdesc(alloc_flag); + struct strcop_meta_out mo = {0}; + + DEBUG(printk("setup_cipher_iv_desc\n")); + + if (!iv_desc) { + DEBUG_API(printk("setup_cipher_iv_desc: failed CBC IV descriptor allocation.\n")); + return -ENOMEM; + } + /* Download IV. */ + iv_desc->dma_descr->buf = (char*)virt_to_phys(tc->tcfg->iv); + iv_desc->dma_descr->after = iv_desc->dma_descr->buf + tc->blocklength; + + /* Setup metadata. */ + mo.hashsel = mo.csumsel = src_none; + mo.ciphsel = src_dma; + mo.ciphconf = tc->ciph_conf; + mo.cbcmode = tc->cbcmode; + + iv_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); + + iv_desc->dma_descr->out_eop = 0; + iv_desc->dma_descr->wait = 1; + iv_desc->dma_descr->intr = 0; + + *id = iv_desc; + return 0; +} + +/* Map the ouput length of the transform to operation output starting on the inject index. */ +static int create_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag) +{ + int err = 0; + struct cryptocop_dma_desc head = {0}; + struct cryptocop_dma_desc *outdesc = &head; + size_t iov_offset = 0; + size_t out_ix = 0; + int outiov_ix = 0; + struct strcop_meta_in mi = {0}; + + size_t out_length = tc->produced; + int rem_length; + int dlength; + + assert(out_length != 0); + if (((tc->produced + tc->tcfg->inject_ix) > operation->tfrm_op.outlen) || (tc->produced && (operation->tfrm_op.outlen == 0))) { + DEBUG_API(printk("create_input_descriptors: operation outdata too small\n")); + return -EINVAL; + } + /* Traverse the out iovec until the result inject index is reached. */ + while ((outiov_ix < operation->tfrm_op.outcount) && ((out_ix + operation->tfrm_op.outdata[outiov_ix].iov_len) <= tc->tcfg->inject_ix)){ + out_ix += operation->tfrm_op.outdata[outiov_ix].iov_len; + outiov_ix++; + } + if (outiov_ix >= operation->tfrm_op.outcount){ + DEBUG_API(printk("create_input_descriptors: operation outdata too small\n")); + return -EINVAL; + } + iov_offset = tc->tcfg->inject_ix - out_ix; + mi.dmasel = tc->unit_no; + + /* Setup the output descriptors. */ + while ((out_length > 0) && (outiov_ix < operation->tfrm_op.outcount)) { + outdesc->next = alloc_cdesc(alloc_flag); + if (!outdesc->next) { + DEBUG_API(printk("create_input_descriptors: alloc_cdesc\n")); + err = -ENOMEM; + goto error_cleanup; + } + outdesc = outdesc->next; + rem_length = operation->tfrm_op.outdata[outiov_ix].iov_len - iov_offset; + dlength = (out_length < rem_length) ? out_length : rem_length; + + DEBUG(printk("create_input_descriptors:\n" + "outiov_ix=%d, rem_length=%d, dlength=%d\n" + "iov_offset=%d, outdata[outiov_ix].iov_len=%d\n" + "outcount=%d, outiov_ix=%d\n", + outiov_ix, rem_length, dlength, iov_offset, operation->tfrm_op.outdata[outiov_ix].iov_len, operation->tfrm_op.outcount, outiov_ix)); + + outdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.outdata[outiov_ix].iov_base + iov_offset); + outdesc->dma_descr->after = outdesc->dma_descr->buf + dlength; + outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); + + out_length -= dlength; + iov_offset += dlength; + if (iov_offset >= operation->tfrm_op.outdata[outiov_ix].iov_len) { + iov_offset = 0; + ++outiov_ix; + } + } + if (out_length > 0){ + DEBUG_API(printk("create_input_descriptors: not enough room for output, %d remained\n", out_length)); + err = -EINVAL; + goto error_cleanup; + } + /* Set sync in last descriptor. */ + mi.sync = 1; + outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); + + *id = head.next; + return 0; + + error_cleanup: + while (head.next) { + outdesc = head.next->next; + free_cdesc(head.next); + head.next = outdesc; + } + return err; +} + + +static int create_output_descriptors(struct cryptocop_operation *operation, int *iniov_ix, int *iniov_offset, size_t desc_len, struct cryptocop_dma_desc **current_out_cdesc, struct strcop_meta_out *meta_out, int alloc_flag) +{ + while (desc_len != 0) { + struct cryptocop_dma_desc *cdesc; + int rem_length = operation->tfrm_op.indata[*iniov_ix].iov_len - *iniov_offset; + int dlength = (desc_len < rem_length) ? desc_len : rem_length; + + cdesc = alloc_cdesc(alloc_flag); + if (!cdesc) { + DEBUG_API(printk("create_output_descriptors: alloc_cdesc\n")); + return -ENOMEM; + } + (*current_out_cdesc)->next = cdesc; + (*current_out_cdesc) = cdesc; + + cdesc->free_buf = NULL; + + cdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.indata[*iniov_ix].iov_base + *iniov_offset); + cdesc->dma_descr->after = cdesc->dma_descr->buf + dlength; + + assert(desc_len >= dlength); + desc_len -= dlength; + *iniov_offset += dlength; + if (*iniov_offset >= operation->tfrm_op.indata[*iniov_ix].iov_len) { + *iniov_offset = 0; + ++(*iniov_ix); + if (*iniov_ix > operation->tfrm_op.incount) { + DEBUG_API(printk("create_output_descriptors: not enough indata in operation.")); + return -EINVAL; + } + } + cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, (*meta_out)); + } /* while (desc_len != 0) */ + /* Last DMA descriptor gets a 'wait' bit to signal expected change in metadata. */ + (*current_out_cdesc)->dma_descr->wait = 1; /* This will set extraneous WAIT in some situations, e.g. when padding hashes and checksums. */ + + return 0; +} + + +static int append_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_dma_desc **current_in_cdesc, struct cryptocop_dma_desc **current_out_cdesc, struct cryptocop_tfrm_ctx *tc, int alloc_flag) +{ + DEBUG(printk("append_input_descriptors, tc=0x%p, unit_no=%d\n", tc, tc->unit_no)); + if (tc->tcfg) { + int failed = 0; + struct cryptocop_dma_desc *idescs = NULL; + DEBUG(printk("append_input_descriptors: pushing output, consumed %d produced %d bytes.\n", tc->consumed, tc->produced)); + if (tc->pad_descs) { + DEBUG(printk("append_input_descriptors: append pad descriptors to DMA out list.\n")); + while (tc->pad_descs) { + DEBUG(printk("append descriptor 0x%p\n", tc->pad_descs)); + (*current_out_cdesc)->next = tc->pad_descs; + tc->pad_descs = tc->pad_descs->next; + (*current_out_cdesc) = (*current_out_cdesc)->next; + } + } + + /* Setup and append output descriptors to DMA in list. */ + if (tc->unit_no == src_dma){ + /* mem2mem. Setup DMA in descriptors to discard all input prior to the requested mem2mem data. */ + struct strcop_meta_in mi = {.sync = 0, .dmasel = src_dma}; + unsigned int start_ix = tc->start_ix; + while (start_ix){ + unsigned int desclen = start_ix < MEM2MEM_DISCARD_BUF_LENGTH ? start_ix : MEM2MEM_DISCARD_BUF_LENGTH; + (*current_in_cdesc)->next = alloc_cdesc(alloc_flag); + if (!(*current_in_cdesc)->next){ + DEBUG_API(printk("append_input_descriptors: alloc_cdesc mem2mem discard failed\n")); + return -ENOMEM; + } + (*current_in_cdesc) = (*current_in_cdesc)->next; + (*current_in_cdesc)->dma_descr->buf = (char*)virt_to_phys(mem2mem_discard_buf); + (*current_in_cdesc)->dma_descr->after = (*current_in_cdesc)->dma_descr->buf + desclen; + (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); + start_ix -= desclen; + } + mi.sync = 1; + (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); + } + + failed = create_input_descriptors(operation, tc, &idescs, alloc_flag); + if (failed){ + DEBUG_API(printk("append_input_descriptors: output descriptor setup failed\n")); + return failed; + } + DEBUG(printk("append_input_descriptors: append output descriptors to DMA in list.\n")); + while (idescs) { + DEBUG(printk("append descriptor 0x%p\n", idescs)); + (*current_in_cdesc)->next = idescs; + idescs = idescs->next; + (*current_in_cdesc) = (*current_in_cdesc)->next; + } + } + return 0; +} + + + +static int cryptocop_setup_dma_list(struct cryptocop_operation *operation, struct cryptocop_int_operation **int_op, int alloc_flag) +{ + struct cryptocop_session *sess; + struct cryptocop_transform_ctx *tctx; + + struct cryptocop_tfrm_ctx digest_ctx = { + .previous_src = src_none, + .current_src = src_none, + .start_ix = 0, + .requires_padding = 1, + .strict_block_length = 0, + .hash_conf = 0, + .hash_mode = 0, + .ciph_conf = 0, + .cbcmode = 0, + .decrypt = 0, + .consumed = 0, + .produced = 0, + .pad_descs = NULL, + .active = 0, + .done = 0, + .prev_src = NULL, + .curr_src = NULL, + .tcfg = NULL}; + struct cryptocop_tfrm_ctx cipher_ctx = { + .previous_src = src_none, + .current_src = src_none, + .start_ix = 0, + .requires_padding = 0, + .strict_block_length = 1, + .hash_conf = 0, + .hash_mode = 0, + .ciph_conf = 0, + .cbcmode = 0, + .decrypt = 0, + .consumed = 0, + .produced = 0, + .pad_descs = NULL, + .active = 0, + .done = 0, + .prev_src = NULL, + .curr_src = NULL, + .tcfg = NULL}; + struct cryptocop_tfrm_ctx csum_ctx = { + .previous_src = src_none, + .current_src = src_none, + .start_ix = 0, + .blocklength = 2, + .requires_padding = 1, + .strict_block_length = 0, + .hash_conf = 0, + .hash_mode = 0, + .ciph_conf = 0, + .cbcmode = 0, + .decrypt = 0, + .consumed = 0, + .produced = 0, + .pad_descs = NULL, + .active = 0, + .done = 0, + .tcfg = NULL, + .prev_src = NULL, + .curr_src = NULL, + .unit_no = src_csum}; + struct cryptocop_tfrm_cfg *tcfg = operation->tfrm_op.tfrm_cfg; + + unsigned int indata_ix = 0; + + /* iovec accounting. */ + int iniov_ix = 0; + int iniov_offset = 0; + + /* Operation descriptor cfg traversal pointer. */ + struct cryptocop_desc *odsc; + + int failed = 0; + /* List heads for allocated descriptors. */ + struct cryptocop_dma_desc out_cdesc_head = {0}; + struct cryptocop_dma_desc in_cdesc_head = {0}; + + struct cryptocop_dma_desc *current_out_cdesc = &out_cdesc_head; + struct cryptocop_dma_desc *current_in_cdesc = &in_cdesc_head; + + struct cryptocop_tfrm_ctx *output_tc = NULL; + void *iop_alloc_ptr; + + assert(operation != NULL); + assert(int_op != NULL); + + DEBUG(printk("cryptocop_setup_dma_list: start\n")); + DEBUG(print_cryptocop_operation(operation)); + + sess = get_session(operation->sid); + if (!sess) { + DEBUG_API(printk("cryptocop_setup_dma_list: no session found for operation.\n")); + failed = -EINVAL; + goto error_cleanup; + } + iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag); + if (!iop_alloc_ptr) { + DEBUG_API(printk("cryptocop_setup_dma_list: kmalloc cryptocop_int_operation\n")); + failed = -ENOMEM; + goto error_cleanup; + } + (*int_op) = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out)); + DEBUG(memset((*int_op), 0xff, sizeof(struct cryptocop_int_operation))); + (*int_op)->alloc_ptr = iop_alloc_ptr; + DEBUG(printk("cryptocop_setup_dma_list: *int_op=0x%p, alloc_ptr=0x%p\n", *int_op, (*int_op)->alloc_ptr)); + + (*int_op)->sid = operation->sid; + (*int_op)->cdesc_out = NULL; + (*int_op)->cdesc_in = NULL; + (*int_op)->tdes_mode = cryptocop_3des_ede; + (*int_op)->csum_mode = cryptocop_csum_le; + (*int_op)->ddesc_out = NULL; + (*int_op)->ddesc_in = NULL; + + /* Scan operation->tfrm_op.tfrm_cfg for bad configuration and set up the local contexts. */ + if (!tcfg) { + DEBUG_API(printk("cryptocop_setup_dma_list: no configured transforms in operation.\n")); + failed = -EINVAL; + goto error_cleanup; + } + while (tcfg) { + tctx = get_transform_ctx(sess, tcfg->tid); + if (!tctx) { + DEBUG_API(printk("cryptocop_setup_dma_list: no transform id %d in session.\n", tcfg->tid)); + failed = -EINVAL; + goto error_cleanup; + } + if (tcfg->inject_ix > operation->tfrm_op.outlen){ + DEBUG_API(printk("cryptocop_setup_dma_list: transform id %d inject_ix (%d) > operation->tfrm_op.outlen(%d)", tcfg->tid, tcfg->inject_ix, operation->tfrm_op.outlen)); + failed = -EINVAL; + goto error_cleanup; + } + switch (tctx->init.alg){ + case cryptocop_alg_mem2mem: + if (cipher_ctx.tcfg != NULL){ + DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n")); + failed = -EINVAL; + goto error_cleanup; + } + /* mem2mem is handled as a NULL cipher. */ + cipher_ctx.cbcmode = 0; + cipher_ctx.decrypt = 0; + cipher_ctx.blocklength = 1; + cipher_ctx.ciph_conf = 0; + cipher_ctx.unit_no = src_dma; + cipher_ctx.tcfg = tcfg; + cipher_ctx.tctx = tctx; + break; + case cryptocop_alg_des: + case cryptocop_alg_3des: + case cryptocop_alg_aes: + /* cipher */ + if (cipher_ctx.tcfg != NULL){ + DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n")); + failed = -EINVAL; + goto error_cleanup; + } + cipher_ctx.tcfg = tcfg; + cipher_ctx.tctx = tctx; + if (cipher_ctx.tcfg->flags & CRYPTOCOP_DECRYPT){ + cipher_ctx.decrypt = 1; + } + switch (tctx->init.cipher_mode) { + case cryptocop_cipher_mode_ecb: + cipher_ctx.cbcmode = 0; + break; + case cryptocop_cipher_mode_cbc: + cipher_ctx.cbcmode = 1; + break; + default: + DEBUG_API(printk("cryptocop_setup_dma_list: cipher_ctx, bad cipher mode==%d\n", tctx->init.cipher_mode)); + failed = -EINVAL; + goto error_cleanup; + } + DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx, set CBC mode==%d\n", cipher_ctx.cbcmode)); + switch (tctx->init.alg){ + case cryptocop_alg_des: + cipher_ctx.ciph_conf = 0; + cipher_ctx.unit_no = src_des; + cipher_ctx.blocklength = DES_BLOCK_LENGTH; + break; + case cryptocop_alg_3des: + cipher_ctx.ciph_conf = 1; + cipher_ctx.unit_no = src_des; + cipher_ctx.blocklength = DES_BLOCK_LENGTH; + break; + case cryptocop_alg_aes: + cipher_ctx.ciph_conf = 2; + cipher_ctx.unit_no = src_aes; + cipher_ctx.blocklength = AES_BLOCK_LENGTH; + break; + default: + panic("cryptocop_setup_dma_list: impossible algorithm %d\n", tctx->init.alg); + } + (*int_op)->tdes_mode = tctx->init.tdes_mode; + break; + case cryptocop_alg_md5: + case cryptocop_alg_sha1: + /* digest */ + if (digest_ctx.tcfg != NULL){ + DEBUG_API(printk("cryptocop_setup_dma_list: multiple digests in operation.\n")); + failed = -EINVAL; + goto error_cleanup; + } + digest_ctx.tcfg = tcfg; + digest_ctx.tctx = tctx; + digest_ctx.hash_mode = 0; /* Don't use explicit IV in this API. */ + switch (tctx->init.alg){ + case cryptocop_alg_md5: + digest_ctx.blocklength = MD5_BLOCK_LENGTH; + digest_ctx.unit_no = src_md5; + digest_ctx.hash_conf = 1; /* 1 => MD-5 */ + break; + case cryptocop_alg_sha1: + digest_ctx.blocklength = SHA1_BLOCK_LENGTH; + digest_ctx.unit_no = src_sha1; + digest_ctx.hash_conf = 0; /* 0 => SHA-1 */ + break; + default: + panic("cryptocop_setup_dma_list: impossible digest algorithm\n"); + } + break; + case cryptocop_alg_csum: + /* digest */ + if (csum_ctx.tcfg != NULL){ + DEBUG_API(printk("cryptocop_setup_dma_list: multiple checksums in operation.\n")); + failed = -EINVAL; + goto error_cleanup; + } + (*int_op)->csum_mode = tctx->init.csum_mode; + csum_ctx.tcfg = tcfg; + csum_ctx.tctx = tctx; + break; + default: + /* no algorithm. */ + DEBUG_API(printk("cryptocop_setup_dma_list: invalid algorithm %d specified in tfrm %d.\n", tctx->init.alg, tcfg->tid)); + failed = -EINVAL; + goto error_cleanup; + } + tcfg = tcfg->next; + } + /* Download key if a cipher is used. */ + if (cipher_ctx.tcfg && (cipher_ctx.tctx->init.alg != cryptocop_alg_mem2mem)){ + struct cryptocop_dma_desc *key_desc = NULL; + + failed = setup_key_dl_desc(&cipher_ctx, &key_desc, alloc_flag); + if (failed) { + DEBUG_API(printk("cryptocop_setup_dma_list: setup key dl\n")); + goto error_cleanup; + } + current_out_cdesc->next = key_desc; + current_out_cdesc = key_desc; + indata_ix += (unsigned int)(key_desc->dma_descr->after - key_desc->dma_descr->buf); + + /* Download explicit IV if a cipher is used and CBC mode and explicit IV selected. */ + if ((cipher_ctx.tctx->init.cipher_mode == cryptocop_cipher_mode_cbc) && (cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV)) { + struct cryptocop_dma_desc *iv_desc = NULL; + + DEBUG(printk("cryptocop_setup_dma_list: setup cipher CBC IV descriptor.\n")); + + failed = setup_cipher_iv_desc(&cipher_ctx, &iv_desc, alloc_flag); + if (failed) { + DEBUG_API(printk("cryptocop_setup_dma_list: CBC IV descriptor.\n")); + goto error_cleanup; + } + current_out_cdesc->next = iv_desc; + current_out_cdesc = iv_desc; + indata_ix += (unsigned int)(iv_desc->dma_descr->after - iv_desc->dma_descr->buf); + } + } + + /* Process descriptors. */ + odsc = operation->tfrm_op.desc; + while (odsc) { + struct cryptocop_desc_cfg *dcfg = odsc->cfg; + struct strcop_meta_out meta_out = {0}; + size_t desc_len = odsc->length; + int active_count, eop_needed_count; + + output_tc = NULL; + + DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor\n")); + + while (dcfg) { + struct cryptocop_tfrm_ctx *tc = NULL; + + DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor configuration.\n")); + /* Get the local context for the transform and mark it as the output unit if it produces output. */ + if (digest_ctx.tcfg && (digest_ctx.tcfg->tid == dcfg->tid)){ + tc = &digest_ctx; + } else if (cipher_ctx.tcfg && (cipher_ctx.tcfg->tid == dcfg->tid)){ + tc = &cipher_ctx; + } else if (csum_ctx.tcfg && (csum_ctx.tcfg->tid == dcfg->tid)){ + tc = &csum_ctx; + } + if (!tc) { + DEBUG_API(printk("cryptocop_setup_dma_list: invalid transform %d specified in descriptor.\n", dcfg->tid)); + failed = -EINVAL; + goto error_cleanup; + } + if (tc->done) { + DEBUG_API(printk("cryptocop_setup_dma_list: completed transform %d reused.\n", dcfg->tid)); + failed = -EINVAL; + goto error_cleanup; + } + if (!tc->active) { + tc->start_ix = indata_ix; + tc->active = 1; + } + + tc->previous_src = tc->current_src; + tc->prev_src = tc->curr_src; + /* Map source unit id to DMA source config. */ + switch (dcfg->src){ + case cryptocop_source_dma: + tc->current_src = src_dma; + break; + case cryptocop_source_des: + tc->current_src = src_des; + break; + case cryptocop_source_3des: + tc->current_src = src_des; + break; + case cryptocop_source_aes: + tc->current_src = src_aes; + break; + case cryptocop_source_md5: + case cryptocop_source_sha1: + case cryptocop_source_csum: + case cryptocop_source_none: + default: + /* We do not allow using accumulating style units (SHA-1, MD5, checksum) as sources to other units. + */ + DEBUG_API(printk("cryptocop_setup_dma_list: bad unit source configured %d.\n", dcfg->src)); + failed = -EINVAL; + goto error_cleanup; + } + if (tc->current_src != src_dma) { + /* Find the unit we are sourcing from. */ + if (digest_ctx.unit_no == tc->current_src){ + tc->curr_src = &digest_ctx; + } else if (cipher_ctx.unit_no == tc->current_src){ + tc->curr_src = &cipher_ctx; + } else if (csum_ctx.unit_no == tc->current_src){ + tc->curr_src = &csum_ctx; + } + if ((tc->curr_src == tc) && (tc->unit_no != src_dma)){ + DEBUG_API(printk("cryptocop_setup_dma_list: unit %d configured to source from itself.\n", tc->unit_no)); + failed = -EINVAL; + goto error_cleanup; + } + } else { + tc->curr_src = NULL; + } + + /* Detect source switch. */ + DEBUG(printk("cryptocop_setup_dma_list: tc->active=%d tc->unit_no=%d tc->current_src=%d tc->previous_src=%d, tc->curr_src=0x%p, tc->prev_srv=0x%p\n", tc->active, tc->unit_no, tc->current_src, tc->previous_src, tc->curr_src, tc->prev_src)); + if (tc->active && (tc->current_src != tc->previous_src)) { + /* Only allow source switch when both the old source unit and the new one have + * no pending data to process (i.e. the consumed length must be a multiple of the + * transform blocklength). */ + /* Note: if the src == NULL we are actually sourcing from DMA out. */ + if (((tc->prev_src != NULL) && (tc->prev_src->consumed % tc->prev_src->blocklength)) || + ((tc->curr_src != NULL) && (tc->curr_src->consumed % tc->curr_src->blocklength))) + { + DEBUG_API(printk("cryptocop_setup_dma_list: can only disconnect from or connect to a unit on a multiple of the blocklength, old: cons=%d, prod=%d, block=%d, new: cons=%d prod=%d, block=%d.\n", tc->prev_src ? tc->prev_src->consumed : INT_MIN, tc->prev_src ? tc->prev_src->produced : INT_MIN, tc->prev_src ? tc->prev_src->blocklength : INT_MIN, tc->curr_src ? tc->curr_src->consumed : INT_MIN, tc->curr_src ? tc->curr_src->produced : INT_MIN, tc->curr_src ? tc->curr_src->blocklength : INT_MIN)); + failed = -EINVAL; + goto error_cleanup; + } + } + /* Detect unit deactivation. */ + if (dcfg->last) { + /* Length check of this is handled below. */ + tc->done = 1; + } + dcfg = dcfg->next; + } /* while (dcfg) */ + DEBUG(printk("cryptocop_setup_dma_list: parsing operation descriptor configuration complete.\n")); + + if (cipher_ctx.active && (cipher_ctx.curr_src != NULL) && !cipher_ctx.curr_src->active){ + DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", cipher_ctx.curr_src->unit_no)); + failed = -EINVAL; + goto error_cleanup; + } + if (digest_ctx.active && (digest_ctx.curr_src != NULL) && !digest_ctx.curr_src->active){ + DEBUG_API(printk("cryptocop_setup_dma_list: digest source from inactive unit %d\n", digest_ctx.curr_src->unit_no)); + failed = -EINVAL; + goto error_cleanup; + } + if (csum_ctx.active && (csum_ctx.curr_src != NULL) && !csum_ctx.curr_src->active){ + DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", csum_ctx.curr_src->unit_no)); + failed = -EINVAL; + goto error_cleanup; + } + + /* Update consumed and produced lengths. + + The consumed length accounting here is actually cheating. If a unit source from DMA (or any + other unit that process data in blocks of one octet) it is correct, but if it source from a + block processing unit, i.e. a cipher, it will be temporarily incorrect at some times. However + since it is only allowed--by the HW--to change source to or from a block processing unit at times where that + unit has processed an exact multiple of its block length the end result will be correct. + Beware that if the source change restriction change this code will need to be (much) reworked. + */ + DEBUG(printk("cryptocop_setup_dma_list: desc->length=%d, desc_len=%d.\n", odsc->length, desc_len)); + + if (csum_ctx.active) { + csum_ctx.consumed += desc_len; + if (csum_ctx.done) { + csum_ctx.produced = 2; + } + DEBUG(printk("cryptocop_setup_dma_list: csum_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", csum_ctx.consumed, csum_ctx.produced, csum_ctx.blocklength)); + } + if (digest_ctx.active) { + digest_ctx.consumed += desc_len; + if (digest_ctx.done) { + if (digest_ctx.unit_no == src_md5) { + digest_ctx.produced = MD5_STATE_LENGTH; + } else { + digest_ctx.produced = SHA1_STATE_LENGTH; + } + } + DEBUG(printk("cryptocop_setup_dma_list: digest_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", digest_ctx.consumed, digest_ctx.produced, digest_ctx.blocklength)); + } + if (cipher_ctx.active) { + /* Ciphers are allowed only to source from DMA out. That is filtered above. */ + assert(cipher_ctx.current_src == src_dma); + cipher_ctx.consumed += desc_len; + cipher_ctx.produced = cipher_ctx.blocklength * (cipher_ctx.consumed / cipher_ctx.blocklength); + if (cipher_ctx.cbcmode && !(cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV) && cipher_ctx.produced){ + cipher_ctx.produced -= cipher_ctx.blocklength; /* Compensate for CBC iv. */ + } + DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", cipher_ctx.consumed, cipher_ctx.produced, cipher_ctx.blocklength)); + } + + /* Setup the DMA out descriptors. */ + /* Configure the metadata. */ + active_count = 0; + eop_needed_count = 0; + if (cipher_ctx.active) { + ++active_count; + if (cipher_ctx.unit_no == src_dma){ + /* mem2mem */ + meta_out.ciphsel = src_none; + } else { + meta_out.ciphsel = cipher_ctx.current_src; + } + meta_out.ciphconf = cipher_ctx.ciph_conf; + meta_out.cbcmode = cipher_ctx.cbcmode; + meta_out.decrypt = cipher_ctx.decrypt; + DEBUG(printk("set ciphsel=%d ciphconf=%d cbcmode=%d decrypt=%d\n", meta_out.ciphsel, meta_out.ciphconf, meta_out.cbcmode, meta_out.decrypt)); + if (cipher_ctx.done) ++eop_needed_count; + } else { + meta_out.ciphsel = src_none; + } + + if (digest_ctx.active) { + ++active_count; + meta_out.hashsel = digest_ctx.current_src; + meta_out.hashconf = digest_ctx.hash_conf; + meta_out.hashmode = 0; /* Explicit mode is not used here. */ + DEBUG(printk("set hashsel=%d hashconf=%d hashmode=%d\n", meta_out.hashsel, meta_out.hashconf, meta_out.hashmode)); + if (digest_ctx.done) { + assert(digest_ctx.pad_descs == NULL); + failed = create_pad_descriptor(&digest_ctx, &digest_ctx.pad_descs, alloc_flag); + if (failed) { + DEBUG_API(printk("cryptocop_setup_dma_list: failed digest pad creation.\n")); + goto error_cleanup; + } + } + } else { + meta_out.hashsel = src_none; + } + + if (csum_ctx.active) { + ++active_count; + meta_out.csumsel = csum_ctx.current_src; + if (csum_ctx.done) { + assert(csum_ctx.pad_descs == NULL); + failed = create_pad_descriptor(&csum_ctx, &csum_ctx.pad_descs, alloc_flag); + if (failed) { + DEBUG_API(printk("cryptocop_setup_dma_list: failed csum pad creation.\n")); + goto error_cleanup; + } + } + } else { + meta_out.csumsel = src_none; + } + DEBUG(printk("cryptocop_setup_dma_list: %d eop needed, %d active units\n", eop_needed_count, active_count)); + /* Setup DMA out descriptors for the indata. */ + failed = create_output_descriptors(operation, &iniov_ix, &iniov_offset, desc_len, ¤t_out_cdesc, &meta_out, alloc_flag); + if (failed) { + DEBUG_API(printk("cryptocop_setup_dma_list: create_output_descriptors %d\n", failed)); + goto error_cleanup; + } + /* Setup out EOP. If there are active units that are not done here they cannot get an EOP + * so we ust setup a zero length descriptor to DMA to signal EOP only to done units. + * If there is a pad descriptor EOP for the padded unit will be EOPed by it. + */ + assert(active_count >= eop_needed_count); + assert((eop_needed_count == 0) || (eop_needed_count == 1)); + if (eop_needed_count) { + /* This means that the bulk operation (cipeher/m2m) is terminated. */ + if (active_count > 1) { + /* Use zero length EOP descriptor. */ + struct cryptocop_dma_desc *ed = alloc_cdesc(alloc_flag); + struct strcop_meta_out ed_mo = {0}; + if (!ed) { + DEBUG_API(printk("cryptocop_setup_dma_list: alloc EOP descriptor for cipher\n")); + failed = -ENOMEM; + goto error_cleanup; + } + + assert(cipher_ctx.active && cipher_ctx.done); + + if (cipher_ctx.unit_no == src_dma){ + /* mem2mem */ + ed_mo.ciphsel = src_none; + } else { + ed_mo.ciphsel = cipher_ctx.current_src; + } + ed_mo.ciphconf = cipher_ctx.ciph_conf; + ed_mo.cbcmode = cipher_ctx.cbcmode; + ed_mo.decrypt = cipher_ctx.decrypt; + + ed->free_buf = NULL; + ed->dma_descr->wait = 1; + ed->dma_descr->out_eop = 1; + + ed->dma_descr->buf = (char*)virt_to_phys(&ed); /* Use any valid physical address for zero length descriptor. */ + ed->dma_descr->after = ed->dma_descr->buf; + ed->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, ed_mo); + current_out_cdesc->next = ed; + current_out_cdesc = ed; + } else { + /* Set EOP in the current out descriptor since the only active module is + * the one needing the EOP. */ + + current_out_cdesc->dma_descr->out_eop = 1; + } + } + + if (cipher_ctx.done && cipher_ctx.active) cipher_ctx.active = 0; + if (digest_ctx.done && digest_ctx.active) digest_ctx.active = 0; + if (csum_ctx.done && csum_ctx.active) csum_ctx.active = 0; + indata_ix += odsc->length; + odsc = odsc->next; + } /* while (odsc) */ /* Process descriptors. */ + DEBUG(printk("cryptocop_setup_dma_list: done parsing operation descriptors\n")); + if (cipher_ctx.tcfg && (cipher_ctx.active || !cipher_ctx.done)){ + DEBUG_API(printk("cryptocop_setup_dma_list: cipher operation not terminated.\n")); + failed = -EINVAL; + goto error_cleanup; + } + if (digest_ctx.tcfg && (digest_ctx.active || !digest_ctx.done)){ + DEBUG_API(printk("cryptocop_setup_dma_list: digest operation not terminated.\n")); + failed = -EINVAL; + goto error_cleanup; + } + if (csum_ctx.tcfg && (csum_ctx.active || !csum_ctx.done)){ + DEBUG_API(printk("cryptocop_setup_dma_list: csum operation not terminated.\n")); + failed = -EINVAL; + goto error_cleanup; + } + + failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &cipher_ctx, alloc_flag); + if (failed){ + DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); + goto error_cleanup; + } + failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &digest_ctx, alloc_flag); + if (failed){ + DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); + goto error_cleanup; + } + failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &csum_ctx, alloc_flag); + if (failed){ + DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); + goto error_cleanup; + } + + DEBUG(printk("cryptocop_setup_dma_list: int_op=0x%p, *int_op=0x%p\n", int_op, *int_op)); + (*int_op)->cdesc_out = out_cdesc_head.next; + (*int_op)->cdesc_in = in_cdesc_head.next; + DEBUG(printk("cryptocop_setup_dma_list: out_cdesc_head=0x%p in_cdesc_head=0x%p\n", (*int_op)->cdesc_out, (*int_op)->cdesc_in)); + + setup_descr_chain(out_cdesc_head.next); + setup_descr_chain(in_cdesc_head.next); + + /* Last but not least: mark the last DMA in descriptor for a INTR and EOL and the the + * last DMA out descriptor for EOL. + */ + current_in_cdesc->dma_descr->intr = 1; + current_in_cdesc->dma_descr->eol = 1; + current_out_cdesc->dma_descr->eol = 1; + + /* Setup DMA contexts. */ + (*int_op)->ctx_out.next = NULL; + (*int_op)->ctx_out.eol = 1; + (*int_op)->ctx_out.intr = 0; + (*int_op)->ctx_out.store_mode = 0; + (*int_op)->ctx_out.en = 0; + (*int_op)->ctx_out.dis = 0; + (*int_op)->ctx_out.md0 = 0; + (*int_op)->ctx_out.md1 = 0; + (*int_op)->ctx_out.md2 = 0; + (*int_op)->ctx_out.md3 = 0; + (*int_op)->ctx_out.md4 = 0; + (*int_op)->ctx_out.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_out->dma_descr); + (*int_op)->ctx_out.saved_data_buf = (*int_op)->cdesc_out->dma_descr->buf; /* Already physical address. */ + + (*int_op)->ctx_in.next = NULL; + (*int_op)->ctx_in.eol = 1; + (*int_op)->ctx_in.intr = 0; + (*int_op)->ctx_in.store_mode = 0; + (*int_op)->ctx_in.en = 0; + (*int_op)->ctx_in.dis = 0; + (*int_op)->ctx_in.md0 = 0; + (*int_op)->ctx_in.md1 = 0; + (*int_op)->ctx_in.md2 = 0; + (*int_op)->ctx_in.md3 = 0; + (*int_op)->ctx_in.md4 = 0; + + (*int_op)->ctx_in.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_in->dma_descr); + (*int_op)->ctx_in.saved_data_buf = (*int_op)->cdesc_in->dma_descr->buf; /* Already physical address. */ + + DEBUG(printk("cryptocop_setup_dma_list: done\n")); + return 0; + +error_cleanup: + { + /* Free all allocated resources. */ + struct cryptocop_dma_desc *tmp_cdesc; + while (digest_ctx.pad_descs){ + tmp_cdesc = digest_ctx.pad_descs->next; + free_cdesc(digest_ctx.pad_descs); + digest_ctx.pad_descs = tmp_cdesc; + } + while (csum_ctx.pad_descs){ + tmp_cdesc = csum_ctx.pad_descs->next; + free_cdesc(csum_ctx.pad_descs); + csum_ctx.pad_descs = tmp_cdesc; + } + assert(cipher_ctx.pad_descs == NULL); /* The ciphers are never padded. */ + + if (*int_op != NULL) delete_internal_operation(*int_op); + } + DEBUG_API(printk("cryptocop_setup_dma_list: done with error %d\n", failed)); + return failed; +} + + +static void delete_internal_operation(struct cryptocop_int_operation *iop) +{ + void *ptr = iop->alloc_ptr; + struct cryptocop_dma_desc *cd = iop->cdesc_out; + struct cryptocop_dma_desc *next; + + DEBUG(printk("delete_internal_operation: iop=0x%p, alloc_ptr=0x%p\n", iop, ptr)); + + while (cd) { + next = cd->next; + free_cdesc(cd); + cd = next; + } + cd = iop->cdesc_in; + while (cd) { + next = cd->next; + free_cdesc(cd); + cd = next; + } + kfree(ptr); +} + +#define MD5_MIN_PAD_LENGTH (9) +#define MD5_PAD_LENGTH_FIELD_LENGTH (8) + +static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length) +{ + size_t padlen = MD5_BLOCK_LENGTH - (hashed_length % MD5_BLOCK_LENGTH); + unsigned char *p; + int i; + unsigned long long int bit_length = hashed_length << 3; + + if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH; + + p = kzalloc(padlen, alloc_flag); + if (!p) return -ENOMEM; + + *p = 0x80; + + DEBUG(printk("create_md5_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length)); + + i = padlen - MD5_PAD_LENGTH_FIELD_LENGTH; + while (bit_length != 0){ + p[i++] = bit_length % 0x100; + bit_length >>= 8; + } + + *pad = (char*)p; + *pad_length = padlen; + + return 0; +} + +#define SHA1_MIN_PAD_LENGTH (9) +#define SHA1_PAD_LENGTH_FIELD_LENGTH (8) + +static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length) +{ + size_t padlen = SHA1_BLOCK_LENGTH - (hashed_length % SHA1_BLOCK_LENGTH); + unsigned char *p; + int i; + unsigned long long int bit_length = hashed_length << 3; + + if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH; + + p = kzalloc(padlen, alloc_flag); + if (!p) return -ENOMEM; + + *p = 0x80; + + DEBUG(printk("create_sha1_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length)); + + i = padlen - 1; + while (bit_length != 0){ + p[i--] = bit_length % 0x100; + bit_length >>= 8; + } + + *pad = (char*)p; + *pad_length = padlen; + + return 0; +} + + +static int transform_ok(struct cryptocop_transform_init *tinit) +{ + switch (tinit->alg){ + case cryptocop_alg_csum: + switch (tinit->csum_mode){ + case cryptocop_csum_le: + case cryptocop_csum_be: + break; + default: + DEBUG_API(printk("transform_ok: Bad mode set for csum transform\n")); + return -EINVAL; + } + case cryptocop_alg_mem2mem: + case cryptocop_alg_md5: + case cryptocop_alg_sha1: + if (tinit->keylen != 0) { + DEBUG_API(printk("transform_ok: non-zero keylength, %d, for a digest/csum algorithm\n", tinit->keylen)); + return -EINVAL; /* This check is a bit strict. */ + } + break; + case cryptocop_alg_des: + if (tinit->keylen != 64) { + DEBUG_API(printk("transform_ok: keylen %d invalid for DES\n", tinit->keylen)); + return -EINVAL; + } + break; + case cryptocop_alg_3des: + if (tinit->keylen != 192) { + DEBUG_API(printk("transform_ok: keylen %d invalid for 3DES\n", tinit->keylen)); + return -EINVAL; + } + break; + case cryptocop_alg_aes: + if (tinit->keylen != 128 && tinit->keylen != 192 && tinit->keylen != 256) { + DEBUG_API(printk("transform_ok: keylen %d invalid for AES\n", tinit->keylen)); + return -EINVAL; + } + break; + case cryptocop_no_alg: + default: + DEBUG_API(printk("transform_ok: no such algorithm %d\n", tinit->alg)); + return -EINVAL; + } + + switch (tinit->alg){ + case cryptocop_alg_des: + case cryptocop_alg_3des: + case cryptocop_alg_aes: + if (tinit->cipher_mode != cryptocop_cipher_mode_ecb && tinit->cipher_mode != cryptocop_cipher_mode_cbc) return -EINVAL; + default: + break; + } + return 0; +} + + +int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag) +{ + struct cryptocop_session *sess; + struct cryptocop_transform_init *tfrm_in = tinit; + struct cryptocop_transform_init *tmp_in; + int no_tfrms = 0; + int i; + unsigned long int flags; + + init_stream_coprocessor(); /* For safety if we are called early */ + + while (tfrm_in){ + int err; + ++no_tfrms; + if ((err = transform_ok(tfrm_in))) { + DEBUG_API(printk("cryptocop_new_session, bad transform\n")); + return err; + } + tfrm_in = tfrm_in->next; + } + if (0 == no_tfrms) { + DEBUG_API(printk("cryptocop_new_session, no transforms specified\n")); + return -EINVAL; + } + + sess = kmalloc(sizeof(struct cryptocop_session), alloc_flag); + if (!sess){ + DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_session\n")); + return -ENOMEM; + } + + sess->tfrm_ctx = kmalloc(no_tfrms * sizeof(struct cryptocop_transform_ctx), alloc_flag); + if (!sess->tfrm_ctx) { + DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_transform_ctx\n")); + kfree(sess); + return -ENOMEM; + } + + tfrm_in = tinit; + for (i = 0; i < no_tfrms; i++){ + tmp_in = tfrm_in->next; + while (tmp_in){ + if (tmp_in->tid == tfrm_in->tid) { + DEBUG_API(printk("cryptocop_new_session, duplicate transform ids\n")); + kfree(sess->tfrm_ctx); + kfree(sess); + return -EINVAL; + } + tmp_in = tmp_in->next; + } + memcpy(&sess->tfrm_ctx[i].init, tfrm_in, sizeof(struct cryptocop_transform_init)); + sess->tfrm_ctx[i].dec_key_set = 0; + sess->tfrm_ctx[i].next = &sess->tfrm_ctx[i] + 1; + + tfrm_in = tfrm_in->next; + } + sess->tfrm_ctx[i-1].next = NULL; + + spin_lock_irqsave(&cryptocop_sessions_lock, flags); + sess->sid = next_sid; + next_sid++; + /* TODO If we are really paranoid we should do duplicate check to handle sid wraparound. + * OTOH 2^64 is a really large number of session. */ + if (next_sid == 0) next_sid = 1; + + /* Prepend to session list. */ + sess->next = cryptocop_sessions; + cryptocop_sessions = sess; + spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); + *sid = sess->sid; + return 0; +} + + +int cryptocop_free_session(cryptocop_session_id sid) +{ + struct cryptocop_transform_ctx *tc; + struct cryptocop_session *sess = NULL; + struct cryptocop_session *psess = NULL; + unsigned long int flags; + int i; + LIST_HEAD(remove_list); + struct list_head *node, *tmp; + struct cryptocop_prio_job *pj; + + DEBUG(printk("cryptocop_free_session: sid=%lld\n", sid)); + + spin_lock_irqsave(&cryptocop_sessions_lock, flags); + sess = cryptocop_sessions; + while (sess && sess->sid != sid){ + psess = sess; + sess = sess->next; + } + if (sess){ + if (psess){ + psess->next = sess->next; + } else { + cryptocop_sessions = sess->next; + } + } + spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); + + if (!sess) return -EINVAL; + + /* Remove queued jobs. */ + spin_lock_irqsave(&cryptocop_job_queue_lock, flags); + + for (i = 0; i < cryptocop_prio_no_prios; i++){ + if (!list_empty(&(cryptocop_job_queues[i].jobs))){ + list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) { + pj = list_entry(node, struct cryptocop_prio_job, node); + if (pj->oper->sid == sid) { + list_move_tail(node, &remove_list); + } + } + } + } + spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); + + list_for_each_safe(node, tmp, &remove_list) { + list_del(node); + pj = list_entry(node, struct cryptocop_prio_job, node); + pj->oper->operation_status = -EAGAIN; /* EAGAIN is not ideal for job/session terminated but it's the best choice I know of. */ + DEBUG(printk("cryptocop_free_session: pj=0x%p, pj->oper=0x%p, pj->iop=0x%p\n", pj, pj->oper, pj->iop)); + pj->oper->cb(pj->oper, pj->oper->cb_data); + delete_internal_operation(pj->iop); + kfree(pj); + } + + tc = sess->tfrm_ctx; + /* Erase keying data. */ + while (tc){ + DEBUG(printk("cryptocop_free_session: memset keys, tfrm id=%d\n", tc->init.tid)); + memset(tc->init.key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH); + memset(tc->dec_key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH); + tc = tc->next; + } + kfree(sess->tfrm_ctx); + kfree(sess); + + return 0; +} + +static struct cryptocop_session *get_session(cryptocop_session_id sid) +{ + struct cryptocop_session *sess; + unsigned long int flags; + + spin_lock_irqsave(&cryptocop_sessions_lock, flags); + sess = cryptocop_sessions; + while (sess && (sess->sid != sid)){ + sess = sess->next; + } + spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); + + return sess; +} + +static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid) +{ + struct cryptocop_transform_ctx *tc = sess->tfrm_ctx; + + DEBUG(printk("get_transform_ctx, sess=0x%p, tid=%d\n", sess, tid)); + assert(sess != NULL); + while (tc && tc->init.tid != tid){ + DEBUG(printk("tc=0x%p, tc->next=0x%p\n", tc, tc->next)); + tc = tc->next; + } + DEBUG(printk("get_transform_ctx, returning tc=0x%p\n", tc)); + return tc; +} + + + +/* The AES s-transform matrix (s-box). */ +static const u8 aes_sbox[256] = { + 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118, + 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192, + 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21, + 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117, + 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132, + 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207, + 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168, + 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210, + 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115, + 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219, + 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121, + 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8, + 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138, + 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158, + 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223, + 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22 +}; + +/* AES has a 32 bit word round constants for each round in the + * key schedule. round_constant[i] is really Rcon[i+1] in FIPS187. + */ +static u32 round_constant[11] = { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, + 0x10000000, 0x20000000, 0x40000000, 0x80000000, + 0x1B000000, 0x36000000, 0x6C000000 +}; + +/* Apply the s-box to each of the four occtets in w. */ +static u32 aes_ks_subword(const u32 w) +{ + u8 bytes[4]; + + *(u32*)(&bytes[0]) = w; + bytes[0] = aes_sbox[bytes[0]]; + bytes[1] = aes_sbox[bytes[1]]; + bytes[2] = aes_sbox[bytes[2]]; + bytes[3] = aes_sbox[bytes[3]]; + return *(u32*)(&bytes[0]); +} + +/* The encrypt (forward) Rijndael key schedule algorithm pseudo code: + * (Note that AES words are 32 bit long) + * + * KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)], Nk){ + * word temp + * i = 0 + * while (i < Nk) { + * w[i] = word(key[4*i, 4*i + 1, 4*i + 2, 4*i + 3]) + * i = i + 1 + * } + * i = Nk + * + * while (i < (Nb * (Nr + 1))) { + * temp = w[i - 1] + * if ((i mod Nk) == 0) { + * temp = SubWord(RotWord(temp)) xor Rcon[i/Nk] + * } + * else if ((Nk > 6) && ((i mod Nk) == 4)) { + * temp = SubWord(temp) + * } + * w[i] = w[i - Nk] xor temp + * } + * RotWord(t) does a 8 bit cyclic shift left on a 32 bit word. + * SubWord(t) applies the AES s-box individually to each octet + * in a 32 bit word. + * + * For AES Nk can have the values 4, 6, and 8 (corresponding to + * values for Nr of 10, 12, and 14). Nb is always 4. + * + * To construct w[i], w[i - 1] and w[i - Nk] must be + * available. Consequently we must keep a state of the last Nk words + * to be able to create the last round keys. + */ +static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength) +{ + u32 temp; + u32 w_ring[8]; /* nk is max 8, use elements 0..(nk - 1) as a ringbuffer */ + u8 w_last_ix; + int i; + u8 nr, nk; + + switch (keylength){ + case 128: + nk = 4; + nr = 10; + break; + case 192: + nk = 6; + nr = 12; + break; + case 256: + nk = 8; + nr = 14; + break; + default: + panic("stream co-processor: bad aes key length in get_aes_decrypt_key\n"); + }; + + /* Need to do host byte order correction here since key is byte oriented and the + * kx algorithm is word (u32) oriented. */ + for (i = 0; i < nk; i+=1) { + w_ring[i] = be32_to_cpu(*(u32*)&key[4*i]); + } + + i = (int)nk; + w_last_ix = i - 1; + while (i < (4 * (nr + 2))) { + temp = w_ring[w_last_ix]; + if (!(i % nk)) { + /* RotWord(temp) */ + temp = (temp << 8) | (temp >> 24); + temp = aes_ks_subword(temp); + temp ^= round_constant[i/nk - 1]; + } else if ((nk > 6) && ((i % nk) == 4)) { + temp = aes_ks_subword(temp); + } + w_last_ix = (w_last_ix + 1) % nk; /* This is the same as (i-Nk) mod Nk */ + temp ^= w_ring[w_last_ix]; + w_ring[w_last_ix] = temp; + + /* We need the round keys for round Nr+1 and Nr+2 (round key + * Nr+2 is the round key beyond the last one used when + * encrypting). Rounds are numbered starting from 0, Nr=10 + * implies 11 rounds are used in encryption/decryption. + */ + if (i >= (4 * nr)) { + /* Need to do host byte order correction here, the key + * is byte oriented. */ + *(u32*)dec_key = cpu_to_be32(temp); + dec_key += 4; + } + ++i; + } +} + + +/**** Job/operation management. ****/ + +int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation) +{ + return cryptocop_job_queue_insert(cryptocop_prio_kernel_csum, operation); +} + +int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation) +{ + return cryptocop_job_queue_insert(cryptocop_prio_kernel, operation); +} + +int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation) +{ + return cryptocop_job_queue_insert(cryptocop_prio_user, operation); +} + +static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation) +{ + int ret; + struct cryptocop_prio_job *pj = NULL; + unsigned long int flags; + + DEBUG(printk("cryptocop_job_queue_insert(%d, 0x%p)\n", prio, operation)); + + if (!operation || !operation->cb){ + DEBUG_API(printk("cryptocop_job_queue_insert oper=0x%p, NULL operation or callback\n", operation)); + return -EINVAL; + } + + if ((ret = cryptocop_job_setup(&pj, operation)) != 0){ + DEBUG_API(printk("cryptocop_job_queue_insert: job setup failed\n")); + return ret; + } + assert(pj != NULL); + + spin_lock_irqsave(&cryptocop_job_queue_lock, flags); + list_add_tail(&pj->node, &cryptocop_job_queues[prio].jobs); + spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); + + /* Make sure a job is running */ + cryptocop_start_job(); + return 0; +} + +static void cryptocop_do_tasklet(unsigned long unused); +DECLARE_TASKLET (cryptocop_tasklet, cryptocop_do_tasklet, 0); + +static void cryptocop_do_tasklet(unsigned long unused) +{ + struct list_head *node; + struct cryptocop_prio_job *pj = NULL; + unsigned long flags; + + DEBUG(printk("cryptocop_do_tasklet: entering\n")); + + do { + spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags); + if (!list_empty(&cryptocop_completed_jobs)){ + node = cryptocop_completed_jobs.next; + list_del(node); + pj = list_entry(node, struct cryptocop_prio_job, node); + } else { + pj = NULL; + } + spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags); + if (pj) { + assert(pj->oper != NULL); + + /* Notify consumer of operation completeness. */ + DEBUG(printk("cryptocop_do_tasklet: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); + + pj->oper->operation_status = 0; /* Job is completed. */ + pj->oper->cb(pj->oper, pj->oper->cb_data); + delete_internal_operation(pj->iop); + kfree(pj); + } + } while (pj != NULL); + + DEBUG(printk("cryptocop_do_tasklet: exiting\n")); +} + +static irqreturn_t +dma_done_interrupt(int irq, void *dev_id) +{ + struct cryptocop_prio_job *done_job; + reg_dma_rw_ack_intr ack_intr = { + .data = 1, + }; + + REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); + + DEBUG(printk("cryptocop DMA done\n")); + + spin_lock(&running_job_lock); + if (cryptocop_running_job == NULL){ + printk("stream co-processor got interrupt when not busy\n"); + spin_unlock(&running_job_lock); + return IRQ_HANDLED; + } + done_job = cryptocop_running_job; + cryptocop_running_job = NULL; + spin_unlock(&running_job_lock); + + /* Start processing a job. */ + if (!spin_trylock(&cryptocop_process_lock)){ + DEBUG(printk("cryptocop irq handler, not starting a job\n")); + } else { + cryptocop_start_job(); + spin_unlock(&cryptocop_process_lock); + } + + done_job->oper->operation_status = 0; /* Job is completed. */ + if (done_job->oper->fast_callback){ + /* This operation wants callback from interrupt. */ + done_job->oper->cb(done_job->oper, done_job->oper->cb_data); + delete_internal_operation(done_job->iop); + kfree(done_job); + } else { + spin_lock(&cryptocop_completed_jobs_lock); + list_add_tail(&(done_job->node), &cryptocop_completed_jobs); + spin_unlock(&cryptocop_completed_jobs_lock); + tasklet_schedule(&cryptocop_tasklet); + } + + DEBUG(printk("cryptocop leave irq handler\n")); + return IRQ_HANDLED; +} + + +/* Setup interrupts and DMA channels. */ +static int init_cryptocop(void) +{ + unsigned long flags; + reg_dma_rw_cfg dma_cfg = {.en = 1}; + reg_dma_rw_intr_mask intr_mask_in = {.data = regk_dma_yes}; /* Only want descriptor interrupts from the DMA in channel. */ + reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 }; + reg_strcop_rw_cfg strcop_cfg = { + .ipend = regk_strcop_little, + .td1 = regk_strcop_e, + .td2 = regk_strcop_d, + .td3 = regk_strcop_e, + .ignore_sync = 0, + .en = 1 + }; + + if (request_irq(DMA_IRQ, dma_done_interrupt, 0, + "stream co-processor DMA", NULL)) + panic("request_irq stream co-processor irq dma9"); + + (void)crisv32_request_dma(OUT_DMA, "strcop", DMA_PANIC_ON_ERROR, + 0, dma_strp); + (void)crisv32_request_dma(IN_DMA, "strcop", DMA_PANIC_ON_ERROR, + 0, dma_strp); + + local_irq_save(flags); + + /* Reset and enable the cryptocop. */ + strcop_cfg.en = 0; + REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); + strcop_cfg.en = 1; + REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); + + /* Enable DMAs. */ + REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */ + REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */ + + /* Set up wordsize = 4 for DMAs. */ + DMA_WR_CMD(OUT_DMA_INST, regk_dma_set_w_size4); + DMA_WR_CMD(IN_DMA_INST, regk_dma_set_w_size4); + + /* Enable interrupts. */ + REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in); + + /* Clear intr ack. */ + REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); + + local_irq_restore(flags); + + return 0; +} + +/* Free used cryptocop hw resources (interrupt and DMA channels). */ +static void release_cryptocop(void) +{ + unsigned long flags; + reg_dma_rw_cfg dma_cfg = {.en = 0}; + reg_dma_rw_intr_mask intr_mask_in = {0}; + reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 }; + + local_irq_save(flags); + + /* Clear intr ack. */ + REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); + + /* Disable DMAs. */ + REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */ + REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */ + + /* Disable interrupts. */ + REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in); + + local_irq_restore(flags); + + free_irq(DMA_IRQ, NULL); + + (void)crisv32_free_dma(OUT_DMA); + (void)crisv32_free_dma(IN_DMA); +} + + +/* Init job queue. */ +static int cryptocop_job_queue_init(void) +{ + int i; + + INIT_LIST_HEAD(&cryptocop_completed_jobs); + + for (i = 0; i < cryptocop_prio_no_prios; i++){ + cryptocop_job_queues[i].prio = (cryptocop_queue_priority)i; + INIT_LIST_HEAD(&cryptocop_job_queues[i].jobs); + } + return 0; +} + + +static void cryptocop_job_queue_close(void) +{ + struct list_head *node, *tmp; + struct cryptocop_prio_job *pj = NULL; + unsigned long int process_flags, flags; + int i; + + /* FIXME: This is as yet untested code. */ + + /* Stop strcop from getting an operation to process while we are closing the + module. */ + spin_lock_irqsave(&cryptocop_process_lock, process_flags); + + /* Empty the job queue. */ + for (i = 0; i < cryptocop_prio_no_prios; i++){ + if (!list_empty(&(cryptocop_job_queues[i].jobs))){ + list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) { + pj = list_entry(node, struct cryptocop_prio_job, node); + list_del(node); + + /* Call callback to notify consumer of job removal. */ + DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); + pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ + pj->oper->cb(pj->oper, pj->oper->cb_data); + + delete_internal_operation(pj->iop); + kfree(pj); + } + } + } + spin_unlock_irqrestore(&cryptocop_process_lock, process_flags); + + /* Remove the running job, if any. */ + spin_lock_irqsave(&running_job_lock, flags); + if (cryptocop_running_job){ + reg_strcop_rw_cfg rw_cfg; + reg_dma_rw_cfg dma_out_cfg, dma_in_cfg; + + /* Stop DMA. */ + dma_out_cfg = REG_RD(dma, OUT_DMA_INST, rw_cfg); + dma_out_cfg.en = regk_dma_no; + REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_out_cfg); + + dma_in_cfg = REG_RD(dma, IN_DMA_INST, rw_cfg); + dma_in_cfg.en = regk_dma_no; + REG_WR(dma, IN_DMA_INST, rw_cfg, dma_in_cfg); + + /* Disble the cryptocop. */ + rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg); + rw_cfg.en = 0; + REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg); + + pj = cryptocop_running_job; + cryptocop_running_job = NULL; + + /* Call callback to notify consumer of job removal. */ + DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); + pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ + pj->oper->cb(pj->oper, pj->oper->cb_data); + + delete_internal_operation(pj->iop); + kfree(pj); + } + spin_unlock_irqrestore(&running_job_lock, flags); + + /* Remove completed jobs, if any. */ + spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags); + + list_for_each_safe(node, tmp, &cryptocop_completed_jobs) { + pj = list_entry(node, struct cryptocop_prio_job, node); + list_del(node); + /* Call callback to notify consumer of job removal. */ + DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); + pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ + pj->oper->cb(pj->oper, pj->oper->cb_data); + + delete_internal_operation(pj->iop); + kfree(pj); + } + spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags); +} + + +static void cryptocop_start_job(void) +{ + int i; + struct cryptocop_prio_job *pj; + unsigned long int flags; + unsigned long int running_job_flags; + reg_strcop_rw_cfg rw_cfg = {.en = 1, .ignore_sync = 0}; + + DEBUG(printk("cryptocop_start_job: entering\n")); + + spin_lock_irqsave(&running_job_lock, running_job_flags); + if (cryptocop_running_job != NULL){ + /* Already running. */ + DEBUG(printk("cryptocop_start_job: already running, exit\n")); + spin_unlock_irqrestore(&running_job_lock, running_job_flags); + return; + } + spin_lock_irqsave(&cryptocop_job_queue_lock, flags); + + /* Check the queues in priority order. */ + for (i = cryptocop_prio_kernel_csum; (i < cryptocop_prio_no_prios) && list_empty(&cryptocop_job_queues[i].jobs); i++); + if (i == cryptocop_prio_no_prios) { + spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); + spin_unlock_irqrestore(&running_job_lock, running_job_flags); + DEBUG(printk("cryptocop_start_job: no jobs to run\n")); + return; /* No jobs to run */ + } + DEBUG(printk("starting job for prio %d\n", i)); + + /* TODO: Do not starve lower priority jobs. Let in a lower + * prio job for every N-th processed higher prio job or some + * other scheduling policy. This could reasonably be + * tweakable since the optimal balance would depend on the + * type of load on the system. */ + + /* Pull the DMA lists from the job and start the DMA client. */ + pj = list_entry(cryptocop_job_queues[i].jobs.next, struct cryptocop_prio_job, node); + list_del(&pj->node); + spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); + cryptocop_running_job = pj; + + /* Set config register (3DES and CSUM modes). */ + switch (pj->iop->tdes_mode){ + case cryptocop_3des_eee: + rw_cfg.td1 = regk_strcop_e; + rw_cfg.td2 = regk_strcop_e; + rw_cfg.td3 = regk_strcop_e; + break; + case cryptocop_3des_eed: + rw_cfg.td1 = regk_strcop_e; + rw_cfg.td2 = regk_strcop_e; + rw_cfg.td3 = regk_strcop_d; + break; + case cryptocop_3des_ede: + rw_cfg.td1 = regk_strcop_e; + rw_cfg.td2 = regk_strcop_d; + rw_cfg.td3 = regk_strcop_e; + break; + case cryptocop_3des_edd: + rw_cfg.td1 = regk_strcop_e; + rw_cfg.td2 = regk_strcop_d; + rw_cfg.td3 = regk_strcop_d; + break; + case cryptocop_3des_dee: + rw_cfg.td1 = regk_strcop_d; + rw_cfg.td2 = regk_strcop_e; + rw_cfg.td3 = regk_strcop_e; + break; + case cryptocop_3des_ded: + rw_cfg.td1 = regk_strcop_d; + rw_cfg.td2 = regk_strcop_e; + rw_cfg.td3 = regk_strcop_d; + break; + case cryptocop_3des_dde: + rw_cfg.td1 = regk_strcop_d; + rw_cfg.td2 = regk_strcop_d; + rw_cfg.td3 = regk_strcop_e; + break; + case cryptocop_3des_ddd: + rw_cfg.td1 = regk_strcop_d; + rw_cfg.td2 = regk_strcop_d; + rw_cfg.td3 = regk_strcop_d; + break; + default: + DEBUG(printk("cryptocop_setup_dma_list: bad 3DES mode\n")); + } + switch (pj->iop->csum_mode){ + case cryptocop_csum_le: + rw_cfg.ipend = regk_strcop_little; + break; + case cryptocop_csum_be: + rw_cfg.ipend = regk_strcop_big; + break; + default: + DEBUG(printk("cryptocop_setup_dma_list: bad checksum mode\n")); + } + REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg); + + DEBUG(printk("cryptocop_start_job: starting DMA, new cryptocop_running_job=0x%p\n" + "ctx_in: 0x%p, phys: 0x%p\n" + "ctx_out: 0x%p, phys: 0x%p\n", + pj, + &pj->iop->ctx_in, (char*)virt_to_phys(&pj->iop->ctx_in), + &pj->iop->ctx_out, (char*)virt_to_phys(&pj->iop->ctx_out))); + + /* Start input DMA. */ + flush_dma_context(&pj->iop->ctx_in); + DMA_START_CONTEXT(IN_DMA_INST, virt_to_phys(&pj->iop->ctx_in)); + + /* Start output DMA. */ + DMA_START_CONTEXT(OUT_DMA_INST, virt_to_phys(&pj->iop->ctx_out)); + + spin_unlock_irqrestore(&running_job_lock, running_job_flags); + DEBUG(printk("cryptocop_start_job: exiting\n")); +} + + +static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation) +{ + int err; + int alloc_flag = operation->in_interrupt ? GFP_ATOMIC : GFP_KERNEL; + void *iop_alloc_ptr = NULL; + + *pj = kmalloc(sizeof (struct cryptocop_prio_job), alloc_flag); + if (!*pj) return -ENOMEM; + + DEBUG(printk("cryptocop_job_setup: operation=0x%p\n", operation)); + + (*pj)->oper = operation; + DEBUG(printk("cryptocop_job_setup, cb=0x%p cb_data=0x%p\n", (*pj)->oper->cb, (*pj)->oper->cb_data)); + + if (operation->use_dmalists) { + DEBUG(print_user_dma_lists(&operation->list_op)); + if (!operation->list_op.inlist || !operation->list_op.outlist || !operation->list_op.out_data_buf || !operation->list_op.in_data_buf){ + DEBUG_API(printk("cryptocop_job_setup: bad indata (use_dmalists)\n")); + kfree(*pj); + return -EINVAL; + } + iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag); + if (!iop_alloc_ptr) { + DEBUG_API(printk("cryptocop_job_setup: kmalloc cryptocop_int_operation\n")); + kfree(*pj); + return -ENOMEM; + } + (*pj)->iop = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out)); + DEBUG(memset((*pj)->iop, 0xff, sizeof(struct cryptocop_int_operation))); + (*pj)->iop->alloc_ptr = iop_alloc_ptr; + (*pj)->iop->sid = operation->sid; + (*pj)->iop->cdesc_out = NULL; + (*pj)->iop->cdesc_in = NULL; + (*pj)->iop->tdes_mode = operation->list_op.tdes_mode; + (*pj)->iop->csum_mode = operation->list_op.csum_mode; + (*pj)->iop->ddesc_out = operation->list_op.outlist; + (*pj)->iop->ddesc_in = operation->list_op.inlist; + + /* Setup DMA contexts. */ + (*pj)->iop->ctx_out.next = NULL; + (*pj)->iop->ctx_out.eol = 1; + (*pj)->iop->ctx_out.saved_data = operation->list_op.outlist; + (*pj)->iop->ctx_out.saved_data_buf = operation->list_op.out_data_buf; + + (*pj)->iop->ctx_in.next = NULL; + (*pj)->iop->ctx_in.eol = 1; + (*pj)->iop->ctx_in.saved_data = operation->list_op.inlist; + (*pj)->iop->ctx_in.saved_data_buf = operation->list_op.in_data_buf; + } else { + if ((err = cryptocop_setup_dma_list(operation, &(*pj)->iop, alloc_flag))) { + DEBUG_API(printk("cryptocop_job_setup: cryptocop_setup_dma_list failed %d\n", err)); + kfree(*pj); + return err; + } + } + DEBUG(print_dma_descriptors((*pj)->iop)); + + DEBUG(printk("cryptocop_job_setup, DMA list setup successful\n")); + + return 0; +} + +static int cryptocop_open(struct inode *inode, struct file *filp) +{ + int p = iminor(inode); + + if (p != CRYPTOCOP_MINOR) return -EINVAL; + + filp->private_data = NULL; + return 0; +} + + +static int cryptocop_release(struct inode *inode, struct file *filp) +{ + struct cryptocop_private *dev = filp->private_data; + struct cryptocop_private *dev_next; + + while (dev){ + dev_next = dev->next; + if (dev->sid != CRYPTOCOP_SESSION_ID_NONE) { + (void)cryptocop_free_session(dev->sid); + } + kfree(dev); + dev = dev_next; + } + + return 0; +} + + +static int cryptocop_ioctl_close_session(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + struct cryptocop_private *dev = filp->private_data; + struct cryptocop_private *prev_dev = NULL; + struct strcop_session_op *sess_op = (struct strcop_session_op *)arg; + struct strcop_session_op sop; + int err; + + DEBUG(printk("cryptocop_ioctl_close_session\n")); + + if (!access_ok(VERIFY_READ, sess_op, sizeof(struct strcop_session_op))) + return -EFAULT; + err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op)); + if (err) return -EFAULT; + + while (dev && (dev->sid != sop.ses_id)) { + prev_dev = dev; + dev = dev->next; + } + if (dev){ + if (prev_dev){ + prev_dev->next = dev->next; + } else { + filp->private_data = dev->next; + } + err = cryptocop_free_session(dev->sid); + if (err) return -EFAULT; + } else { + DEBUG_API(printk("cryptocop_ioctl_close_session: session %lld not found\n", sop.ses_id)); + return -EINVAL; + } + return 0; +} + + +static void ioctl_process_job_callback(struct cryptocop_operation *op, void*cb_data) +{ + struct ioctl_job_cb_ctx *jc = (struct ioctl_job_cb_ctx *)cb_data; + + DEBUG(printk("ioctl_process_job_callback: op=0x%p, cb_data=0x%p\n", op, cb_data)); + + jc->processed = 1; + wake_up(&cryptocop_ioc_process_wq); +} + + +#define CRYPTOCOP_IOCTL_CIPHER_TID (1) +#define CRYPTOCOP_IOCTL_DIGEST_TID (2) +#define CRYPTOCOP_IOCTL_CSUM_TID (3) + +static size_t first_cfg_change_ix(struct strcop_crypto_op *crp_op) +{ + size_t ch_ix = 0; + + if (crp_op->do_cipher) ch_ix = crp_op->cipher_start; + if (crp_op->do_digest && (crp_op->digest_start < ch_ix)) ch_ix = crp_op->digest_start; + if (crp_op->do_csum && (crp_op->csum_start < ch_ix)) ch_ix = crp_op->csum_start; + + DEBUG(printk("first_cfg_change_ix: ix=%d\n", ch_ix)); + return ch_ix; +} + + +static size_t next_cfg_change_ix(struct strcop_crypto_op *crp_op, size_t ix) +{ + size_t ch_ix = INT_MAX; + size_t tmp_ix = 0; + + if (crp_op->do_cipher && ((crp_op->cipher_start + crp_op->cipher_len) > ix)){ + if (crp_op->cipher_start > ix) { + ch_ix = crp_op->cipher_start; + } else { + ch_ix = crp_op->cipher_start + crp_op->cipher_len; + } + } + if (crp_op->do_digest && ((crp_op->digest_start + crp_op->digest_len) > ix)){ + if (crp_op->digest_start > ix) { + tmp_ix = crp_op->digest_start; + } else { + tmp_ix = crp_op->digest_start + crp_op->digest_len; + } + if (tmp_ix < ch_ix) ch_ix = tmp_ix; + } + if (crp_op->do_csum && ((crp_op->csum_start + crp_op->csum_len) > ix)){ + if (crp_op->csum_start > ix) { + tmp_ix = crp_op->csum_start; + } else { + tmp_ix = crp_op->csum_start + crp_op->csum_len; + } + if (tmp_ix < ch_ix) ch_ix = tmp_ix; + } + if (ch_ix == INT_MAX) ch_ix = ix; + DEBUG(printk("next_cfg_change_ix prev ix=%d, next ix=%d\n", ix, ch_ix)); + return ch_ix; +} + + +/* Map map_length bytes from the pages starting on *pageix and *pageoffset to iovecs starting on *iovix. + * Return -1 for ok, 0 for fail. */ +static int map_pages_to_iovec(struct iovec *iov, int iovlen, int *iovix, struct page **pages, int nopages, int *pageix, int *pageoffset, int map_length ) +{ + int tmplen; + + assert(iov != NULL); + assert(iovix != NULL); + assert(pages != NULL); + assert(pageix != NULL); + assert(pageoffset != NULL); + + DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset)); + + while (map_length > 0){ + DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset)); + if (*iovix >= iovlen){ + DEBUG_API(printk("map_page_to_iovec: *iovix=%d >= iovlen=%d\n", *iovix, iovlen)); + return 0; + } + if (*pageix >= nopages){ + DEBUG_API(printk("map_page_to_iovec: *pageix=%d >= nopages=%d\n", *pageix, nopages)); + return 0; + } + iov[*iovix].iov_base = (unsigned char*)page_address(pages[*pageix]) + *pageoffset; + tmplen = PAGE_SIZE - *pageoffset; + if (tmplen < map_length){ + (*pageoffset) = 0; + (*pageix)++; + } else { + tmplen = map_length; + (*pageoffset) += map_length; + } + DEBUG(printk("mapping %d bytes from page %d (or %d) to iovec %d\n", tmplen, *pageix, *pageix-1, *iovix)); + iov[*iovix].iov_len = tmplen; + map_length -= tmplen; + (*iovix)++; + } + DEBUG(printk("map_page_to_iovec, exit, *iovix=%d\n", *iovix)); + return -1; +} + + + +static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) +{ + int i; + struct cryptocop_private *dev = filp->private_data; + struct strcop_crypto_op *crp_oper = (struct strcop_crypto_op *)arg; + struct strcop_crypto_op oper = {0}; + int err = 0; + struct cryptocop_operation *cop = NULL; + + struct ioctl_job_cb_ctx *jc = NULL; + + struct page **inpages = NULL; + struct page **outpages = NULL; + int noinpages = 0; + int nooutpages = 0; + + struct cryptocop_desc descs[5]; /* Max 5 descriptors are needed, there are three transforms that + * can get connected/disconnected on different places in the indata. */ + struct cryptocop_desc_cfg dcfgs[5*3]; + int desc_ix = 0; + int dcfg_ix = 0; + struct cryptocop_tfrm_cfg ciph_tcfg = {0}; + struct cryptocop_tfrm_cfg digest_tcfg = {0}; + struct cryptocop_tfrm_cfg csum_tcfg = {0}; + + unsigned char *digest_result = NULL; + int digest_length = 0; + int cblocklen = 0; + unsigned char csum_result[CSUM_BLOCK_LENGTH]; + struct cryptocop_session *sess; + + int iovlen = 0; + int iovix = 0; + int pageix = 0; + int pageoffset = 0; + + size_t prev_ix = 0; + size_t next_ix; + + int cipher_active, digest_active, csum_active; + int end_digest, end_csum; + int digest_done = 0; + int cipher_done = 0; + int csum_done = 0; + + DEBUG(printk("cryptocop_ioctl_process\n")); + + if (!access_ok(VERIFY_WRITE, crp_oper, sizeof(struct strcop_crypto_op))){ + DEBUG_API(printk("cryptocop_ioctl_process: !access_ok crp_oper!\n")); + return -EFAULT; + } + if (copy_from_user(&oper, crp_oper, sizeof(struct strcop_crypto_op))) { + DEBUG_API(printk("cryptocop_ioctl_process: copy_from_user\n")); + return -EFAULT; + } + DEBUG(print_strcop_crypto_op(&oper)); + + while (dev && dev->sid != oper.ses_id) dev = dev->next; + if (!dev){ + DEBUG_API(printk("cryptocop_ioctl_process: session %lld not found\n", oper.ses_id)); + return -EINVAL; + } + + /* Check buffers. */ + if (((oper.indata + oper.inlen) < oper.indata) || ((oper.cipher_outdata + oper.cipher_outlen) < oper.cipher_outdata)){ + DEBUG_API(printk("cryptocop_ioctl_process: user buffers wrapped around, bad user!\n")); + return -EINVAL; + } + + if (!access_ok(VERIFY_WRITE, oper.cipher_outdata, oper.cipher_outlen)){ + DEBUG_API(printk("cryptocop_ioctl_process: !access_ok out data!\n")); + return -EFAULT; + } + if (!access_ok(VERIFY_READ, oper.indata, oper.inlen)){ + DEBUG_API(printk("cryptocop_ioctl_process: !access_ok in data!\n")); + return -EFAULT; + } + + cop = kmalloc(sizeof(struct cryptocop_operation), GFP_KERNEL); + if (!cop) { + DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n")); + return -ENOMEM; + } + jc = kmalloc(sizeof(struct ioctl_job_cb_ctx), GFP_KERNEL); + if (!jc) { + DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n")); + err = -ENOMEM; + goto error_cleanup; + } + jc->processed = 0; + + cop->cb_data = jc; + cop->cb = ioctl_process_job_callback; + cop->operation_status = 0; + cop->use_dmalists = 0; + cop->in_interrupt = 0; + cop->fast_callback = 0; + cop->tfrm_op.tfrm_cfg = NULL; + cop->tfrm_op.desc = NULL; + cop->tfrm_op.indata = NULL; + cop->tfrm_op.incount = 0; + cop->tfrm_op.inlen = 0; + cop->tfrm_op.outdata = NULL; + cop->tfrm_op.outcount = 0; + cop->tfrm_op.outlen = 0; + + sess = get_session(oper.ses_id); + if (!sess){ + DEBUG_API(printk("cryptocop_ioctl_process: bad session id.\n")); + kfree(cop); + kfree(jc); + return -EINVAL; + } + + if (oper.do_cipher) { + unsigned int cipher_outlen = 0; + struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_CIPHER_TID); + if (!tc) { + DEBUG_API(printk("cryptocop_ioctl_process: no cipher transform in session.\n")); + err = -EINVAL; + goto error_cleanup; + } + ciph_tcfg.tid = CRYPTOCOP_IOCTL_CIPHER_TID; + ciph_tcfg.inject_ix = 0; + ciph_tcfg.flags = 0; + if ((oper.cipher_start < 0) || (oper.cipher_len <= 0) || (oper.cipher_start > oper.inlen) || ((oper.cipher_start + oper.cipher_len) > oper.inlen)){ + DEBUG_API(printk("cryptocop_ioctl_process: bad cipher length\n")); + kfree(cop); + kfree(jc); + return -EINVAL; + } + cblocklen = tc->init.alg == cryptocop_alg_aes ? AES_BLOCK_LENGTH : DES_BLOCK_LENGTH; + if (oper.cipher_len % cblocklen) { + kfree(cop); + kfree(jc); + DEBUG_API(printk("cryptocop_ioctl_process: cipher inlength not multiple of block length.\n")); + return -EINVAL; + } + cipher_outlen = oper.cipher_len; + if (tc->init.cipher_mode == cryptocop_cipher_mode_cbc){ + if (oper.cipher_explicit) { + ciph_tcfg.flags |= CRYPTOCOP_EXPLICIT_IV; + memcpy(ciph_tcfg.iv, oper.cipher_iv, cblocklen); + } else { + cipher_outlen = oper.cipher_len - cblocklen; + } + } else { + if (oper.cipher_explicit){ + kfree(cop); + kfree(jc); + DEBUG_API(printk("cryptocop_ioctl_process: explicit_iv when not CBC mode\n")); + return -EINVAL; + } + } + if (oper.cipher_outlen != cipher_outlen) { + kfree(cop); + kfree(jc); + DEBUG_API(printk("cryptocop_ioctl_process: cipher_outlen incorrect, should be %d not %d.\n", cipher_outlen, oper.cipher_outlen)); + return -EINVAL; + } + + if (oper.decrypt){ + ciph_tcfg.flags |= CRYPTOCOP_DECRYPT; + } else { + ciph_tcfg.flags |= CRYPTOCOP_ENCRYPT; + } + ciph_tcfg.next = cop->tfrm_op.tfrm_cfg; + cop->tfrm_op.tfrm_cfg = &ciph_tcfg; + } + if (oper.do_digest){ + struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_DIGEST_TID); + if (!tc) { + DEBUG_API(printk("cryptocop_ioctl_process: no digest transform in session.\n")); + err = -EINVAL; + goto error_cleanup; + } + digest_length = tc->init.alg == cryptocop_alg_md5 ? 16 : 20; + digest_result = kmalloc(digest_length, GFP_KERNEL); + if (!digest_result) { + DEBUG_API(printk("cryptocop_ioctl_process: kmalloc digest_result\n")); + err = -EINVAL; + goto error_cleanup; + } + DEBUG(memset(digest_result, 0xff, digest_length)); + + digest_tcfg.tid = CRYPTOCOP_IOCTL_DIGEST_TID; + digest_tcfg.inject_ix = 0; + ciph_tcfg.inject_ix += digest_length; + if ((oper.digest_start < 0) || (oper.digest_len <= 0) || (oper.digest_start > oper.inlen) || ((oper.digest_start + oper.digest_len) > oper.inlen)){ + DEBUG_API(printk("cryptocop_ioctl_process: bad digest length\n")); + err = -EINVAL; + goto error_cleanup; + } + + digest_tcfg.next = cop->tfrm_op.tfrm_cfg; + cop->tfrm_op.tfrm_cfg = &digest_tcfg; + } + if (oper.do_csum){ + csum_tcfg.tid = CRYPTOCOP_IOCTL_CSUM_TID; + csum_tcfg.inject_ix = digest_length; + ciph_tcfg.inject_ix += 2; + + if ((oper.csum_start < 0) || (oper.csum_len <= 0) || (oper.csum_start > oper.inlen) || ((oper.csum_start + oper.csum_len) > oper.inlen)){ + DEBUG_API(printk("cryptocop_ioctl_process: bad csum length\n")); + kfree(cop); + kfree(jc); + return -EINVAL; + } + + csum_tcfg.next = cop->tfrm_op.tfrm_cfg; + cop->tfrm_op.tfrm_cfg = &csum_tcfg; + } + + prev_ix = first_cfg_change_ix(&oper); + if (prev_ix > oper.inlen) { + DEBUG_API(printk("cryptocop_ioctl_process: length mismatch\n")); + nooutpages = noinpages = 0; + err = -EINVAL; + goto error_cleanup; + } + DEBUG(printk("cryptocop_ioctl_process: inlen=%d, cipher_outlen=%d\n", oper.inlen, oper.cipher_outlen)); + + /* Map user pages for in and out data of the operation. */ + noinpages = (((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK) + oper.inlen - 1 - prev_ix + ~PAGE_MASK) >> PAGE_SHIFT; + DEBUG(printk("cryptocop_ioctl_process: noinpages=%d\n", noinpages)); + inpages = kmalloc(noinpages * sizeof(struct page*), GFP_KERNEL); + if (!inpages){ + DEBUG_API(printk("cryptocop_ioctl_process: kmalloc inpages\n")); + nooutpages = noinpages = 0; + err = -ENOMEM; + goto error_cleanup; + } + if (oper.do_cipher){ + nooutpages = (((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) + oper.cipher_outlen - 1 + ~PAGE_MASK) >> PAGE_SHIFT; + DEBUG(printk("cryptocop_ioctl_process: nooutpages=%d\n", nooutpages)); + outpages = kmalloc(nooutpages * sizeof(struct page*), GFP_KERNEL); + if (!outpages){ + DEBUG_API(printk("cryptocop_ioctl_process: kmalloc outpages\n")); + nooutpages = noinpages = 0; + err = -ENOMEM; + goto error_cleanup; + } + } + + /* Acquire the mm page semaphore. */ + down_read(¤t->mm->mmap_sem); + + err = get_user_pages(current, + current->mm, + (unsigned long int)(oper.indata + prev_ix), + noinpages, + 0, /* read access only for in data */ + 0, /* no force */ + inpages, + NULL); + + if (err < 0) { + up_read(¤t->mm->mmap_sem); + nooutpages = noinpages = 0; + DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages indata\n")); + goto error_cleanup; + } + noinpages = err; + if (oper.do_cipher){ + err = get_user_pages(current, + current->mm, + (unsigned long int)oper.cipher_outdata, + nooutpages, + 1, /* write access for out data */ + 0, /* no force */ + outpages, + NULL); + up_read(¤t->mm->mmap_sem); + if (err < 0) { + nooutpages = 0; + DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages outdata\n")); + goto error_cleanup; + } + nooutpages = err; + } else { + up_read(¤t->mm->mmap_sem); + } + + /* Add 6 to nooutpages to make room for possibly inserted buffers for storing digest and + * csum output and splits when units are (dis-)connected. */ + cop->tfrm_op.indata = kmalloc((noinpages) * sizeof(struct iovec), GFP_KERNEL); + cop->tfrm_op.outdata = kmalloc((6 + nooutpages) * sizeof(struct iovec), GFP_KERNEL); + if (!cop->tfrm_op.indata || !cop->tfrm_op.outdata) { + DEBUG_API(printk("cryptocop_ioctl_process: kmalloc iovecs\n")); + err = -ENOMEM; + goto error_cleanup; + } + + cop->tfrm_op.inlen = oper.inlen - prev_ix; + cop->tfrm_op.outlen = 0; + if (oper.do_cipher) cop->tfrm_op.outlen += oper.cipher_outlen; + if (oper.do_digest) cop->tfrm_op.outlen += digest_length; + if (oper.do_csum) cop->tfrm_op.outlen += 2; + + /* Setup the in iovecs. */ + cop->tfrm_op.incount = noinpages; + if (noinpages > 1){ + size_t tmplen = cop->tfrm_op.inlen; + + cop->tfrm_op.indata[0].iov_len = PAGE_SIZE - ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); + cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); + tmplen -= cop->tfrm_op.indata[0].iov_len; + for (i = 1; itfrm_op.indata[i].iov_len = tmplen < PAGE_SIZE ? tmplen : PAGE_SIZE; + cop->tfrm_op.indata[i].iov_base = (unsigned char*)page_address(inpages[i]); + tmplen -= PAGE_SIZE; + } + } else { + cop->tfrm_op.indata[0].iov_len = oper.inlen - prev_ix; + cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); + } + + iovlen = nooutpages + 6; + pageoffset = oper.do_cipher ? ((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) : 0; + + next_ix = next_cfg_change_ix(&oper, prev_ix); + if (prev_ix == next_ix){ + DEBUG_API(printk("cryptocop_ioctl_process: length configuration broken.\n")); + err = -EINVAL; /* This should be impossible barring bugs. */ + goto error_cleanup; + } + while (prev_ix != next_ix){ + end_digest = end_csum = cipher_active = digest_active = csum_active = 0; + descs[desc_ix].cfg = NULL; + descs[desc_ix].length = next_ix - prev_ix; + + if (oper.do_cipher && (oper.cipher_start < next_ix) && (prev_ix < (oper.cipher_start + oper.cipher_len))) { + dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CIPHER_TID; + dcfgs[dcfg_ix].src = cryptocop_source_dma; + cipher_active = 1; + + if (next_ix == (oper.cipher_start + oper.cipher_len)){ + cipher_done = 1; + dcfgs[dcfg_ix].last = 1; + } else { + dcfgs[dcfg_ix].last = 0; + } + dcfgs[dcfg_ix].next = descs[desc_ix].cfg; + descs[desc_ix].cfg = &dcfgs[dcfg_ix]; + ++dcfg_ix; + } + if (oper.do_digest && (oper.digest_start < next_ix) && (prev_ix < (oper.digest_start + oper.digest_len))) { + digest_active = 1; + dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_DIGEST_TID; + dcfgs[dcfg_ix].src = cryptocop_source_dma; + if (next_ix == (oper.digest_start + oper.digest_len)){ + assert(!digest_done); + digest_done = 1; + dcfgs[dcfg_ix].last = 1; + } else { + dcfgs[dcfg_ix].last = 0; + } + dcfgs[dcfg_ix].next = descs[desc_ix].cfg; + descs[desc_ix].cfg = &dcfgs[dcfg_ix]; + ++dcfg_ix; + } + if (oper.do_csum && (oper.csum_start < next_ix) && (prev_ix < (oper.csum_start + oper.csum_len))){ + csum_active = 1; + dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CSUM_TID; + dcfgs[dcfg_ix].src = cryptocop_source_dma; + if (next_ix == (oper.csum_start + oper.csum_len)){ + csum_done = 1; + dcfgs[dcfg_ix].last = 1; + } else { + dcfgs[dcfg_ix].last = 0; + } + dcfgs[dcfg_ix].next = descs[desc_ix].cfg; + descs[desc_ix].cfg = &dcfgs[dcfg_ix]; + ++dcfg_ix; + } + if (!descs[desc_ix].cfg){ + DEBUG_API(printk("cryptocop_ioctl_process: data segment %d (%d to %d) had no active transforms\n", desc_ix, prev_ix, next_ix)); + err = -EINVAL; + goto error_cleanup; + } + descs[desc_ix].next = &(descs[desc_ix]) + 1; + ++desc_ix; + prev_ix = next_ix; + next_ix = next_cfg_change_ix(&oper, prev_ix); + } + if (desc_ix > 0){ + descs[desc_ix-1].next = NULL; + } else { + descs[0].next = NULL; + } + if (oper.do_digest) { + DEBUG(printk("cryptocop_ioctl_process: mapping %d byte digest output to iovec %d\n", digest_length, iovix)); + /* Add outdata iovec, length == */ + cop->tfrm_op.outdata[iovix].iov_base = digest_result; + cop->tfrm_op.outdata[iovix].iov_len = digest_length; + ++iovix; + } + if (oper.do_csum) { + /* Add outdata iovec, length == 2, the length of csum. */ + DEBUG(printk("cryptocop_ioctl_process: mapping 2 byte csum output to iovec %d\n", iovix)); + /* Add outdata iovec, length == */ + cop->tfrm_op.outdata[iovix].iov_base = csum_result; + cop->tfrm_op.outdata[iovix].iov_len = 2; + ++iovix; + } + if (oper.do_cipher) { + if (!map_pages_to_iovec(cop->tfrm_op.outdata, iovlen, &iovix, outpages, nooutpages, &pageix, &pageoffset, oper.cipher_outlen)){ + DEBUG_API(printk("cryptocop_ioctl_process: failed to map pages to iovec.\n")); + err = -ENOSYS; /* This should be impossible barring bugs. */ + goto error_cleanup; + } + } + DEBUG(printk("cryptocop_ioctl_process: setting cop->tfrm_op.outcount %d\n", iovix)); + cop->tfrm_op.outcount = iovix; + assert(iovix <= (nooutpages + 6)); + + cop->sid = oper.ses_id; + cop->tfrm_op.desc = &descs[0]; + + DEBUG(printk("cryptocop_ioctl_process: inserting job, cb_data=0x%p\n", cop->cb_data)); + + if ((err = cryptocop_job_queue_insert_user_job(cop)) != 0) { + DEBUG_API(printk("cryptocop_ioctl_process: insert job %d\n", err)); + err = -EINVAL; + goto error_cleanup; + } + + DEBUG(printk("cryptocop_ioctl_process: begin wait for result\n")); + + wait_event(cryptocop_ioc_process_wq, (jc->processed != 0)); + DEBUG(printk("cryptocop_ioctl_process: end wait for result\n")); + if (!jc->processed){ + printk(KERN_WARNING "cryptocop_ioctl_process: job not processed at completion\n"); + err = -EIO; + goto error_cleanup; + } + + /* Job process done. Cipher output should already be correct in job so no post processing of outdata. */ + DEBUG(printk("cryptocop_ioctl_process: operation_status = %d\n", cop->operation_status)); + if (cop->operation_status == 0){ + if (oper.do_digest){ + DEBUG(printk("cryptocop_ioctl_process: copy %d bytes digest to user\n", digest_length)); + err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, digest), digest_result, digest_length); + if (0 != err){ + DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, digest length %d, err %d\n", digest_length, err)); + err = -EFAULT; + goto error_cleanup; + } + } + if (oper.do_csum){ + DEBUG(printk("cryptocop_ioctl_process: copy 2 bytes checksum to user\n")); + err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, csum), csum_result, 2); + if (0 != err){ + DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, csum, err %d\n", err)); + err = -EFAULT; + goto error_cleanup; + } + } + err = 0; + } else { + DEBUG(printk("cryptocop_ioctl_process: returning err = operation_status = %d\n", cop->operation_status)); + err = cop->operation_status; + } + + error_cleanup: + /* Release page caches. */ + for (i = 0; i < noinpages; i++){ + put_page(inpages[i]); + } + for (i = 0; i < nooutpages; i++){ + int spdl_err; + /* Mark output pages dirty. */ + spdl_err = set_page_dirty_lock(outpages[i]); + DEBUG(if (spdl_err < 0)printk("cryptocop_ioctl_process: set_page_dirty_lock returned %d\n", spdl_err)); + } + for (i = 0; i < nooutpages; i++){ + put_page(outpages[i]); + } + + kfree(digest_result); + kfree(inpages); + kfree(outpages); + if (cop){ + kfree(cop->tfrm_op.indata); + kfree(cop->tfrm_op.outdata); + kfree(cop); + } + kfree(jc); + + DEBUG(print_lock_status()); + + return err; +} + + +static int cryptocop_ioctl_create_session(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) +{ + cryptocop_session_id sid; + int err; + struct cryptocop_private *dev; + struct strcop_session_op *sess_op = (struct strcop_session_op *)arg; + struct strcop_session_op sop; + struct cryptocop_transform_init *tis = NULL; + struct cryptocop_transform_init ti_cipher = {0}; + struct cryptocop_transform_init ti_digest = {0}; + struct cryptocop_transform_init ti_csum = {0}; + + if (!access_ok(VERIFY_WRITE, sess_op, sizeof(struct strcop_session_op))) + return -EFAULT; + err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op)); + if (err) return -EFAULT; + if (sop.cipher != cryptocop_cipher_none) { + if (!access_ok(VERIFY_READ, sop.key, sop.keylen)) return -EFAULT; + } + DEBUG(printk("cryptocop_ioctl_create_session, sess_op:\n")); + + DEBUG(printk("\tcipher:%d\n" + "\tcipher_mode:%d\n" + "\tdigest:%d\n" + "\tcsum:%d\n", + (int)sop.cipher, + (int)sop.cmode, + (int)sop.digest, + (int)sop.csum)); + + if (sop.cipher != cryptocop_cipher_none){ + /* Init the cipher. */ + switch (sop.cipher){ + case cryptocop_cipher_des: + ti_cipher.alg = cryptocop_alg_des; + break; + case cryptocop_cipher_3des: + ti_cipher.alg = cryptocop_alg_3des; + break; + case cryptocop_cipher_aes: + ti_cipher.alg = cryptocop_alg_aes; + break; + default: + DEBUG_API(printk("create session, bad cipher algorithm %d\n", sop.cipher)); + return -EINVAL; + }; + DEBUG(printk("setting cipher transform %d\n", ti_cipher.alg)); + copy_from_user(ti_cipher.key, sop.key, sop.keylen/8); + ti_cipher.keylen = sop.keylen; + switch (sop.cmode){ + case cryptocop_cipher_mode_cbc: + case cryptocop_cipher_mode_ecb: + ti_cipher.cipher_mode = sop.cmode; + break; + default: + DEBUG_API(printk("create session, bad cipher mode %d\n", sop.cmode)); + return -EINVAL; + } + DEBUG(printk("cryptocop_ioctl_create_session: setting CBC mode %d\n", ti_cipher.cipher_mode)); + switch (sop.des3_mode){ + case cryptocop_3des_eee: + case cryptocop_3des_eed: + case cryptocop_3des_ede: + case cryptocop_3des_edd: + case cryptocop_3des_dee: + case cryptocop_3des_ded: + case cryptocop_3des_dde: + case cryptocop_3des_ddd: + ti_cipher.tdes_mode = sop.des3_mode; + break; + default: + DEBUG_API(printk("create session, bad 3DES mode %d\n", sop.des3_mode)); + return -EINVAL; + } + ti_cipher.tid = CRYPTOCOP_IOCTL_CIPHER_TID; + ti_cipher.next = tis; + tis = &ti_cipher; + } /* if (sop.cipher != cryptocop_cipher_none) */ + if (sop.digest != cryptocop_digest_none){ + DEBUG(printk("setting digest transform\n")); + switch (sop.digest){ + case cryptocop_digest_md5: + ti_digest.alg = cryptocop_alg_md5; + break; + case cryptocop_digest_sha1: + ti_digest.alg = cryptocop_alg_sha1; + break; + default: + DEBUG_API(printk("create session, bad digest algorithm %d\n", sop.digest)); + return -EINVAL; + } + ti_digest.tid = CRYPTOCOP_IOCTL_DIGEST_TID; + ti_digest.next = tis; + tis = &ti_digest; + } /* if (sop.digest != cryptocop_digest_none) */ + if (sop.csum != cryptocop_csum_none){ + DEBUG(printk("setting csum transform\n")); + switch (sop.csum){ + case cryptocop_csum_le: + case cryptocop_csum_be: + ti_csum.csum_mode = sop.csum; + break; + default: + DEBUG_API(printk("create session, bad checksum algorithm %d\n", sop.csum)); + return -EINVAL; + } + ti_csum.alg = cryptocop_alg_csum; + ti_csum.tid = CRYPTOCOP_IOCTL_CSUM_TID; + ti_csum.next = tis; + tis = &ti_csum; + } /* (sop.csum != cryptocop_csum_none) */ + dev = kmalloc(sizeof(struct cryptocop_private), GFP_KERNEL); + if (!dev){ + DEBUG_API(printk("create session, alloc dev\n")); + return -ENOMEM; + } + + err = cryptocop_new_session(&sid, tis, GFP_KERNEL); + DEBUG({ if (err) printk("create session, cryptocop_new_session %d\n", err);}); + + if (err) { + kfree(dev); + return err; + } + sess_op->ses_id = sid; + dev->sid = sid; + dev->next = filp->private_data; + filp->private_data = dev; + + return 0; +} + +static long cryptocop_ioctl_unlocked(struct inode *inode, + struct file *filp, unsigned int cmd, unsigned long arg) +{ + int err = 0; + if (_IOC_TYPE(cmd) != ETRAXCRYPTOCOP_IOCTYPE) { + DEBUG_API(printk("cryptocop_ioctl: wrong type\n")); + return -ENOTTY; + } + if (_IOC_NR(cmd) > CRYPTOCOP_IO_MAXNR){ + return -ENOTTY; + } + /* Access check of the argument. Some commands, e.g. create session and process op, + needs additional checks. Those are handled in the command handling functions. */ + if (_IOC_DIR(cmd) & _IOC_READ) + err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd)); + else if (_IOC_DIR(cmd) & _IOC_WRITE) + err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd)); + if (err) return -EFAULT; + + switch (cmd) { + case CRYPTOCOP_IO_CREATE_SESSION: + return cryptocop_ioctl_create_session(inode, filp, cmd, arg); + case CRYPTOCOP_IO_CLOSE_SESSION: + return cryptocop_ioctl_close_session(inode, filp, cmd, arg); + case CRYPTOCOP_IO_PROCESS_OP: + return cryptocop_ioctl_process(inode, filp, cmd, arg); + default: + DEBUG_API(printk("cryptocop_ioctl: unknown command\n")); + return -ENOTTY; + } + return 0; +} + +static long +cryptocop_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + long ret; + + mutex_lock(&cryptocop_mutex); + ret = cryptocop_ioctl_unlocked(file_inode(filp), filp, cmd, arg); + mutex_unlock(&cryptocop_mutex); + + return ret; +} + + +#ifdef LDEBUG +static void print_dma_descriptors(struct cryptocop_int_operation *iop) +{ + struct cryptocop_dma_desc *cdesc_out = iop->cdesc_out; + struct cryptocop_dma_desc *cdesc_in = iop->cdesc_in; + int i; + + printk("print_dma_descriptors start\n"); + + printk("iop:\n"); + printk("\tsid: 0x%lld\n", iop->sid); + + printk("\tcdesc_out: 0x%p\n", iop->cdesc_out); + printk("\tcdesc_in: 0x%p\n", iop->cdesc_in); + printk("\tddesc_out: 0x%p\n", iop->ddesc_out); + printk("\tddesc_in: 0x%p\n", iop->ddesc_in); + + printk("\niop->ctx_out: 0x%p phys: 0x%p\n", &iop->ctx_out, (char*)virt_to_phys(&iop->ctx_out)); + printk("\tnext: 0x%p\n" + "\tsaved_data: 0x%p\n" + "\tsaved_data_buf: 0x%p\n", + iop->ctx_out.next, + iop->ctx_out.saved_data, + iop->ctx_out.saved_data_buf); + + printk("\niop->ctx_in: 0x%p phys: 0x%p\n", &iop->ctx_in, (char*)virt_to_phys(&iop->ctx_in)); + printk("\tnext: 0x%p\n" + "\tsaved_data: 0x%p\n" + "\tsaved_data_buf: 0x%p\n", + iop->ctx_in.next, + iop->ctx_in.saved_data, + iop->ctx_in.saved_data_buf); + + i = 0; + while (cdesc_out) { + dma_descr_data *td; + printk("cdesc_out %d, desc=0x%p\n", i, cdesc_out->dma_descr); + printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_out->dma_descr)); + td = cdesc_out->dma_descr; + printk("\n\tbuf: 0x%p\n" + "\tafter: 0x%p\n" + "\tmd: 0x%04x\n" + "\tnext: 0x%p\n", + td->buf, + td->after, + td->md, + td->next); + printk("flags:\n" + "\twait:\t%d\n" + "\teol:\t%d\n" + "\touteop:\t%d\n" + "\tineop:\t%d\n" + "\tintr:\t%d\n", + td->wait, + td->eol, + td->out_eop, + td->in_eop, + td->intr); + cdesc_out = cdesc_out->next; + i++; + } + i = 0; + while (cdesc_in) { + dma_descr_data *td; + printk("cdesc_in %d, desc=0x%p\n", i, cdesc_in->dma_descr); + printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_in->dma_descr)); + td = cdesc_in->dma_descr; + printk("\n\tbuf: 0x%p\n" + "\tafter: 0x%p\n" + "\tmd: 0x%04x\n" + "\tnext: 0x%p\n", + td->buf, + td->after, + td->md, + td->next); + printk("flags:\n" + "\twait:\t%d\n" + "\teol:\t%d\n" + "\touteop:\t%d\n" + "\tineop:\t%d\n" + "\tintr:\t%d\n", + td->wait, + td->eol, + td->out_eop, + td->in_eop, + td->intr); + cdesc_in = cdesc_in->next; + i++; + } + + printk("print_dma_descriptors end\n"); +} + + +static void print_strcop_crypto_op(struct strcop_crypto_op *cop) +{ + printk("print_strcop_crypto_op, 0x%p\n", cop); + + /* Indata. */ + printk("indata=0x%p\n" + "inlen=%d\n" + "do_cipher=%d\n" + "decrypt=%d\n" + "cipher_explicit=%d\n" + "cipher_start=%d\n" + "cipher_len=%d\n" + "outdata=0x%p\n" + "outlen=%d\n", + cop->indata, + cop->inlen, + cop->do_cipher, + cop->decrypt, + cop->cipher_explicit, + cop->cipher_start, + cop->cipher_len, + cop->cipher_outdata, + cop->cipher_outlen); + + printk("do_digest=%d\n" + "digest_start=%d\n" + "digest_len=%d\n", + cop->do_digest, + cop->digest_start, + cop->digest_len); + + printk("do_csum=%d\n" + "csum_start=%d\n" + "csum_len=%d\n", + cop->do_csum, + cop->csum_start, + cop->csum_len); +} + +static void print_cryptocop_operation(struct cryptocop_operation *cop) +{ + struct cryptocop_desc *d; + struct cryptocop_tfrm_cfg *tc; + struct cryptocop_desc_cfg *dc; + int i; + + printk("print_cryptocop_operation, cop=0x%p\n\n", cop); + printk("sid: %lld\n", cop->sid); + printk("operation_status=%d\n" + "use_dmalists=%d\n" + "in_interrupt=%d\n" + "fast_callback=%d\n", + cop->operation_status, + cop->use_dmalists, + cop->in_interrupt, + cop->fast_callback); + + if (cop->use_dmalists){ + print_user_dma_lists(&cop->list_op); + } else { + printk("cop->tfrm_op\n" + "tfrm_cfg=0x%p\n" + "desc=0x%p\n" + "indata=0x%p\n" + "incount=%d\n" + "inlen=%d\n" + "outdata=0x%p\n" + "outcount=%d\n" + "outlen=%d\n\n", + cop->tfrm_op.tfrm_cfg, + cop->tfrm_op.desc, + cop->tfrm_op.indata, + cop->tfrm_op.incount, + cop->tfrm_op.inlen, + cop->tfrm_op.outdata, + cop->tfrm_op.outcount, + cop->tfrm_op.outlen); + + tc = cop->tfrm_op.tfrm_cfg; + while (tc){ + printk("tfrm_cfg, 0x%p\n" + "tid=%d\n" + "flags=%d\n" + "inject_ix=%d\n" + "next=0x%p\n", + tc, + tc->tid, + tc->flags, + tc->inject_ix, + tc->next); + tc = tc->next; + } + d = cop->tfrm_op.desc; + while (d){ + printk("\n======================desc, 0x%p\n" + "length=%d\n" + "cfg=0x%p\n" + "next=0x%p\n", + d, + d->length, + d->cfg, + d->next); + dc = d->cfg; + while (dc){ + printk("=========desc_cfg, 0x%p\n" + "tid=%d\n" + "src=%d\n" + "last=%d\n" + "next=0x%p\n", + dc, + dc->tid, + dc->src, + dc->last, + dc->next); + dc = dc->next; + } + d = d->next; + } + printk("\n====iniov\n"); + for (i = 0; i < cop->tfrm_op.incount; i++){ + printk("indata[%d]\n" + "base=0x%p\n" + "len=%d\n", + i, + cop->tfrm_op.indata[i].iov_base, + cop->tfrm_op.indata[i].iov_len); + } + printk("\n====outiov\n"); + for (i = 0; i < cop->tfrm_op.outcount; i++){ + printk("outdata[%d]\n" + "base=0x%p\n" + "len=%d\n", + i, + cop->tfrm_op.outdata[i].iov_base, + cop->tfrm_op.outdata[i].iov_len); + } + } + printk("------------end print_cryptocop_operation\n"); +} + + +static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op) +{ + dma_descr_data *dd; + int i; + + printk("print_user_dma_lists, dma_op=0x%p\n", dma_op); + + printk("out_data_buf = 0x%p, phys_to_virt(out_data_buf) = 0x%p\n", dma_op->out_data_buf, phys_to_virt((unsigned long int)dma_op->out_data_buf)); + printk("in_data_buf = 0x%p, phys_to_virt(in_data_buf) = 0x%p\n", dma_op->in_data_buf, phys_to_virt((unsigned long int)dma_op->in_data_buf)); + + printk("##############outlist\n"); + dd = phys_to_virt((unsigned long int)dma_op->outlist); + i = 0; + while (dd != NULL) { + printk("#%d phys_to_virt(desc) 0x%p\n", i, dd); + printk("\n\tbuf: 0x%p\n" + "\tafter: 0x%p\n" + "\tmd: 0x%04x\n" + "\tnext: 0x%p\n", + dd->buf, + dd->after, + dd->md, + dd->next); + printk("flags:\n" + "\twait:\t%d\n" + "\teol:\t%d\n" + "\touteop:\t%d\n" + "\tineop:\t%d\n" + "\tintr:\t%d\n", + dd->wait, + dd->eol, + dd->out_eop, + dd->in_eop, + dd->intr); + if (dd->eol) + dd = NULL; + else + dd = phys_to_virt((unsigned long int)dd->next); + ++i; + } + + printk("##############inlist\n"); + dd = phys_to_virt((unsigned long int)dma_op->inlist); + i = 0; + while (dd != NULL) { + printk("#%d phys_to_virt(desc) 0x%p\n", i, dd); + printk("\n\tbuf: 0x%p\n" + "\tafter: 0x%p\n" + "\tmd: 0x%04x\n" + "\tnext: 0x%p\n", + dd->buf, + dd->after, + dd->md, + dd->next); + printk("flags:\n" + "\twait:\t%d\n" + "\teol:\t%d\n" + "\touteop:\t%d\n" + "\tineop:\t%d\n" + "\tintr:\t%d\n", + dd->wait, + dd->eol, + dd->out_eop, + dd->in_eop, + dd->intr); + if (dd->eol) + dd = NULL; + else + dd = phys_to_virt((unsigned long int)dd->next); + ++i; + } +} + + +static void print_lock_status(void) +{ + printk("**********************print_lock_status\n"); + printk("cryptocop_completed_jobs_lock %d\n", spin_is_locked(&cryptocop_completed_jobs_lock)); + printk("cryptocop_job_queue_lock %d\n", spin_is_locked(&cryptocop_job_queue_lock)); + printk("descr_pool_lock %d\n", spin_is_locked(&descr_pool_lock)); + printk("cryptocop_sessions_lock %d\n", spin_is_locked(cryptocop_sessions_lock)); + printk("running_job_lock %d\n", spin_is_locked(running_job_lock)); + printk("cryptocop_process_lock %d\n", spin_is_locked(cryptocop_process_lock)); +} +#endif /* LDEBUG */ + + +static const char cryptocop_name[] = "ETRAX FS stream co-processor"; + +static int init_stream_coprocessor(void) +{ + int err; + int i; + static int initialized = 0; + + if (initialized) + return 0; + + initialized = 1; + + printk("ETRAX FS stream co-processor driver v0.01, (c) 2003 Axis Communications AB\n"); + + err = register_chrdev(CRYPTOCOP_MAJOR, cryptocop_name, &cryptocop_fops); + if (err < 0) { + printk(KERN_ERR "stream co-processor: could not get major number.\n"); + return err; + } + + err = init_cryptocop(); + if (err) { + (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name); + return err; + } + err = cryptocop_job_queue_init(); + if (err) { + release_cryptocop(); + (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name); + return err; + } + /* Init the descriptor pool. */ + for (i = 0; i < CRYPTOCOP_DESCRIPTOR_POOL_SIZE - 1; i++) { + descr_pool[i].from_pool = 1; + descr_pool[i].next = &descr_pool[i + 1]; + } + descr_pool[i].from_pool = 1; + descr_pool[i].next = NULL; + descr_pool_free_list = &descr_pool[0]; + descr_pool_no_free = CRYPTOCOP_DESCRIPTOR_POOL_SIZE; + + spin_lock_init(&cryptocop_completed_jobs_lock); + spin_lock_init(&cryptocop_job_queue_lock); + spin_lock_init(&descr_pool_lock); + spin_lock_init(&cryptocop_sessions_lock); + spin_lock_init(&running_job_lock); + spin_lock_init(&cryptocop_process_lock); + + cryptocop_sessions = NULL; + next_sid = 1; + + cryptocop_running_job = NULL; + + printk("stream co-processor: init done.\n"); + return 0; +} + +static void __exit exit_stream_coprocessor(void) +{ + release_cryptocop(); + cryptocop_job_queue_close(); +} + +module_init(init_stream_coprocessor); +module_exit(exit_stream_coprocessor); + diff --git a/kernel/arch/cris/arch-v32/drivers/i2c.c b/kernel/arch/cris/arch-v32/drivers/i2c.c new file mode 100644 index 000000000..3b2c82ce8 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/i2c.c @@ -0,0 +1,751 @@ +/*!*************************************************************************** +*! +*! FILE NAME : i2c.c +*! +*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other +*! kernel modules (i2c_writereg/readreg) and from userspace using +*! ioctl()'s +*! +*! Nov 30 1998 Torbjorn Eliasson Initial version. +*! Bjorn Wesen Elinux kernel version. +*! Jan 14 2000 Johan Adolfsson Fixed PB shadow register stuff - +*! don't use PB_I2C if DS1302 uses same bits, +*! use PB. +*| June 23 2003 Pieter Grimmerink Added 'i2c_sendnack'. i2c_readreg now +*| generates nack on last received byte, +*| instead of ack. +*| i2c_getack changed data level while clock +*| was high, causing DS75 to see a stop condition +*! +*! --------------------------------------------------------------------------- +*! +*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN +*! +*!***************************************************************************/ + +/****************** INCLUDE FILES SECTION ***********************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include "i2c.h" + +/****************** I2C DEFINITION SECTION *************************/ + +#define D(x) + +#define I2C_MAJOR 123 /* LOCAL/EXPERIMENTAL */ +static DEFINE_MUTEX(i2c_mutex); +static const char i2c_name[] = "i2c"; + +#define CLOCK_LOW_TIME 8 +#define CLOCK_HIGH_TIME 8 +#define START_CONDITION_HOLD_TIME 8 +#define STOP_CONDITION_HOLD_TIME 8 +#define ENABLE_OUTPUT 0x01 +#define ENABLE_INPUT 0x00 +#define I2C_CLOCK_HIGH 1 +#define I2C_CLOCK_LOW 0 +#define I2C_DATA_HIGH 1 +#define I2C_DATA_LOW 0 + +#define i2c_enable() +#define i2c_disable() + +/* enable or disable output-enable, to select output or input on the i2c bus */ + +#define i2c_dir_out() crisv32_io_set_dir(&cris_i2c_data, crisv32_io_dir_out) +#define i2c_dir_in() crisv32_io_set_dir(&cris_i2c_data, crisv32_io_dir_in) + +/* control the i2c clock and data signals */ + +#define i2c_clk(x) crisv32_io_set(&cris_i2c_clk, x) +#define i2c_data(x) crisv32_io_set(&cris_i2c_data, x) + +/* read a bit from the i2c interface */ + +#define i2c_getbit() crisv32_io_rd(&cris_i2c_data) + +#define i2c_delay(usecs) udelay(usecs) + +static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */ + +/****************** VARIABLE SECTION ************************************/ + +static struct crisv32_iopin cris_i2c_clk; +static struct crisv32_iopin cris_i2c_data; + +/****************** FUNCTION DEFINITION SECTION *************************/ + + +/* generate i2c start condition */ + +void +i2c_start(void) +{ + /* + * SCL=1 SDA=1 + */ + i2c_dir_out(); + i2c_delay(CLOCK_HIGH_TIME/6); + i2c_data(I2C_DATA_HIGH); + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + /* + * SCL=1 SDA=0 + */ + i2c_data(I2C_DATA_LOW); + i2c_delay(START_CONDITION_HOLD_TIME); + /* + * SCL=0 SDA=0 + */ + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME); +} + +/* generate i2c stop condition */ + +void +i2c_stop(void) +{ + i2c_dir_out(); + + /* + * SCL=0 SDA=0 + */ + i2c_clk(I2C_CLOCK_LOW); + i2c_data(I2C_DATA_LOW); + i2c_delay(CLOCK_LOW_TIME*2); + /* + * SCL=1 SDA=0 + */ + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME*2); + /* + * SCL=1 SDA=1 + */ + i2c_data(I2C_DATA_HIGH); + i2c_delay(STOP_CONDITION_HOLD_TIME); + + i2c_dir_in(); +} + +/* write a byte to the i2c interface */ + +void +i2c_outbyte(unsigned char x) +{ + int i; + + i2c_dir_out(); + + for (i = 0; i < 8; i++) { + if (x & 0x80) { + i2c_data(I2C_DATA_HIGH); + } else { + i2c_data(I2C_DATA_LOW); + } + + i2c_delay(CLOCK_LOW_TIME/2); + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME/2); + x <<= 1; + } + i2c_data(I2C_DATA_LOW); + i2c_delay(CLOCK_LOW_TIME/2); + + /* + * enable input + */ + i2c_dir_in(); +} + +/* read a byte from the i2c interface */ + +unsigned char +i2c_inbyte(void) +{ + unsigned char aBitByte = 0; + int i; + + /* Switch off I2C to get bit */ + i2c_disable(); + i2c_dir_in(); + i2c_delay(CLOCK_HIGH_TIME/2); + + /* Get bit */ + aBitByte |= i2c_getbit(); + + /* Enable I2C */ + i2c_enable(); + i2c_delay(CLOCK_LOW_TIME/2); + + for (i = 1; i < 8; i++) { + aBitByte <<= 1; + /* Clock pulse */ + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME); + + /* Switch off I2C to get bit */ + i2c_disable(); + i2c_dir_in(); + i2c_delay(CLOCK_HIGH_TIME/2); + + /* Get bit */ + aBitByte |= i2c_getbit(); + + /* Enable I2C */ + i2c_enable(); + i2c_delay(CLOCK_LOW_TIME/2); + } + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + + /* + * we leave the clock low, getbyte is usually followed + * by sendack/nack, they assume the clock to be low + */ + i2c_clk(I2C_CLOCK_LOW); + return aBitByte; +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_getack +*# +*# DESCRIPTION : checks if ack was received from ic2 +*# +*#--------------------------------------------------------------------------*/ + +int +i2c_getack(void) +{ + int ack = 1; + /* + * enable output + */ + i2c_dir_out(); + /* + * Release data bus by setting + * data high + */ + i2c_data(I2C_DATA_HIGH); + /* + * enable input + */ + i2c_dir_in(); + i2c_delay(CLOCK_HIGH_TIME/4); + /* + * generate ACK clock pulse + */ + i2c_clk(I2C_CLOCK_HIGH); +#if 0 + /* + * Use PORT PB instead of I2C + * for input. (I2C not working) + */ + i2c_clk(1); + i2c_data(1); + /* + * switch off I2C + */ + i2c_data(1); + i2c_disable(); + i2c_dir_in(); +#endif + + /* + * now wait for ack + */ + i2c_delay(CLOCK_HIGH_TIME/2); + /* + * check for ack + */ + if (i2c_getbit()) + ack = 0; + i2c_delay(CLOCK_HIGH_TIME/2); + if (!ack) { + if (!i2c_getbit()) /* receiver pulld SDA low */ + ack = 1; + i2c_delay(CLOCK_HIGH_TIME/2); + } + + /* + * our clock is high now, make sure data is low + * before we enable our output. If we keep data high + * and enable output, we would generate a stop condition. + */ +#if 0 + i2c_data(I2C_DATA_LOW); + + /* + * end clock pulse + */ + i2c_enable(); + i2c_dir_out(); +#endif + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_HIGH_TIME/4); + /* + * enable output + */ + i2c_dir_out(); + /* + * remove ACK clock pulse + */ + i2c_data(I2C_DATA_HIGH); + i2c_delay(CLOCK_LOW_TIME/2); + return ack; +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: I2C::sendAck +*# +*# DESCRIPTION : Send ACK on received data +*# +*#--------------------------------------------------------------------------*/ +void +i2c_sendack(void) +{ + /* + * enable output + */ + i2c_delay(CLOCK_LOW_TIME); + i2c_dir_out(); + /* + * set ack pulse high + */ + i2c_data(I2C_DATA_LOW); + /* + * generate clock pulse + */ + i2c_delay(CLOCK_HIGH_TIME/6); + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME/6); + /* + * reset data out + */ + i2c_data(I2C_DATA_HIGH); + i2c_delay(CLOCK_LOW_TIME); + + i2c_dir_in(); +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_sendnack +*# +*# DESCRIPTION : Sends NACK on received data +*# +*#--------------------------------------------------------------------------*/ +void +i2c_sendnack(void) +{ + /* + * enable output + */ + i2c_delay(CLOCK_LOW_TIME); + i2c_dir_out(); + /* + * set data high + */ + i2c_data(I2C_DATA_HIGH); + /* + * generate clock pulse + */ + i2c_delay(CLOCK_HIGH_TIME/6); + i2c_clk(I2C_CLOCK_HIGH); + i2c_delay(CLOCK_HIGH_TIME); + i2c_clk(I2C_CLOCK_LOW); + i2c_delay(CLOCK_LOW_TIME); + + i2c_dir_in(); +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_write +*# +*# DESCRIPTION : Writes a value to an I2C device +*# +*#--------------------------------------------------------------------------*/ +int +i2c_write(unsigned char theSlave, void *data, size_t nbytes) +{ + int error, cntr = 3; + unsigned char bytes_wrote = 0; + unsigned char value; + unsigned long flags; + + spin_lock_irqsave(&i2c_lock, flags); + + do { + error = 0; + + i2c_start(); + /* + * send slave address + */ + i2c_outbyte((theSlave & 0xfe)); + /* + * wait for ack + */ + if (!i2c_getack()) + error = 1; + /* + * send data + */ + for (bytes_wrote = 0; bytes_wrote < nbytes; bytes_wrote++) { + memcpy(&value, data + bytes_wrote, sizeof value); + i2c_outbyte(value); + /* + * now it's time to wait for ack + */ + if (!i2c_getack()) + error |= 4; + } + /* + * end byte stream + */ + i2c_stop(); + + } while (error && cntr--); + + i2c_delay(CLOCK_LOW_TIME); + + spin_unlock_irqrestore(&i2c_lock, flags); + + return -error; +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_read +*# +*# DESCRIPTION : Reads a value from an I2C device +*# +*#--------------------------------------------------------------------------*/ +int +i2c_read(unsigned char theSlave, void *data, size_t nbytes) +{ + unsigned char b = 0; + unsigned char bytes_read = 0; + int error, cntr = 3; + unsigned long flags; + + spin_lock_irqsave(&i2c_lock, flags); + + do { + error = 0; + memset(data, 0, nbytes); + /* + * generate start condition + */ + i2c_start(); + /* + * send slave address + */ + i2c_outbyte((theSlave | 0x01)); + /* + * wait for ack + */ + if (!i2c_getack()) + error = 1; + /* + * fetch data + */ + for (bytes_read = 0; bytes_read < nbytes; bytes_read++) { + b = i2c_inbyte(); + memcpy(data + bytes_read, &b, sizeof b); + + if (bytes_read < (nbytes - 1)) + i2c_sendack(); + } + /* + * last received byte needs to be nacked + * instead of acked + */ + i2c_sendnack(); + /* + * end sequence + */ + i2c_stop(); + } while (error && cntr--); + + spin_unlock_irqrestore(&i2c_lock, flags); + + return -error; +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_writereg +*# +*# DESCRIPTION : Writes a value to an I2C device +*# +*#--------------------------------------------------------------------------*/ +int +i2c_writereg(unsigned char theSlave, unsigned char theReg, + unsigned char theValue) +{ + int error, cntr = 3; + unsigned long flags; + + spin_lock_irqsave(&i2c_lock, flags); + + do { + error = 0; + + i2c_start(); + /* + * send slave address + */ + i2c_outbyte((theSlave & 0xfe)); + /* + * wait for ack + */ + if(!i2c_getack()) + error = 1; + /* + * now select register + */ + i2c_dir_out(); + i2c_outbyte(theReg); + /* + * now it's time to wait for ack + */ + if(!i2c_getack()) + error |= 2; + /* + * send register register data + */ + i2c_outbyte(theValue); + /* + * now it's time to wait for ack + */ + if(!i2c_getack()) + error |= 4; + /* + * end byte stream + */ + i2c_stop(); + } while(error && cntr--); + + i2c_delay(CLOCK_LOW_TIME); + + spin_unlock_irqrestore(&i2c_lock, flags); + + return -error; +} + +/*#--------------------------------------------------------------------------- +*# +*# FUNCTION NAME: i2c_readreg +*# +*# DESCRIPTION : Reads a value from the decoder registers. +*# +*#--------------------------------------------------------------------------*/ +unsigned char +i2c_readreg(unsigned char theSlave, unsigned char theReg) +{ + unsigned char b = 0; + int error, cntr = 3; + unsigned long flags; + + spin_lock_irqsave(&i2c_lock, flags); + + do { + error = 0; + /* + * generate start condition + */ + i2c_start(); + + /* + * send slave address + */ + i2c_outbyte((theSlave & 0xfe)); + /* + * wait for ack + */ + if(!i2c_getack()) + error = 1; + /* + * now select register + */ + i2c_dir_out(); + i2c_outbyte(theReg); + /* + * now it's time to wait for ack + */ + if(!i2c_getack()) + error |= 2; + /* + * repeat start condition + */ + i2c_delay(CLOCK_LOW_TIME); + i2c_start(); + /* + * send slave address + */ + i2c_outbyte(theSlave | 0x01); + /* + * wait for ack + */ + if(!i2c_getack()) + error |= 4; + /* + * fetch register + */ + b = i2c_inbyte(); + /* + * last received byte needs to be nacked + * instead of acked + */ + i2c_sendnack(); + /* + * end sequence + */ + i2c_stop(); + + } while(error && cntr--); + + spin_unlock_irqrestore(&i2c_lock, flags); + + return b; +} + +static int +i2c_open(struct inode *inode, struct file *filp) +{ + return 0; +} + +static int +i2c_release(struct inode *inode, struct file *filp) +{ + return 0; +} + +/* Main device API. ioctl's to write or read to/from i2c registers. + */ + +static long +i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int ret; + if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) { + return -ENOTTY; + } + + switch (_IOC_NR(cmd)) { + case I2C_WRITEREG: + /* write to an i2c slave */ + D(printk("i2cw %d %d %d\n", + I2C_ARGSLAVE(arg), + I2C_ARGREG(arg), + I2C_ARGVALUE(arg))); + + mutex_lock(&i2c_mutex); + ret = i2c_writereg(I2C_ARGSLAVE(arg), + I2C_ARGREG(arg), + I2C_ARGVALUE(arg)); + mutex_unlock(&i2c_mutex); + return ret; + + case I2C_READREG: + { + unsigned char val; + /* read from an i2c slave */ + D(printk("i2cr %d %d ", + I2C_ARGSLAVE(arg), + I2C_ARGREG(arg))); + mutex_lock(&i2c_mutex); + val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg)); + mutex_unlock(&i2c_mutex); + D(printk("= %d\n", val)); + return val; + } + default: + return -EINVAL; + + } + + return 0; +} + +static const struct file_operations i2c_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = i2c_ioctl, + .open = i2c_open, + .release = i2c_release, + .llseek = noop_llseek, +}; + +static int __init i2c_init(void) +{ + static int res; + static int first = 1; + + if (!first) + return res; + + first = 0; + + /* Setup and enable the DATA and CLK pins */ + + res = crisv32_io_get_name(&cris_i2c_data, + CONFIG_ETRAX_V32_I2C_DATA_PORT); + if (res < 0) + return res; + + res = crisv32_io_get_name(&cris_i2c_clk, CONFIG_ETRAX_V32_I2C_CLK_PORT); + crisv32_io_set_dir(&cris_i2c_clk, crisv32_io_dir_out); + + return res; +} + + +static int __init i2c_register(void) +{ + int res; + + res = i2c_init(); + if (res < 0) + return res; + + /* register char device */ + + res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops); + if (res < 0) { + printk(KERN_ERR "i2c: couldn't get a major number.\n"); + return res; + } + + printk(KERN_INFO + "I2C driver v2.2, (c) 1999-2007 Axis Communications AB\n"); + + return 0; +} +/* this makes sure that i2c_init is called during boot */ +module_init(i2c_register); + +/****************** END OF FILE i2c.c ********************************/ diff --git a/kernel/arch/cris/arch-v32/drivers/i2c.h b/kernel/arch/cris/arch-v32/drivers/i2c.h new file mode 100644 index 000000000..d9cc856f8 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/i2c.h @@ -0,0 +1,16 @@ + +#include + +/* High level I2C actions */ +int i2c_write(unsigned char theSlave, void *data, size_t nbytes); +int i2c_read(unsigned char theSlave, void *data, size_t nbytes); +int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); +unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg); + +/* Low level I2C */ +void i2c_start(void); +void i2c_stop(void); +void i2c_outbyte(unsigned char x); +unsigned char i2c_inbyte(void); +int i2c_getack(void); +void i2c_sendack(void); diff --git a/kernel/arch/cris/arch-v32/drivers/iop_fw_load.c b/kernel/arch/cris/arch-v32/drivers/iop_fw_load.c new file mode 100644 index 000000000..2f8ea0f7a --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/iop_fw_load.c @@ -0,0 +1,230 @@ +/* + * Firmware loader for ETRAX FS IO-Processor + * + * Copyright (C) 2004 Axis Communications AB + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define IOP_TIMEOUT 100 + +#error "This driver is broken with regard to its driver core usage." +#error "Please contact for details on how to fix it properly." + +static struct device iop_spu_device[2] = { + { .init_name = "iop-spu0", }, + { .init_name = "iop-spu1", }, +}; + +static struct device iop_mpu_device = { + .init_name = "iop-mpu", +}; + +static int wait_mpu_idle(void) +{ + reg_iop_mpu_r_stat mpu_stat; + unsigned int timeout = IOP_TIMEOUT; + + do { + mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat); + } while (mpu_stat.instr_reg_busy == regk_iop_mpu_yes && --timeout > 0); + if (timeout == 0) { + printk(KERN_ERR "Timeout waiting for MPU to be idle\n"); + return -EBUSY; + } + return 0; +} + +int iop_fw_load_spu(const unsigned char *fw_name, unsigned int spu_inst) +{ + reg_iop_sw_cpu_rw_mc_ctrl mc_ctrl = { + .wr_spu0_mem = regk_iop_sw_cpu_no, + .wr_spu1_mem = regk_iop_sw_cpu_no, + .size = 4, + .cmd = regk_iop_sw_cpu_reg_copy, + .keep_owner = regk_iop_sw_cpu_yes + }; + reg_iop_spu_rw_ctrl spu_ctrl = { + .en = regk_iop_spu_no, + .fsm = regk_iop_spu_no, + }; + reg_iop_sw_cpu_r_mc_stat mc_stat; + const struct firmware *fw_entry; + u32 *data; + unsigned int timeout; + int retval, i; + + if (spu_inst > 1) + return -ENODEV; + + /* get firmware */ + retval = request_firmware(&fw_entry, + fw_name, + &iop_spu_device[spu_inst]); + if (retval != 0) + { + printk(KERN_ERR + "iop_load_spu: Failed to load firmware \"%s\"\n", + fw_name); + return retval; + } + data = (u32 *) fw_entry->data; + + /* acquire ownership of memory controller */ + switch (spu_inst) { + case 0: + mc_ctrl.wr_spu0_mem = regk_iop_sw_cpu_yes; + REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl); + break; + case 1: + mc_ctrl.wr_spu1_mem = regk_iop_sw_cpu_yes; + REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl); + break; + } + timeout = IOP_TIMEOUT; + do { + REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl); + mc_stat = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, r_mc_stat); + } while (mc_stat.owned_by_cpu == regk_iop_sw_cpu_no && --timeout > 0); + if (timeout == 0) { + printk(KERN_ERR "Timeout waiting to acquire MC\n"); + retval = -EBUSY; + goto out; + } + + /* write to SPU memory */ + for (i = 0; i < (fw_entry->size/4); i++) { + switch (spu_inst) { + case 0: + REG_WR_INT(iop_spu, regi_iop_spu0, rw_seq_pc, (i*4)); + break; + case 1: + REG_WR_INT(iop_spu, regi_iop_spu1, rw_seq_pc, (i*4)); + break; + } + REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_data, *data); + data++; + } + + /* release ownership of memory controller */ + (void) REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rs_mc_data); + + out: + release_firmware(fw_entry); + return retval; +} + +int iop_fw_load_mpu(unsigned char *fw_name) +{ + const unsigned int start_addr = 0; + reg_iop_mpu_rw_ctrl mpu_ctrl; + const struct firmware *fw_entry; + u32 *data; + int retval, i; + + /* get firmware */ + retval = request_firmware(&fw_entry, fw_name, &iop_mpu_device); + if (retval != 0) + { + printk(KERN_ERR + "iop_load_spu: Failed to load firmware \"%s\"\n", + fw_name); + return retval; + } + data = (u32 *) fw_entry->data; + + /* disable MPU */ + mpu_ctrl.en = regk_iop_mpu_no; + REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); + /* put start address in R0 */ + REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, 0, start_addr); + /* write to memory by executing 'SWX i, 4, R0' for each word */ + if ((retval = wait_mpu_idle()) != 0) + goto out; + REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0)); + for (i = 0; i < (fw_entry->size / 4); i++) { + REG_WR_INT(iop_mpu, regi_iop_mpu, rw_immediate, *data); + if ((retval = wait_mpu_idle()) != 0) + goto out; + data++; + } + + out: + release_firmware(fw_entry); + return retval; +} + +int iop_start_mpu(unsigned int start_addr) +{ + reg_iop_mpu_rw_ctrl mpu_ctrl = { .en = regk_iop_mpu_yes }; + int retval; + + /* disable MPU */ + if ((retval = wait_mpu_idle()) != 0) + goto out; + REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT()); + if ((retval = wait_mpu_idle()) != 0) + goto out; + /* set PC and wait for it to bite */ + if ((retval = wait_mpu_idle()) != 0) + goto out; + REG_WR_INT(iop_mpu, regi_iop_mpu, rw_instr, MPU_BA_I(start_addr)); + if ((retval = wait_mpu_idle()) != 0) + goto out; + /* make sure the MPU starts executing with interrupts disabled */ + REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI()); + if ((retval = wait_mpu_idle()) != 0) + goto out; + /* enable MPU */ + REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); + out: + return retval; +} + +static int __init iop_fw_load_init(void) +{ +#if 0 + /* + * static struct devices can not be added directly to sysfs by ignoring + * the driver model infrastructure. To fix this properly, please use + * the platform_bus to register these devices to be able to properly + * use the firmware infrastructure. + */ + device_initialize(&iop_spu_device[0]); + kobject_set_name(&iop_spu_device[0].kobj, "iop-spu0"); + kobject_add(&iop_spu_device[0].kobj); + device_initialize(&iop_spu_device[1]); + kobject_set_name(&iop_spu_device[1].kobj, "iop-spu1"); + kobject_add(&iop_spu_device[1].kobj); + device_initialize(&iop_mpu_device); + kobject_set_name(&iop_mpu_device.kobj, "iop-mpu"); + kobject_add(&iop_mpu_device.kobj); +#endif + return 0; +} + +static void __exit iop_fw_load_exit(void) +{ +} + +module_init(iop_fw_load_init); +module_exit(iop_fw_load_exit); + +MODULE_DESCRIPTION("ETRAX FS IO-Processor Firmware Loader"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(iop_fw_load_spu); +EXPORT_SYMBOL(iop_fw_load_mpu); +EXPORT_SYMBOL(iop_start_mpu); diff --git a/kernel/arch/cris/arch-v32/drivers/mach-a3/Makefile b/kernel/arch/cris/arch-v32/drivers/mach-a3/Makefile new file mode 100644 index 000000000..5c6d2a2a0 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/mach-a3/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for Etrax-specific drivers +# + +obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o +obj-$(CONFIG_ETRAX_GPIO) += gpio.o diff --git a/kernel/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/kernel/arch/cris/arch-v32/drivers/mach-a3/gpio.c new file mode 100644 index 000000000..74f9fe809 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/mach-a3/gpio.c @@ -0,0 +1,999 @@ +/* + * Artec-3 general port I/O device + * + * Copyright (c) 2007 Axis Communications AB + * + * Authors: Bjorn Wesen (initial version) + * Ola Knutsson (LED handling) + * Johan Adolfsson (read/set directions, write, port G, + * port to ETRAX FS. + * Ricard Wanderlof (PWM for Artpec-3) + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#include "../i2c.h" + +#define VIRT_I2C_ADDR 0x40 +#endif + +/* The following gio ports on ARTPEC-3 is available: + * pa 32 bits + * pb 32 bits + * pc 16 bits + * each port has a rw_px_dout, r_px_din and rw_px_oe register. + */ + +#define GPIO_MAJOR 120 /* experimental MAJOR number */ + +#define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */ + +#define D(x) + +#if 0 +static int dp_cnt; +#define DP(x) \ + do { \ + dp_cnt++; \ + if (dp_cnt % 1000 == 0) \ + x; \ + } while (0) +#else +#define DP(x) +#endif + +static DEFINE_MUTEX(gpio_mutex); +static char gpio_name[] = "etrax gpio"; + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +static int virtual_gpio_ioctl(struct file *file, unsigned int cmd, + unsigned long arg); +#endif +static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg); +static ssize_t gpio_write(struct file *file, const char __user *buf, + size_t count, loff_t *off); +static int gpio_open(struct inode *inode, struct file *filp); +static int gpio_release(struct inode *inode, struct file *filp); +static unsigned int gpio_poll(struct file *filp, + struct poll_table_struct *wait); + +/* private data per open() of this driver */ + +struct gpio_private { + struct gpio_private *next; + /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */ + unsigned char clk_mask; + unsigned char data_mask; + unsigned char write_msb; + unsigned char pad1; + /* These fields are generic */ + unsigned long highalarm, lowalarm; + wait_queue_head_t alarm_wq; + int minor; +}; + +static void gpio_set_alarm(struct gpio_private *priv); +static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg); +static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, + unsigned long arg); + + +/* linked list of alarms to check for */ + +static struct gpio_private *alarmlist; + +static int wanted_interrupts; + +static DEFINE_SPINLOCK(gpio_lock); + +#define NUM_PORTS (GPIO_MINOR_LAST+1) +#define GIO_REG_RD_ADDR(reg) \ + (unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg) +#define GIO_REG_WR_ADDR(reg) \ + (unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg) +static unsigned long led_dummy; +static unsigned long port_d_dummy; /* Only input on Artpec-3 */ +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +static unsigned long port_e_dummy; /* Non existent on Artpec-3 */ +static unsigned long virtual_dummy; +static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE; +static unsigned short cached_virtual_gpio_read; +#endif + +static unsigned long *data_out[NUM_PORTS] = { + GIO_REG_WR_ADDR(rw_pa_dout), + GIO_REG_WR_ADDR(rw_pb_dout), + &led_dummy, + GIO_REG_WR_ADDR(rw_pc_dout), + &port_d_dummy, +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + &port_e_dummy, + &virtual_dummy, +#endif +}; + +static unsigned long *data_in[NUM_PORTS] = { + GIO_REG_RD_ADDR(r_pa_din), + GIO_REG_RD_ADDR(r_pb_din), + &led_dummy, + GIO_REG_RD_ADDR(r_pc_din), + GIO_REG_RD_ADDR(r_pd_din), +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + &port_e_dummy, + &virtual_dummy, +#endif +}; + +static unsigned long changeable_dir[NUM_PORTS] = { + CONFIG_ETRAX_PA_CHANGEABLE_DIR, + CONFIG_ETRAX_PB_CHANGEABLE_DIR, + 0, + CONFIG_ETRAX_PC_CHANGEABLE_DIR, + 0, +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + 0, + CONFIG_ETRAX_PV_CHANGEABLE_DIR, +#endif +}; + +static unsigned long changeable_bits[NUM_PORTS] = { + CONFIG_ETRAX_PA_CHANGEABLE_BITS, + CONFIG_ETRAX_PB_CHANGEABLE_BITS, + 0, + CONFIG_ETRAX_PC_CHANGEABLE_BITS, + 0, +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + 0, + CONFIG_ETRAX_PV_CHANGEABLE_BITS, +#endif +}; + +static unsigned long *dir_oe[NUM_PORTS] = { + GIO_REG_WR_ADDR(rw_pa_oe), + GIO_REG_WR_ADDR(rw_pb_oe), + &led_dummy, + GIO_REG_WR_ADDR(rw_pc_oe), + &port_d_dummy, +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + &port_e_dummy, + &virtual_rw_pv_oe, +#endif +}; + +static void gpio_set_alarm(struct gpio_private *priv) +{ + int bit; + int intr_cfg; + int mask; + int pins; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg); + pins = REG_RD_INT(gio, regi_gio, rw_intr_pins); + mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS; + + for (bit = 0; bit < 32; bit++) { + int intr = bit % 8; + int pin = bit / 8; + if (priv->minor < GPIO_MINOR_LEDS) + pin += priv->minor * 4; + else + pin += (priv->minor - 1) * 4; + + if (priv->highalarm & (1<lowalarm & (1<private_data; + unsigned long data; + unsigned long tmp; + + if (priv->minor >= GPIO_MINOR_PWM0 && + priv->minor <= GPIO_MINOR_LAST_PWM) + return 0; + + poll_wait(file, &priv->alarm_wq, wait); + if (priv->minor <= GPIO_MINOR_D) { + data = readl(data_in[priv->minor]); + REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts); + tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask); + tmp &= I2C_INTERRUPT_BITS; + tmp |= wanted_interrupts; + REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp); + } else + return 0; + + if ((data & priv->highalarm) || (~data & priv->lowalarm)) + mask = POLLIN|POLLRDNORM; + + DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask)); + return mask; +} + +static irqreturn_t gpio_interrupt(int irq, void *dev_id) +{ + reg_gio_rw_intr_mask intr_mask; + reg_gio_r_masked_intr masked_intr; + reg_gio_rw_ack_intr ack_intr; + unsigned long flags; + unsigned long tmp; + unsigned long tmp2; +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + unsigned char enable_gpiov_ack = 0; +#endif + + /* Find what PA interrupts are active */ + masked_intr = REG_RD(gio, regi_gio, r_masked_intr); + tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr); + + /* Find those that we have enabled */ + spin_lock_irqsave(&gpio_lock, flags); + tmp &= wanted_interrupts; + spin_unlock_irqrestore(&gpio_lock, flags); + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + /* Something changed on virtual GPIO. Interrupt is acked by + * reading the device. + */ + if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) { + i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read, + sizeof(cached_virtual_gpio_read)); + enable_gpiov_ack = 1; + } +#endif + + /* Ack them */ + ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp); + REG_WR(gio, regi_gio, rw_ack_intr, ack_intr); + + /* Disable those interrupts.. */ + intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); + tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask); + tmp2 &= ~tmp; +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + /* Do not disable interrupt on virtual GPIO. Changes on virtual + * pins are only noticed by an interrupt. + */ + if (enable_gpiov_ack) + tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN); +#endif + intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2); + REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); + + return IRQ_RETVAL(tmp); +} + +static void gpio_write_bit(unsigned long *port, unsigned char data, int bit, + unsigned char clk_mask, unsigned char data_mask) +{ + unsigned long shadow = readl(port) & ~clk_mask; + writel(shadow, port); + if (data & 1 << bit) + shadow |= data_mask; + else + shadow &= ~data_mask; + writel(shadow, port); + /* For FPGA: min 5.0ns (DCC) before CCLK high */ + shadow |= clk_mask; + writel(shadow, port); +} + +static void gpio_write_byte(struct gpio_private *priv, unsigned long *port, + unsigned char data) +{ + int i; + + if (priv->write_msb) + for (i = 7; i >= 0; i--) + gpio_write_bit(port, data, i, priv->clk_mask, + priv->data_mask); + else + for (i = 0; i <= 7; i++) + gpio_write_bit(port, data, i, priv->clk_mask, + priv->data_mask); +} + + +static ssize_t gpio_write(struct file *file, const char __user *buf, + size_t count, loff_t *off) +{ + struct gpio_private *priv = file->private_data; + unsigned long flags; + ssize_t retval = count; + /* Only bits 0-7 may be used for write operations but allow all + devices except leds... */ +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + if (priv->minor == GPIO_MINOR_V) + return -EFAULT; +#endif + if (priv->minor == GPIO_MINOR_LEDS) + return -EFAULT; + + if (priv->minor >= GPIO_MINOR_PWM0 && + priv->minor <= GPIO_MINOR_LAST_PWM) + return -EFAULT; + + if (!access_ok(VERIFY_READ, buf, count)) + return -EFAULT; + + /* It must have been configured using the IO_CFG_WRITE_MODE */ + /* Perhaps a better error code? */ + if (priv->clk_mask == 0 || priv->data_mask == 0) + return -EPERM; + + D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X " + "msb: %i\n", + count, priv->data_mask, priv->clk_mask, priv->write_msb)); + + spin_lock_irqsave(&gpio_lock, flags); + + while (count--) + gpio_write_byte(priv, data_out[priv->minor], *buf++); + + spin_unlock_irqrestore(&gpio_lock, flags); + return retval; +} + +static int gpio_open(struct inode *inode, struct file *filp) +{ + struct gpio_private *priv; + int p = iminor(inode); + + if (p > GPIO_MINOR_LAST_PWM || + (p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0)) + return -EINVAL; + + priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL); + + if (!priv) + return -ENOMEM; + + mutex_lock(&gpio_mutex); + memset(priv, 0, sizeof(*priv)); + + priv->minor = p; + filp->private_data = priv; + + /* initialize the io/alarm struct, not for PWM ports though */ + if (p <= GPIO_MINOR_LAST) { + + priv->clk_mask = 0; + priv->data_mask = 0; + priv->highalarm = 0; + priv->lowalarm = 0; + + init_waitqueue_head(&priv->alarm_wq); + + /* link it into our alarmlist */ + spin_lock_irq(&gpio_lock); + priv->next = alarmlist; + alarmlist = priv; + spin_unlock_irq(&gpio_lock); + } + + mutex_unlock(&gpio_mutex); + return 0; +} + +static int gpio_release(struct inode *inode, struct file *filp) +{ + struct gpio_private *p; + struct gpio_private *todel; + /* local copies while updating them: */ + unsigned long a_high, a_low; + + /* prepare to free private structure */ + todel = filp->private_data; + + /* unlink from alarmlist - only for non-PWM ports though */ + if (todel->minor <= GPIO_MINOR_LAST) { + spin_lock_irq(&gpio_lock); + p = alarmlist; + + if (p == todel) + alarmlist = todel->next; + else { + while (p->next != todel) + p = p->next; + p->next = todel->next; + } + + /* Check if there are still any alarms set */ + p = alarmlist; + a_high = 0; + a_low = 0; + while (p) { + if (p->minor == GPIO_MINOR_A) { +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN); +#endif + a_high |= p->highalarm; + a_low |= p->lowalarm; + } + + p = p->next; + } + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + /* Variable 'a_low' needs to be set here again + * to ensure that interrupt for virtual GPIO is handled. + */ + a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN); +#endif + + spin_unlock_irq(&gpio_lock); + } + kfree(todel); + + return 0; +} + +/* Main device API. ioctl's to read/set/clear bits, as well as to + * set alarms to wait for using a subsequent select(). + */ + +inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg) +{ + /* Set direction 0=unchanged 1=input, + * return mask with 1=input + */ + unsigned long flags; + unsigned long dir_shadow; + + spin_lock_irqsave(&gpio_lock, flags); + + dir_shadow = readl(dir_oe[priv->minor]) & + ~(arg & changeable_dir[priv->minor]); + writel(dir_shadow, dir_oe[priv->minor]); + + spin_unlock_irqrestore(&gpio_lock, flags); + + if (priv->minor == GPIO_MINOR_C) + dir_shadow ^= 0xFFFF; /* Only 16 bits */ +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + else if (priv->minor == GPIO_MINOR_V) + dir_shadow ^= 0xFFFF; /* Only 16 bits */ +#endif + else + dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */ + + return dir_shadow; + +} /* setget_input */ + +static inline unsigned long setget_output(struct gpio_private *priv, + unsigned long arg) +{ + unsigned long flags; + unsigned long dir_shadow; + + spin_lock_irqsave(&gpio_lock, flags); + + dir_shadow = readl(dir_oe[priv->minor]) | + (arg & changeable_dir[priv->minor]); + writel(dir_shadow, dir_oe[priv->minor]); + + spin_unlock_irqrestore(&gpio_lock, flags); + return dir_shadow; +} /* setget_output */ + +static long gpio_ioctl_unlocked(struct file *file, + unsigned int cmd, unsigned long arg) +{ + unsigned long flags; + unsigned long val; + unsigned long shadow; + struct gpio_private *priv = file->private_data; + + if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) + return -ENOTTY; + + /* Check for special ioctl handlers first */ + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + if (priv->minor == GPIO_MINOR_V) + return virtual_gpio_ioctl(file, cmd, arg); +#endif + + if (priv->minor == GPIO_MINOR_LEDS) + return gpio_leds_ioctl(cmd, arg); + + if (priv->minor >= GPIO_MINOR_PWM0 && + priv->minor <= GPIO_MINOR_LAST_PWM) + return gpio_pwm_ioctl(priv, cmd, arg); + + switch (_IOC_NR(cmd)) { + case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ + /* Read the port. */ + return readl(data_in[priv->minor]); + case IO_SETBITS: + spin_lock_irqsave(&gpio_lock, flags); + /* Set changeable bits with a 1 in arg. */ + shadow = readl(data_out[priv->minor]) | + (arg & changeable_bits[priv->minor]); + writel(shadow, data_out[priv->minor]); + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_CLRBITS: + spin_lock_irqsave(&gpio_lock, flags); + /* Clear changeable bits with a 1 in arg. */ + shadow = readl(data_out[priv->minor]) & + ~(arg & changeable_bits[priv->minor]); + writel(shadow, data_out[priv->minor]); + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_HIGHALARM: + /* Set alarm when bits with 1 in arg go high. */ + priv->highalarm |= arg; + gpio_set_alarm(priv); + break; + case IO_LOWALARM: + /* Set alarm when bits with 1 in arg go low. */ + priv->lowalarm |= arg; + gpio_set_alarm(priv); + break; + case IO_CLRALARM: + /* Clear alarm for bits with 1 in arg. */ + priv->highalarm &= ~arg; + priv->lowalarm &= ~arg; + gpio_set_alarm(priv); + break; + case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ + /* Read direction 0=input 1=output */ + return readl(dir_oe[priv->minor]); + + case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */ + /* Set direction 0=unchanged 1=input, + * return mask with 1=input + */ + return setget_input(priv, arg); + + case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */ + /* Set direction 0=unchanged 1=output, + * return mask with 1=output + */ + return setget_output(priv, arg); + + case IO_CFG_WRITE_MODE: + { + int res = -EPERM; + unsigned long dir_shadow, clk_mask, data_mask, write_msb; + + clk_mask = arg & 0xFF; + data_mask = (arg >> 8) & 0xFF; + write_msb = (arg >> 16) & 0x01; + + /* Check if we're allowed to change the bits and + * the direction is correct + */ + spin_lock_irqsave(&gpio_lock, flags); + dir_shadow = readl(dir_oe[priv->minor]); + if ((clk_mask & changeable_bits[priv->minor]) && + (data_mask & changeable_bits[priv->minor]) && + (clk_mask & dir_shadow) && + (data_mask & dir_shadow)) { + priv->clk_mask = clk_mask; + priv->data_mask = data_mask; + priv->write_msb = write_msb; + res = 0; + } + spin_unlock_irqrestore(&gpio_lock, flags); + + return res; + } + case IO_READ_INBITS: + /* *arg is result of reading the input pins */ + val = readl(data_in[priv->minor]); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + return -EFAULT; + return 0; + case IO_READ_OUTBITS: + /* *arg is result of reading the output shadow */ + val = *data_out[priv->minor]; + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + return -EFAULT; + break; + case IO_SETGET_INPUT: + /* bits set in *arg is set to input, + * *arg updated with current input pins. + */ + if (copy_from_user(&val, (void __user *)arg, sizeof(val))) + return -EFAULT; + val = setget_input(priv, val); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + return -EFAULT; + break; + case IO_SETGET_OUTPUT: + /* bits set in *arg is set to output, + * *arg updated with current output pins. + */ + if (copy_from_user(&val, (void __user *)arg, sizeof(val))) + return -EFAULT; + val = setget_output(priv, val); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + return -EFAULT; + break; + default: + return -EINVAL; + } /* switch */ + + return 0; +} + +static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret; + + mutex_lock(&gpio_mutex); + ret = gpio_ioctl_unlocked(file, cmd, arg); + mutex_unlock(&gpio_mutex); + + return ret; +} + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +static int virtual_gpio_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + unsigned long flags; + unsigned short val; + unsigned short shadow; + struct gpio_private *priv = file->private_data; + + switch (_IOC_NR(cmd)) { + case IO_SETBITS: + spin_lock_irqsave(&gpio_lock, flags); + /* Set changeable bits with a 1 in arg. */ + i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + shadow |= ~readl(dir_oe[priv->minor]) | + (arg & changeable_bits[priv->minor]); + i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_CLRBITS: + spin_lock_irqsave(&gpio_lock, flags); + /* Clear changeable bits with a 1 in arg. */ + i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + shadow |= ~readl(dir_oe[priv->minor]) & + ~(arg & changeable_bits[priv->minor]); + i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + spin_unlock_irqrestore(&gpio_lock, flags); + break; + case IO_HIGHALARM: + /* Set alarm when bits with 1 in arg go high. */ + priv->highalarm |= arg; + break; + case IO_LOWALARM: + /* Set alarm when bits with 1 in arg go low. */ + priv->lowalarm |= arg; + break; + case IO_CLRALARM: + /* Clear alarm for bits with 1 in arg. */ + priv->highalarm &= ~arg; + priv->lowalarm &= ~arg; + break; + case IO_CFG_WRITE_MODE: + { + unsigned long dir_shadow; + dir_shadow = readl(dir_oe[priv->minor]); + + priv->clk_mask = arg & 0xFF; + priv->data_mask = (arg >> 8) & 0xFF; + priv->write_msb = (arg >> 16) & 0x01; + /* Check if we're allowed to change the bits and + * the direction is correct + */ + if (!((priv->clk_mask & changeable_bits[priv->minor]) && + (priv->data_mask & changeable_bits[priv->minor]) && + (priv->clk_mask & dir_shadow) && + (priv->data_mask & dir_shadow))) { + priv->clk_mask = 0; + priv->data_mask = 0; + return -EPERM; + } + break; + } + case IO_READ_INBITS: + /* *arg is result of reading the input pins */ + val = cached_virtual_gpio_read & ~readl(dir_oe[priv->minor]); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + return -EFAULT; + return 0; + + case IO_READ_OUTBITS: + /* *arg is result of reading the output shadow */ + i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val)); + val &= readl(dir_oe[priv->minor]); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + return -EFAULT; + break; + case IO_SETGET_INPUT: + { + /* bits set in *arg is set to input, + * *arg updated with current input pins. + */ + unsigned short input_mask = ~readl(dir_oe[priv->minor]); + if (copy_from_user(&val, (void __user *)arg, sizeof(val))) + return -EFAULT; + val = setget_input(priv, val); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + return -EFAULT; + if ((input_mask & val) != input_mask) { + /* Input pins changed. All ports desired as input + * should be set to logic 1. + */ + unsigned short change = input_mask ^ val; + i2c_read(VIRT_I2C_ADDR, (void *)&shadow, + sizeof(shadow)); + shadow &= ~change; + shadow |= val; + i2c_write(VIRT_I2C_ADDR, (void *)&shadow, + sizeof(shadow)); + } + break; + } + case IO_SETGET_OUTPUT: + /* bits set in *arg is set to output, + * *arg updated with current output pins. + */ + if (copy_from_user(&val, (void __user *)arg, sizeof(val))) + return -EFAULT; + val = setget_output(priv, val); + if (copy_to_user((void __user *)arg, &val, sizeof(val))) + return -EFAULT; + break; + default: + return -EINVAL; + } /* switch */ + return 0; +} +#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */ + +static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg) +{ + unsigned char green; + unsigned char red; + + switch (_IOC_NR(cmd)) { + case IO_LEDACTIVE_SET: + green = ((unsigned char) arg) & 1; + red = (((unsigned char) arg) >> 1) & 1; + CRIS_LED_ACTIVE_SET_G(green); + CRIS_LED_ACTIVE_SET_R(red); + break; + + default: + return -EINVAL; + } /* switch */ + + return 0; +} + +static int gpio_pwm_set_mode(unsigned long arg, int pwm_port) +{ + int pinmux_pwm = pinmux_pwm0 + pwm_port; + int mode; + reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = { + .ccd_val = 0, + .ccd_override = regk_gio_no, + .mode = regk_gio_no + }; + int allocstatus; + + if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode)) + return -EFAULT; + rw_pwm_ctrl.mode = mode; + if (mode != PWM_OFF) + allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm); + else + allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm); + if (allocstatus) + return allocstatus; + REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) + + 12 * pwm_port, rw_pwm_ctrl); + return 0; +} + +static int gpio_pwm_set_period(unsigned long arg, int pwm_port) +{ + struct io_pwm_set_period periods; + reg_gio_rw_pwm0_var rw_pwm_widths; + + if (copy_from_user(&periods, (void __user *)arg, sizeof(periods))) + return -EFAULT; + if (periods.lo > 8191 || periods.hi > 8191) + return -EINVAL; + rw_pwm_widths.lo = periods.lo; + rw_pwm_widths.hi = periods.hi; + REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) + + 12 * pwm_port, rw_pwm_widths); + return 0; +} + +static int gpio_pwm_set_duty(unsigned long arg, int pwm_port) +{ + unsigned int duty; + reg_gio_rw_pwm0_data rw_pwm_duty; + + if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty)) + return -EFAULT; + if (duty > 255) + return -EINVAL; + rw_pwm_duty.data = duty; + REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) + + 12 * pwm_port, rw_pwm_duty); + return 0; +} + +static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, + unsigned long arg) +{ + int pwm_port = priv->minor - GPIO_MINOR_PWM0; + + switch (_IOC_NR(cmd)) { + case IO_PWM_SET_MODE: + return gpio_pwm_set_mode(arg, pwm_port); + case IO_PWM_SET_PERIOD: + return gpio_pwm_set_period(arg, pwm_port); + case IO_PWM_SET_DUTY: + return gpio_pwm_set_duty(arg, pwm_port); + default: + return -EINVAL; + } + return 0; +} + +static const struct file_operations gpio_fops = { + .owner = THIS_MODULE, + .poll = gpio_poll, + .unlocked_ioctl = gpio_ioctl, + .write = gpio_write, + .open = gpio_open, + .release = gpio_release, + .llseek = noop_llseek, +}; + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +static void __init virtual_gpio_init(void) +{ + reg_gio_rw_intr_cfg intr_cfg; + reg_gio_rw_intr_mask intr_mask; + unsigned short shadow; + + shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */ + shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT; + i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + + /* Set interrupt mask and on what state the interrupt shall trigger. + * For virtual gpio the interrupt shall trigger on logic '0'. + */ + intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg); + intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); + + switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) { + case 0: + intr_cfg.pa0 = regk_gio_lo; + intr_mask.pa0 = regk_gio_yes; + break; + case 1: + intr_cfg.pa1 = regk_gio_lo; + intr_mask.pa1 = regk_gio_yes; + break; + case 2: + intr_cfg.pa2 = regk_gio_lo; + intr_mask.pa2 = regk_gio_yes; + break; + case 3: + intr_cfg.pa3 = regk_gio_lo; + intr_mask.pa3 = regk_gio_yes; + break; + case 4: + intr_cfg.pa4 = regk_gio_lo; + intr_mask.pa4 = regk_gio_yes; + break; + case 5: + intr_cfg.pa5 = regk_gio_lo; + intr_mask.pa5 = regk_gio_yes; + break; + case 6: + intr_cfg.pa6 = regk_gio_lo; + intr_mask.pa6 = regk_gio_yes; + break; + case 7: + intr_cfg.pa7 = regk_gio_lo; + intr_mask.pa7 = regk_gio_yes; + break; + } + + REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg); + REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); +} +#endif + +/* main driver initialization routine, called from mem.c */ + +static int __init gpio_init(void) +{ + int res; + + printk(KERN_INFO "ETRAX FS GPIO driver v2.7, (c) 2003-2008 " + "Axis Communications AB\n"); + + /* do the formalities */ + + res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops); + if (res < 0) { + printk(KERN_ERR "gpio: couldn't get a major number.\n"); + return res; + } + + /* Clear all leds */ + CRIS_LED_NETWORK_GRP0_SET(0); + CRIS_LED_NETWORK_GRP1_SET(0); + CRIS_LED_ACTIVE_SET(0); + CRIS_LED_DISK_READ(0); + CRIS_LED_DISK_WRITE(0); + + int res2 = request_irq(GIO_INTR_VECT, gpio_interrupt, + IRQF_SHARED, "gpio", &alarmlist); + if (res2) { + printk(KERN_ERR "err: irq for gpio\n"); + return res2; + } + + /* No IRQs by default. */ + REG_WR_INT(gio, regi_gio, rw_intr_pins, 0); + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + virtual_gpio_init(); +#endif + + return res; +} + +/* this makes sure that gpio_init is called during kernel boot */ + +module_init(gpio_init); diff --git a/kernel/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/kernel/arch/cris/arch-v32/drivers/mach-a3/nandflash.c new file mode 100644 index 000000000..7fb52128d --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/mach-a3/nandflash.c @@ -0,0 +1,180 @@ +/* + * arch/cris/arch-v32/drivers/nandflash.c + * + * Copyright (c) 2007 + * + * Derived from drivers/mtd/nand/spia.c + * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MANUAL_ALE_CLE_CONTROL 1 + +#define regf_ALE a0 +#define regf_CLE a1 +#define regf_NCE ce0_n + +#define CLE_BIT 10 +#define ALE_BIT 11 +#define CE_BIT 12 + +struct mtd_info_wrapper { + struct mtd_info info; + struct nand_chip chip; +}; + +/* Bitmask for control pins */ +#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT)) + +static struct mtd_info *crisv32_mtd; +/* + * hardware specific access to control-lines + */ +static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + unsigned long flags; + reg_pio_rw_dout dout; + struct nand_chip *this = mtd->priv; + + local_irq_save(flags); + + /* control bits change */ + if (ctrl & NAND_CTRL_CHANGE) { + dout = REG_RD(pio, regi_pio, rw_dout); + dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1; + +#if !MANUAL_ALE_CLE_CONTROL + if (ctrl & NAND_ALE) { + /* A0 = ALE high */ + this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio, + regi_pio, rw_io_access1); + } else if (ctrl & NAND_CLE) { + /* A1 = CLE high */ + this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio, + regi_pio, rw_io_access2); + } else { + /* A1 = CLE and A0 = ALE low */ + this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio, + regi_pio, rw_io_access0); + } +#else + + dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0; + dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0; +#endif + REG_WR(pio, regi_pio, rw_dout, dout); + } + + /* command to chip */ + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); + + local_irq_restore(flags); +} + +/* +* read device ready pin +*/ +static int crisv32_device_ready(struct mtd_info *mtd) +{ + reg_pio_r_din din = REG_RD(pio, regi_pio, r_din); + return din.rdy; +} + +/* + * Main initialization routine + */ +struct mtd_info *__init crisv32_nand_flash_probe(void) +{ + void __iomem *read_cs; + void __iomem *write_cs; + + struct mtd_info_wrapper *wrapper; + struct nand_chip *this; + int err = 0; + + reg_pio_rw_man_ctrl man_ctrl = { + .regf_NCE = regk_pio_yes, +#if MANUAL_ALE_CLE_CONTROL + .regf_ALE = regk_pio_yes, + .regf_CLE = regk_pio_yes +#endif + }; + reg_pio_rw_oe oe = { + .regf_NCE = regk_pio_yes, +#if MANUAL_ALE_CLE_CONTROL + .regf_ALE = regk_pio_yes, + .regf_CLE = regk_pio_yes +#endif + }; + reg_pio_rw_dout dout = { .regf_NCE = 1 }; + + /* Allocate pio pins to pio */ + crisv32_pinmux_alloc_fixed(pinmux_pio); + /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */ + REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl); + REG_WR(pio, regi_pio, rw_dout, dout); + REG_WR(pio, regi_pio, rw_oe, oe); + + /* Allocate memory for MTD device structure and private data */ + wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL); + if (!wrapper) { + printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD " + "device structure.\n"); + err = -ENOMEM; + return NULL; + } + + read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio, + rw_io_access0); + + /* Get pointer to private data */ + this = &wrapper->chip; + crisv32_mtd = &wrapper->info; + + /* Link the private data with the MTD structure */ + crisv32_mtd->priv = this; + + /* Set address of NAND IO lines */ + this->IO_ADDR_R = read_cs; + this->IO_ADDR_W = write_cs; + this->cmd_ctrl = crisv32_hwcontrol; + this->dev_ready = crisv32_device_ready; + /* 20 us command delay time */ + this->chip_delay = 20; + this->ecc.mode = NAND_ECC_SOFT; + + /* Enable the following for a flash based bad block table */ + /* this->bbt_options = NAND_BBT_USE_FLASH; */ + + /* Scan to find existence of the device */ + if (nand_scan(crisv32_mtd, 1)) { + err = -ENXIO; + goto out_mtd; + } + + return crisv32_mtd; + +out_mtd: + kfree(wrapper); + return NULL; +} + diff --git a/kernel/arch/cris/arch-v32/drivers/mach-fs/Makefile b/kernel/arch/cris/arch-v32/drivers/mach-fs/Makefile new file mode 100644 index 000000000..5c6d2a2a0 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/mach-fs/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for Etrax-specific drivers +# + +obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o +obj-$(CONFIG_ETRAX_GPIO) += gpio.o diff --git a/kernel/arch/cris/arch-v32/drivers/mach-fs/gpio.c b/kernel/arch/cris/arch-v32/drivers/mach-fs/gpio.c new file mode 100644 index 000000000..009f4ee1b --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/mach-fs/gpio.c @@ -0,0 +1,979 @@ +/* + * ETRAX CRISv32 general port I/O device + * + * Copyright (c) 1999-2006 Axis Communications AB + * + * Authors: Bjorn Wesen (initial version) + * Ola Knutsson (LED handling) + * Johan Adolfsson (read/set directions, write, port G, + * port to ETRAX FS. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#include "../i2c.h" + +#define VIRT_I2C_ADDR 0x40 +#endif + +/* The following gio ports on ETRAX FS is available: + * pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge + * pb 18 bits + * pc 18 bits + * pd 18 bits + * pe 18 bits + * each port has a rw_px_dout, r_px_din and rw_px_oe register. + */ + +#define GPIO_MAJOR 120 /* experimental MAJOR number */ + +#define D(x) + +#if 0 +static int dp_cnt; +#define DP(x) \ + do { \ + dp_cnt++; \ + if (dp_cnt % 1000 == 0) \ + x; \ + } while (0) +#else +#define DP(x) +#endif + +static DEFINE_MUTEX(gpio_mutex); +static char gpio_name[] = "etrax gpio"; + +#if 0 +static wait_queue_head_t *gpio_wq; +#endif + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +static int virtual_gpio_ioctl(struct file *file, unsigned int cmd, + unsigned long arg); +#endif +static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg); +static ssize_t gpio_write(struct file *file, const char *buf, size_t count, + loff_t *off); +static int gpio_open(struct inode *inode, struct file *filp); +static int gpio_release(struct inode *inode, struct file *filp); +static unsigned int gpio_poll(struct file *filp, + struct poll_table_struct *wait); + +/* private data per open() of this driver */ + +struct gpio_private { + struct gpio_private *next; + /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */ + unsigned char clk_mask; + unsigned char data_mask; + unsigned char write_msb; + unsigned char pad1; + /* These fields are generic */ + unsigned long highalarm, lowalarm; + wait_queue_head_t alarm_wq; + int minor; +}; + +/* linked list of alarms to check for */ + +static struct gpio_private *alarmlist; + +static int gpio_some_alarms; /* Set if someone uses alarm */ +static unsigned long gpio_pa_high_alarms; +static unsigned long gpio_pa_low_alarms; + +static DEFINE_SPINLOCK(alarm_lock); + +#define NUM_PORTS (GPIO_MINOR_LAST+1) +#define GIO_REG_RD_ADDR(reg) \ + (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg) +#define GIO_REG_WR_ADDR(reg) \ + (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg) +unsigned long led_dummy; +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +static unsigned long virtual_dummy; +static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE; +static unsigned short cached_virtual_gpio_read; +#endif + +static volatile unsigned long *data_out[NUM_PORTS] = { + GIO_REG_WR_ADDR(rw_pa_dout), + GIO_REG_WR_ADDR(rw_pb_dout), + &led_dummy, + GIO_REG_WR_ADDR(rw_pc_dout), + GIO_REG_WR_ADDR(rw_pd_dout), + GIO_REG_WR_ADDR(rw_pe_dout), +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + &virtual_dummy, +#endif +}; + +static volatile unsigned long *data_in[NUM_PORTS] = { + GIO_REG_RD_ADDR(r_pa_din), + GIO_REG_RD_ADDR(r_pb_din), + &led_dummy, + GIO_REG_RD_ADDR(r_pc_din), + GIO_REG_RD_ADDR(r_pd_din), + GIO_REG_RD_ADDR(r_pe_din), +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + &virtual_dummy, +#endif +}; + +static unsigned long changeable_dir[NUM_PORTS] = { + CONFIG_ETRAX_PA_CHANGEABLE_DIR, + CONFIG_ETRAX_PB_CHANGEABLE_DIR, + 0, + CONFIG_ETRAX_PC_CHANGEABLE_DIR, + CONFIG_ETRAX_PD_CHANGEABLE_DIR, + CONFIG_ETRAX_PE_CHANGEABLE_DIR, +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + CONFIG_ETRAX_PV_CHANGEABLE_DIR, +#endif +}; + +static unsigned long changeable_bits[NUM_PORTS] = { + CONFIG_ETRAX_PA_CHANGEABLE_BITS, + CONFIG_ETRAX_PB_CHANGEABLE_BITS, + 0, + CONFIG_ETRAX_PC_CHANGEABLE_BITS, + CONFIG_ETRAX_PD_CHANGEABLE_BITS, + CONFIG_ETRAX_PE_CHANGEABLE_BITS, +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + CONFIG_ETRAX_PV_CHANGEABLE_BITS, +#endif +}; + +static volatile unsigned long *dir_oe[NUM_PORTS] = { + GIO_REG_WR_ADDR(rw_pa_oe), + GIO_REG_WR_ADDR(rw_pb_oe), + &led_dummy, + GIO_REG_WR_ADDR(rw_pc_oe), + GIO_REG_WR_ADDR(rw_pd_oe), + GIO_REG_WR_ADDR(rw_pe_oe), +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + &virtual_rw_pv_oe, +#endif +}; + + + +static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait) +{ + unsigned int mask = 0; + struct gpio_private *priv = file->private_data; + unsigned long data; + poll_wait(file, &priv->alarm_wq, wait); + if (priv->minor == GPIO_MINOR_A) { + reg_gio_rw_intr_cfg intr_cfg; + unsigned long tmp; + unsigned long flags; + + local_irq_save(flags); + data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din, + REG_RD(gio, regi_gio, r_pa_din)); + /* PA has support for interrupt + * lets activate high for those low and with highalarm set + */ + intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg); + + tmp = ~data & priv->highalarm & 0xFF; + if (tmp & (1 << 0)) + intr_cfg.pa0 = regk_gio_hi; + if (tmp & (1 << 1)) + intr_cfg.pa1 = regk_gio_hi; + if (tmp & (1 << 2)) + intr_cfg.pa2 = regk_gio_hi; + if (tmp & (1 << 3)) + intr_cfg.pa3 = regk_gio_hi; + if (tmp & (1 << 4)) + intr_cfg.pa4 = regk_gio_hi; + if (tmp & (1 << 5)) + intr_cfg.pa5 = regk_gio_hi; + if (tmp & (1 << 6)) + intr_cfg.pa6 = regk_gio_hi; + if (tmp & (1 << 7)) + intr_cfg.pa7 = regk_gio_hi; + /* + * lets activate low for those high and with lowalarm set + */ + tmp = data & priv->lowalarm & 0xFF; + if (tmp & (1 << 0)) + intr_cfg.pa0 = regk_gio_lo; + if (tmp & (1 << 1)) + intr_cfg.pa1 = regk_gio_lo; + if (tmp & (1 << 2)) + intr_cfg.pa2 = regk_gio_lo; + if (tmp & (1 << 3)) + intr_cfg.pa3 = regk_gio_lo; + if (tmp & (1 << 4)) + intr_cfg.pa4 = regk_gio_lo; + if (tmp & (1 << 5)) + intr_cfg.pa5 = regk_gio_lo; + if (tmp & (1 << 6)) + intr_cfg.pa6 = regk_gio_lo; + if (tmp & (1 << 7)) + intr_cfg.pa7 = regk_gio_lo; + + REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg); + local_irq_restore(flags); + } else if (priv->minor <= GPIO_MINOR_E) + data = *data_in[priv->minor]; + else + return 0; + + if ((data & priv->highalarm) || (~data & priv->lowalarm)) + mask = POLLIN|POLLRDNORM; + + DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask)); + return mask; +} + +int etrax_gpio_wake_up_check(void) +{ + struct gpio_private *priv; + unsigned long data = 0; + unsigned long flags; + int ret = 0; + spin_lock_irqsave(&alarm_lock, flags); + priv = alarmlist; + while (priv) { +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + if (priv->minor == GPIO_MINOR_V) + data = (unsigned long)cached_virtual_gpio_read; + else { + data = *data_in[priv->minor]; + if (priv->minor == GPIO_MINOR_A) + priv->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN); + } +#else + data = *data_in[priv->minor]; +#endif + if ((data & priv->highalarm) || + (~data & priv->lowalarm)) { + DP(printk(KERN_DEBUG + "etrax_gpio_wake_up_check %i\n", priv->minor)); + wake_up_interruptible(&priv->alarm_wq); + ret = 1; + } + priv = priv->next; + } + spin_unlock_irqrestore(&alarm_lock, flags); + return ret; +} + +static irqreturn_t +gpio_poll_timer_interrupt(int irq, void *dev_id) +{ + if (gpio_some_alarms) + return IRQ_RETVAL(etrax_gpio_wake_up_check()); + return IRQ_NONE; +} + +static irqreturn_t +gpio_pa_interrupt(int irq, void *dev_id) +{ + reg_gio_rw_intr_mask intr_mask; + reg_gio_r_masked_intr masked_intr; + reg_gio_rw_ack_intr ack_intr; + unsigned long tmp; + unsigned long tmp2; +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + unsigned char enable_gpiov_ack = 0; +#endif + + /* Find what PA interrupts are active */ + masked_intr = REG_RD(gio, regi_gio, r_masked_intr); + tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr); + + /* Find those that we have enabled */ + spin_lock(&alarm_lock); + tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms); + spin_unlock(&alarm_lock); + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + /* Something changed on virtual GPIO. Interrupt is acked by + * reading the device. + */ + if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) { + i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read, + sizeof(cached_virtual_gpio_read)); + enable_gpiov_ack = 1; + } +#endif + + /* Ack them */ + ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp); + REG_WR(gio, regi_gio, rw_ack_intr, ack_intr); + + /* Disable those interrupts.. */ + intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); + tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask); + tmp2 &= ~tmp; +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + /* Do not disable interrupt on virtual GPIO. Changes on virtual + * pins are only noticed by an interrupt. + */ + if (enable_gpiov_ack) + tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN); +#endif + intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2); + REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); + + if (gpio_some_alarms) + return IRQ_RETVAL(etrax_gpio_wake_up_check()); + return IRQ_NONE; +} + + +static ssize_t gpio_write(struct file *file, const char *buf, size_t count, + loff_t *off) +{ + struct gpio_private *priv = file->private_data; + unsigned char data, clk_mask, data_mask, write_msb; + unsigned long flags; + unsigned long shadow; + volatile unsigned long *port; + ssize_t retval = count; + /* Only bits 0-7 may be used for write operations but allow all + devices except leds... */ +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + if (priv->minor == GPIO_MINOR_V) + return -EFAULT; +#endif + if (priv->minor == GPIO_MINOR_LEDS) + return -EFAULT; + + if (!access_ok(VERIFY_READ, buf, count)) + return -EFAULT; + clk_mask = priv->clk_mask; + data_mask = priv->data_mask; + /* It must have been configured using the IO_CFG_WRITE_MODE */ + /* Perhaps a better error code? */ + if (clk_mask == 0 || data_mask == 0) + return -EPERM; + write_msb = priv->write_msb; + D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X " + "msb: %i\n", count, data_mask, clk_mask, write_msb)); + port = data_out[priv->minor]; + + while (count--) { + int i; + data = *buf++; + if (priv->write_msb) { + for (i = 7; i >= 0; i--) { + local_irq_save(flags); + shadow = *port; + *port = shadow &= ~clk_mask; + if (data & 1< GPIO_MINOR_LAST) + return -EINVAL; + + priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_lock(&gpio_mutex); + memset(priv, 0, sizeof(*priv)); + + priv->minor = p; + + /* initialize the io/alarm struct */ + + priv->clk_mask = 0; + priv->data_mask = 0; + priv->highalarm = 0; + priv->lowalarm = 0; + init_waitqueue_head(&priv->alarm_wq); + + filp->private_data = (void *)priv; + + /* link it into our alarmlist */ + spin_lock_irq(&alarm_lock); + priv->next = alarmlist; + alarmlist = priv; + spin_unlock_irq(&alarm_lock); + + mutex_unlock(&gpio_mutex); + return 0; +} + +static int +gpio_release(struct inode *inode, struct file *filp) +{ + struct gpio_private *p; + struct gpio_private *todel; + /* local copies while updating them: */ + unsigned long a_high, a_low; + unsigned long some_alarms; + + /* unlink from alarmlist and free the private structure */ + + spin_lock_irq(&alarm_lock); + p = alarmlist; + todel = filp->private_data; + + if (p == todel) { + alarmlist = todel->next; + } else { + while (p->next != todel) + p = p->next; + p->next = todel->next; + } + + kfree(todel); + /* Check if there are still any alarms set */ + p = alarmlist; + some_alarms = 0; + a_high = 0; + a_low = 0; + while (p) { + if (p->minor == GPIO_MINOR_A) { +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN); +#endif + a_high |= p->highalarm; + a_low |= p->lowalarm; + } + + if (p->highalarm | p->lowalarm) + some_alarms = 1; + p = p->next; + } + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + /* Variables 'some_alarms' and 'a_low' needs to be set here again + * to ensure that interrupt for virtual GPIO is handled. + */ + some_alarms = 1; + a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN); +#endif + + gpio_some_alarms = some_alarms; + gpio_pa_high_alarms = a_high; + gpio_pa_low_alarms = a_low; + spin_unlock_irq(&alarm_lock); + + return 0; +} + +/* Main device API. ioctl's to read/set/clear bits, as well as to + * set alarms to wait for using a subsequent select(). + */ + +inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg) +{ + /* Set direction 0=unchanged 1=input, + * return mask with 1=input + */ + unsigned long flags; + unsigned long dir_shadow; + + local_irq_save(flags); + dir_shadow = *dir_oe[priv->minor]; + dir_shadow &= ~(arg & changeable_dir[priv->minor]); + *dir_oe[priv->minor] = dir_shadow; + local_irq_restore(flags); + + if (priv->minor == GPIO_MINOR_A) + dir_shadow ^= 0xFF; /* Only 8 bits */ +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + else if (priv->minor == GPIO_MINOR_V) + dir_shadow ^= 0xFFFF; /* Only 16 bits */ +#endif + else + dir_shadow ^= 0x3FFFF; /* Only 18 bits */ + return dir_shadow; + +} /* setget_input */ + +inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg) +{ + unsigned long flags; + unsigned long dir_shadow; + + local_irq_save(flags); + dir_shadow = *dir_oe[priv->minor]; + dir_shadow |= (arg & changeable_dir[priv->minor]); + *dir_oe[priv->minor] = dir_shadow; + local_irq_restore(flags); + return dir_shadow; +} /* setget_output */ + +static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg); + +static int +gpio_ioctl_unlocked(struct file *file, unsigned int cmd, unsigned long arg) +{ + unsigned long flags; + unsigned long val; + unsigned long shadow; + struct gpio_private *priv = file->private_data; + if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) + return -EINVAL; + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + if (priv->minor == GPIO_MINOR_V) + return virtual_gpio_ioctl(file, cmd, arg); +#endif + + switch (_IOC_NR(cmd)) { + case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ + /* Read the port. */ + return *data_in[priv->minor]; + break; + case IO_SETBITS: + local_irq_save(flags); + /* Set changeable bits with a 1 in arg. */ + shadow = *data_out[priv->minor]; + shadow |= (arg & changeable_bits[priv->minor]); + *data_out[priv->minor] = shadow; + local_irq_restore(flags); + break; + case IO_CLRBITS: + local_irq_save(flags); + /* Clear changeable bits with a 1 in arg. */ + shadow = *data_out[priv->minor]; + shadow &= ~(arg & changeable_bits[priv->minor]); + *data_out[priv->minor] = shadow; + local_irq_restore(flags); + break; + case IO_HIGHALARM: + /* Set alarm when bits with 1 in arg go high. */ + priv->highalarm |= arg; + spin_lock_irqsave(&alarm_lock, flags); + gpio_some_alarms = 1; + if (priv->minor == GPIO_MINOR_A) + gpio_pa_high_alarms |= arg; + spin_unlock_irqrestore(&alarm_lock, flags); + break; + case IO_LOWALARM: + /* Set alarm when bits with 1 in arg go low. */ + priv->lowalarm |= arg; + spin_lock_irqsave(&alarm_lock, flags); + gpio_some_alarms = 1; + if (priv->minor == GPIO_MINOR_A) + gpio_pa_low_alarms |= arg; + spin_unlock_irqrestore(&alarm_lock, flags); + break; + case IO_CLRALARM: + /* Clear alarm for bits with 1 in arg. */ + priv->highalarm &= ~arg; + priv->lowalarm &= ~arg; + spin_lock_irqsave(&alarm_lock, flags); + if (priv->minor == GPIO_MINOR_A) { + if (gpio_pa_high_alarms & arg || + gpio_pa_low_alarms & arg) + /* Must update the gpio_pa_*alarms masks */ + ; + } + spin_unlock_irqrestore(&alarm_lock, flags); + break; + case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ + /* Read direction 0=input 1=output */ + return *dir_oe[priv->minor]; + case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */ + /* Set direction 0=unchanged 1=input, + * return mask with 1=input + */ + return setget_input(priv, arg); + break; + case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */ + /* Set direction 0=unchanged 1=output, + * return mask with 1=output + */ + return setget_output(priv, arg); + + case IO_CFG_WRITE_MODE: + { + unsigned long dir_shadow; + dir_shadow = *dir_oe[priv->minor]; + + priv->clk_mask = arg & 0xFF; + priv->data_mask = (arg >> 8) & 0xFF; + priv->write_msb = (arg >> 16) & 0x01; + /* Check if we're allowed to change the bits and + * the direction is correct + */ + if (!((priv->clk_mask & changeable_bits[priv->minor]) && + (priv->data_mask & changeable_bits[priv->minor]) && + (priv->clk_mask & dir_shadow) && + (priv->data_mask & dir_shadow))) { + priv->clk_mask = 0; + priv->data_mask = 0; + return -EPERM; + } + break; + } + case IO_READ_INBITS: + /* *arg is result of reading the input pins */ + val = *data_in[priv->minor]; + if (copy_to_user((unsigned long *)arg, &val, sizeof(val))) + return -EFAULT; + return 0; + break; + case IO_READ_OUTBITS: + /* *arg is result of reading the output shadow */ + val = *data_out[priv->minor]; + if (copy_to_user((unsigned long *)arg, &val, sizeof(val))) + return -EFAULT; + break; + case IO_SETGET_INPUT: + /* bits set in *arg is set to input, + * *arg updated with current input pins. + */ + if (copy_from_user(&val, (unsigned long *)arg, sizeof(val))) + return -EFAULT; + val = setget_input(priv, val); + if (copy_to_user((unsigned long *)arg, &val, sizeof(val))) + return -EFAULT; + break; + case IO_SETGET_OUTPUT: + /* bits set in *arg is set to output, + * *arg updated with current output pins. + */ + if (copy_from_user(&val, (unsigned long *)arg, sizeof(val))) + return -EFAULT; + val = setget_output(priv, val); + if (copy_to_user((unsigned long *)arg, &val, sizeof(val))) + return -EFAULT; + break; + default: + if (priv->minor == GPIO_MINOR_LEDS) + return gpio_leds_ioctl(cmd, arg); + else + return -EINVAL; + } /* switch */ + + return 0; +} + +static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret; + + mutex_lock(&gpio_mutex); + ret = gpio_ioctl_unlocked(file, cmd, arg); + mutex_unlock(&gpio_mutex); + + return ret; +} + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +static int +virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + unsigned long flags; + unsigned short val; + unsigned short shadow; + struct gpio_private *priv = file->private_data; + + switch (_IOC_NR(cmd)) { + case IO_SETBITS: + local_irq_save(flags); + /* Set changeable bits with a 1 in arg. */ + i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + shadow |= ~*dir_oe[priv->minor]; + shadow |= (arg & changeable_bits[priv->minor]); + i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + local_irq_restore(flags); + break; + case IO_CLRBITS: + local_irq_save(flags); + /* Clear changeable bits with a 1 in arg. */ + i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + shadow |= ~*dir_oe[priv->minor]; + shadow &= ~(arg & changeable_bits[priv->minor]); + i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + local_irq_restore(flags); + break; + case IO_HIGHALARM: + /* Set alarm when bits with 1 in arg go high. */ + priv->highalarm |= arg; + spin_lock(&alarm_lock); + gpio_some_alarms = 1; + spin_unlock(&alarm_lock); + break; + case IO_LOWALARM: + /* Set alarm when bits with 1 in arg go low. */ + priv->lowalarm |= arg; + spin_lock(&alarm_lock); + gpio_some_alarms = 1; + spin_unlock(&alarm_lock); + break; + case IO_CLRALARM: + /* Clear alarm for bits with 1 in arg. */ + priv->highalarm &= ~arg; + priv->lowalarm &= ~arg; + spin_lock(&alarm_lock); + spin_unlock(&alarm_lock); + break; + case IO_CFG_WRITE_MODE: + { + unsigned long dir_shadow; + dir_shadow = *dir_oe[priv->minor]; + + priv->clk_mask = arg & 0xFF; + priv->data_mask = (arg >> 8) & 0xFF; + priv->write_msb = (arg >> 16) & 0x01; + /* Check if we're allowed to change the bits and + * the direction is correct + */ + if (!((priv->clk_mask & changeable_bits[priv->minor]) && + (priv->data_mask & changeable_bits[priv->minor]) && + (priv->clk_mask & dir_shadow) && + (priv->data_mask & dir_shadow))) { + priv->clk_mask = 0; + priv->data_mask = 0; + return -EPERM; + } + break; + } + case IO_READ_INBITS: + /* *arg is result of reading the input pins */ + val = cached_virtual_gpio_read; + val &= ~*dir_oe[priv->minor]; + if (copy_to_user((unsigned long *)arg, &val, sizeof(val))) + return -EFAULT; + return 0; + break; + case IO_READ_OUTBITS: + /* *arg is result of reading the output shadow */ + i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val)); + val &= *dir_oe[priv->minor]; + if (copy_to_user((unsigned long *)arg, &val, sizeof(val))) + return -EFAULT; + break; + case IO_SETGET_INPUT: + { + /* bits set in *arg is set to input, + * *arg updated with current input pins. + */ + unsigned short input_mask = ~*dir_oe[priv->minor]; + if (copy_from_user(&val, (unsigned long *)arg, sizeof(val))) + return -EFAULT; + val = setget_input(priv, val); + if (copy_to_user((unsigned long *)arg, &val, sizeof(val))) + return -EFAULT; + if ((input_mask & val) != input_mask) { + /* Input pins changed. All ports desired as input + * should be set to logic 1. + */ + unsigned short change = input_mask ^ val; + i2c_read(VIRT_I2C_ADDR, (void *)&shadow, + sizeof(shadow)); + shadow &= ~change; + shadow |= val; + i2c_write(VIRT_I2C_ADDR, (void *)&shadow, + sizeof(shadow)); + } + break; + } + case IO_SETGET_OUTPUT: + /* bits set in *arg is set to output, + * *arg updated with current output pins. + */ + if (copy_from_user(&val, (unsigned long *)arg, sizeof(val))) + return -EFAULT; + val = setget_output(priv, val); + if (copy_to_user((unsigned long *)arg, &val, sizeof(val))) + return -EFAULT; + break; + default: + return -EINVAL; + } /* switch */ + return 0; +} +#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */ + +static int +gpio_leds_ioctl(unsigned int cmd, unsigned long arg) +{ + unsigned char green; + unsigned char red; + + switch (_IOC_NR(cmd)) { + case IO_LEDACTIVE_SET: + green = ((unsigned char) arg) & 1; + red = (((unsigned char) arg) >> 1) & 1; + CRIS_LED_ACTIVE_SET_G(green); + CRIS_LED_ACTIVE_SET_R(red); + break; + + default: + return -EINVAL; + } /* switch */ + + return 0; +} + +static const struct file_operations gpio_fops = { + .owner = THIS_MODULE, + .poll = gpio_poll, + .unlocked_ioctl = gpio_ioctl, + .write = gpio_write, + .open = gpio_open, + .release = gpio_release, + .llseek = noop_llseek, +}; + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +static void +virtual_gpio_init(void) +{ + reg_gio_rw_intr_cfg intr_cfg; + reg_gio_rw_intr_mask intr_mask; + unsigned short shadow; + + shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */ + shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT; + i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow)); + + /* Set interrupt mask and on what state the interrupt shall trigger. + * For virtual gpio the interrupt shall trigger on logic '0'. + */ + intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg); + intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); + + switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) { + case 0: + intr_cfg.pa0 = regk_gio_lo; + intr_mask.pa0 = regk_gio_yes; + break; + case 1: + intr_cfg.pa1 = regk_gio_lo; + intr_mask.pa1 = regk_gio_yes; + break; + case 2: + intr_cfg.pa2 = regk_gio_lo; + intr_mask.pa2 = regk_gio_yes; + break; + case 3: + intr_cfg.pa3 = regk_gio_lo; + intr_mask.pa3 = regk_gio_yes; + break; + case 4: + intr_cfg.pa4 = regk_gio_lo; + intr_mask.pa4 = regk_gio_yes; + break; + case 5: + intr_cfg.pa5 = regk_gio_lo; + intr_mask.pa5 = regk_gio_yes; + break; + case 6: + intr_cfg.pa6 = regk_gio_lo; + intr_mask.pa6 = regk_gio_yes; + break; + case 7: + intr_cfg.pa7 = regk_gio_lo; + intr_mask.pa7 = regk_gio_yes; + break; + } + + REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg); + REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); + + gpio_pa_low_alarms |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN); + gpio_some_alarms = 1; +} +#endif + +/* main driver initialization routine, called from mem.c */ + +static __init int +gpio_init(void) +{ + int res; + + /* do the formalities */ + + res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops); + if (res < 0) { + printk(KERN_ERR "gpio: couldn't get a major number.\n"); + return res; + } + + /* Clear all leds */ + CRIS_LED_NETWORK_GRP0_SET(0); + CRIS_LED_NETWORK_GRP1_SET(0); + CRIS_LED_ACTIVE_SET(0); + CRIS_LED_DISK_READ(0); + CRIS_LED_DISK_WRITE(0); + + printk(KERN_INFO "ETRAX FS GPIO driver v2.5, (c) 2003-2007 " + "Axis Communications AB\n"); + /* We call etrax_gpio_wake_up_check() from timer interrupt */ + if (request_irq(TIMER0_INTR_VECT, gpio_poll_timer_interrupt, + IRQF_SHARED, "gpio poll", &alarmlist)) + printk(KERN_ERR "timer0 irq for gpio\n"); + + if (request_irq(GIO_INTR_VECT, gpio_pa_interrupt, + IRQF_SHARED, "gpio PA", &alarmlist)) + printk(KERN_ERR "PA irq for gpio\n"); + +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + virtual_gpio_init(); +#endif + + return res; +} + +/* this makes sure that gpio_init is called during kernel boot */ + +module_init(gpio_init); diff --git a/kernel/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/kernel/arch/cris/arch-v32/drivers/mach-fs/nandflash.c new file mode 100644 index 000000000..e03238454 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/mach-fs/nandflash.c @@ -0,0 +1,174 @@ +/* + * arch/cris/arch-v32/drivers/nandflash.c + * + * Copyright (c) 2004 + * + * Derived from drivers/mtd/nand/spia.c + * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CE_BIT 4 +#define CLE_BIT 5 +#define ALE_BIT 6 +#define BY_BIT 7 + +struct mtd_info_wrapper { + struct mtd_info info; + struct nand_chip chip; +}; + +/* Bitmask for control pins */ +#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT)) + +/* Bitmask for mtd nand control bits */ +#define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE) + + +static struct mtd_info *crisv32_mtd; +/* + * hardware specific access to control-lines + */ +static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + unsigned long flags; + reg_gio_rw_pa_dout dout; + struct nand_chip *this = mtd->priv; + + local_irq_save(flags); + + /* control bits change */ + if (ctrl & NAND_CTRL_CHANGE) { + dout = REG_RD(gio, regi_gio, rw_pa_dout); + dout.data &= ~PIN_BITMASK; + +#if (CE_BIT == 4 && NAND_NCE == 1 && \ + CLE_BIT == 5 && NAND_CLE == 2 && \ + ALE_BIT == 6 && NAND_ALE == 4) + /* Pins in same order as control bits, but shifted. + * Optimize for this case; works for 2.6.18 */ + dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT; +#else + /* the slow way */ + if (!(ctrl & NAND_NCE)) + dout.data |= (1 << CE_BIT); + if (ctrl & NAND_CLE) + dout.data |= (1 << CLE_BIT); + if (ctrl & NAND_ALE) + dout.data |= (1 << ALE_BIT); +#endif + REG_WR(gio, regi_gio, rw_pa_dout, dout); + } + + /* command to chip */ + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); + + local_irq_restore(flags); +} + +/* +* read device ready pin +*/ +static int crisv32_device_ready(struct mtd_info *mtd) +{ + reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din); + return ((din.data & (1 << BY_BIT)) >> BY_BIT); +} + +/* + * Main initialization routine + */ +struct mtd_info *__init crisv32_nand_flash_probe(void) +{ + void __iomem *read_cs; + void __iomem *write_cs; + + reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, + rw_grp3_cfg); + reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); + struct mtd_info_wrapper *wrapper; + struct nand_chip *this; + int err = 0; + + /* Allocate memory for MTD device structure and private data */ + wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL); + if (!wrapper) { + printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD " + "device structure.\n"); + err = -ENOMEM; + return NULL; + } + + read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192); + write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192); + + if (!read_cs || !write_cs) { + printk(KERN_ERR "CRISv32 NAND ioremap failed\n"); + err = -EIO; + goto out_mtd; + } + + /* Get pointer to private data */ + this = &wrapper->chip; + crisv32_mtd = &wrapper->info; + + pa_oe.oe |= 1 << CE_BIT; + pa_oe.oe |= 1 << ALE_BIT; + pa_oe.oe |= 1 << CLE_BIT; + pa_oe.oe &= ~(1 << BY_BIT); + REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); + + bif_cfg.gated_csp0 = regk_bif_core_rd; + bif_cfg.gated_csp1 = regk_bif_core_wr; + REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); + + /* Link the private data with the MTD structure */ + crisv32_mtd->priv = this; + + /* Set address of NAND IO lines */ + this->IO_ADDR_R = read_cs; + this->IO_ADDR_W = write_cs; + this->cmd_ctrl = crisv32_hwcontrol; + this->dev_ready = crisv32_device_ready; + /* 20 us command delay time */ + this->chip_delay = 20; + this->ecc.mode = NAND_ECC_SOFT; + + /* Enable the following for a flash based bad block table */ + /* this->bbt_options = NAND_BBT_USE_FLASH; */ + + /* Scan to find existence of the device */ + if (nand_scan(crisv32_mtd, 1)) { + err = -ENXIO; + goto out_ior; + } + + return crisv32_mtd; + +out_ior: + iounmap((void *)read_cs); + iounmap((void *)write_cs); +out_mtd: + kfree(wrapper); + return NULL; +} + diff --git a/kernel/arch/cris/arch-v32/drivers/pci/Makefile b/kernel/arch/cris/arch-v32/drivers/pci/Makefile new file mode 100644 index 000000000..bff7482f2 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/pci/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for Etrax cardbus driver +# + +obj-$(CONFIG_ETRAX_CARDBUS) += bios.o dma.o diff --git a/kernel/arch/cris/arch-v32/drivers/pci/bios.c b/kernel/arch/cris/arch-v32/drivers/pci/bios.c new file mode 100644 index 000000000..64a5fb937 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/pci/bios.c @@ -0,0 +1,99 @@ +#include +#include +#include + +void pcibios_fixup_bus(struct pci_bus *b) +{ +} + +void pcibios_set_master(struct pci_dev *dev) +{ + u8 lat; + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); +} + +int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine) +{ + unsigned long prot; + + /* Leave vm_pgoff as-is, the PCI space address is the physical + * address on this platform. + */ + prot = pgprot_val(vma->vm_page_prot); + vma->vm_page_prot = __pgprot(prot); + + /* Write-combine setting is ignored, it is changed via the mtrr + * interfaces on this platform. + */ + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) + return -EAGAIN; + + return 0; +} + +resource_size_t +pcibios_align_resource(void *data, const struct resource *res, + resource_size_t size, resource_size_t align) +{ + resource_size_t start = res->start; + + if ((res->flags & IORESOURCE_IO) && (start & 0x300)) + start = (start + 0x3ff) & ~0x3ff; + + return start; +} + +int pcibios_enable_resources(struct pci_dev *dev, int mask) +{ + u16 cmd, old_cmd; + int idx; + struct resource *r; + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + old_cmd = cmd; + for(idx=0; idx<6; idx++) { + /* Only set up the requested stuff */ + if (!(mask & (1<resource[idx]; + if (!r->start && r->end) { + printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + if (dev->resource[PCI_ROM_RESOURCE].start) + cmd |= PCI_COMMAND_MEMORY; + if (cmd != old_cmd) { + printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd); + } + return 0; +} + +int pcibios_enable_irq(struct pci_dev *dev) +{ + dev->irq = EXT_INTR_VECT; + return 0; +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + int err; + + if ((err = pcibios_enable_resources(dev, mask)) < 0) + return err; + + if (!dev->msi_enabled) + pcibios_enable_irq(dev); + return 0; +} diff --git a/kernel/arch/cris/arch-v32/drivers/pci/dma.c b/kernel/arch/cris/arch-v32/drivers/pci/dma.c new file mode 100644 index 000000000..ee55578d9 --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/pci/dma.c @@ -0,0 +1,50 @@ +/* + * Dynamic DMA mapping support. + * + * On cris there is no hardware dynamic DMA address translation, + * so consistent alloc/free are merely page allocation/freeing. + * The rest of the dynamic DMA mapping interface is implemented + * in asm/pci.h. + * + * Borrowed from i386. + */ + +#include +#include +#include +#include +#include +#include + +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t gfp) +{ + void *ret; + int order = get_order(size); + /* ignore region specifiers */ + gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); + + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) + return ret; + + if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff)) + gfp |= GFP_DMA; + + ret = (void *)__get_free_pages(gfp, order); + + if (ret != NULL) { + memset(ret, 0, size); + *dma_handle = virt_to_phys(ret); + } + return ret; +} + +void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + int order = get_order(size); + + if (!dma_release_from_coherent(dev, order, vaddr)) + free_pages((unsigned long)vaddr, order); +} + diff --git a/kernel/arch/cris/arch-v32/drivers/sync_serial.c b/kernel/arch/cris/arch-v32/drivers/sync_serial.c new file mode 100644 index 000000000..4dda9bd6b --- /dev/null +++ b/kernel/arch/cris/arch-v32/drivers/sync_serial.c @@ -0,0 +1,1709 @@ +/* + * Simple synchronous serial port driver for ETRAX FS and ARTPEC-3. + * + * Copyright (c) 2005, 2008 Axis Communications AB + * Author: Mikael Starvik + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* The receiver is a bit tricky because of the continuous stream of data.*/ +/* */ +/* Three DMA descriptors are linked together. Each DMA descriptor is */ +/* responsible for port->bufchunk of a common buffer. */ +/* */ +/* +---------------------------------------------+ */ +/* | +----------+ +----------+ +----------+ | */ +/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */ +/* +----------+ +----------+ +----------+ */ +/* | | | */ +/* v v v */ +/* +-------------------------------------+ */ +/* | BUFFER | */ +/* +-------------------------------------+ */ +/* |<- data_avail ->| */ +/* readp writep */ +/* */ +/* If the application keeps up the pace readp will be right after writep.*/ +/* If the application can't keep the pace we have to throw away data. */ +/* The idea is that readp should be ready with the data pointed out by */ +/* Descr[i] when the DMA has filled in Descr[i+1]. */ +/* Otherwise we will discard */ +/* the rest of the data pointed out by Descr1 and set readp to the start */ +/* of Descr2 */ + +/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ +/* words can be handled */ +#define IN_DESCR_SIZE SSP_INPUT_CHUNK_SIZE +#define NBR_IN_DESCR (8*6) +#define IN_BUFFER_SIZE (IN_DESCR_SIZE * NBR_IN_DESCR) + +#define NBR_OUT_DESCR 8 +#define OUT_BUFFER_SIZE (1024 * NBR_OUT_DESCR) + +#define DEFAULT_FRAME_RATE 0 +#define DEFAULT_WORD_RATE 7 + +/* To be removed when we move to pure udev. */ +#define SYNC_SERIAL_MAJOR 125 + +/* NOTE: Enabling some debug will likely cause overrun or underrun, + * especially if manual mode is used. + */ +#define DEBUG(x) +#define DEBUGREAD(x) +#define DEBUGWRITE(x) +#define DEBUGPOLL(x) +#define DEBUGRXINT(x) +#define DEBUGTXINT(x) +#define DEBUGTRDMA(x) +#define DEBUGOUTBUF(x) + +enum syncser_irq_setup { + no_irq_setup = 0, + dma_irq_setup = 1, + manual_irq_setup = 2, +}; + +struct sync_port { + unsigned long regi_sser; + unsigned long regi_dmain; + unsigned long regi_dmaout; + + /* Interrupt vectors. */ + unsigned long dma_in_intr_vect; /* Used for DMA in. */ + unsigned long dma_out_intr_vect; /* Used for DMA out. */ + unsigned long syncser_intr_vect; /* Used when no DMA. */ + + /* DMA number for in and out. */ + unsigned int dma_in_nbr; + unsigned int dma_out_nbr; + + /* DMA owner. */ + enum dma_owner req_dma; + + char started; /* 1 if port has been started */ + char port_nbr; /* Port 0 or 1 */ + char busy; /* 1 if port is busy */ + + char enabled; /* 1 if port is enabled */ + char use_dma; /* 1 if port uses dma */ + char tr_running; + + enum syncser_irq_setup init_irqs; + int output; + int input; + + /* Next byte to be read by application */ + unsigned char *readp; + /* Next byte to be written by etrax */ + unsigned char *writep; + + unsigned int in_buffer_size; + unsigned int in_buffer_len; + unsigned int inbufchunk; + /* Data buffers for in and output. */ + unsigned char out_buffer[OUT_BUFFER_SIZE] __aligned(32); + unsigned char in_buffer[IN_BUFFER_SIZE] __aligned(32); + unsigned char flip[IN_BUFFER_SIZE] __aligned(32); + struct timespec timestamp[NBR_IN_DESCR]; + struct dma_descr_data *next_rx_desc; + struct dma_descr_data *prev_rx_desc; + + struct timeval last_timestamp; + int read_ts_idx; + int write_ts_idx; + + /* Pointer to the first available descriptor in the ring, + * unless active_tr_descr == catch_tr_descr and a dma + * transfer is active */ + struct dma_descr_data *active_tr_descr; + + /* Pointer to the first allocated descriptor in the ring */ + struct dma_descr_data *catch_tr_descr; + + /* Pointer to the descriptor with the current end-of-list */ + struct dma_descr_data *prev_tr_descr; + int full; + + /* Pointer to the first byte being read by DMA + * or current position in out_buffer if not using DMA. */ + unsigned char *out_rd_ptr; + + /* Number of bytes currently locked for being read by DMA */ + int out_buf_count; + + dma_descr_context in_context __aligned(32); + dma_descr_context out_context __aligned(32); + dma_descr_data in_descr[NBR_IN_DESCR] __aligned(16); + dma_descr_data out_descr[NBR_OUT_DESCR] __aligned(16); + + wait_queue_head_t out_wait_q; + wait_queue_head_t in_wait_q; + + spinlock_t lock; +}; + +static DEFINE_MUTEX(sync_serial_mutex); +static int etrax_sync_serial_init(void); +static void initialize_port(int portnbr); +static inline int sync_data_avail(struct sync_port *port); + +static int sync_serial_open(struct inode *, struct file *); +static int sync_serial_release(struct inode *, struct file *); +static unsigned int sync_serial_poll(struct file *filp, poll_table *wait); + +static long sync_serial_ioctl(struct file *file, + unsigned int cmd, unsigned long arg); +static int sync_serial_ioctl_unlocked(struct file *file, + unsigned int cmd, unsigned long arg); +static ssize_t sync_serial_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos); +static ssize_t sync_serial_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos); + +#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ + defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ + (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ + defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) +#define SYNC_SER_DMA +#else +#define SYNC_SER_MANUAL +#endif + +#ifdef SYNC_SER_DMA +static void start_dma_out(struct sync_port *port, const char *data, int count); +static void start_dma_in(struct sync_port *port); +static irqreturn_t tr_interrupt(int irq, void *dev_id); +static irqreturn_t rx_interrupt(int irq, void *dev_id); +#endif +#ifdef SYNC_SER_MANUAL +static void send_word(struct sync_port *port); +static irqreturn_t manual_interrupt(int irq, void *dev_id); +#endif + +#define artpec_pinmux_alloc_fixed crisv32_pinmux_alloc_fixed +#define artpec_request_dma crisv32_request_dma +#define artpec_free_dma crisv32_free_dma + +#ifdef CONFIG_ETRAXFS +/* ETRAX FS */ +#define DMA_OUT_NBR0 SYNC_SER0_TX_DMA_NBR +#define DMA_IN_NBR0 SYNC_SER0_RX_DMA_NBR +#define DMA_OUT_NBR1 SYNC_SER1_TX_DMA_NBR +#define DMA_IN_NBR1 SYNC_SER1_RX_DMA_NBR +#define PINMUX_SSER0 pinmux_sser0 +#define PINMUX_SSER1 pinmux_sser1 +#define SYNCSER_INST0 regi_sser0 +#define SYNCSER_INST1 regi_sser1 +#define SYNCSER_INTR_VECT0 SSER0_INTR_VECT +#define SYNCSER_INTR_VECT1 SSER1_INTR_VECT +#define OUT_DMA_INST0 regi_dma4 +#define IN_DMA_INST0 regi_dma5 +#define DMA_OUT_INTR_VECT0 DMA4_INTR_VECT +#define DMA_OUT_INTR_VECT1 DMA7_INTR_VECT +#define DMA_IN_INTR_VECT0 DMA5_INTR_VECT +#define DMA_IN_INTR_VECT1 DMA6_INTR_VECT +#define REQ_DMA_SYNCSER0 dma_sser0 +#define REQ_DMA_SYNCSER1 dma_sser1 +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) +#define PORT1_DMA 1 +#else +#define PORT1_DMA 0 +#endif +#elif defined(CONFIG_CRIS_MACH_ARTPEC3) +/* ARTPEC-3 */ +#define DMA_OUT_NBR0 SYNC_SER_TX_DMA_NBR +#define DMA_IN_NBR0 SYNC_SER_RX_DMA_NBR +#define PINMUX_SSER0 pinmux_sser +#define SYNCSER_INST0 regi_sser +#define SYNCSER_INTR_VECT0 SSER_INTR_VECT +#define OUT_DMA_INST0 regi_dma6 +#define IN_DMA_INST0 regi_dma7 +#define DMA_OUT_INTR_VECT0 DMA6_INTR_VECT +#define DMA_IN_INTR_VECT0 DMA7_INTR_VECT +#define REQ_DMA_SYNCSER0 dma_sser +#define REQ_DMA_SYNCSER1 dma_sser +#endif + +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) +#define PORT0_DMA 1 +#else +#define PORT0_DMA 0 +#endif + +/* The ports */ +static struct sync_port ports[] = { + { + .regi_sser = SYNCSER_INST0, + .regi_dmaout = OUT_DMA_INST0, + .regi_dmain = IN_DMA_INST0, + .use_dma = PORT0_DMA, + .dma_in_intr_vect = DMA_IN_INTR_VECT0, + .dma_out_intr_vect = DMA_OUT_INTR_VECT0, + .dma_in_nbr = DMA_IN_NBR0, + .dma_out_nbr = DMA_OUT_NBR0, + .req_dma = REQ_DMA_SYNCSER0, + .syncser_intr_vect = SYNCSER_INTR_VECT0, + }, +#ifdef CONFIG_ETRAXFS + { + .regi_sser = SYNCSER_INST1, + .regi_dmaout = regi_dma6, + .regi_dmain = regi_dma7, + .use_dma = PORT1_DMA, + .dma_in_intr_vect = DMA_IN_INTR_VECT1, + .dma_out_intr_vect = DMA_OUT_INTR_VECT1, + .dma_in_nbr = DMA_IN_NBR1, + .dma_out_nbr = DMA_OUT_NBR1, + .req_dma = REQ_DMA_SYNCSER1, + .syncser_intr_vect = SYNCSER_INTR_VECT1, + }, +#endif +}; + +#define NBR_PORTS ARRAY_SIZE(ports) + +static const struct file_operations syncser_fops = { + .owner = THIS_MODULE, + .write = sync_serial_write, + .read = sync_serial_read, + .poll = sync_serial_poll, + .unlocked_ioctl = sync_serial_ioctl, + .open = sync_serial_open, + .release = sync_serial_release, + .llseek = noop_llseek, +}; + +static dev_t syncser_first; +static int minor_count = NBR_PORTS; +#define SYNCSER_NAME "syncser" +static struct cdev *syncser_cdev; +static struct class *syncser_class; + +static void sync_serial_start_port(struct sync_port *port) +{ + reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); + reg_sser_rw_tr_cfg tr_cfg = + REG_RD(sser, port->regi_sser, rw_tr_cfg); + reg_sser_rw_rec_cfg rec_cfg = + REG_RD(sser, port->regi_sser, rw_rec_cfg); + cfg.en = regk_sser_yes; + tr_cfg.tr_en = regk_sser_yes; + rec_cfg.rec_en = regk_sser_yes; + REG_WR(sser, port->regi_sser, rw_cfg, cfg); + REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); + REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); + port->started = 1; +} + +static void __init initialize_port(int portnbr) +{ + struct sync_port *port = &ports[portnbr]; + reg_sser_rw_cfg cfg = { 0 }; + reg_sser_rw_frm_cfg frm_cfg = { 0 }; + reg_sser_rw_tr_cfg tr_cfg = { 0 }; + reg_sser_rw_rec_cfg rec_cfg = { 0 }; + + DEBUG(pr_info("Init sync serial port %d\n", portnbr)); + + port->port_nbr = portnbr; + port->init_irqs = no_irq_setup; + + port->out_rd_ptr = port->out_buffer; + port->out_buf_count = 0; + + port->output = 1; + port->input = 0; + + port->readp = port->flip; + port->writep = port->flip; + port->in_buffer_size = IN_BUFFER_SIZE; + port->in_buffer_len = 0; + port->inbufchunk = IN_DESCR_SIZE; + + port->read_ts_idx = 0; + port->write_ts_idx = 0; + + init_waitqueue_head(&port->out_wait_q); + init_waitqueue_head(&port->in_wait_q); + + spin_lock_init(&port->lock); + + cfg.out_clk_src = regk_sser_intern_clk; + cfg.out_clk_pol = regk_sser_pos; + cfg.clk_od_mode = regk_sser_no; + cfg.clk_dir = regk_sser_out; + cfg.gate_clk = regk_sser_no; + cfg.base_freq = regk_sser_f29_493; + cfg.clk_div = 256; + REG_WR(sser, port->regi_sser, rw_cfg, cfg); + + frm_cfg.wordrate = DEFAULT_WORD_RATE; + frm_cfg.type = regk_sser_edge; + frm_cfg.frame_pin_dir = regk_sser_out; + frm_cfg.frame_pin_use = regk_sser_frm; + frm_cfg.status_pin_dir = regk_sser_in; + frm_cfg.status_pin_use = regk_sser_hold; + frm_cfg.out_on = regk_sser_tr; + frm_cfg.tr_delay = 1; + REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); + + tr_cfg.urun_stop = regk_sser_no; + tr_cfg.sample_size = 7; + tr_cfg.sh_dir = regk_sser_msbfirst; + tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no; +#if 0 + tr_cfg.rate_ctrl = regk_sser_bulk; + tr_cfg.data_pin_use = regk_sser_dout; +#else + tr_cfg.rate_ctrl = regk_sser_iso; + tr_cfg.data_pin_use = regk_sser_dout; +#endif + tr_cfg.bulk_wspace = 1; + REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); + + rec_cfg.sample_size = 7; + rec_cfg.sh_dir = regk_sser_msbfirst; + rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no; + rec_cfg.fifo_thr = regk_sser_inf; + REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); + +#ifdef SYNC_SER_DMA + { + int i; + /* Setup the descriptor ring for dma out/transmit. */ + for (i = 0; i < NBR_OUT_DESCR; i++) { + dma_descr_data *descr = &port->out_descr[i]; + descr->wait = 0; + descr->intr = 1; + descr->eol = 0; + descr->out_eop = 0; + descr->next = + (dma_descr_data *)virt_to_phys(&descr[i+1]); + } + } + + /* Create a ring from the list. */ + port->out_descr[NBR_OUT_DESCR-1].next = + (dma_descr_data *)virt_to_phys(&port->out_descr[0]); + + /* Setup context for traversing the ring. */ + port->active_tr_descr = &port->out_descr[0]; + port->prev_tr_descr = &port->out_descr[NBR_OUT_DESCR-1]; + port->catch_tr_descr = &port->out_descr[0]; +#endif +} + +static inline int sync_data_avail(struct sync_port *port) +{ + return port->in_buffer_len; +} + +static int sync_serial_open(struct inode *inode, struct file *file) +{ + int ret = 0; + int dev = iminor(inode); + struct sync_port *port; +#ifdef SYNC_SER_DMA + reg_dma_rw_cfg cfg = { .en = regk_dma_yes }; + reg_dma_rw_intr_mask intr_mask = { .data = regk_dma_yes }; +#endif + + DEBUG(pr_debug("Open sync serial port %d\n", dev)); + + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { + DEBUG(pr_info("Invalid minor %d\n", dev)); + return -ENODEV; + } + port = &ports[dev]; + /* Allow open this device twice (assuming one reader and one writer) */ + if (port->busy == 2) { + DEBUG(pr_info("syncser%d is busy\n", dev)); + return -EBUSY; + } + + mutex_lock(&sync_serial_mutex); + + /* Clear any stale date left in the flip buffer */ + port->readp = port->writep = port->flip; + port->in_buffer_len = 0; + port->read_ts_idx = 0; + port->write_ts_idx = 0; + + if (port->init_irqs != no_irq_setup) { + /* Init only on first call. */ + port->busy++; + mutex_unlock(&sync_serial_mutex); + return 0; + } + if (port->use_dma) { +#ifdef SYNC_SER_DMA + const char *tmp; + DEBUG(pr_info("Using DMA for syncser%d\n", dev)); + + tmp = dev == 0 ? "syncser0 tx" : "syncser1 tx"; + if (request_irq(port->dma_out_intr_vect, tr_interrupt, 0, + tmp, port)) { + pr_err("Can't alloc syncser%d TX IRQ", dev); + ret = -EBUSY; + goto unlock_and_exit; + } + if (artpec_request_dma(port->dma_out_nbr, tmp, + DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) { + free_irq(port->dma_out_intr_vect, port); + pr_err("Can't alloc syncser%d TX DMA", dev); + ret = -EBUSY; + goto unlock_and_exit; + } + tmp = dev == 0 ? "syncser0 rx" : "syncser1 rx"; + if (request_irq(port->dma_in_intr_vect, rx_interrupt, 0, + tmp, port)) { + artpec_free_dma(port->dma_out_nbr); + free_irq(port->dma_out_intr_vect, port); + pr_err("Can't alloc syncser%d RX IRQ", dev); + ret = -EBUSY; + goto unlock_and_exit; + } + if (artpec_request_dma(port->dma_in_nbr, tmp, + DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) { + artpec_free_dma(port->dma_out_nbr); + free_irq(port->dma_out_intr_vect, port); + free_irq(port->dma_in_intr_vect, port); + pr_err("Can't alloc syncser%d RX DMA", dev); + ret = -EBUSY; + goto unlock_and_exit; + } + /* Enable DMAs */ + REG_WR(dma, port->regi_dmain, rw_cfg, cfg); + REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); + /* Enable DMA IRQs */ + REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); + REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask); + /* Set up wordsize = 1 for DMAs. */ + DMA_WR_CMD(port->regi_dmain, regk_dma_set_w_size1); + DMA_WR_CMD(port->regi_dmaout, regk_dma_set_w_size1); + + start_dma_in(port); + port->init_irqs = dma_irq_setup; +#endif + } else { /* !port->use_dma */ +#ifdef SYNC_SER_MANUAL + const char *tmp = dev == 0 ? "syncser0 manual irq" : + "syncser1 manual irq"; + if (request_irq(port->syncser_intr_vect, manual_interrupt, + 0, tmp, port)) { + pr_err("Can't alloc syncser%d manual irq", + dev); + ret = -EBUSY; + goto unlock_and_exit; + } + port->init_irqs = manual_irq_setup; +#else + panic("sync_serial: Manual mode not supported\n"); +#endif /* SYNC_SER_MANUAL */ + } + port->busy++; + ret = 0; + +unlock_and_exit: + mutex_unlock(&sync_serial_mutex); + return ret; +} + +static int sync_serial_release(struct inode *inode, struct file *file) +{ + int dev = iminor(inode); + struct sync_port *port; + + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { + DEBUG(pr_info("Invalid minor %d\n", dev)); + return -ENODEV; + } + port = &ports[dev]; + if (port->busy) + port->busy--; + if (!port->busy) + /* XXX */; + return 0; +} + +static unsigned int sync_serial_poll(struct file *file, poll_table *wait) +{ + int dev = iminor(file_inode(file)); + unsigned int mask = 0; + struct sync_port *port; + DEBUGPOLL( + static unsigned int prev_mask; + ); + + port = &ports[dev]; + + if (!port->started) + sync_serial_start_port(port); + + poll_wait(file, &port->out_wait_q, wait); + poll_wait(file, &port->in_wait_q, wait); + + /* No active transfer, descriptors are available */ + if (port->output && !port->tr_running) + mask |= POLLOUT | POLLWRNORM; + + /* Descriptor and buffer space available. */ + if (port->output && + port->active_tr_descr != port->catch_tr_descr && + port->out_buf_count < OUT_BUFFER_SIZE) + mask |= POLLOUT | POLLWRNORM; + + /* At least an inbufchunk of data */ + if (port->input && sync_data_avail(port) >= port->inbufchunk) + mask |= POLLIN | POLLRDNORM; + + DEBUGPOLL( + if (mask != prev_mask) + pr_info("sync_serial_poll: mask 0x%08X %s %s\n", + mask, + mask & POLLOUT ? "POLLOUT" : "", + mask & POLLIN ? "POLLIN" : ""); + prev_mask = mask; + ); + return mask; +} + +static ssize_t __sync_serial_read(struct file *file, + char __user *buf, + size_t count, + loff_t *ppos, + struct timespec *ts) +{ + unsigned long flags; + int dev = MINOR(file_inode(file)->i_rdev); + int avail; + struct sync_port *port; + unsigned char *start; + unsigned char *end; + + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { + DEBUG(pr_info("Invalid minor %d\n", dev)); + return -ENODEV; + } + port = &ports[dev]; + + if (!port->started) + sync_serial_start_port(port); + + /* Calculate number of available bytes */ + /* Save pointers to avoid that they are modified by interrupt */ + spin_lock_irqsave(&port->lock, flags); + start = port->readp; + end = port->writep; + spin_unlock_irqrestore(&port->lock, flags); + + while ((start == end) && !port->in_buffer_len) { + if (file->f_flags & O_NONBLOCK) + return -EAGAIN; + + wait_event_interruptible(port->in_wait_q, + !(start == end && !port->full)); + + if (signal_pending(current)) + return -EINTR; + + spin_lock_irqsave(&port->lock, flags); + start = port->readp; + end = port->writep; + spin_unlock_irqrestore(&port->lock, flags); + } + + DEBUGREAD(pr_info("R%d c %d ri %u wi %u /%u\n", + dev, count, + start - port->flip, end - port->flip, + port->in_buffer_size)); + + /* Lazy read, never return wrapped data. */ + if (end > start) + avail = end - start; + else + avail = port->flip + port->in_buffer_size - start; + + count = count > avail ? avail : count; + if (copy_to_user(buf, start, count)) + return -EFAULT; + + /* If timestamp requested, find timestamp of first returned byte + * and copy it. + * N.B: Applications that request timstamps MUST read data in + * chunks that are multiples of IN_DESCR_SIZE. + * Otherwise the timestamps will not be aligned to the data read. + */ + if (ts != NULL) { + int idx = port->read_ts_idx; + memcpy(ts, &port->timestamp[idx], sizeof(struct timespec)); + port->read_ts_idx += count / IN_DESCR_SIZE; + if (port->read_ts_idx >= NBR_IN_DESCR) + port->read_ts_idx = 0; + } + + spin_lock_irqsave(&port->lock, flags); + port->readp += count; + /* Check for wrap */ + if (port->readp >= port->flip + port->in_buffer_size) + port->readp = port->flip; + port->in_buffer_len -= count; + port->full = 0; + spin_unlock_irqrestore(&port->lock, flags); + + DEBUGREAD(pr_info("r %d\n", count)); + + return count; +} + +static ssize_t sync_serial_input(struct file *file, unsigned long arg) +{ + struct ssp_request req; + int count; + int ret; + + /* Copy the request structure from user-mode. */ + ret = copy_from_user(&req, (struct ssp_request __user *)arg, + sizeof(struct ssp_request)); + + if (ret) { + DEBUG(pr_info("sync_serial_input copy from user failed\n")); + return -EFAULT; + } + + /* To get the timestamps aligned, make sure that 'len' + * is a multiple of IN_DESCR_SIZE. + */ + if ((req.len % IN_DESCR_SIZE) != 0) { + DEBUG(pr_info("sync_serial: req.len %x, IN_DESCR_SIZE %x\n", + req.len, IN_DESCR_SIZE)); + return -EFAULT; + } + + /* Do the actual read. */ + /* Note that req.buf is actually a pointer to user space. */ + count = __sync_serial_read(file, req.buf, req.len, + NULL, &req.ts); + + if (count < 0) { + DEBUG(pr_info("sync_serial_input read failed\n")); + return count; + } + + /* Copy the request back to user-mode. */ + ret = copy_to_user((struct ssp_request __user *)arg, &req, + sizeof(struct ssp_request)); + + if (ret) { + DEBUG(pr_info("syncser input copy2user failed\n")); + return -EFAULT; + } + + /* Return the number of bytes read. */ + return count; +} + + +static int sync_serial_ioctl_unlocked(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int return_val = 0; + int dma_w_size = regk_dma_set_w_size1; + int dev = iminor(file_inode(file)); + struct sync_port *port; + reg_sser_rw_tr_cfg tr_cfg; + reg_sser_rw_rec_cfg rec_cfg; + reg_sser_rw_frm_cfg frm_cfg; + reg_sser_rw_cfg gen_cfg; + reg_sser_rw_intr_mask intr_mask; + + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { + DEBUG(pr_info("Invalid minor %d\n", dev)); + return -1; + } + + if (cmd == SSP_INPUT) + return sync_serial_input(file, arg); + + port = &ports[dev]; + spin_lock_irq(&port->lock); + + tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); + rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); + frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg); + gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg); + intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); + + switch (cmd) { + case SSP_SPEED: + if (GET_SPEED(arg) == CODEC) { + unsigned int freq; + + gen_cfg.base_freq = regk_sser_f32; + + /* Clock divider will internally be + * gen_cfg.clk_div + 1. + */ + + freq = GET_FREQ(arg); + switch (freq) { + case FREQ_32kHz: + case FREQ_64kHz: + case FREQ_128kHz: + case FREQ_256kHz: + gen_cfg.clk_div = 125 * + (1 << (freq - FREQ_256kHz)) - 1; + break; + case FREQ_512kHz: + gen_cfg.clk_div = 62; + break; + case FREQ_1MHz: + case FREQ_2MHz: + case FREQ_4MHz: + gen_cfg.clk_div = 8 * (1 << freq) - 1; + break; + } + } else if (GET_SPEED(arg) == CODEC_f32768) { + gen_cfg.base_freq = regk_sser_f32_768; + switch (GET_FREQ(arg)) { + case FREQ_4096kHz: + gen_cfg.clk_div = 7; + break; + default: + spin_unlock_irq(&port->lock); + return -EINVAL; + } + } else { + gen_cfg.base_freq = regk_sser_f29_493; + switch (GET_SPEED(arg)) { + case SSP150: + gen_cfg.clk_div = 29493000 / (150 * 8) - 1; + break; + case SSP300: + gen_cfg.clk_div = 29493000 / (300 * 8) - 1; + break; + case SSP600: + gen_cfg.clk_div = 29493000 / (600 * 8) - 1; + break; + case SSP1200: + gen_cfg.clk_div = 29493000 / (1200 * 8) - 1; + break; + case SSP2400: + gen_cfg.clk_div = 29493000 / (2400 * 8) - 1; + break; + case SSP4800: + gen_cfg.clk_div = 29493000 / (4800 * 8) - 1; + break; + case SSP9600: + gen_cfg.clk_div = 29493000 / (9600 * 8) - 1; + break; + case SSP19200: + gen_cfg.clk_div = 29493000 / (19200 * 8) - 1; + break; + case SSP28800: + gen_cfg.clk_div = 29493000 / (28800 * 8) - 1; + break; + case SSP57600: + gen_cfg.clk_div = 29493000 / (57600 * 8) - 1; + break; + case SSP115200: + gen_cfg.clk_div = 29493000 / (115200 * 8) - 1; + break; + case SSP230400: + gen_cfg.clk_div = 29493000 / (230400 * 8) - 1; + break; + case SSP460800: + gen_cfg.clk_div = 29493000 / (460800 * 8) - 1; + break; + case SSP921600: + gen_cfg.clk_div = 29493000 / (921600 * 8) - 1; + break; + case SSP3125000: + gen_cfg.base_freq = regk_sser_f100; + gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1; + break; + + } + } + frm_cfg.wordrate = GET_WORD_RATE(arg); + + break; + case SSP_MODE: + switch (arg) { + case MASTER_OUTPUT: + port->output = 1; + port->input = 0; + frm_cfg.out_on = regk_sser_tr; + frm_cfg.frame_pin_dir = regk_sser_out; + gen_cfg.clk_dir = regk_sser_out; + break; + case SLAVE_OUTPUT: + port->output = 1; + port->input = 0; + frm_cfg.frame_pin_dir = regk_sser_in; + gen_cfg.clk_dir = regk_sser_in; + break; + case MASTER_INPUT: + port->output = 0; + port->input = 1; + frm_cfg.frame_pin_dir = regk_sser_out; + frm_cfg.out_on = regk_sser_intern_tb; + gen_cfg.clk_dir = regk_sser_out; + break; + case SLAVE_INPUT: + port->output = 0; + port->input = 1; + frm_cfg.frame_pin_dir = regk_sser_in; + gen_cfg.clk_dir = regk_sser_in; + break; + case MASTER_BIDIR: + port->output = 1; + port->input = 1; + frm_cfg.frame_pin_dir = regk_sser_out; + frm_cfg.out_on = regk_sser_intern_tb; + gen_cfg.clk_dir = regk_sser_out; + break; + case SLAVE_BIDIR: + port->output = 1; + port->input = 1; + frm_cfg.frame_pin_dir = regk_sser_in; + gen_cfg.clk_dir = regk_sser_in; + break; + default: + spin_unlock_irq(&port->lock); + return -EINVAL; + } + if (!port->use_dma || arg == MASTER_OUTPUT || + arg == SLAVE_OUTPUT) + intr_mask.rdav = regk_sser_yes; + break; + case SSP_FRAME_SYNC: + if (arg & NORMAL_SYNC) { + frm_cfg.rec_delay = 1; + frm_cfg.tr_delay = 1; + } else if (arg & EARLY_SYNC) + frm_cfg.rec_delay = frm_cfg.tr_delay = 0; + else if (arg & LATE_SYNC) { + frm_cfg.tr_delay = 2; + frm_cfg.rec_delay = 2; + } else if (arg & SECOND_WORD_SYNC) { + frm_cfg.rec_delay = 7; + frm_cfg.tr_delay = 1; + } + + tr_cfg.bulk_wspace = frm_cfg.tr_delay; + frm_cfg.early_wend = regk_sser_yes; + if (arg & BIT_SYNC) + frm_cfg.type = regk_sser_edge; + else if (arg & WORD_SYNC) + frm_cfg.type = regk_sser_level; + else if (arg & EXTENDED_SYNC) + frm_cfg.early_wend = regk_sser_no; + + if (arg & SYNC_ON) + frm_cfg.frame_pin_use = regk_sser_frm; + else if (arg & SYNC_OFF) + frm_cfg.frame_pin_use = regk_sser_gio0; + + dma_w_size = regk_dma_set_w_size2; + if (arg & WORD_SIZE_8) { + rec_cfg.sample_size = tr_cfg.sample_size = 7; + dma_w_size = regk_dma_set_w_size1; + } else if (arg & WORD_SIZE_12) + rec_cfg.sample_size = tr_cfg.sample_size = 11; + else if (arg & WORD_SIZE_16) + rec_cfg.sample_size = tr_cfg.sample_size = 15; + else if (arg & WORD_SIZE_24) + rec_cfg.sample_size = tr_cfg.sample_size = 23; + else if (arg & WORD_SIZE_32) + rec_cfg.sample_size = tr_cfg.sample_size = 31; + + if (arg & BIT_ORDER_MSB) + rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst; + else if (arg & BIT_ORDER_LSB) + rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst; + + if (arg & FLOW_CONTROL_ENABLE) { + frm_cfg.status_pin_use = regk_sser_frm; + rec_cfg.fifo_thr = regk_sser_thr16; + } else if (arg & FLOW_CONTROL_DISABLE) { + frm_cfg.status_pin_use = regk_sser_gio0; + rec_cfg.fifo_thr = regk_sser_inf; + } + + if (arg & CLOCK_NOT_GATED) + gen_cfg.gate_clk = regk_sser_no; + else if (arg & CLOCK_GATED) + gen_cfg.gate_clk = regk_sser_yes; + + break; + case SSP_IPOLARITY: + /* NOTE!! negedge is considered NORMAL */ + if (arg & CLOCK_NORMAL) + rec_cfg.clk_pol = regk_sser_neg; + else if (arg & CLOCK_INVERT) + rec_cfg.clk_pol = regk_sser_pos; + + if (arg & FRAME_NORMAL) + frm_cfg.level = regk_sser_pos_hi; + else if (arg & FRAME_INVERT) + frm_cfg.level = regk_sser_neg_lo; + + if (arg & STATUS_NORMAL) + gen_cfg.hold_pol = regk_sser_pos; + else if (arg & STATUS_INVERT) + gen_cfg.hold_pol = regk_sser_neg; + break; + case SSP_OPOLARITY: + if (arg & CLOCK_NORMAL) + gen_cfg.out_clk_pol = regk_sser_pos; + else if (arg & CLOCK_INVERT) + gen_cfg.out_clk_pol = regk_sser_neg; + + if (arg & FRAME_NORMAL) + frm_cfg.level = regk_sser_pos_hi; + else if (arg & FRAME_INVERT) + frm_cfg.level = regk_sser_neg_lo; + + if (arg & STATUS_NORMAL) + gen_cfg.hold_pol = regk_sser_pos; + else if (arg & STATUS_INVERT) + gen_cfg.hold_pol = regk_sser_neg; + break; + case SSP_SPI: + rec_cfg.fifo_thr = regk_sser_inf; + rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst; + rec_cfg.sample_size = tr_cfg.sample_size = 7; + frm_cfg.frame_pin_use = regk_sser_frm; + frm_cfg.type = regk_sser_level; + frm_cfg.tr_delay = 1; + frm_cfg.level = regk_sser_neg_lo; + if (arg & SPI_SLAVE) { + rec_cfg.clk_pol = regk_sser_neg; + gen_cfg.clk_dir = regk_sser_in; + port->input = 1; + port->output = 0; + } else { + gen_cfg.out_clk_pol = regk_sser_pos; + port->input = 0; + port->output = 1; + gen_cfg.clk_dir = regk_sser_out; + } + break; + case SSP_INBUFCHUNK: + break; + default: + return_val = -1; + } + + + if (port->started) { + rec_cfg.rec_en = port->input; + gen_cfg.en = (port->output | port->input); + } + + REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); + REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); + REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); + REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); + REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); + + + if (cmd == SSP_FRAME_SYNC && (arg & (WORD_SIZE_8 | WORD_SIZE_12 | + WORD_SIZE_16 | WORD_SIZE_24 | WORD_SIZE_32))) { + int en = gen_cfg.en; + gen_cfg.en = 0; + REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); + /* ##### Should DMA be stoped before we change dma size? */ + DMA_WR_CMD(port->regi_dmain, dma_w_size); + DMA_WR_CMD(port->regi_dmaout, dma_w_size); + gen_cfg.en = en; + REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); + } + + spin_unlock_irq(&port->lock); + return return_val; +} + +static long sync_serial_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + long ret; + + mutex_lock(&sync_serial_mutex); + ret = sync_serial_ioctl_unlocked(file, cmd, arg); + mutex_unlock(&sync_serial_mutex); + + return ret; +} + +/* NOTE: sync_serial_write does not support concurrency */ +static ssize_t sync_serial_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + int dev = iminor(file_inode(file)); + DECLARE_WAITQUEUE(wait, current); + struct sync_port *port; + int trunc_count; + unsigned long flags; + int bytes_free; + int out_buf_count; + + unsigned char *rd_ptr; /* First allocated byte in the buffer */ + unsigned char *wr_ptr; /* First free byte in the buffer */ + unsigned char *buf_stop_ptr; /* Last byte + 1 */ + + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { + DEBUG(pr_info("Invalid minor %d\n", dev)); + return -ENODEV; + } + port = &ports[dev]; + + /* |<- OUT_BUFFER_SIZE ->| + * |<- out_buf_count ->| + * |<- trunc_count ->| ...->| + * ______________________________________________________ + * | free | data | free | + * |_________|___________________|________________________| + * ^ rd_ptr ^ wr_ptr + */ + DEBUGWRITE(pr_info("W d%d c %u a: %p c: %p\n", + port->port_nbr, count, port->active_tr_descr, + port->catch_tr_descr)); + + /* Read variables that may be updated by interrupts */ + spin_lock_irqsave(&port->lock, flags); + rd_ptr = port->out_rd_ptr; + out_buf_count = port->out_buf_count; + spin_unlock_irqrestore(&port->lock, flags); + + /* Check if resources are available */ + if (port->tr_running && + ((port->use_dma && port->active_tr_descr == port->catch_tr_descr) || + out_buf_count >= OUT_BUFFER_SIZE)) { + DEBUGWRITE(pr_info("sser%d full\n", dev)); + return -EAGAIN; + } + + buf_stop_ptr = port->out_buffer + OUT_BUFFER_SIZE; + + /* Determine pointer to the first free byte, before copying. */ + wr_ptr = rd_ptr + out_buf_count; + if (wr_ptr >= buf_stop_ptr) + wr_ptr -= OUT_BUFFER_SIZE; + + /* If we wrap the ring buffer, let the user space program handle it by + * truncating the data. This could be more elegant, small buffer + * fragments may occur. + */ + bytes_free = OUT_BUFFER_SIZE - out_buf_count; + if (wr_ptr + bytes_free > buf_stop_ptr) + bytes_free = buf_stop_ptr - wr_ptr; + trunc_count = (count < bytes_free) ? count : bytes_free; + + if (copy_from_user(wr_ptr, buf, trunc_count)) + return -EFAULT; + + DEBUGOUTBUF(pr_info("%-4d + %-4d = %-4d %p %p %p\n", + out_buf_count, trunc_count, + port->out_buf_count, port->out_buffer, + wr_ptr, buf_stop_ptr)); + + /* Make sure transmitter/receiver is running */ + if (!port->started) { + reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); + reg_sser_rw_rec_cfg rec_cfg = + REG_RD(sser, port->regi_sser, rw_rec_cfg); + cfg.en = regk_sser_yes; + rec_cfg.rec_en = port->input; + REG_WR(sser, port->regi_sser, rw_cfg, cfg); + REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); + port->started = 1; + } + + /* Setup wait if blocking */ + if (!(file->f_flags & O_NONBLOCK)) { + add_wait_queue(&port->out_wait_q, &wait); + set_current_state(TASK_INTERRUPTIBLE); + } + + spin_lock_irqsave(&port->lock, flags); + port->out_buf_count += trunc_count; + if (port->use_dma) { +#ifdef SYNC_SER_DMA + start_dma_out(port, wr_ptr, trunc_count); +#endif + } else if (!port->tr_running) { +#ifdef SYNC_SER_MANUAL + reg_sser_rw_intr_mask intr_mask; + intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); + /* Start sender by writing data */ + send_word(port); + /* and enable transmitter ready IRQ */ + intr_mask.trdy = 1; + REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); +#endif + } + spin_unlock_irqrestore(&port->lock, flags); + + /* Exit if non blocking */ + if (file->f_flags & O_NONBLOCK) { + DEBUGWRITE(pr_info("w d%d c %u %08x\n", + port->port_nbr, trunc_count, + REG_RD_INT(dma, port->regi_dmaout, r_intr))); + return trunc_count; + } + + schedule(); + remove_wait_queue(&port->out_wait_q, &wait); + + if (signal_pending(current)) + return -EINTR; + + DEBUGWRITE(pr_info("w d%d c %u\n", port->port_nbr, trunc_count)); + return trunc_count; +} + +static ssize_t sync_serial_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + return __sync_serial_read(file, buf, count, ppos, NULL); +} + +#ifdef SYNC_SER_MANUAL +static void send_word(struct sync_port *port) +{ + reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); + reg_sser_rw_tr_data tr_data = {0}; + + switch (tr_cfg.sample_size) { + case 8: + port->out_buf_count--; + tr_data.data = *port->out_rd_ptr++; + REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); + if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) + port->out_rd_ptr = port->out_buffer; + break; + case 12: + { + int data = (*port->out_rd_ptr++) << 8; + data |= *port->out_rd_ptr++; + port->out_buf_count -= 2; + tr_data.data = data; + REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); + if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) + port->out_rd_ptr = port->out_buffer; + break; + } + case 16: + port->out_buf_count -= 2; + tr_data.data = *(unsigned short *)port->out_rd_ptr; + REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); + port->out_rd_ptr += 2; + if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) + port->out_rd_ptr = port->out_buffer; + break; + case 24: + port->out_buf_count -= 3; + tr_data.data = *(unsigned short *)port->out_rd_ptr; + REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); + port->out_rd_ptr += 2; + tr_data.data = *port->out_rd_ptr++; + REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); + if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) + port->out_rd_ptr = port->out_buffer; + break; + case 32: + port->out_buf_count -= 4; + tr_data.data = *(unsigned short *)port->out_rd_ptr; + REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); + port->out_rd_ptr += 2; + tr_data.data = *(unsigned short *)port->out_rd_ptr; + REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); + port->out_rd_ptr += 2; + if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) + port->out_rd_ptr = port->out_buffer; + break; + } +} +#endif + +#ifdef SYNC_SER_DMA +static void start_dma_out(struct sync_port *port, const char *data, int count) +{ + port->active_tr_descr->buf = (char *)virt_to_phys((char *)data); + port->active_tr_descr->after = port->active_tr_descr->buf + count; + port->active_tr_descr->intr = 1; + + port->active_tr_descr->eol = 1; + port->prev_tr_descr->eol = 0; + + DEBUGTRDMA(pr_info("Inserting eolr:%p eol@:%p\n", + port->prev_tr_descr, port->active_tr_descr)); + port->prev_tr_descr = port->active_tr_descr; + port->active_tr_descr = phys_to_virt((int)port->active_tr_descr->next); + + if (!port->tr_running) { + reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, + rw_tr_cfg); + + port->out_context.next = NULL; + port->out_context.saved_data = + (dma_descr_data *)virt_to_phys(port->prev_tr_descr); + port->out_context.saved_data_buf = port->prev_tr_descr->buf; + + DMA_START_CONTEXT(port->regi_dmaout, + virt_to_phys((char *)&port->out_context)); + + tr_cfg.tr_en = regk_sser_yes; + REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); + DEBUGTRDMA(pr_info("dma s\n");); + } else { + DMA_CONTINUE_DATA(port->regi_dmaout); + DEBUGTRDMA(pr_info("dma c\n");); + } + + port->tr_running = 1; +} + +static void start_dma_in(struct sync_port *port) +{ + int i; + char *buf; + unsigned long flags; + spin_lock_irqsave(&port->lock, flags); + port->writep = port->flip; + spin_unlock_irqrestore(&port->lock, flags); + + buf = (char *)virt_to_phys(port->in_buffer); + for (i = 0; i < NBR_IN_DESCR; i++) { + port->in_descr[i].buf = buf; + port->in_descr[i].after = buf + port->inbufchunk; + port->in_descr[i].intr = 1; + port->in_descr[i].next = + (dma_descr_data *)virt_to_phys(&port->in_descr[i+1]); + port->in_descr[i].buf = buf; + buf += port->inbufchunk; + } + /* Link the last descriptor to the first */ + port->in_descr[i-1].next = + (dma_descr_data *)virt_to_phys(&port->in_descr[0]); + port->in_descr[i-1].eol = regk_sser_yes; + port->next_rx_desc = &port->in_descr[0]; + port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR - 1]; + port->in_context.saved_data = + (dma_descr_data *)virt_to_phys(&port->in_descr[0]); + port->in_context.saved_data_buf = port->in_descr[0].buf; + DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context)); +} + +static irqreturn_t tr_interrupt(int irq, void *dev_id) +{ + reg_dma_r_masked_intr masked; + reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes }; + reg_dma_rw_stat stat; + int i; + int found = 0; + int stop_sser = 0; + + for (i = 0; i < NBR_PORTS; i++) { + struct sync_port *port = &ports[i]; + if (!port->enabled || !port->use_dma) + continue; + + /* IRQ active for the port? */ + masked = REG_RD(dma, port->regi_dmaout, r_masked_intr); + if (!masked.data) + continue; + + found = 1; + + /* Check if we should stop the DMA transfer */ + stat = REG_RD(dma, port->regi_dmaout, rw_stat); + if (stat.list_state == regk_dma_data_at_eol) + stop_sser = 1; + + /* Clear IRQ */ + REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr); + + if (!stop_sser) { + /* The DMA has completed a descriptor, EOL was not + * encountered, so step relevant descriptor and + * datapointers forward. */ + int sent; + sent = port->catch_tr_descr->after - + port->catch_tr_descr->buf; + DEBUGTXINT(pr_info("%-4d - %-4d = %-4d\t" + "in descr %p (ac: %p)\n", + port->out_buf_count, sent, + port->out_buf_count - sent, + port->catch_tr_descr, + port->active_tr_descr);); + port->out_buf_count -= sent; + port->catch_tr_descr = + phys_to_virt((int) port->catch_tr_descr->next); + port->out_rd_ptr = + phys_to_virt((int) port->catch_tr_descr->buf); + } else { + reg_sser_rw_tr_cfg tr_cfg; + int j, sent; + /* EOL handler. + * Note that if an EOL was encountered during the irq + * locked section of sync_ser_write the DMA will be + * restarted and the eol flag will be cleared. + * The remaining descriptors will be traversed by + * the descriptor interrupts as usual. + */ + j = 0; + while (!port->catch_tr_descr->eol) { + sent = port->catch_tr_descr->after - + port->catch_tr_descr->buf; + DEBUGOUTBUF(pr_info( + "traversing descr %p -%d (%d)\n", + port->catch_tr_descr, + sent, + port->out_buf_count)); + port->out_buf_count -= sent; + port->catch_tr_descr = phys_to_virt( + (int)port->catch_tr_descr->next); + j++; + if (j >= NBR_OUT_DESCR) { + /* TODO: Reset and recover */ + panic("sync_serial: missing eol"); + } + } + sent = port->catch_tr_descr->after - + port->catch_tr_descr->buf; + DEBUGOUTBUF(pr_info("eol at descr %p -%d (%d)\n", + port->catch_tr_descr, + sent, + port->out_buf_count)); + + port->out_buf_count -= sent; + + /* Update read pointer to first free byte, we + * may already be writing data there. */ + port->out_rd_ptr = + phys_to_virt((int) port->catch_tr_descr->after); + if (port->out_rd_ptr > port->out_buffer + + OUT_BUFFER_SIZE) + port->out_rd_ptr = port->out_buffer; + + tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); + DEBUGTXINT(pr_info( + "tr_int DMA stop %d, set catch @ %p\n", + port->out_buf_count, + port->active_tr_descr)); + if (port->out_buf_count != 0) + pr_err("sync_ser: buf not empty after eol\n"); + port->catch_tr_descr = port->active_tr_descr; + port->tr_running = 0; + tr_cfg.tr_en = regk_sser_no; + REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); + } + /* wake up the waiting process */ + wake_up_interruptible(&port->out_wait_q); + } + return IRQ_RETVAL(found); +} /* tr_interrupt */ + + +static inline void handle_rx_packet(struct sync_port *port) +{ + int idx; + reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes }; + unsigned long flags; + + DEBUGRXINT(pr_info("!")); + spin_lock_irqsave(&port->lock, flags); + + /* If we overrun the user experience is crap regardless if we + * drop new or old data. Its much easier to get it right when + * dropping new data so lets do that. + */ + if ((port->writep + port->inbufchunk <= + port->flip + port->in_buffer_size) && + (port->in_buffer_len + port->inbufchunk < IN_BUFFER_SIZE)) { + memcpy(port->writep, + phys_to_virt((unsigned)port->next_rx_desc->buf), + port->inbufchunk); + port->writep += port->inbufchunk; + if (port->writep >= port->flip + port->in_buffer_size) + port->writep = port->flip; + + /* Timestamp the new data chunk. */ + if (port->write_ts_idx == NBR_IN_DESCR) + port->write_ts_idx = 0; + idx = port->write_ts_idx++; + do_posix_clock_monotonic_gettime(&port->timestamp[idx]); + port->in_buffer_len += port->inbufchunk; + } + spin_unlock_irqrestore(&port->lock, flags); + + port->next_rx_desc->eol = 1; + port->prev_rx_desc->eol = 0; + /* Cache bug workaround */ + flush_dma_descr(port->prev_rx_desc, 0); + port->prev_rx_desc = port->next_rx_desc; + port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next); + /* Cache bug workaround */ + flush_dma_descr(port->prev_rx_desc, 1); + /* wake up the waiting process */ + wake_up_interruptible(&port->in_wait_q); + DMA_CONTINUE(port->regi_dmain); + REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr); + +} + +static irqreturn_t rx_interrupt(int irq, void *dev_id) +{ + reg_dma_r_masked_intr masked; + + int i; + int found = 0; + + DEBUG(pr_info("rx_interrupt\n")); + + for (i = 0; i < NBR_PORTS; i++) { + struct sync_port *port = &ports[i]; + + if (!port->enabled || !port->use_dma) + continue; + + masked = REG_RD(dma, port->regi_dmain, r_masked_intr); + + if (!masked.data) + continue; + + /* Descriptor interrupt */ + found = 1; + while (REG_RD(dma, port->regi_dmain, rw_data) != + virt_to_phys(port->next_rx_desc)) + handle_rx_packet(port); + } + return IRQ_RETVAL(found); +} /* rx_interrupt */ +#endif /* SYNC_SER_DMA */ + +#ifdef SYNC_SER_MANUAL +static irqreturn_t manual_interrupt(int irq, void *dev_id) +{ + unsigned long flags; + int i; + int found = 0; + reg_sser_r_masked_intr masked; + + for (i = 0; i < NBR_PORTS; i++) { + struct sync_port *port = &ports[i]; + + if (!port->enabled || port->use_dma) + continue; + + masked = REG_RD(sser, port->regi_sser, r_masked_intr); + /* Data received? */ + if (masked.rdav) { + reg_sser_rw_rec_cfg rec_cfg = + REG_RD(sser, port->regi_sser, rw_rec_cfg); + reg_sser_r_rec_data data = REG_RD(sser, + port->regi_sser, r_rec_data); + found = 1; + /* Read data */ + spin_lock_irqsave(&port->lock, flags); + switch (rec_cfg.sample_size) { + case 8: + *port->writep++ = data.data & 0xff; + break; + case 12: + *port->writep = (data.data & 0x0ff0) >> 4; + *(port->writep + 1) = data.data & 0x0f; + port->writep += 2; + break; + case 16: + *(unsigned short *)port->writep = data.data; + port->writep += 2; + break; + case 24: + *(unsigned int *)port->writep = data.data; + port->writep += 3; + break; + case 32: + *(unsigned int *)port->writep = data.data; + port->writep += 4; + break; + } + + /* Wrap? */ + if (port->writep >= port->flip + port->in_buffer_size) + port->writep = port->flip; + if (port->writep == port->readp) { + /* Receive buf overrun, discard oldest data */ + port->readp++; + /* Wrap? */ + if (port->readp >= port->flip + + port->in_buffer_size) + port->readp = port->flip; + } + spin_unlock_irqrestore(&port->lock, flags); + if (sync_data_avail(port) >= port->inbufchunk) + /* Wake up application */ + wake_up_interruptible(&port->in_wait_q); + } + + /* Transmitter ready? */ + if (masked.trdy) { + found = 1; + /* More data to send */ + if (port->out_buf_count > 0) + send_word(port); + else { + /* Transmission finished */ + reg_sser_rw_intr_mask intr_mask; + intr_mask = REG_RD(sser, port->regi_sser, + rw_intr_mask); + intr_mask.trdy = 0; + REG_WR(sser, port->regi_sser, + rw_intr_mask, intr_mask); + /* Wake up application */ + wake_up_interruptible(&port->out_wait_q); + } + } + } + return IRQ_RETVAL(found); +} +#endif + +static int __init etrax_sync_serial_init(void) +{ +#if 1 + /* This code will be removed when we move to udev for all devices. */ + syncser_first = MKDEV(SYNC_SERIAL_MAJOR, 0); + if (register_chrdev_region(syncser_first, minor_count, SYNCSER_NAME)) { + pr_err("Failed to register major %d\n", SYNC_SERIAL_MAJOR); + return -1; + } +#else + /* Allocate dynamic major number. */ + if (alloc_chrdev_region(&syncser_first, 0, minor_count, SYNCSER_NAME)) { + pr_err("Failed to allocate character device region\n"); + return -1; + } +#endif + syncser_cdev = cdev_alloc(); + if (!syncser_cdev) { + pr_err("Failed to allocate cdev for syncser\n"); + unregister_chrdev_region(syncser_first, minor_count); + return -1; + } + cdev_init(syncser_cdev, &syncser_fops); + + /* Create a sysfs class for syncser */ + syncser_class = class_create(THIS_MODULE, "syncser_class"); + + /* Initialize Ports */ +#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) + if (artpec_pinmux_alloc_fixed(PINMUX_SSER0)) { + pr_warn("Unable to alloc pins for synchronous serial port 0\n"); + unregister_chrdev_region(syncser_first, minor_count); + return -EIO; + } + initialize_port(0); + ports[0].enabled = 1; + /* Register with sysfs so udev can pick it up. */ + device_create(syncser_class, NULL, syncser_first, NULL, + "%s%d", SYNCSER_NAME, 0); +#endif + +#if defined(CONFIG_ETRAXFS) && defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) + if (artpec_pinmux_alloc_fixed(PINMUX_SSER1)) { + pr_warn("Unable to alloc pins for synchronous serial port 1\n"); + unregister_chrdev_region(syncser_first, minor_count); + class_destroy(syncser_class); + return -EIO; + } + initialize_port(1); + ports[1].enabled = 1; + /* Register with sysfs so udev can pick it up. */ + device_create(syncser_class, NULL, syncser_first, NULL, + "%s%d", SYNCSER_NAME, 0); +#endif + + /* Add it to system */ + if (cdev_add(syncser_cdev, syncser_first, minor_count) < 0) { + pr_err("Failed to add syncser as char device\n"); + device_destroy(syncser_class, syncser_first); + class_destroy(syncser_class); + cdev_del(syncser_cdev); + unregister_chrdev_region(syncser_first, minor_count); + return -1; + } + + + pr_info("ARTPEC synchronous serial port (%s: %d, %d)\n", + SYNCSER_NAME, MAJOR(syncser_first), MINOR(syncser_first)); + + return 0; +} + +static void __exit etrax_sync_serial_exit(void) +{ + int i; + device_destroy(syncser_class, syncser_first); + class_destroy(syncser_class); + + if (syncser_cdev) { + cdev_del(syncser_cdev); + unregister_chrdev_region(syncser_first, minor_count); + } + for (i = 0; i < NBR_PORTS; i++) { + struct sync_port *port = &ports[i]; + if (port->init_irqs == dma_irq_setup) { + /* Free dma irqs and dma channels. */ +#ifdef SYNC_SER_DMA + artpec_free_dma(port->dma_in_nbr); + artpec_free_dma(port->dma_out_nbr); + free_irq(port->dma_out_intr_vect, port); + free_irq(port->dma_in_intr_vect, port); +#endif + } else if (port->init_irqs == manual_irq_setup) { + /* Free manual irq. */ + free_irq(port->syncser_intr_vect, port); + } + } + + pr_info("ARTPEC synchronous serial port unregistered\n"); +} + +module_init(etrax_sync_serial_init); +module_exit(etrax_sync_serial_exit); + +MODULE_LICENSE("GPL"); + diff --git a/kernel/arch/cris/arch-v32/kernel/Makefile b/kernel/arch/cris/arch-v32/kernel/Makefile new file mode 100644 index 000000000..d9fc617ea --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/Makefile @@ -0,0 +1,17 @@ +# +# Makefile for the linux kernel. +# + +extra-y := head.o + + +obj-y := entry.o traps.o irq.o debugport.o \ + process.o ptrace.o setup.o signal.o traps.o time.o \ + cache.o cacheflush.o + +obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o +obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o +obj-$(CONFIG_MODULES) += crisksyms.o + +clean: + diff --git a/kernel/arch/cris/arch-v32/kernel/cache.c b/kernel/arch/cris/arch-v32/kernel/cache.c new file mode 100644 index 000000000..f38433b1f --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/cache.c @@ -0,0 +1,33 @@ +#include +#include +#include +#include + +/* This file is used to workaround a cache bug, Guinness TR 106. */ + +inline void flush_dma_descr(struct dma_descr_data *descr, int flush_buf) +{ + /* Flush descriptor to make sure we get correct in_eop and after. */ + asm volatile ("ftagd [%0]" :: "r" (descr)); + /* Flush buffer pointed out by descriptor. */ + if (flush_buf) + cris_flush_cache_range(phys_to_virt((unsigned)descr->buf), + (unsigned)(descr->after - descr->buf)); +} +EXPORT_SYMBOL(flush_dma_descr); + +void flush_dma_list(struct dma_descr_data *descr) +{ + while (1) { + flush_dma_descr(descr, 1); + if (descr->eol) + break; + descr = phys_to_virt((unsigned)descr->next); + } +} +EXPORT_SYMBOL(flush_dma_list); + +/* From cacheflush.S */ +EXPORT_SYMBOL(cris_flush_cache); +/* From cacheflush.S */ +EXPORT_SYMBOL(cris_flush_cache_range); diff --git a/kernel/arch/cris/arch-v32/kernel/cacheflush.S b/kernel/arch/cris/arch-v32/kernel/cacheflush.S new file mode 100644 index 000000000..6fc3d95d7 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/cacheflush.S @@ -0,0 +1,99 @@ + .global cris_flush_cache_range + .type cris_flush_cache_range, @function +cris_flush_cache_range: + move.d 1024, $r12 + cmp.d $r11, $r12 + bhi cris_flush_1KB + nop + add.d $r10, $r11 + ftagd [$r10] +cris_flush_last: + addq 32, $r10 + cmp.d $r11, $r10 + blt cris_flush_last + ftagd [$r10] + ret + nop +cris_flush_1KB: + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ftagd [$r10] + addq 32, $r10 + ba cris_flush_cache_range + sub.d $r12, $r11 + .size cris_flush_cache_range, . - cris_flush_cache_range + + .global cris_flush_cache + .type cris_flush_cache, @function +cris_flush_cache: + moveq 0, $r10 +cris_flush_line: + move.d 16*1024, $r11 + addq 16, $r10 + cmp.d $r10, $r11 + blt cris_flush_line + fidxd [$r10] + ret + nop + .size cris_flush_cache, . - cris_flush_cache + diff --git a/kernel/arch/cris/arch-v32/kernel/crisksyms.c b/kernel/arch/cris/arch-v32/kernel/crisksyms.c new file mode 100644 index 000000000..bde8d1a10 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/crisksyms.c @@ -0,0 +1,28 @@ +#include +#include +#include +#include +#include +#include + +/* Functions for allocating DMA channels */ +EXPORT_SYMBOL(crisv32_request_dma); +EXPORT_SYMBOL(crisv32_free_dma); + +/* Functions for handling internal RAM */ +EXPORT_SYMBOL(crisv32_intmem_alloc); +EXPORT_SYMBOL(crisv32_intmem_free); +EXPORT_SYMBOL(crisv32_intmem_phys_to_virt); +EXPORT_SYMBOL(crisv32_intmem_virt_to_phys); + +/* Functions for handling pinmux */ +EXPORT_SYMBOL(crisv32_pinmux_alloc); +EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed); +EXPORT_SYMBOL(crisv32_pinmux_dealloc); +EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed); +EXPORT_SYMBOL(crisv32_io_get_name); +EXPORT_SYMBOL(crisv32_io_get); + +/* Functions masking/unmasking interrupts */ +EXPORT_SYMBOL(crisv32_mask_irq); +EXPORT_SYMBOL(crisv32_unmask_irq); diff --git a/kernel/arch/cris/arch-v32/kernel/debugport.c b/kernel/arch/cris/arch-v32/kernel/debugport.c new file mode 100644 index 000000000..02e33ebe5 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/debugport.c @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2003, Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct dbg_port +{ + unsigned char nbr; + unsigned long instance; + unsigned int started; + unsigned long baudrate; + unsigned char parity; + unsigned int bits; +}; + +struct dbg_port ports[] = +{ + { + 0, + regi_ser0, + 0, + 115200, + 'N', + 8 + }, + { + 1, + regi_ser1, + 0, + 115200, + 'N', + 8 + }, + { + 2, + regi_ser2, + 0, + 115200, + 'N', + 8 + }, + { + 3, + regi_ser3, + 0, + 115200, + 'N', + 8 + }, +#if CONFIG_ETRAX_SERIAL_PORTS == 5 + { + 4, + regi_ser4, + 0, + 115200, + 'N', + 8 + }, +#endif +}; + +static struct dbg_port *port = +#if defined(CONFIG_ETRAX_DEBUG_PORT0) + &ports[0]; +#elif defined(CONFIG_ETRAX_DEBUG_PORT1) + &ports[1]; +#elif defined(CONFIG_ETRAX_DEBUG_PORT2) + &ports[2]; +#elif defined(CONFIG_ETRAX_DEBUG_PORT3) + &ports[3]; +#elif defined(CONFIG_ETRAX_DEBUG_PORT4) + &ports[4]; +#else + NULL; +#endif + +#ifdef CONFIG_ETRAX_KGDB +static struct dbg_port *kgdb_port = +#if defined(CONFIG_ETRAX_KGDB_PORT0) + &ports[0]; +#elif defined(CONFIG_ETRAX_KGDB_PORT1) + &ports[1]; +#elif defined(CONFIG_ETRAX_KGDB_PORT2) + &ports[2]; +#elif defined(CONFIG_ETRAX_KGDB_PORT3) + &ports[3]; +#elif defined(CONFIG_ETRAX_KGDB_PORT4) + &ports[4]; +#else + NULL; +#endif +#endif + +static void start_port(struct dbg_port *p) +{ + /* Set up serial port registers */ + reg_ser_rw_tr_ctrl tr_ctrl = {0}; + reg_ser_rw_tr_dma_en tr_dma_en = {0}; + + reg_ser_rw_rec_ctrl rec_ctrl = {0}; + reg_ser_rw_tr_baud_div tr_baud_div = {0}; + reg_ser_rw_rec_baud_div rec_baud_div = {0}; + + if (!p || p->started) + return; + + p->started = 1; + + if (p->nbr == 1) + crisv32_pinmux_alloc_fixed(pinmux_ser1); + else if (p->nbr == 2) + crisv32_pinmux_alloc_fixed(pinmux_ser2); + else if (p->nbr == 3) + crisv32_pinmux_alloc_fixed(pinmux_ser3); +#if CONFIG_ETRAX_SERIAL_PORTS == 5 + else if (p->nbr == 4) + crisv32_pinmux_alloc_fixed(pinmux_ser4); +#endif + + tr_ctrl.base_freq = rec_ctrl.base_freq = regk_ser_f29_493; + tr_dma_en.en = rec_ctrl.dma_mode = regk_ser_no; + tr_baud_div.div = rec_baud_div.div = 29493000 / p->baudrate / 8; + tr_ctrl.en = rec_ctrl.en = 1; + + if (p->parity == 'O') { + tr_ctrl.par_en = regk_ser_yes; + tr_ctrl.par = regk_ser_odd; + rec_ctrl.par_en = regk_ser_yes; + rec_ctrl.par = regk_ser_odd; + } else if (p->parity == 'E') { + tr_ctrl.par_en = regk_ser_yes; + tr_ctrl.par = regk_ser_even; + rec_ctrl.par_en = regk_ser_yes; + rec_ctrl.par = regk_ser_odd; + } + + if (p->bits == 7) { + tr_ctrl.data_bits = regk_ser_bits7; + rec_ctrl.data_bits = regk_ser_bits7; + } + + REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div); + REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div); + REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en); + REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl); + REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl); +} + +#ifdef CONFIG_ETRAX_KGDB +/* Use polling to get a single character from the kernel debug port */ +int getDebugChar(void) +{ + reg_ser_rs_stat_din stat; + reg_ser_rw_ack_intr ack_intr = { 0 }; + + do { + stat = REG_RD(ser, kgdb_port->instance, rs_stat_din); + } while (!stat.dav); + + /* Ack the data_avail interrupt. */ + ack_intr.dav = 1; + REG_WR(ser, kgdb_port->instance, rw_ack_intr, ack_intr); + + return stat.data; +} + +/* Use polling to put a single character to the kernel debug port */ +void putDebugChar(int val) +{ + reg_ser_r_stat_din stat; + do { + stat = REG_RD(ser, kgdb_port->instance, r_stat_din); + } while (!stat.tr_rdy); + REG_WR_INT(ser, kgdb_port->instance, rw_dout, val); +} +#endif /* CONFIG_ETRAX_KGDB */ + +static void __init early_putch(int c) +{ + reg_ser_r_stat_din stat; + /* Wait until transmitter is ready and send. */ + do + stat = REG_RD(ser, port->instance, r_stat_din); + while (!stat.tr_rdy); + REG_WR_INT(ser, port->instance, rw_dout, c); +} + +static void __init +early_console_write(struct console *con, const char *s, unsigned n) +{ + extern void reset_watchdog(void); + int i; + + /* Send data. */ + for (i = 0; i < n; i++) { + /* TODO: the '\n' -> '\n\r' translation should be done at the + receiver. Remove it when the serial driver removes it. */ + if (s[i] == '\n') + early_putch('\r'); + early_putch(s[i]); + reset_watchdog(); + } +} + +static struct console early_console_dev __initdata = { + .name = "early", + .write = early_console_write, + .flags = CON_PRINTBUFFER | CON_BOOT, + .index = -1 +}; + +/* Register console for printk's, etc. */ +int __init init_etrax_debug(void) +{ + start_port(port); + + /* Register an early console if a debug port was chosen. */ + register_console(&early_console_dev); + +#ifdef CONFIG_ETRAX_KGDB + start_port(kgdb_port); +#endif /* CONFIG_ETRAX_KGDB */ + return 0; +} diff --git a/kernel/arch/cris/arch-v32/kernel/entry.S b/kernel/arch/cris/arch-v32/kernel/entry.S new file mode 100644 index 000000000..026a0b21b --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/entry.S @@ -0,0 +1,889 @@ +/* + * Copyright (C) 2000-2003 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * Tobias Anderberg (tobiasa@axis.com), CRISv32 port. + * + * Code for the system-call and fault low-level handling routines. + * + * NOTE: This code handles signal-recognition, which happens every time + * after a timer-interrupt and after each system call. + * + * Stack layout in 'ret_from_system_call': + * ptrace needs to have all regs on the stack. + * if the order here is changed, it needs to be + * updated in fork.c:copy_process, signal.c:do_signal, + * ptrace.c and ptrace.h + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + + ;; Exported functions. + .globl system_call + .globl ret_from_intr + .globl ret_from_fork + .globl ret_from_kernel_thread + .globl resume + .globl multiple_interrupt + .globl nmi_interrupt + .globl spurious_interrupt + .globl do_sigtrap + .globl gdb_handle_exception + .globl sys_call_table + + ; Check if preemptive kernel scheduling should be done. +#ifdef CONFIG_PREEMPT +_resume_kernel: + di + ; Load current task struct. + movs.w -8192, $r0 ; THREAD_SIZE = 8192 + and.d $sp, $r0 + + addoq +TI_preempt_count, $r0, $acr + move.d [$acr], $r10 ; Preemption disabled? + bne _Rexit + nop + +_need_resched: + addoq +TI_flags, $r0, $acr + move.d [$acr], $r10 + btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set. + bpl _Rexit + nop + + ; Do preemptive kernel scheduling. + jsr preempt_schedule_irq + nop + + ; Load new task struct. + movs.w -8192, $r0 ; THREAD_SIZE = 8192. + and.d $sp, $r0 + + ; One more time with new task. + ba _need_resched + nop +#else +#define _resume_kernel _Rexit +#endif + + ; Called at exit from fork. schedule_tail must be called to drop + ; spinlock if CONFIG_PREEMPT. + .type ret_from_fork,@function +ret_from_fork: + jsr schedule_tail + nop + ba ret_from_sys_call + nop + .size ret_from_fork, . - ret_from_fork + + .type ret_from_kernel_thread,@function +ret_from_kernel_thread: + jsr schedule_tail + nop + move.d $r2, $r10 + jsr $r1 + nop + moveq 0, $r9 ; no syscall restarts, TYVM... + ba ret_from_sys_call + nop + .size ret_from_kernel_thread, . - ret_from_kernel_thread + + .type ret_from_intr,@function +ret_from_intr: + moveq 0, $r9 ; not a syscall + + ;; Check for resched if preemptive kernel, or if we're going back to + ;; user-mode. This test matches the user_regs(regs) macro. Don't simply + ;; test CCS since that doesn't necessarily reflect what mode we'll + ;; return into. + addoq +PT_ccs, $sp, $acr + move.d [$acr], $r0 + btstq 16, $r0 ; User-mode flag. + bpl _resume_kernel + .size ret_from_intr, . - ret_from_intr + 2 ; +2 includes the dslot. + + ; Note that di below is in delay slot. + .type _resume_userspace,@function +_resume_userspace: + di ; So need_resched and sigpending don't change. + + movs.w -8192, $r0 ; THREAD_SIZE == 8192 + and.d $sp, $r0 + + addoq +TI_flags, $r0, $acr ; current->work + move.d [$acr], $r10 + and.d _TIF_WORK_MASK, $r10 ; Work to be done on return? + bne _work_pending + nop + ba _Rexit + nop + .size _resume_userspace, . - _resume_userspace + + ;; The system_call is called by a BREAK instruction, which looks pretty + ;; much like any other exception. + ;; + ;; System calls can't be made from interrupts but we still stack ERP + ;; to have a complete stack frame. + ;; + ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12, + ;; r13,mof,srp + ;; + ;; This function looks on the _surface_ like spaghetti programming, but it's + ;; really designed so that the fast-path does not force cache-loading of + ;; non-used instructions. Only the non-common cases cause the outlined code + ;; to run.. + + .type system_call,@function +system_call: + ;; Stack-frame similar to the irq heads, which is reversed in + ;; ret_from_sys_call. + + sub.d 92, $sp ; Skip EDA. + movem $r13, [$sp] + move.d $sp, $r8 + addq 14*4, $r8 + move.d $acr, $r0 + move $srs, $r1 + move $mof, $r2 + move $spc, $r3 + move $ccs, $r4 + move $srp, $r5 + move $erp, $r6 + move.d $r9, $r7 ; Store syscall number in EXS + subq 4, $sp + movem $r7, [$r8] + ei ; Enable interrupts while processing syscalls. + move.d $r10, [$sp] + + ; Set S-bit when kernel debugging to keep hardware breakpoints active. +#ifdef CONFIG_ETRAX_KGDB + move $ccs, $r0 + or.d (1<<9), $r0 + move $r0, $ccs +#endif + + movs.w -ENOSYS, $r0 + addoq +PT_r10, $sp, $acr + move.d $r0, [$acr] + + ;; Check if this process is syscall-traced. + movs.w -8192, $r0 ; THREAD_SIZE == 8192 + and.d $sp, $r0 + + addoq +TI_flags, $r0, $acr + move.d [$acr], $r0 + btstq TIF_SYSCALL_TRACE, $r0 + bmi _syscall_trace_entry + nop + +_syscall_traced: + ;; Check for sanity in the requested syscall number. + cmpu.w NR_syscalls, $r9 + bhs ret_from_sys_call + lslq 2, $r9 ; Multiply by 4, in the delay slot. + + ;; The location on the stack for the register structure is passed as a + ;; seventh argument. Some system calls need this. + move.d $sp, $r0 + subq 4, $sp + move.d $r0, [$sp] + + ;; The registers carrying parameters (R10-R13) are intact. The optional + ;; fifth and sixth parameters is in MOF and SRP respectively. Put them + ;; back on the stack. + subq 4, $sp + move $srp, [$sp] + subq 4, $sp + move $mof, [$sp] + + ;; Actually to the system call. + addo.d +sys_call_table, $r9, $acr + move.d [$acr], $acr + jsr $acr + nop + + addq 3*4, $sp ; Pop the mof, srp and regs parameters. + addoq +PT_r10, $sp, $acr + move.d $r10, [$acr] ; Save the return value. + + moveq 1, $r9 ; "Parameter" to ret_from_sys_call to + ; show it was a sys call. + + ;; Fall through into ret_from_sys_call to return. + +ret_from_sys_call: + ;; R9 is a parameter: + ;; >= 1 from syscall + ;; 0 from irq + + ;; Get the current task-struct pointer. + movs.w -8192, $r0 ; THREAD_SIZE == 8192 + and.d $sp, $r0 + + di ; Make sure need_resched and sigpending don't change. + + addoq +TI_flags, $r0, $acr + move.d [$acr], $r1 + and.d _TIF_ALLWORK_MASK, $r1 + bne _syscall_exit_work + nop + .size system_call, . - system_call + + .type _Rexit,@function +_Rexit: + ;; This epilogue MUST match the prologues in multiple_interrupt, irq.h + ;; and ptregs.h. + addq 4, $sp ; Skip orig_r10. + movem [$sp+], $r13 ; Registers R0-R13. + move.d [$sp+], $acr + move [$sp], $srs + addq 4, $sp + move [$sp+], $mof + move [$sp+], $spc + move [$sp+], $ccs + move [$sp+], $srp + move [$sp+], $erp + addq 8, $sp ; Skip EXS, EDA. + jump $erp + rfe ; Restore condition code stack in delay-slot. + .size _Rexit, . - _Rexit + + ;; We get here after doing a syscall if extra work might need to be done + ;; perform syscall exit tracing if needed. + + .type _syscall_exit_work,@function +_syscall_exit_work: + ;; R0 contains current at this point and irq's are disabled. + + addoq +TI_flags, $r0, $acr + move.d [$acr], $r1 + btstq TIF_SYSCALL_TRACE, $r1 + bpl _work_pending + nop + ei + move.d $r9, $r1 ; Preserve R9. + jsr do_syscall_trace + nop + move.d $r1, $r9 + ba _resume_userspace + nop + .size _syscall_exit_work, . - _syscall_exit_work + + .type _work_pending,@function +_work_pending: + addoq +TI_flags, $r0, $acr + move.d [$acr], $r12 ; The thread_info_flags parameter. + move.d $sp, $r11 ; The regs param. + jsr do_work_pending + move.d $r9, $r10 ; The syscall/irq param. + + ba _Rexit + nop + .size _work_pending, . - _work_pending + + ;; We get here as a sidetrack when we've entered a syscall with the + ;; trace-bit set. We need to call do_syscall_trace and then continue + ;; with the call. + +_syscall_trace_entry: + ;; PT_r10 in the frame contains -ENOSYS as required, at this point. + + jsr do_syscall_trace + nop + + ;; Now re-enter the syscall code to do the syscall itself. We need to + ;; restore R9 here to contain the wanted syscall, and the other + ;; parameter-bearing registers. + addoq +PT_r9, $sp, $acr + move.d [$acr], $r9 + addoq +PT_orig_r10, $sp, $acr + move.d [$acr], $r10 ; PT_r10 is already -ENOSYS. + addoq +PT_r11, $sp, $acr + move.d [$acr], $r11 + addoq +PT_r12, $sp, $acr + move.d [$acr], $r12 + addoq +PT_r13, $sp, $acr + move.d [$acr], $r13 + addoq +PT_mof, $sp, $acr + move [$acr], $mof + addoq +PT_srp, $sp, $acr + move [$acr], $srp + + ba _syscall_traced + nop + + ;; Resume performs the actual task-switching, by switching stack + ;; pointers. Input arguments are: + ;; + ;; R10 = prev + ;; R11 = next + ;; R12 = thread offset in task struct. + ;; + ;; Returns old current in R10. + + .type resume,@function +resume: + subq 4, $sp ; Make space for srp. + + add.d $r12, $r10 ; R10 = current tasks tss. + addoq +THREAD_ccs, $r10, $acr + move $srp, [$sp] ; Keep old/new PC on the stack. + move $ccs, [$acr] ; Save IRQ enable state. + di + + addoq +THREAD_usp, $r10, $acr + subq 10*4, $sp ; Make room for R9. + move $usp, [$acr] ; Save user-mode stackpointer. + + ;; See copy_thread for the reason why register R9 is saved. + movem $r9, [$sp] ; Save non-scratch registers and R9. + + addoq +THREAD_ksp, $r10, $acr + move.d $sp, $r10 ; Return last running task in R10. + move.d $sp, [$acr] ; Save kernel SP for old task. + + and.d -8192, $r10 ; Get thread_info from stackpointer. + addoq +TI_task, $r10, $acr + add.d $r12, $r11 ; Find the new tasks tss. + move.d [$acr], $r10 ; Get task. + addoq +THREAD_ksp, $r11, $acr + move.d [$acr], $sp ; Switch to new stackframe. + addoq +THREAD_usp, $r11, $acr + movem [$sp+], $r9 ; Restore non-scratch registers and R9. + + move [$acr], $usp ; Restore user-mode stackpointer. + + addoq +THREAD_ccs, $r11, $acr + move.d [$sp+], $r11 + jump $r11 ; Restore PC. + move [$acr], $ccs ; Restore IRQ enable status. + .size resume, . - resume + +nmi_interrupt: + +;; If we receive a watchdog interrupt while it is not expected, then set +;; up a canonical frame and dump register contents before dying. + + ;; This prologue MUST match the one in irq.h and the struct in ptregs.h! + subq 12, $sp ; Skip EXS, EDA. + move $nrp, [$sp] + subq 4, $sp + move $srp, [$sp] + subq 4, $sp + move $ccs, [$sp] + subq 4, $sp + move $spc, [$sp] + subq 4, $sp + move $mof, [$sp] + subq 4, $sp + move $srs, [$sp] + subq 4, $sp + move.d $acr, [$sp] + subq 14*4, $sp ; Make room for R0-R13. + movem $r13, [$sp] ; Push R0-R13. + subq 4, $sp + move.d $r10, [$sp] ; Push orig_r10. + move.d REG_ADDR(intr_vect, regi_irq, r_nmi), $r0 + move.d [$r0], $r0 + btstq REG_BIT(intr_vect, r_nmi, watchdog), $r0 + bpl 1f + nop + jsr handle_watchdog_bite ; In time.c. + move.d $sp, $r10 ; Pointer to registers +1: btstq REG_BIT(intr_vect, r_nmi, ext), $r0 + bpl 1f + nop + jsr handle_nmi + move.d $sp, $r10 ; Pointer to registers +1: addq 4, $sp ; Skip orig_r10 + movem [$sp+], $r13 + move.d [$sp+], $acr + move [$sp], $srs + addq 4, $sp + move [$sp+], $mof + move [$sp+], $spc + move [$sp+], $ccs + move [$sp+], $srp + move [$sp+], $nrp + addq 8, $sp ; Skip EXS, EDA. + jump $nrp + rfn + + .comm cause_of_death, 4 ;; Don't declare this anywhere. + +spurious_interrupt: + di + jump hard_reset_now + nop + + ;; This handles the case when multiple interrupts arrive at the same + ;; time. Jump to the first set interrupt bit in a priority fashion. The + ;; hardware will call the unserved interrupts after the handler + ;; finishes. + .type multiple_interrupt, @function +multiple_interrupt: + ;; This prologue MUST match the one in irq.h and the struct in ptregs.h! + subq 12, $sp ; Skip EXS, EDA. + move $erp, [$sp] + subq 4, $sp + move $srp, [$sp] + subq 4, $sp + move $ccs, [$sp] + subq 4, $sp + move $spc, [$sp] + subq 4, $sp + move $mof, [$sp] + subq 4, $sp + move $srs, [$sp] + subq 4, $sp + move.d $acr, [$sp] + subq 14*4, $sp ; Make room for R0-R13. + movem $r13, [$sp] ; Push R0-R13. + subq 4, $sp + move.d $r10, [$sp] ; Push orig_r10. + +; Set S-bit when kernel debugging to keep hardware breakpoints active. +#ifdef CONFIG_ETRAX_KGDB + move $ccs, $r0 + or.d (1<<9), $r0 + move $r0, $ccs +#endif + + jsr crisv32_do_multiple + move.d $sp, $r10 + jump ret_from_intr + nop + .size multiple_interrupt, . - multiple_interrupt + +do_sigtrap: + ;; Sigtraps the process that executed the BREAK instruction. Creates a + ;; frame that Rexit expects. + subq 4, $sp + move $eda, [$sp] + subq 4, $sp + move $exs, [$sp] + subq 4, $sp + move $erp, [$sp] + subq 4, $sp + move $srp, [$sp] + subq 4, $sp + move $ccs, [$sp] + subq 4, $sp + move $spc, [$sp] + subq 4, $sp + move $mof, [$sp] + subq 4, $sp + move $srs, [$sp] + subq 4, $sp + move.d $acr, [$sp] + di ; Need to disable irq's at this point. + subq 14*4, $sp ; Make room for r0-r13. + movem $r13, [$sp] ; Push the r0-r13 registers. + subq 4, $sp + move.d $r10, [$sp] ; Push orig_r10. + + movs.w -8192, $r9 ; THREAD_SIZE == 8192 + and.d $sp, $r9 + + ;; thread_info as first parameter + move.d $r9, $r10 + moveq 5, $r11 ; SIGTRAP as second argument. + jsr ugdb_trap_user + nop + jump ret_from_intr ; Use the return routine for interrupts. + nop + +gdb_handle_exception: + subq 4, $sp + move.d $r0, [$sp] +#ifdef CONFIG_ETRAX_KGDB + move $ccs, $r0 ; U-flag not affected by previous insns. + btstq 16, $r0 ; Test the U-flag. + bmi _ugdb_handle_exception ; Go to user mode debugging. + nop ; Empty delay-slot (cannot pop R0 here). + ba kgdb_handle_exception ; Go to kernel debugging. + move.d [$sp+], $r0 ; Restore R0 in delay slot. +#endif + +_ugdb_handle_exception: + ba do_sigtrap ; SIGTRAP the offending process. + move.d [$sp+], $r0 ; Restore R0 in delay slot. + + .data + + .section .rodata,"a" +sys_call_table: + .long sys_restart_syscall ; 0 - old "setup()" system call, used + ; for restarting. + .long sys_exit + .long sys_fork + .long sys_read + .long sys_write + .long sys_open /* 5 */ + .long sys_close + .long sys_waitpid + .long sys_creat + .long sys_link + .long sys_unlink /* 10 */ + .long sys_execve + .long sys_chdir + .long sys_time + .long sys_mknod + .long sys_chmod /* 15 */ + .long sys_lchown16 + .long sys_ni_syscall /* old break syscall holder */ + .long sys_stat + .long sys_lseek + .long sys_getpid /* 20 */ + .long sys_mount + .long sys_oldumount + .long sys_setuid16 + .long sys_getuid16 + .long sys_stime /* 25 */ + .long sys_ptrace + .long sys_alarm + .long sys_fstat + .long sys_pause + .long sys_utime /* 30 */ + .long sys_ni_syscall /* old stty syscall holder */ + .long sys_ni_syscall /* old gtty syscall holder */ + .long sys_access + .long sys_nice + .long sys_ni_syscall /* 35 old ftime syscall holder */ + .long sys_sync + .long sys_kill + .long sys_rename + .long sys_mkdir + .long sys_rmdir /* 40 */ + .long sys_dup + .long sys_pipe + .long sys_times + .long sys_ni_syscall /* old prof syscall holder */ + .long sys_brk /* 45 */ + .long sys_setgid16 + .long sys_getgid16 + .long sys_signal + .long sys_geteuid16 + .long sys_getegid16 /* 50 */ + .long sys_acct + .long sys_umount /* recycled never used phys( */ + .long sys_ni_syscall /* old lock syscall holder */ + .long sys_ioctl + .long sys_fcntl /* 55 */ + .long sys_ni_syscall /* old mpx syscall holder */ + .long sys_setpgid + .long sys_ni_syscall /* old ulimit syscall holder */ + .long sys_ni_syscall /* old sys_olduname holder */ + .long sys_umask /* 60 */ + .long sys_chroot + .long sys_ustat + .long sys_dup2 + .long sys_getppid + .long sys_getpgrp /* 65 */ + .long sys_setsid + .long sys_sigaction + .long sys_sgetmask + .long sys_ssetmask + .long sys_setreuid16 /* 70 */ + .long sys_setregid16 + .long sys_sigsuspend + .long sys_sigpending + .long sys_sethostname + .long sys_setrlimit /* 75 */ + .long sys_old_getrlimit + .long sys_getrusage + .long sys_gettimeofday + .long sys_settimeofday + .long sys_getgroups16 /* 80 */ + .long sys_setgroups16 + .long sys_select /* was old_select in Linux/E100 */ + .long sys_symlink + .long sys_lstat + .long sys_readlink /* 85 */ + .long sys_uselib + .long sys_swapon + .long sys_reboot + .long sys_old_readdir + .long sys_old_mmap /* 90 */ + .long sys_munmap + .long sys_truncate + .long sys_ftruncate + .long sys_fchmod + .long sys_fchown16 /* 95 */ + .long sys_getpriority + .long sys_setpriority + .long sys_ni_syscall /* old profil syscall holder */ + .long sys_statfs + .long sys_fstatfs /* 100 */ + .long sys_ni_syscall /* sys_ioperm in i386 */ + .long sys_socketcall + .long sys_syslog + .long sys_setitimer + .long sys_getitimer /* 105 */ + .long sys_newstat + .long sys_newlstat + .long sys_newfstat + .long sys_ni_syscall /* old sys_uname holder */ + .long sys_ni_syscall /* sys_iopl in i386 */ + .long sys_vhangup + .long sys_ni_syscall /* old "idle" system call */ + .long sys_ni_syscall /* vm86old in i386 */ + .long sys_wait4 + .long sys_swapoff /* 115 */ + .long sys_sysinfo + .long sys_ipc + .long sys_fsync + .long sys_sigreturn + .long sys_clone /* 120 */ + .long sys_setdomainname + .long sys_newuname + .long sys_ni_syscall /* sys_modify_ldt */ + .long sys_adjtimex + .long sys_mprotect /* 125 */ + .long sys_sigprocmask + .long sys_ni_syscall /* old "create_module" */ + .long sys_init_module + .long sys_delete_module + .long sys_ni_syscall /* 130: old "get_kernel_syms" */ + .long sys_quotactl + .long sys_getpgid + .long sys_fchdir + .long sys_bdflush + .long sys_sysfs /* 135 */ + .long sys_personality + .long sys_ni_syscall /* for afs_syscall */ + .long sys_setfsuid16 + .long sys_setfsgid16 + .long sys_llseek /* 140 */ + .long sys_getdents + .long sys_select + .long sys_flock + .long sys_msync + .long sys_readv /* 145 */ + .long sys_writev + .long sys_getsid + .long sys_fdatasync + .long sys_sysctl + .long sys_mlock /* 150 */ + .long sys_munlock + .long sys_mlockall + .long sys_munlockall + .long sys_sched_setparam + .long sys_sched_getparam /* 155 */ + .long sys_sched_setscheduler + .long sys_sched_getscheduler + .long sys_sched_yield + .long sys_sched_get_priority_max + .long sys_sched_get_priority_min /* 160 */ + .long sys_sched_rr_get_interval + .long sys_nanosleep + .long sys_mremap + .long sys_setresuid16 + .long sys_getresuid16 /* 165 */ + .long sys_ni_syscall /* sys_vm86 */ + .long sys_ni_syscall /* Old sys_query_module */ + .long sys_poll + .long sys_ni_syscall /* Old nfsservctl */ + .long sys_setresgid16 /* 170 */ + .long sys_getresgid16 + .long sys_prctl + .long sys_rt_sigreturn + .long sys_rt_sigaction + .long sys_rt_sigprocmask /* 175 */ + .long sys_rt_sigpending + .long sys_rt_sigtimedwait + .long sys_rt_sigqueueinfo + .long sys_rt_sigsuspend + .long sys_pread64 /* 180 */ + .long sys_pwrite64 + .long sys_chown16 + .long sys_getcwd + .long sys_capget + .long sys_capset /* 185 */ + .long sys_sigaltstack + .long sys_sendfile + .long sys_ni_syscall /* streams1 */ + .long sys_ni_syscall /* streams2 */ + .long sys_vfork /* 190 */ + .long sys_getrlimit + .long sys_mmap2 + .long sys_truncate64 + .long sys_ftruncate64 + .long sys_stat64 /* 195 */ + .long sys_lstat64 + .long sys_fstat64 + .long sys_lchown + .long sys_getuid + .long sys_getgid /* 200 */ + .long sys_geteuid + .long sys_getegid + .long sys_setreuid + .long sys_setregid + .long sys_getgroups /* 205 */ + .long sys_setgroups + .long sys_fchown + .long sys_setresuid + .long sys_getresuid + .long sys_setresgid /* 210 */ + .long sys_getresgid + .long sys_chown + .long sys_setuid + .long sys_setgid + .long sys_setfsuid /* 215 */ + .long sys_setfsgid + .long sys_pivot_root + .long sys_mincore + .long sys_madvise + .long sys_getdents64 /* 220 */ + .long sys_fcntl64 + .long sys_ni_syscall /* reserved for TUX */ + .long sys_ni_syscall + .long sys_gettid + .long sys_readahead /* 225 */ + .long sys_setxattr + .long sys_lsetxattr + .long sys_fsetxattr + .long sys_getxattr + .long sys_lgetxattr /* 230 */ + .long sys_fgetxattr + .long sys_listxattr + .long sys_llistxattr + .long sys_flistxattr + .long sys_removexattr /* 235 */ + .long sys_lremovexattr + .long sys_fremovexattr + .long sys_tkill + .long sys_sendfile64 + .long sys_futex /* 240 */ + .long sys_sched_setaffinity + .long sys_sched_getaffinity + .long sys_ni_syscall /* sys_set_thread_area */ + .long sys_ni_syscall /* sys_get_thread_area */ + .long sys_io_setup /* 245 */ + .long sys_io_destroy + .long sys_io_getevents + .long sys_io_submit + .long sys_io_cancel + .long sys_fadvise64 /* 250 */ + .long sys_ni_syscall + .long sys_exit_group + .long sys_lookup_dcookie + .long sys_epoll_create + .long sys_epoll_ctl /* 255 */ + .long sys_epoll_wait + .long sys_remap_file_pages + .long sys_set_tid_address + .long sys_timer_create + .long sys_timer_settime /* 260 */ + .long sys_timer_gettime + .long sys_timer_getoverrun + .long sys_timer_delete + .long sys_clock_settime + .long sys_clock_gettime /* 265 */ + .long sys_clock_getres + .long sys_clock_nanosleep + .long sys_statfs64 + .long sys_fstatfs64 + .long sys_tgkill /* 270 */ + .long sys_utimes + .long sys_fadvise64_64 + .long sys_ni_syscall /* sys_vserver */ + .long sys_ni_syscall /* sys_mbind */ + .long sys_ni_syscall /* 275 sys_get_mempolicy */ + .long sys_ni_syscall /* sys_set_mempolicy */ + .long sys_mq_open + .long sys_mq_unlink + .long sys_mq_timedsend + .long sys_mq_timedreceive /* 280 */ + .long sys_mq_notify + .long sys_mq_getsetattr + .long sys_ni_syscall /* reserved for kexec */ + .long sys_waitid + .long sys_ni_syscall /* 285 */ /* available */ + .long sys_add_key + .long sys_request_key + .long sys_keyctl + .long sys_ioprio_set + .long sys_ioprio_get /* 290 */ + .long sys_inotify_init + .long sys_inotify_add_watch + .long sys_inotify_rm_watch + .long sys_migrate_pages + .long sys_openat /* 295 */ + .long sys_mkdirat + .long sys_mknodat + .long sys_fchownat + .long sys_futimesat + .long sys_fstatat64 /* 300 */ + .long sys_unlinkat + .long sys_renameat + .long sys_linkat + .long sys_symlinkat + .long sys_readlinkat /* 305 */ + .long sys_fchmodat + .long sys_faccessat + .long sys_pselect6 + .long sys_ppoll + .long sys_unshare /* 310 */ + .long sys_set_robust_list + .long sys_get_robust_list + .long sys_splice + .long sys_sync_file_range + .long sys_tee /* 315 */ + .long sys_vmsplice + .long sys_move_pages + .long sys_getcpu + .long sys_epoll_pwait + .long sys_utimensat /* 320 */ + .long sys_signalfd + .long sys_timerfd_create + .long sys_eventfd + .long sys_fallocate + .long sys_timerfd_settime /* 325 */ + .long sys_timerfd_gettime + .long sys_signalfd4 + .long sys_eventfd2 + .long sys_epoll_create1 + .long sys_dup3 /* 330 */ + .long sys_pipe2 + .long sys_inotify_init1 + .long sys_preadv + .long sys_pwritev + .long sys_setns /* 335 */ + .long sys_name_to_handle_at + .long sys_open_by_handle_at + .long sys_rt_tgsigqueueinfo + .long sys_perf_event_open + .long sys_recvmmsg /* 340 */ + .long sys_accept4 + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 + .long sys_clock_adjtime /* 345 */ + .long sys_syncfs + .long sys_sendmmsg + .long sys_process_vm_readv + .long sys_process_vm_writev + .long sys_kcmp /* 350 */ + .long sys_finit_module + + /* + * NOTE!! This doesn't have to be exact - we just have + * to make sure we have _enough_ of the "sys_ni_syscall" + * entries. Don't panic if you notice that this hasn't + * been shrunk every time we add a new system call. + */ + + .rept NR_syscalls - (.-sys_call_table) / 4 + .long sys_ni_syscall + .endr + diff --git a/kernel/arch/cris/arch-v32/kernel/fasttimer.c b/kernel/arch/cris/arch-v32/kernel/fasttimer.c new file mode 100644 index 000000000..5c84dbb99 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/fasttimer.c @@ -0,0 +1,793 @@ +/* + * linux/arch/cris/kernel/fasttimer.c + * + * Fast timers for ETRAX FS + * + * Copyright (C) 2000-2006 Axis Communications AB, Lund, Sweden + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +/* + * timer0 is running at 100MHz and generating jiffies timer ticks + * at 100 or 1000 HZ. + * fasttimer gives an API that gives timers that expire "between" the jiffies + * giving microsecond resolution (10 ns). + * fasttimer uses reg_timer_rw_trig register to get interrupt when + * r_time reaches a certain value. + */ + + +#define DEBUG_LOG_INCLUDED +#define FAST_TIMER_LOG +/* #define FAST_TIMER_TEST */ + +#define FAST_TIMER_SANITY_CHECKS + +#ifdef FAST_TIMER_SANITY_CHECKS +static int sanity_failed; +#endif + +#define D1(x) +#define D2(x) +#define DP(x) + +static unsigned int fast_timer_running; +static unsigned int fast_timers_added; +static unsigned int fast_timers_started; +static unsigned int fast_timers_expired; +static unsigned int fast_timers_deleted; +static unsigned int fast_timer_is_init; +static unsigned int fast_timer_ints; + +struct fast_timer *fast_timer_list = NULL; + +#ifdef DEBUG_LOG_INCLUDED +#define DEBUG_LOG_MAX 128 +static const char * debug_log_string[DEBUG_LOG_MAX]; +static unsigned long debug_log_value[DEBUG_LOG_MAX]; +static unsigned int debug_log_cnt; +static unsigned int debug_log_cnt_wrapped; + +#define DEBUG_LOG(string, value) \ +{ \ + unsigned long log_flags; \ + local_irq_save(log_flags); \ + debug_log_string[debug_log_cnt] = (string); \ + debug_log_value[debug_log_cnt] = (unsigned long)(value); \ + if (++debug_log_cnt >= DEBUG_LOG_MAX) \ + { \ + debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \ + debug_log_cnt_wrapped = 1; \ + } \ + local_irq_restore(log_flags); \ +} +#else +#define DEBUG_LOG(string, value) +#endif + + +#define NUM_TIMER_STATS 16 +#ifdef FAST_TIMER_LOG +struct fast_timer timer_added_log[NUM_TIMER_STATS]; +struct fast_timer timer_started_log[NUM_TIMER_STATS]; +struct fast_timer timer_expired_log[NUM_TIMER_STATS]; +#endif + +int timer_div_settings[NUM_TIMER_STATS]; +int timer_delay_settings[NUM_TIMER_STATS]; + +struct work_struct fast_work; + +static void +timer_trig_handler(struct work_struct *work); + + + +/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */ +inline void do_gettimeofday_fast(struct fasttime_t *tv) +{ + tv->tv_jiff = jiffies; + tv->tv_usec = GET_JIFFIES_USEC(); +} + +inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1) +{ + /* Compare jiffies. Takes care of wrapping */ + if (time_before(t0->tv_jiff, t1->tv_jiff)) + return -1; + else if (time_after(t0->tv_jiff, t1->tv_jiff)) + return 1; + + /* Compare us */ + if (t0->tv_usec < t1->tv_usec) + return -1; + else if (t0->tv_usec > t1->tv_usec) + return 1; + return 0; +} + +/* Called with ints off */ +inline void start_timer_trig(unsigned long delay_us) +{ + reg_timer_rw_ack_intr ack_intr = { 0 }; + reg_timer_rw_intr_mask intr_mask; + reg_timer_rw_trig trig; + reg_timer_rw_trig_cfg trig_cfg = { 0 }; + reg_timer_r_time r_time0; + reg_timer_r_time r_time1; + unsigned char trig_wrap; + unsigned char time_wrap; + + r_time0 = REG_RD(timer, regi_timer0, r_time); + + D1(printk("start_timer_trig : %d us freq: %i div: %i\n", + delay_us, freq_index, div)); + /* Clear trig irq */ + intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); + intr_mask.trig = 0; + REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); + + /* Set timer values and check if trigger wraps. */ + /* r_time is 100MHz (10 ns resolution) */ + trig_wrap = (trig = r_time0 + delay_us*(1000/10)) < r_time0; + + timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig; + timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us; + + /* Ack interrupt */ + ack_intr.trig = 1; + REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); + + /* Start timer */ + REG_WR(timer, regi_timer0, rw_trig, trig); + trig_cfg.tmr = regk_timer_time; + REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); + + /* Check if we have already passed the trig time */ + r_time1 = REG_RD(timer, regi_timer0, r_time); + time_wrap = r_time1 < r_time0; + + if ((trig_wrap && !time_wrap) || (r_time1 < trig)) { + /* No, Enable trig irq */ + intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); + intr_mask.trig = 1; + REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); + fast_timers_started++; + fast_timer_running = 1; + } else { + /* We have passed the time, disable trig point, ack intr */ + trig_cfg.tmr = regk_timer_off; + REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); + REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); + /* call the int routine */ + INIT_WORK(&fast_work, timer_trig_handler); + schedule_work(&fast_work); + } + +} + +/* In version 1.4 this function takes 27 - 50 us */ +void start_one_shot_timer(struct fast_timer *t, + fast_timer_function_type *function, + unsigned long data, + unsigned long delay_us, + const char *name) +{ + unsigned long flags; + struct fast_timer *tmp; + + D1(printk("sft %s %d us\n", name, delay_us)); + + local_irq_save(flags); + + do_gettimeofday_fast(&t->tv_set); + tmp = fast_timer_list; + +#ifdef FAST_TIMER_SANITY_CHECKS + /* Check so this is not in the list already... */ + while (tmp != NULL) { + if (tmp == t) { + printk(KERN_DEBUG + "timer name: %s data: 0x%08lX already " + "in list!\n", name, data); + sanity_failed++; + goto done; + } else + tmp = tmp->next; + } + tmp = fast_timer_list; +#endif + + t->delay_us = delay_us; + t->function = function; + t->data = data; + t->name = name; + + t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000; + t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ; + if (t->tv_expires.tv_usec > 1000000) { + t->tv_expires.tv_usec -= 1000000; + t->tv_expires.tv_jiff += HZ; + } +#ifdef FAST_TIMER_LOG + timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t; +#endif + fast_timers_added++; + + /* Check if this should timeout before anything else */ + if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0) { + /* Put first in list and modify the timer value */ + t->prev = NULL; + t->next = fast_timer_list; + if (fast_timer_list) + fast_timer_list->prev = t; + fast_timer_list = t; +#ifdef FAST_TIMER_LOG + timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; +#endif + start_timer_trig(delay_us); + } else { + /* Put in correct place in list */ + while (tmp->next && + fasttime_cmp(&t->tv_expires, &tmp->next->tv_expires) > 0) + tmp = tmp->next; + /* Insert t after tmp */ + t->prev = tmp; + t->next = tmp->next; + if (tmp->next) + { + tmp->next->prev = t; + } + tmp->next = t; + } + + D2(printk("start_one_shot_timer: %d us done\n", delay_us)); + +done: + local_irq_restore(flags); +} /* start_one_shot_timer */ + +static inline int fast_timer_pending (const struct fast_timer * t) +{ + return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list); +} + +static inline int detach_fast_timer (struct fast_timer *t) +{ + struct fast_timer *next, *prev; + if (!fast_timer_pending(t)) + return 0; + next = t->next; + prev = t->prev; + if (next) + next->prev = prev; + if (prev) + prev->next = next; + else + fast_timer_list = next; + fast_timers_deleted++; + return 1; +} + +int del_fast_timer(struct fast_timer * t) +{ + unsigned long flags; + int ret; + + local_irq_save(flags); + ret = detach_fast_timer(t); + t->next = t->prev = NULL; + local_irq_restore(flags); + return ret; +} /* del_fast_timer */ + + +/* Interrupt routines or functions called in interrupt context */ + +/* Timer interrupt handler for trig interrupts */ + +static irqreturn_t +timer_trig_interrupt(int irq, void *dev_id) +{ + reg_timer_r_masked_intr masked_intr; + /* Check if the timer interrupt is for us (a trig int) */ + masked_intr = REG_RD(timer, regi_timer0, r_masked_intr); + if (!masked_intr.trig) + return IRQ_NONE; + timer_trig_handler(NULL); + return IRQ_HANDLED; +} + +static void timer_trig_handler(struct work_struct *work) +{ + reg_timer_rw_ack_intr ack_intr = { 0 }; + reg_timer_rw_intr_mask intr_mask; + reg_timer_rw_trig_cfg trig_cfg = { 0 }; + struct fast_timer *t; + unsigned long flags; + + /* We keep interrupts disabled not only when we modify the + * fast timer list, but any time we hold a reference to a + * timer in the list, since del_fast_timer may be called + * from (another) interrupt context. Thus, the only time + * when interrupts are enabled is when calling the timer + * callback function. + */ + local_irq_save(flags); + + /* Clear timer trig interrupt */ + intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); + intr_mask.trig = 0; + REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); + + /* First stop timer, then ack interrupt */ + /* Stop timer */ + trig_cfg.tmr = regk_timer_off; + REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); + + /* Ack interrupt */ + ack_intr.trig = 1; + REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); + + fast_timer_running = 0; + fast_timer_ints++; + + fast_timer_function_type *f; + unsigned long d; + + t = fast_timer_list; + while (t) { + struct fasttime_t tv; + + /* Has it really expired? */ + do_gettimeofday_fast(&tv); + D1(printk(KERN_DEBUG + "t: %is %06ius\n", tv.tv_jiff, tv.tv_usec)); + + if (fasttime_cmp(&t->tv_expires, &tv) <= 0) { + /* Yes it has expired */ +#ifdef FAST_TIMER_LOG + timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t; +#endif + fast_timers_expired++; + + /* Remove this timer before call, since it may reuse the timer */ + if (t->prev) + t->prev->next = t->next; + else + fast_timer_list = t->next; + if (t->next) + t->next->prev = t->prev; + t->prev = NULL; + t->next = NULL; + + /* Save function callback data before enabling + * interrupts, since the timer may be removed and we + * don't know how it was allocated (e.g. ->function + * and ->data may become overwritten after deletion + * if the timer was stack-allocated). + */ + f = t->function; + d = t->data; + + if (f != NULL) { + /* Run the callback function with interrupts + * enabled. */ + local_irq_restore(flags); + f(d); + local_irq_save(flags); + } else + DEBUG_LOG("!trimertrig %i function==NULL!\n", fast_timer_ints); + } else { + /* Timer is to early, let's set it again using the normal routines */ + D1(printk(".\n")); + } + + t = fast_timer_list; + if (t != NULL) { + /* Start next timer.. */ + long us = 0; + struct fasttime_t tv; + + do_gettimeofday_fast(&tv); + + /* time_after_eq takes care of wrapping */ + if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff)) + us = ((t->tv_expires.tv_jiff - tv.tv_jiff) * + 1000000 / HZ + t->tv_expires.tv_usec - + tv.tv_usec); + + if (us > 0) { + if (!fast_timer_running) { +#ifdef FAST_TIMER_LOG + timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; +#endif + start_timer_trig(us); + } + break; + } else { + /* Timer already expired, let's handle it better late than never. + * The normal loop handles it + */ + D1(printk("e! %d\n", us)); + } + } + } + + local_irq_restore(flags); + + if (!t) + D1(printk("ttrig stop!\n")); +} + +static void wake_up_func(unsigned long data) +{ + wait_queue_head_t *sleep_wait_p = (wait_queue_head_t*)data; + wake_up(sleep_wait_p); +} + + +/* Useful API */ + +void schedule_usleep(unsigned long us) +{ + struct fast_timer t; + wait_queue_head_t sleep_wait; + init_waitqueue_head(&sleep_wait); + + D1(printk("schedule_usleep(%d)\n", us)); + start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us, + "usleep"); + /* Uninterruptible sleep on the fast timer. (The condition is + * somewhat redundant since the timer is what wakes us up.) */ + wait_event(sleep_wait, !fast_timer_pending(&t)); + + D1(printk("done schedule_usleep(%d)\n", us)); +} + +#ifdef CONFIG_PROC_FS +/* This value is very much based on testing */ +#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300) + +static int proc_fasttimer_show(struct seq_file *m, void *v) +{ + unsigned long flags; + int i = 0; + int num_to_show; + struct fasttime_t tv; + struct fast_timer *t, *nextt; + + do_gettimeofday_fast(&tv); + + seq_printf(m, "Fast timers added: %i\n", fast_timers_added); + seq_printf(m, "Fast timers started: %i\n", fast_timers_started); + seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints); + seq_printf(m, "Fast timers expired: %i\n", fast_timers_expired); + seq_printf(m, "Fast timers deleted: %i\n", fast_timers_deleted); + seq_printf(m, "Fast timer running: %s\n", + fast_timer_running ? "yes" : "no"); + seq_printf(m, "Current time: %lu.%06lu\n", + (unsigned long)tv.tv_jiff, + (unsigned long)tv.tv_usec); +#ifdef FAST_TIMER_SANITY_CHECKS + seq_printf(m, "Sanity failed: %i\n", sanity_failed); +#endif + seq_putc(m, '\n'); + +#ifdef DEBUG_LOG_INCLUDED + { + int end_i = debug_log_cnt; + i = 0; + + if (debug_log_cnt_wrapped) + i = debug_log_cnt; + + while ((i != end_i || debug_log_cnt_wrapped)) { + seq_printf(m, debug_log_string[i], debug_log_value[i]); + if (seq_has_overflowed(m)) + return 0; + i = (i+1) % DEBUG_LOG_MAX; + } + } + seq_putc(m, '\n'); +#endif + + num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started: + NUM_TIMER_STATS); + seq_printf(m, "Timers started: %i\n", fast_timers_started); + for (i = 0; i < num_to_show; i++) { + int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS; + +#if 1 //ndef FAST_TIMER_LOG + seq_printf(m, "div: %i delay: %i\n", + timer_div_settings[cur], + timer_delay_settings[cur]); +#endif +#ifdef FAST_TIMER_LOG + t = &timer_started_log[cur]; + seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", + t->name, + (unsigned long)t->tv_set.tv_jiff, + (unsigned long)t->tv_set.tv_usec, + (unsigned long)t->tv_expires.tv_jiff, + (unsigned long)t->tv_expires.tv_usec, + t->delay_us, + t->data); + if (seq_has_overflowed(m)) + return 0; +#endif + } + seq_putc(m, '\n'); + +#ifdef FAST_TIMER_LOG + num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added: + NUM_TIMER_STATS); + seq_printf(m, "Timers added: %i\n", fast_timers_added); + for (i = 0; i < num_to_show; i++) { + t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS]; + seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", + t->name, + (unsigned long)t->tv_set.tv_jiff, + (unsigned long)t->tv_set.tv_usec, + (unsigned long)t->tv_expires.tv_jiff, + (unsigned long)t->tv_expires.tv_usec, + t->delay_us, + t->data); + if (seq_has_overflowed(m)) + return 0; + } + seq_putc(m, '\n'); + + num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired: + NUM_TIMER_STATS); + seq_printf(m, "Timers expired: %i\n", fast_timers_expired); + for (i = 0; i < num_to_show; i++){ + t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS]; + seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", + t->name, + (unsigned long)t->tv_set.tv_jiff, + (unsigned long)t->tv_set.tv_usec, + (unsigned long)t->tv_expires.tv_jiff, + (unsigned long)t->tv_expires.tv_usec, + t->delay_us, + t->data); + if (seq_has_overflowed(m)) + return 0; + } + seq_putc(m, '\n'); +#endif + + seq_puts(m, "Active timers:\n"); + local_irq_save(flags); + t = fast_timer_list; + while (t != NULL){ + nextt = t->next; + local_irq_restore(flags); + seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", + t->name, + (unsigned long)t->tv_set.tv_jiff, + (unsigned long)t->tv_set.tv_usec, + (unsigned long)t->tv_expires.tv_jiff, + (unsigned long)t->tv_expires.tv_usec, + t->delay_us, + t->data); + if (seq_has_overflowed(m)) + return 0; + local_irq_save(flags); + if (t->next != nextt) + printk("timer removed!\n"); + t = nextt; + } + local_irq_restore(flags); + return 0; +} + +static int proc_fasttimer_open(struct inode *inode, struct file *file) +{ + return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE); +} + +static const struct file_operations proc_fasttimer_fops = { + .open = proc_fasttimer_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +#endif /* PROC_FS */ + +#ifdef FAST_TIMER_TEST +static volatile unsigned long i = 0; +static volatile int num_test_timeout = 0; +static struct fast_timer tr[10]; +static int exp_num[10]; + +static struct fasttime_t tv_exp[100]; + +static void test_timeout(unsigned long data) +{ + do_gettimeofday_fast(&tv_exp[data]); + exp_num[data] = num_test_timeout; + + num_test_timeout++; +} + +static void test_timeout1(unsigned long data) +{ + do_gettimeofday_fast(&tv_exp[data]); + exp_num[data] = num_test_timeout; + if (data < 7) + { + start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1"); + i++; + } + num_test_timeout++; +} + +DP( +static char buf0[2000]; +static char buf1[2000]; +static char buf2[2000]; +static char buf3[2000]; +static char buf4[2000]; +); + +static char buf5[6000]; +static int j_u[1000]; + +static void fast_timer_test(void) +{ + int prev_num; + int j; + + struct fasttime_t tv, tv0, tv1, tv2; + + printk("fast_timer_test() start\n"); + do_gettimeofday_fast(&tv); + + for (j = 0; j < 1000; j++) + { + j_u[j] = GET_JIFFIES_USEC(); + } + for (j = 0; j < 100; j++) + { + do_gettimeofday_fast(&tv_exp[j]); + } + printk(KERN_DEBUG "fast_timer_test() %is %06i\n", tv.tv_jiff, tv.tv_usec); + + for (j = 0; j < 1000; j++) + { + printk(KERN_DEBUG "%i %i %i %i %i\n", + j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]); + j += 4; + } + for (j = 0; j < 100; j++) + { + printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n", + tv_exp[j].tv_jiff, tv_exp[j].tv_usec, + tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec, + tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec, + tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec, + tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec); + j += 4; + } + do_gettimeofday_fast(&tv0); + start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0"); + DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0)); + i++; + start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1"); + DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0)); + i++; + start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2"); + DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0)); + i++; + start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3"); + DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0)); + i++; + start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx"); + DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0)); + i++; + do_gettimeofday_fast(&tv1); + + proc_fasttimer_read(buf5, NULL, 0, 0, 0); + + prev_num = num_test_timeout; + while (num_test_timeout < i) + { + if (num_test_timeout != prev_num) + prev_num = num_test_timeout; + } + do_gettimeofday_fast(&tv2); + printk(KERN_INFO "Timers started %is %06i\n", + tv0.tv_jiff, tv0.tv_usec); + printk(KERN_INFO "Timers started at %is %06i\n", + tv1.tv_jiff, tv1.tv_usec); + printk(KERN_INFO "Timers done %is %06i\n", + tv2.tv_jiff, tv2.tv_usec); + DP(printk("buf0:\n"); + printk(buf0); + printk("buf1:\n"); + printk(buf1); + printk("buf2:\n"); + printk(buf2); + printk("buf3:\n"); + printk(buf3); + printk("buf4:\n"); + printk(buf4); + ); + printk("buf5:\n"); + printk(buf5); + + printk("timers set:\n"); + for(j = 0; jname, + t->tv_set.tv_jiff, + t->tv_set.tv_usec, + t->tv_expires.tv_jiff, + t->tv_expires.tv_usec, + t->data, + t->function + ); + + printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n", + t->delay_us, + tv_exp[j].tv_jiff, + tv_exp[j].tv_usec, + exp_num[j], + (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) * + 1000000 + tv_exp[j].tv_usec - + t->tv_expires.tv_usec); + } + proc_fasttimer_read(buf5, NULL, 0, 0, 0); + printk("buf5 after all done:\n"); + printk(buf5); + printk("fast_timer_test() done\n"); +} +#endif + + +int fast_timer_init(void) +{ + /* For some reason, request_irq() hangs when called froom time_init() */ + if (!fast_timer_is_init) + { + printk("fast_timer_init()\n"); + +#ifdef CONFIG_PROC_FS + proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops); +#endif /* PROC_FS */ + if (request_irq(TIMER0_INTR_VECT, timer_trig_interrupt, + IRQF_SHARED, + "fast timer int", &fast_timer_list)) + printk(KERN_ERR "err: fasttimer irq\n"); + fast_timer_is_init = 1; +#ifdef FAST_TIMER_TEST + printk("do test\n"); + fast_timer_test(); +#endif + } + return 0; +} +__initcall(fast_timer_init); diff --git a/kernel/arch/cris/arch-v32/kernel/head.S b/kernel/arch/cris/arch-v32/kernel/head.S new file mode 100644 index 000000000..74a66e0e3 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/head.S @@ -0,0 +1,440 @@ +/* + * CRISv32 kernel startup code. + * + * Copyright (C) 2003, Axis Communications AB + */ + +#define ASSEMBLER_MACROS_ONLY + +/* + * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so + * -traditional must not be used when assembling this file. + */ +#include +#include +#include +#include +#include +#include + +#define CRAMFS_MAGIC 0x28cd3d45 +#define JHEAD_MAGIC 0x1FF528A6 +#define JHEAD_SIZE 8 +#define RAM_INIT_MAGIC 0x56902387 +#define COMMAND_LINE_MAGIC 0x87109563 +#define NAND_BOOT_MAGIC 0x9a9db001 + + ;; NOTE: R8 and R9 carry information from the decompressor (if the + ;; kernel was compressed). They must not be used in the code below + ;; until they are read! + + ;; Exported symbols. + .global etrax_irv + .global romfs_start + .global romfs_length + .global romfs_in_flash + .global nand_boot + .global swapper_pg_dir + + .text +tstart: + ;; This is the entry point of the kernel. The CPU is currently in + ;; supervisor mode. + ;; + ;; 0x00000000 if flash. + ;; 0x40004000 if DRAM. + ;; + di + + START_CLOCKS + + SETUP_WAIT_STATES + + GIO_INIT + + ;; Setup and enable the MMU. Use same configuration for both the data + ;; and the instruction MMU. + ;; + ;; Note; 3 cycles is needed for a bank-select to take effect. Further; + ;; bank 1 is the instruction MMU, bank 2 is the data MMU. + +#ifdef CONFIG_CRIS_MACH_ARTPEC3 + move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \ + | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \ + | REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 5) \ + | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0 +#else + move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \ + | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \ + | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0 +#endif + + ;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00. + move.d REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4) \ + | REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1 + + ;; Enable certain page protections and setup linear mapping + ;; for f,e,c,b,4,0. + + ;; ARTPEC-3: + ;; c,d used for linear kernel mapping, up to 512 MB + ;; e used for vmalloc + ;; f unused, but page mapped to get page faults + + ;; ETRAX FS: + ;; c used for linear kernel mapping, up to 256 MB + ;; d used for vmalloc + ;; e,f used for memory-mapped NOR flash + +#ifdef CONFIG_CRIS_MACH_ARTPEC3 + move.d REG_STATE(mmu, rw_mm_cfg, we, on) \ + | REG_STATE(mmu, rw_mm_cfg, acc, on) \ + | REG_STATE(mmu, rw_mm_cfg, ex, on) \ + | REG_STATE(mmu, rw_mm_cfg, inv, on) \ + | REG_STATE(mmu, rw_mm_cfg, seg_f, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_e, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_d, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2 +#else + move.d REG_STATE(mmu, rw_mm_cfg, we, on) \ + | REG_STATE(mmu, rw_mm_cfg, acc, on) \ + | REG_STATE(mmu, rw_mm_cfg, ex, on) \ + | REG_STATE(mmu, rw_mm_cfg, inv, on) \ + | REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_d, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \ + | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \ + | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2 +#endif + + ;; Update instruction MMU. + move 1, $srs + nop + nop + nop + move $r0, $s2 ; kbase_hi. + move $r1, $s1 ; kbase_lo. + move $r2, $s0 ; mm_cfg, virtual memory configuration. + + ;; Update data MMU. + move 2, $srs + nop + nop + nop + move $r0, $s2 ; kbase_hi. + move $r1, $s1 ; kbase_lo + move $r2, $s0 ; mm_cfg, virtual memory configuration. + + ;; Enable data and instruction MMU. + move 0, $srs + moveq 0xf, $r0 ; IMMU, DMMU, DCache, Icache on + nop + nop + nop + move $r0, $s0 + nop + nop + nop + + ; Check if starting from DRAM (network->RAM boot or unpacked + ; compressed kernel), or directly from flash. + lapcq ., $r0 + and.d 0x7fffffff, $r0 ; Mask off the non-cache bit. + cmp.d 0x10000, $r0 ; Arbitrary, something above this code. + blo _inflash0 + nop + + jump _inram ; Jump to cached RAM. + nop + + ;; Jumpgate. +_inflash0: + jump _inflash + nop + + ;; Put the following in a section so that storage for it can be + ;; reclaimed after init is finished. + .section ".init.text", "ax" + +_inflash: + + ;; Initialize DRAM. + cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? + beq _dram_initialized + nop + +#if defined CONFIG_ETRAXFS +#include "../mach-fs/dram_init.S" +#elif defined CONFIG_CRIS_MACH_ARTPEC3 +#include "../mach-a3/dram_init.S" +#else +#error Only ETRAXFS and ARTPEC-3 supported! +#endif + + +_dram_initialized: + ;; Copy the text and data section to DRAM. This depends on that the + ;; variables used below are correctly set up by the linker script. + ;; The calculated value stored in R4 is used below. + ;; Leave the cramfs file system (piggybacked after the kernel) in flash. + moveq 0, $r0 ; Source. + move.d text_start, $r1 ; Destination. + move.d __vmlinux_end, $r2 + move.d $r2, $r4 + sub.d $r1, $r4 +1: move.w [$r0+], $r3 + move.w $r3, [$r1+] + cmp.d $r2, $r1 + blo 1b + nop + + ;; Check for cramfs. + moveq 0, $r0 + move.d romfs_length, $r1 + move.d $r0, [$r1] + move.d [$r4], $r0 ; cramfs_super.magic + cmp.d CRAMFS_MAGIC, $r0 + bne 1f + nop + + ;; Set length and start of cramfs, set romfs_in_flash flag + addoq +4, $r4, $acr + move.d [$acr], $r0 + move.d romfs_length, $r1 + move.d $r0, [$r1] + add.d 0xf0000000, $r4 ; Add cached flash start in virtual memory. + move.d romfs_start, $r1 + move.d $r4, [$r1] +1: moveq 1, $r0 + move.d romfs_in_flash, $r1 + move.d $r0, [$r1] + + jump _start_it ; Jump to cached code. + nop + +_inram: + ;; Check if booting from NAND flash; if so, set appropriate flags + ;; and move on. + cmp.d NAND_BOOT_MAGIC, $r12 + bne move_cramfs ; not nand, jump + moveq 1, $r0 + move.d nand_boot, $r1 ; tell axisflashmap we're booting from NAND + move.d $r0, [$r1] + moveq 0, $r0 ; tell axisflashmap romfs is not in + move.d romfs_in_flash, $r1 ; (directly accessed) flash + move.d $r0, [$r1] + jump _start_it ; continue with boot + nop + +move_cramfs: + ;; kernel is in DRAM. + ;; Must figure out if there is a piggybacked rootfs image or not. + ;; Set romfs_length to 0 => no rootfs image available by default. + moveq 0, $r0 + move.d romfs_length, $r1 + move.d $r0, [$r1] + + ;; The kernel could have been unpacked to DRAM by the loader, but + ;; the cramfs image could still be in the flash immediately + ;; following the compressed kernel image. The loader passes the address + ;; of the byte succeeding the last compressed byte in the flash in + ;; register R9 when starting the kernel. + cmp.d 0x0ffffff8, $r9 + bhs _no_romfs_in_flash ; R9 points outside the flash area. + nop + ;; cramfs rootfs might to be in flash. Check for it. + move.d [$r9], $r0 ; cramfs_super.magic + cmp.d CRAMFS_MAGIC, $r0 + bne _no_romfs_in_flash + nop + + ;; found cramfs in flash. set address and size, and romfs_in_flash flag. + addoq +4, $r9, $acr + move.d [$acr], $r0 + move.d romfs_length, $r1 + move.d $r0, [$r1] + add.d 0xf0000000, $r9 ; Add cached flash start in virtual memory. + move.d romfs_start, $r1 + move.d $r9, [$r1] + moveq 1, $r0 + move.d romfs_in_flash, $r1 + move.d $r0, [$r1] + + jump _start_it ; Jump to cached code. + nop + +_no_romfs_in_flash: + ;; No romfs in flash, so look for cramfs, or jffs2 with jhead, + ;; after kernel in RAM, as is the case with network->RAM boot. + ;; For cramfs, partition starts with magic and length. + ;; For jffs2, a jhead is prepended which contains with magic and length. + ;; The jhead is not part of the jffs2 partition however. +#ifndef CONFIG_ETRAXFS_SIM + move.d __bss_start, $r0 +#else + move.d __end, $r0 +#endif + move.d [$r0], $r1 + cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic? + beq 2f ; yes, jump + nop + cmp.d JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic? + bne 4f ; no, skip copy + nop + addq 4, $r0 ; location of jffs2 size + move.d [$r0+], $r2 ; fetch jffs2 size -> r2 + ; r0 now points to start of jffs2 + ba 3f + nop +2: + addoq +4, $r0, $acr ; location of cramfs size + move.d [$acr], $r2 ; fetch cramfs size -> r2 + ; r0 still points to start of cramfs +3: + ;; Now, move the root fs to after kernel's BSS + + move.d _end, $r1 ; start of cramfs -> r1 + move.d romfs_start, $r3 + move.d $r1, [$r3] ; store at romfs_start (for axisflashmap) + move.d romfs_length, $r3 + move.d $r2, [$r3] ; store size at romfs_length + + add.d $r2, $r0 ; copy from end and downwards + add.d $r2, $r1 + + lsrq 1, $r2 ; Size is in bytes, we copy words. + addq 1, $r2 +1: + move.w [$r0], $r3 + move.w $r3, [$r1] + subq 2, $r0 + subq 2, $r1 + subq 1, $r2 + bne 1b + nop + +4: + ;; BSS move done. + ;; Clear romfs_in_flash flag, as we now know romfs is in DRAM + ;; Also clear nand_boot flag; if we got here, we know we've not + ;; booted from NAND flash. + moveq 0, $r0 + move.d romfs_in_flash, $r1 + move.d $r0, [$r1] + moveq 0, $r0 + move.d nand_boot, $r1 + move.d $r0, [$r1] + + jump _start_it ; Jump to cached code. + nop + +_start_it: + + ;; Check if kernel command line is supplied + cmp.d COMMAND_LINE_MAGIC, $r10 + bne no_command_line + nop + + move.d 256, $r13 + move.d cris_command_line, $r10 + or.d 0x80000000, $r11 ; Make it virtual +1: + move.b [$r11+], $r1 + move.b $r1, [$r10+] + subq 1, $r13 + bne 1b + nop + +no_command_line: + + ;; The kernel stack contains a task structure for each task. This + ;; the initial kernel stack is in the same page as the init_task, + ;; but starts at the top of the page, i.e. + 8192 bytes. + move.d init_thread_union + 8192, $sp + move.d ebp_start, $r0 ; Defined in linker-script. + move $r0, $ebp + move.d etrax_irv, $r1 ; Set the exception base register and pointer. + move.d $r0, [$r1] + + ;; Clear the BSS region from _bss_start to _end. + move.d __bss_start, $r0 + move.d _end, $r1 +1: clear.d [$r0+] + cmp.d $r1, $r0 + blo 1b + nop + + ; Initialize registers to increase determinism + move.d __bss_start, $r0 + movem [$r0], $r13 + +#ifdef CONFIG_ETRAX_L2CACHE + jsr l2cache_init + nop +#endif + + jump start_kernel ; Jump to start_kernel() in init/main.c. + nop + + .data +etrax_irv: + .dword 0 + +; Variables for communication with the Axis flash map driver (axisflashmap), +; and for setting up memory in arch/cris/kernel/setup.c . + +; romfs_start is set to the start of the root file system, if it exists +; in directly accessible memory (i.e. NOR Flash when booting from Flash, +; or RAM when booting directly from a network-downloaded RAM image) +romfs_start: + .dword 0 + +; romfs_length is set to the size of the root file system image, if it exists +; in directly accessible memory (see romfs_start). Otherwise it is set to 0. +romfs_length: + .dword 0 + +; romfs_in_flash is set to 1 if the root file system resides in directly +; accessible flash memory (i.e. NOR flash). It is set to 0 for RAM boot +; or NAND flash boot. +romfs_in_flash: + .dword 0 + +; nand_boot is set to 1 when the kernel has been booted from NAND flash +nand_boot: + .dword 0 + +swapper_pg_dir = 0xc0002000 + + .section ".init.data", "aw" + +#if defined CONFIG_ETRAXFS +#include "../mach-fs/hw_settings.S" +#elif defined CONFIG_CRIS_MACH_ARTPEC3 +#include "../mach-a3/hw_settings.S" +#else +#error Only ETRAXFS and ARTPEC-3 supported! +#endif diff --git a/kernel/arch/cris/arch-v32/kernel/irq.c b/kernel/arch/cris/arch-v32/kernel/irq.c new file mode 100644 index 000000000..6a881e0e9 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/irq.c @@ -0,0 +1,520 @@ +/* + * Copyright (C) 2003, Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CPU_FIXED -1 + +/* IRQ masks (refer to comment for crisv32_do_multiple) */ +#if TIMER0_INTR_VECT - FIRST_IRQ < 32 +#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ)) +#undef TIMER_VECT1 +#else +#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32)) +#define TIMER_VECT1 +#endif +#ifdef CONFIG_ETRAX_KGDB +#if defined(CONFIG_ETRAX_KGDB_PORT0) +#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ)) +#elif defined(CONFIG_ETRAX_KGDB_PORT1) +#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ)) +#elif defined(CONFIG_ETRAX_KGB_PORT2) +#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ)) +#elif defined(CONFIG_ETRAX_KGDB_PORT3) +#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ)) +#endif +#endif + +DEFINE_SPINLOCK(irq_lock); + +struct cris_irq_allocation +{ + int cpu; /* The CPU to which the IRQ is currently allocated. */ + cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */ +}; + +struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] = + { [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} }; + +static unsigned long irq_regs[NR_CPUS] = +{ + regi_irq, +}; + +#if NR_REAL_IRQS > 32 +#define NBR_REGS 2 +#else +#define NBR_REGS 1 +#endif + +unsigned long cpu_irq_counters[NR_CPUS]; +unsigned long irq_counters[NR_REAL_IRQS]; + +/* From irq.c. */ +extern void weird_irq(void); + +/* From entry.S. */ +extern void system_call(void); +extern void nmi_interrupt(void); +extern void multiple_interrupt(void); +extern void gdb_handle_exception(void); +extern void i_mmu_refill(void); +extern void i_mmu_invalid(void); +extern void i_mmu_access(void); +extern void i_mmu_execute(void); +extern void d_mmu_refill(void); +extern void d_mmu_invalid(void); +extern void d_mmu_access(void); +extern void d_mmu_write(void); + +/* From kgdb.c. */ +extern void kgdb_init(void); +extern void breakpoint(void); + +/* From traps.c. */ +extern void breakh_BUG(void); + +/* + * Build the IRQ handler stubs using macros from irq.h. + */ +#ifdef CONFIG_CRIS_MACH_ARTPEC3 +BUILD_TIMER_IRQ(0x31, 0) +#else +BUILD_IRQ(0x31) +#endif +BUILD_IRQ(0x32) +BUILD_IRQ(0x33) +BUILD_IRQ(0x34) +BUILD_IRQ(0x35) +BUILD_IRQ(0x36) +BUILD_IRQ(0x37) +BUILD_IRQ(0x38) +BUILD_IRQ(0x39) +BUILD_IRQ(0x3a) +BUILD_IRQ(0x3b) +BUILD_IRQ(0x3c) +BUILD_IRQ(0x3d) +BUILD_IRQ(0x3e) +BUILD_IRQ(0x3f) +BUILD_IRQ(0x40) +BUILD_IRQ(0x41) +BUILD_IRQ(0x42) +BUILD_IRQ(0x43) +BUILD_IRQ(0x44) +BUILD_IRQ(0x45) +BUILD_IRQ(0x46) +BUILD_IRQ(0x47) +BUILD_IRQ(0x48) +BUILD_IRQ(0x49) +BUILD_IRQ(0x4a) +#ifdef CONFIG_ETRAXFS +BUILD_TIMER_IRQ(0x4b, 0) +#else +BUILD_IRQ(0x4b) +#endif +BUILD_IRQ(0x4c) +BUILD_IRQ(0x4d) +BUILD_IRQ(0x4e) +BUILD_IRQ(0x4f) +BUILD_IRQ(0x50) +#if MACH_IRQS > 32 +BUILD_IRQ(0x51) +BUILD_IRQ(0x52) +BUILD_IRQ(0x53) +BUILD_IRQ(0x54) +BUILD_IRQ(0x55) +BUILD_IRQ(0x56) +BUILD_IRQ(0x57) +BUILD_IRQ(0x58) +BUILD_IRQ(0x59) +BUILD_IRQ(0x5a) +BUILD_IRQ(0x5b) +BUILD_IRQ(0x5c) +BUILD_IRQ(0x5d) +BUILD_IRQ(0x5e) +BUILD_IRQ(0x5f) +BUILD_IRQ(0x60) +BUILD_IRQ(0x61) +BUILD_IRQ(0x62) +BUILD_IRQ(0x63) +BUILD_IRQ(0x64) +BUILD_IRQ(0x65) +BUILD_IRQ(0x66) +BUILD_IRQ(0x67) +BUILD_IRQ(0x68) +BUILD_IRQ(0x69) +BUILD_IRQ(0x6a) +BUILD_IRQ(0x6b) +BUILD_IRQ(0x6c) +BUILD_IRQ(0x6d) +BUILD_IRQ(0x6e) +BUILD_IRQ(0x6f) +BUILD_IRQ(0x70) +#endif + +/* Pointers to the low-level handlers. */ +static void (*interrupt[MACH_IRQS])(void) = { + IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt, + IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt, + IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt, + IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt, + IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt, + IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt, + IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt, + IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt, + IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt, + IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt, + IRQ0x4f_interrupt, IRQ0x50_interrupt, +#if MACH_IRQS > 32 + IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt, + IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt, + IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt, + IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt, + IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt, + IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt, + IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt, + IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt, + IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt, + IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt, + IRQ0x6f_interrupt, IRQ0x70_interrupt, +#endif +}; + +void +block_irq(int irq, int cpu) +{ + int intr_mask; + unsigned long flags; + + spin_lock_irqsave(&irq_lock, flags); + /* Remember, 1 let thru, 0 block. */ + if (irq - FIRST_IRQ < 32) { + intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], + rw_mask, 0); + intr_mask &= ~(1 << (irq - FIRST_IRQ)); + REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, + 0, intr_mask); + } else { + intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], + rw_mask, 1); + intr_mask &= ~(1 << (irq - FIRST_IRQ - 32)); + REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, + 1, intr_mask); + } + spin_unlock_irqrestore(&irq_lock, flags); +} + +void +unblock_irq(int irq, int cpu) +{ + int intr_mask; + unsigned long flags; + + spin_lock_irqsave(&irq_lock, flags); + /* Remember, 1 let thru, 0 block. */ + if (irq - FIRST_IRQ < 32) { + intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], + rw_mask, 0); + intr_mask |= (1 << (irq - FIRST_IRQ)); + REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, + 0, intr_mask); + } else { + intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], + rw_mask, 1); + intr_mask |= (1 << (irq - FIRST_IRQ - 32)); + REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, + 1, intr_mask); + } + spin_unlock_irqrestore(&irq_lock, flags); +} + +/* Find out which CPU the irq should be allocated to. */ +static int irq_cpu(int irq) +{ + int cpu; + unsigned long flags; + + spin_lock_irqsave(&irq_lock, flags); + cpu = irq_allocations[irq - FIRST_IRQ].cpu; + + /* Fixed interrupts stay on the local CPU. */ + if (cpu == CPU_FIXED) + { + spin_unlock_irqrestore(&irq_lock, flags); + return smp_processor_id(); + } + + + /* Let the interrupt stay if possible */ + if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask)) + goto out; + + /* IRQ must be moved to another CPU. */ + cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask); + irq_allocations[irq - FIRST_IRQ].cpu = cpu; +out: + spin_unlock_irqrestore(&irq_lock, flags); + return cpu; +} + +void crisv32_mask_irq(int irq) +{ + int cpu; + + for (cpu = 0; cpu < NR_CPUS; cpu++) + block_irq(irq, cpu); +} + +void crisv32_unmask_irq(int irq) +{ + unblock_irq(irq, irq_cpu(irq)); +} + + +static void enable_crisv32_irq(struct irq_data *data) +{ + crisv32_unmask_irq(data->irq); +} + +static void disable_crisv32_irq(struct irq_data *data) +{ + crisv32_mask_irq(data->irq); +} + +static int set_affinity_crisv32_irq(struct irq_data *data, + const struct cpumask *dest, bool force) +{ + unsigned long flags; + + spin_lock_irqsave(&irq_lock, flags); + irq_allocations[data->irq - FIRST_IRQ].mask = *dest; + spin_unlock_irqrestore(&irq_lock, flags); + return 0; +} + +static struct irq_chip crisv32_irq_type = { + .name = "CRISv32", + .irq_shutdown = disable_crisv32_irq, + .irq_enable = enable_crisv32_irq, + .irq_disable = disable_crisv32_irq, + .irq_set_affinity = set_affinity_crisv32_irq, +}; + +void +set_exception_vector(int n, irqvectptr addr) +{ + etrax_irv->v[n] = (irqvectptr) addr; +} + +extern void do_IRQ(int irq, struct pt_regs * regs); + +void +crisv32_do_IRQ(int irq, int block, struct pt_regs* regs) +{ + /* Interrupts that may not be moved to another CPU may + * skip blocking. This is currently only valid for the + * timer IRQ and the IPI and is used for the timer + * interrupt to avoid watchdog starvation. + */ + if (!block) { + do_IRQ(irq, regs); + return; + } + + block_irq(irq, smp_processor_id()); + do_IRQ(irq, regs); + + unblock_irq(irq, irq_cpu(irq)); +} + +/* If multiple interrupts occur simultaneously we get a multiple + * interrupt from the CPU and software has to sort out which + * interrupts that happened. There are two special cases here: + * + * 1. Timer interrupts may never be blocked because of the + * watchdog (refer to comment in include/asr/arch/irq.h) + * 2. GDB serial port IRQs are unhandled here and will be handled + * as a single IRQ when it strikes again because the GDB + * stubb wants to save the registers in its own fashion. + */ +void +crisv32_do_multiple(struct pt_regs* regs) +{ + int cpu; + int mask; + int masked[NBR_REGS]; + int bit; + int i; + + cpu = smp_processor_id(); + + /* An extra irq_enter here to prevent softIRQs to run after + * each do_IRQ. This will decrease the interrupt latency. + */ + irq_enter(); + + for (i = 0; i < NBR_REGS; i++) { + /* Get which IRQs that happened. */ + masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], + r_masked_vect, i); + + /* Calculate new IRQ mask with these IRQs disabled. */ + mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i); + mask &= ~masked[i]; + + /* Timer IRQ is never masked */ +#ifdef TIMER_VECT1 + if ((i == 1) && (masked[0] & TIMER_MASK)) + mask |= TIMER_MASK; +#else + if ((i == 0) && (masked[0] & TIMER_MASK)) + mask |= TIMER_MASK; +#endif + /* Block all the IRQs */ + REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask); + + /* Check for timer IRQ and handle it special. */ +#ifdef TIMER_VECT1 + if ((i == 1) && (masked[i] & TIMER_MASK)) { + masked[i] &= ~TIMER_MASK; + do_IRQ(TIMER0_INTR_VECT, regs); + } +#else + if ((i == 0) && (masked[i] & TIMER_MASK)) { + masked[i] &= ~TIMER_MASK; + do_IRQ(TIMER0_INTR_VECT, regs); + } +#endif + } + +#ifdef IGNORE_MASK + /* Remove IRQs that can't be handled as multiple. */ + masked[0] &= ~IGNORE_MASK; +#endif + + /* Handle the rest of the IRQs. */ + for (i = 0; i < NBR_REGS; i++) { + for (bit = 0; bit < 32; bit++) { + if (masked[i] & (1 << bit)) + do_IRQ(bit + FIRST_IRQ + i*32, regs); + } + } + + /* Unblock all the IRQs. */ + for (i = 0; i < NBR_REGS; i++) { + mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i); + mask |= masked[i]; + REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask); + } + + /* This irq_exit() will trigger the soft IRQs. */ + irq_exit(); +} + +static int crisv32_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq); + + return 0; +} + +static struct irq_domain_ops crisv32_irq_ops = { + .map = crisv32_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +/* + * This is called by start_kernel. It fixes the IRQ masks and setup the + * interrupt vector table to point to bad_interrupt pointers. + */ +void __init +init_IRQ(void) +{ + int i; + int j; + reg_intr_vect_rw_mask vect_mask = {0}; + struct device_node *np; + struct irq_domain *domain; + + /* Clear all interrupts masks. */ + for (i = 0; i < NBR_REGS; i++) + REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask); + + for (i = 0; i < 256; i++) + etrax_irv->v[i] = weird_irq; + + np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc"); + domain = irq_domain_add_legacy(np, NR_IRQS - FIRST_IRQ, + FIRST_IRQ, FIRST_IRQ, + &crisv32_irq_ops, NULL); + BUG_ON(!domain); + irq_set_default_host(domain); + of_node_put(np); + + for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { + set_exception_vector(i, interrupt[j]); + } + + /* Mark Timer and IPI IRQs as CPU local */ + irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED; + irq_set_status_flags(TIMER0_INTR_VECT, IRQ_PER_CPU); + irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED; + irq_set_status_flags(IPI_INTR_VECT, IRQ_PER_CPU); + + set_exception_vector(0x00, nmi_interrupt); + set_exception_vector(0x30, multiple_interrupt); + + /* Set up handler for various MMU bus faults. */ + set_exception_vector(0x04, i_mmu_refill); + set_exception_vector(0x05, i_mmu_invalid); + set_exception_vector(0x06, i_mmu_access); + set_exception_vector(0x07, i_mmu_execute); + set_exception_vector(0x08, d_mmu_refill); + set_exception_vector(0x09, d_mmu_invalid); + set_exception_vector(0x0a, d_mmu_access); + set_exception_vector(0x0b, d_mmu_write); + +#ifdef CONFIG_BUG + /* Break 14 handler, used to implement cheap BUG(). */ + set_exception_vector(0x1e, breakh_BUG); +#endif + + /* The system-call trap is reached by "break 13". */ + set_exception_vector(0x1d, system_call); + + /* Exception handlers for debugging, both user-mode and kernel-mode. */ + + /* Break 8. */ + set_exception_vector(0x18, gdb_handle_exception); + /* Hardware single step. */ + set_exception_vector(0x3, gdb_handle_exception); + /* Hardware breakpoint. */ + set_exception_vector(0xc, gdb_handle_exception); + +#ifdef CONFIG_ETRAX_KGDB + kgdb_init(); + /* Everything is set up; now trap the kernel. */ + breakpoint(); +#endif +} + diff --git a/kernel/arch/cris/arch-v32/kernel/kgdb.c b/kernel/arch/cris/arch-v32/kernel/kgdb.c new file mode 100644 index 000000000..b06813aeb --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/kgdb.c @@ -0,0 +1,1612 @@ +/* + * arch/cris/arch-v32/kernel/kgdb.c + * + * CRIS v32 version by Orjan Friberg, Axis Communications AB. + * + * S390 version + * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation + * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), + * + * Originally written by Glenn Engel, Lake Stevens Instrument Division + * + * Contributed by HP Systems + * + * Modified for SPARC by Stu Grossman, Cygnus Support. + * + * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse + * Send complaints, suggestions etc. to + * + * Copyright (C) 1995 Andreas Busse + */ + +/* FIXME: Check the documentation. */ + +/* + * kgdb usage notes: + * ----------------- + * + * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be + * built with different gcc flags: "-g" is added to get debug infos, and + * "-fomit-frame-pointer" is omitted to make debugging easier. Since the + * resulting kernel will be quite big (approx. > 7 MB), it will be stripped + * before compresion. Such a kernel will behave just as usually, except if + * given a "debug=" command line option. (Only serial devices are + * allowed for , i.e. no printers or the like; possible values are + * machine depedend and are the same as for the usual debug device, the one + * for logging kernel messages.) If that option is given and the device can be + * initialized, the kernel will connect to the remote gdb in trap_init(). The + * serial parameters are fixed to 8N1 and 115200 bps, for easyness of + * implementation. + * + * To start a debugging session, start that gdb with the debugging kernel + * image (the one with the symbols, vmlinux.debug) named on the command line. + * This file will be used by gdb to get symbol and debugging infos about the + * kernel. Next, select remote debug mode by + * target remote + * where is the name of the serial device over which the debugged + * machine is connected. Maybe you have to adjust the baud rate by + * set remotebaud + * or also other parameters with stty: + * shell stty ... #. + * + * where + * :: + * :: < two hex digits computed as modulo 256 sum of > + * + * When a packet is received, it is first acknowledged with either '+' or '-'. + * '+' indicates a successful transfer. '-' indicates a failed transfer. + * + * Example: + * + * Host: Reply: + * $m0,10#2a +$00010203040506070809101112131415#42 + * + */ + + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +/* From entry.S. */ +extern void gdb_handle_exception(void); +/* From kgdb_asm.S. */ +extern void kgdb_handle_exception(void); + +static int kgdb_started = 0; + +/********************************* Register image ****************************/ + +typedef +struct register_image +{ + /* Offset */ + unsigned int r0; /* 0x00 */ + unsigned int r1; /* 0x04 */ + unsigned int r2; /* 0x08 */ + unsigned int r3; /* 0x0C */ + unsigned int r4; /* 0x10 */ + unsigned int r5; /* 0x14 */ + unsigned int r6; /* 0x18 */ + unsigned int r7; /* 0x1C */ + unsigned int r8; /* 0x20; Frame pointer (if any) */ + unsigned int r9; /* 0x24 */ + unsigned int r10; /* 0x28 */ + unsigned int r11; /* 0x2C */ + unsigned int r12; /* 0x30 */ + unsigned int r13; /* 0x34 */ + unsigned int sp; /* 0x38; R14, Stack pointer */ + unsigned int acr; /* 0x3C; R15, Address calculation register. */ + + unsigned char bz; /* 0x40; P0, 8-bit zero register */ + unsigned char vr; /* 0x41; P1, Version register (8-bit) */ + unsigned int pid; /* 0x42; P2, Process ID */ + unsigned char srs; /* 0x46; P3, Support register select (8-bit) */ + unsigned short wz; /* 0x47; P4, 16-bit zero register */ + unsigned int exs; /* 0x49; P5, Exception status */ + unsigned int eda; /* 0x4D; P6, Exception data address */ + unsigned int mof; /* 0x51; P7, Multiply overflow register */ + unsigned int dz; /* 0x55; P8, 32-bit zero register */ + unsigned int ebp; /* 0x59; P9, Exception base pointer */ + unsigned int erp; /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */ + unsigned int srp; /* 0x61; P11, Subroutine return pointer */ + unsigned int nrp; /* 0x65; P12, NMI return pointer */ + unsigned int ccs; /* 0x69; P13, Condition code stack */ + unsigned int usp; /* 0x6D; P14, User mode stack pointer */ + unsigned int spc; /* 0x71; P15, Single step PC */ + unsigned int pc; /* 0x75; Pseudo register (for the most part set to ERP). */ + +} registers; + +typedef +struct bp_register_image +{ + /* Support register bank 0. */ + unsigned int s0_0; + unsigned int s1_0; + unsigned int s2_0; + unsigned int s3_0; + unsigned int s4_0; + unsigned int s5_0; + unsigned int s6_0; + unsigned int s7_0; + unsigned int s8_0; + unsigned int s9_0; + unsigned int s10_0; + unsigned int s11_0; + unsigned int s12_0; + unsigned int s13_0; + unsigned int s14_0; + unsigned int s15_0; + + /* Support register bank 1. */ + unsigned int s0_1; + unsigned int s1_1; + unsigned int s2_1; + unsigned int s3_1; + unsigned int s4_1; + unsigned int s5_1; + unsigned int s6_1; + unsigned int s7_1; + unsigned int s8_1; + unsigned int s9_1; + unsigned int s10_1; + unsigned int s11_1; + unsigned int s12_1; + unsigned int s13_1; + unsigned int s14_1; + unsigned int s15_1; + + /* Support register bank 2. */ + unsigned int s0_2; + unsigned int s1_2; + unsigned int s2_2; + unsigned int s3_2; + unsigned int s4_2; + unsigned int s5_2; + unsigned int s6_2; + unsigned int s7_2; + unsigned int s8_2; + unsigned int s9_2; + unsigned int s10_2; + unsigned int s11_2; + unsigned int s12_2; + unsigned int s13_2; + unsigned int s14_2; + unsigned int s15_2; + + /* Support register bank 3. */ + unsigned int s0_3; /* BP_CTRL */ + unsigned int s1_3; /* BP_I0_START */ + unsigned int s2_3; /* BP_I0_END */ + unsigned int s3_3; /* BP_D0_START */ + unsigned int s4_3; /* BP_D0_END */ + unsigned int s5_3; /* BP_D1_START */ + unsigned int s6_3; /* BP_D1_END */ + unsigned int s7_3; /* BP_D2_START */ + unsigned int s8_3; /* BP_D2_END */ + unsigned int s9_3; /* BP_D3_START */ + unsigned int s10_3; /* BP_D3_END */ + unsigned int s11_3; /* BP_D4_START */ + unsigned int s12_3; /* BP_D4_END */ + unsigned int s13_3; /* BP_D5_START */ + unsigned int s14_3; /* BP_D5_END */ + unsigned int s15_3; /* BP_RESERVED */ + +} support_registers; + +enum register_name +{ + R0, R1, R2, R3, + R4, R5, R6, R7, + R8, R9, R10, R11, + R12, R13, SP, ACR, + + BZ, VR, PID, SRS, + WZ, EXS, EDA, MOF, + DZ, EBP, ERP, SRP, + NRP, CCS, USP, SPC, + PC, + + S0, S1, S2, S3, + S4, S5, S6, S7, + S8, S9, S10, S11, + S12, S13, S14, S15 + +}; + +/* The register sizes of the registers in register_name. An unimplemented register + is designated by size 0 in this array. */ +static int register_size[] = +{ + 4, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4, 4, + + 1, 1, 4, 1, + 2, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4, 4, + + 4, + + 4, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4, 4, + 4, 4, 4 + +}; + +/* Contains the register image of the kernel. + (Global so that they can be reached from assembler code.) */ +registers reg; +support_registers sreg; + +/************** Prototypes for local library functions ***********************/ + +/* Copy of strcpy from libc. */ +static char *gdb_cris_strcpy(char *s1, const char *s2); + +/* Copy of strlen from libc. */ +static int gdb_cris_strlen(const char *s); + +/* Copy of memchr from libc. */ +static void *gdb_cris_memchr(const void *s, int c, int n); + +/* Copy of strtol from libc. Does only support base 16. */ +static int gdb_cris_strtol(const char *s, char **endptr, int base); + +/********************** Prototypes for local functions. **********************/ + +/* Write a value to a specified register regno in the register image + of the current thread. */ +static int write_register(int regno, char *val); + +/* Read a value from a specified register in the register image. Returns the + status of the read operation. The register value is returned in valptr. */ +static int read_register(char regno, unsigned int *valptr); + +/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */ +int getDebugChar(void); + +/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */ +void putDebugChar(int val); + +/* Returns the integer equivalent of a hexadecimal character. */ +static int hex(char ch); + +/* Convert the memory, pointed to by mem into hexadecimal representation. + Put the result in buf, and return a pointer to the last character + in buf (null). */ +static char *mem2hex(char *buf, unsigned char *mem, int count); + +/* Convert the array, in hexadecimal representation, pointed to by buf into + binary representation. Put the result in mem, and return a pointer to + the character after the last byte written. */ +static unsigned char *hex2mem(unsigned char *mem, char *buf, int count); + +/* Put the content of the array, in binary representation, pointed to by buf + into memory pointed to by mem, and return a pointer to + the character after the last byte written. */ +static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count); + +/* Await the sequence $# and store in the array buffer + returned. */ +static void getpacket(char *buffer); + +/* Send $# from the in the array buffer. */ +static void putpacket(char *buffer); + +/* Build and send a response packet in order to inform the host the + stub is stopped. */ +static void stub_is_stopped(int sigval); + +/* All expected commands are sent from remote.c. Send a response according + to the description in remote.c. Not static since it needs to be reached + from assembler code. */ +void handle_exception(int sigval); + +/* Performs a complete re-start from scratch. ETRAX specific. */ +static void kill_restart(void); + +/******************** Prototypes for global functions. ***********************/ + +/* The string str is prepended with the GDB printout token and sent. */ +void putDebugString(const unsigned char *str, int len); + +/* A static breakpoint to be used at startup. */ +void breakpoint(void); + +/* Avoid warning as the internal_stack is not used in the C-code. */ +#define USEDVAR(name) { if (name) { ; } } +#define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) } + +/********************************** Packet I/O ******************************/ +/* BUFMAX defines the maximum number of characters in + inbound/outbound buffers */ +/* FIXME: How do we know it's enough? */ +#define BUFMAX 512 + +/* Run-length encoding maximum length. Send 64 at most. */ +#define RUNLENMAX 64 + +/* The inbound/outbound buffers used in packet I/O */ +static char input_buffer[BUFMAX]; +static char output_buffer[BUFMAX]; + +/* Error and warning messages. */ +enum error_type +{ + SUCCESS, E01, E02, E03, E04, E05, E06, +}; + +static char *error_message[] = +{ + "", + "E01 Set current or general thread - H[c,g] - internal error.", + "E02 Change register content - P - cannot change read-only register.", + "E03 Thread is not alive.", /* T, not used. */ + "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.", + "E05 Change register content - P - the register is not implemented..", + "E06 Change memory content - M - internal error.", +}; + +/********************************** Breakpoint *******************************/ +/* Use an internal stack in the breakpoint and interrupt response routines. + FIXME: How do we know the size of this stack is enough? + Global so it can be reached from assembler code. */ +#define INTERNAL_STACK_SIZE 1024 +char internal_stack[INTERNAL_STACK_SIZE]; + +/* Due to the breakpoint return pointer, a state variable is needed to keep + track of whether it is a static (compiled) or dynamic (gdb-invoked) + breakpoint to be handled. A static breakpoint uses the content of register + ERP as it is whereas a dynamic breakpoint requires subtraction with 2 + in order to execute the instruction. The first breakpoint is static; all + following are assumed to be dynamic. */ +static int dynamic_bp = 0; + +/********************************* String library ****************************/ +/* Single-step over library functions creates trap loops. */ + +/* Copy char s2[] to s1[]. */ +static char* +gdb_cris_strcpy(char *s1, const char *s2) +{ + char *s = s1; + + for (s = s1; (*s++ = *s2++) != '\0'; ) + ; + return s1; +} + +/* Find length of s[]. */ +static int +gdb_cris_strlen(const char *s) +{ + const char *sc; + + for (sc = s; *sc != '\0'; sc++) + ; + return (sc - s); +} + +/* Find first occurrence of c in s[n]. */ +static void* +gdb_cris_memchr(const void *s, int c, int n) +{ + const unsigned char uc = c; + const unsigned char *su; + + for (su = s; 0 < n; ++su, --n) + if (*su == uc) + return (void *)su; + return NULL; +} +/******************************* Standard library ****************************/ +/* Single-step over library functions creates trap loops. */ +/* Convert string to long. */ +static int +gdb_cris_strtol(const char *s, char **endptr, int base) +{ + char *s1; + char *sd; + int x = 0; + + for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1) + x = x * base + (sd - hex_asc); + + if (endptr) { + /* Unconverted suffix is stored in endptr unless endptr is NULL. */ + *endptr = s1; + } + + return x; +} + +/********************************* Register image ****************************/ + +/* Write a value to a specified register in the register image of the current + thread. Returns status code SUCCESS, E02 or E05. */ +static int +write_register(int regno, char *val) +{ + int status = SUCCESS; + + if (regno >= R0 && regno <= ACR) { + /* Consecutive 32-bit registers. */ + hex2mem((unsigned char *)®.r0 + (regno - R0) * sizeof(unsigned int), + val, sizeof(unsigned int)); + + } else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) { + /* Read-only registers. */ + status = E02; + + } else if (regno == PID) { + /* 32-bit register. (Even though we already checked SRS and WZ, we cannot + combine this with the EXS - SPC write since SRS and WZ have different size.) */ + hex2mem((unsigned char *)®.pid, val, sizeof(unsigned int)); + + } else if (regno == SRS) { + /* 8-bit register. */ + hex2mem((unsigned char *)®.srs, val, sizeof(unsigned char)); + + } else if (regno >= EXS && regno <= SPC) { + /* Consecutive 32-bit registers. */ + hex2mem((unsigned char *)®.exs + (regno - EXS) * sizeof(unsigned int), + val, sizeof(unsigned int)); + + } else if (regno == PC) { + /* Pseudo-register. Treat as read-only. */ + status = E02; + + } else if (regno >= S0 && regno <= S15) { + /* 32-bit registers. */ + hex2mem((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int), val, sizeof(unsigned int)); + } else { + /* Non-existing register. */ + status = E05; + } + return status; +} + +/* Read a value from a specified register in the register image. Returns the + value in the register or -1 for non-implemented registers. */ +static int +read_register(char regno, unsigned int *valptr) +{ + int status = SUCCESS; + + /* We read the zero registers from the register struct (instead of just returning 0) + to catch errors. */ + + if (regno >= R0 && regno <= ACR) { + /* Consecutive 32-bit registers. */ + *valptr = *(unsigned int *)((char *)®.r0 + (regno - R0) * sizeof(unsigned int)); + + } else if (regno == BZ || regno == VR) { + /* Consecutive 8-bit registers. */ + *valptr = (unsigned int)(*(unsigned char *) + ((char *)®.bz + (regno - BZ) * sizeof(char))); + + } else if (regno == PID) { + /* 32-bit register. */ + *valptr = *(unsigned int *)((char *)®.pid); + + } else if (regno == SRS) { + /* 8-bit register. */ + *valptr = (unsigned int)(*(unsigned char *)((char *)®.srs)); + + } else if (regno == WZ) { + /* 16-bit register. */ + *valptr = (unsigned int)(*(unsigned short *)(char *)®.wz); + + } else if (regno >= EXS && regno <= PC) { + /* Consecutive 32-bit registers. */ + *valptr = *(unsigned int *)((char *)®.exs + (regno - EXS) * sizeof(unsigned int)); + + } else if (regno >= S0 && regno <= S15) { + /* Consecutive 32-bit registers, located elsewhere. */ + *valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int)); + + } else { + /* Non-existing register. */ + status = E05; + } + return status; + +} + +/********************************** Packet I/O ******************************/ +/* Returns the integer equivalent of a hexadecimal character. */ +static int +hex(char ch) +{ + if ((ch >= 'a') && (ch <= 'f')) + return (ch - 'a' + 10); + if ((ch >= '0') && (ch <= '9')) + return (ch - '0'); + if ((ch >= 'A') && (ch <= 'F')) + return (ch - 'A' + 10); + return -1; +} + +/* Convert the memory, pointed to by mem into hexadecimal representation. + Put the result in buf, and return a pointer to the last character + in buf (null). */ + +static char * +mem2hex(char *buf, unsigned char *mem, int count) +{ + int i; + int ch; + + if (mem == NULL) { + /* Invalid address, caught by 'm' packet handler. */ + for (i = 0; i < count; i++) { + *buf++ = '0'; + *buf++ = '0'; + } + } else { + /* Valid mem address. */ + for (i = 0; i < count; i++) { + ch = *mem++; + buf = hex_byte_pack(buf, ch); + } + } + /* Terminate properly. */ + *buf = '\0'; + return buf; +} + +/* Same as mem2hex, but puts it in network byte order. */ +static char * +mem2hex_nbo(char *buf, unsigned char *mem, int count) +{ + int i; + int ch; + + mem += count - 1; + for (i = 0; i < count; i++) { + ch = *mem--; + buf = hex_byte_pack(buf, ch); + } + + /* Terminate properly. */ + *buf = '\0'; + return buf; +} + +/* Convert the array, in hexadecimal representation, pointed to by buf into + binary representation. Put the result in mem, and return a pointer to + the character after the last byte written. */ +static unsigned char* +hex2mem(unsigned char *mem, char *buf, int count) +{ + int i; + unsigned char ch; + for (i = 0; i < count; i++) { + ch = hex (*buf++) << 4; + ch = ch + hex (*buf++); + *mem++ = ch; + } + return mem; +} + +/* Put the content of the array, in binary representation, pointed to by buf + into memory pointed to by mem, and return a pointer to the character after + the last byte written. + Gdb will escape $, #, and the escape char (0x7d). */ +static unsigned char* +bin2mem(unsigned char *mem, unsigned char *buf, int count) +{ + int i; + unsigned char *next; + for (i = 0; i < count; i++) { + /* Check for any escaped characters. Be paranoid and + only unescape chars that should be escaped. */ + if (*buf == 0x7d) { + next = buf + 1; + if (*next == 0x3 || *next == 0x4 || *next == 0x5D) { + /* #, $, ESC */ + buf++; + *buf += 0x20; + } + } + *mem++ = *buf++; + } + return mem; +} + +/* Await the sequence $# and store in the array buffer + returned. */ +static void +getpacket(char *buffer) +{ + unsigned char checksum; + unsigned char xmitcsum; + int i; + int count; + char ch; + + do { + while((ch = getDebugChar ()) != '$') + /* Wait for the start character $ and ignore all other characters */; + checksum = 0; + xmitcsum = -1; + count = 0; + /* Read until a # or the end of the buffer is reached */ + while (count < BUFMAX) { + ch = getDebugChar(); + if (ch == '#') + break; + checksum = checksum + ch; + buffer[count] = ch; + count = count + 1; + } + + if (count >= BUFMAX) + continue; + + buffer[count] = 0; + + if (ch == '#') { + xmitcsum = hex(getDebugChar()) << 4; + xmitcsum += hex(getDebugChar()); + if (checksum != xmitcsum) { + /* Wrong checksum */ + putDebugChar('-'); + } else { + /* Correct checksum */ + putDebugChar('+'); + /* If sequence characters are received, reply with them */ + if (buffer[2] == ':') { + putDebugChar(buffer[0]); + putDebugChar(buffer[1]); + /* Remove the sequence characters from the buffer */ + count = gdb_cris_strlen(buffer); + for (i = 3; i <= count; i++) + buffer[i - 3] = buffer[i]; + } + } + } + } while (checksum != xmitcsum); +} + +/* Send $# from the in the array buffer. */ + +static void +putpacket(char *buffer) +{ + int checksum; + int runlen; + int encode; + + do { + char *src = buffer; + putDebugChar('$'); + checksum = 0; + while (*src) { + /* Do run length encoding */ + putDebugChar(*src); + checksum += *src; + runlen = 0; + while (runlen < RUNLENMAX && *src == src[runlen]) { + runlen++; + } + if (runlen > 3) { + /* Got a useful amount */ + putDebugChar ('*'); + checksum += '*'; + encode = runlen + ' ' - 4; + putDebugChar(encode); + checksum += encode; + src += runlen; + } else { + src++; + } + } + putDebugChar('#'); + putDebugChar(hex_asc_hi(checksum)); + putDebugChar(hex_asc_lo(checksum)); + } while(kgdb_started && (getDebugChar() != '+')); +} + +/* The string str is prepended with the GDB printout token and sent. Required + in traditional implementations. */ +void +putDebugString(const unsigned char *str, int len) +{ + /* Move SPC forward if we are single-stepping. */ + asm("spchere:"); + asm("move $spc, $r10"); + asm("cmp.d spchere, $r10"); + asm("bne nosstep"); + asm("nop"); + asm("move.d spccont, $r10"); + asm("move $r10, $spc"); + asm("nosstep:"); + + output_buffer[0] = 'O'; + mem2hex(&output_buffer[1], (unsigned char *)str, len); + putpacket(output_buffer); + + asm("spccont:"); +} + +/********************************** Handle exceptions ************************/ +/* Build and send a response packet in order to inform the host the + stub is stopped. TAAn...:r...;n...:r...;n...:r...; + AA = signal number + n... = register number (hex) + r... = register contents + n... = `thread' + r... = thread process ID. This is a hex integer. + n... = other string not starting with valid hex digit. + gdb should ignore this n,r pair and go on to the next. + This way we can extend the protocol. */ +static void +stub_is_stopped(int sigval) +{ + char *ptr = output_buffer; + unsigned int reg_cont; + + /* Send trap type (converted to signal) */ + + *ptr++ = 'T'; + ptr = hex_byte_pack(ptr, sigval); + + if (((reg.exs & 0xff00) >> 8) == 0xc) { + + /* Some kind of hardware watchpoint triggered. Find which one + and determine its type (read/write/access). */ + int S, bp, trig_bits = 0, rw_bits = 0; + int trig_mask = 0; + unsigned int *bp_d_regs = &sreg.s3_3; + /* In a lot of cases, the stopped data address will simply be EDA. + In some cases, we adjust it to match the watched data range. + (We don't want to change the actual EDA though). */ + unsigned int stopped_data_address; + /* The S field of EXS. */ + S = (reg.exs & 0xffff0000) >> 16; + + if (S & 1) { + /* Instruction watchpoint. */ + /* FIXME: Check against, and possibly adjust reported EDA. */ + } else { + /* Data watchpoint. Find the one that triggered. */ + for (bp = 0; bp < 6; bp++) { + + /* Dx_RD, Dx_WR in the S field of EXS for this BP. */ + int bitpos_trig = 1 + bp * 2; + /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */ + int bitpos_config = 2 + bp * 4; + + /* Get read/write trig bits for this BP. */ + trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig; + + /* Read/write config bits for this BP. */ + rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config; + if (trig_bits) { + /* Sanity check: the BP shouldn't trigger for accesses + that it isn't configured for. */ + if ((rw_bits == 0x1 && trig_bits != 0x1) || + (rw_bits == 0x2 && trig_bits != 0x2)) + panic("Invalid r/w trigging for this BP"); + + /* Mark this BP as trigged for future reference. */ + trig_mask |= (1 << bp); + + if (reg.eda >= bp_d_regs[bp * 2] && + reg.eda <= bp_d_regs[bp * 2 + 1]) { + /* EDA within range for this BP; it must be the one + we're looking for. */ + stopped_data_address = reg.eda; + break; + } + } + } + if (bp < 6) { + /* Found a trigged BP with EDA within its configured data range. */ + } else if (trig_mask) { + /* Something triggered, but EDA doesn't match any BP's range. */ + for (bp = 0; bp < 6; bp++) { + /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */ + int bitpos_config = 2 + bp * 4; + + /* Read/write config bits for this BP (needed later). */ + rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config; + + if (trig_mask & (1 << bp)) { + /* EDA within 31 bytes of the configured start address? */ + if (reg.eda + 31 >= bp_d_regs[bp * 2]) { + /* Changing the reported address to match + the start address of the first applicable BP. */ + stopped_data_address = bp_d_regs[bp * 2]; + break; + } else { + /* We continue since we might find another useful BP. */ + printk("EDA doesn't match trigged BP's range"); + } + } + } + } + + /* No match yet? */ + BUG_ON(bp >= 6); + /* Note that we report the type according to what the BP is configured + for (otherwise we'd never report an 'awatch'), not according to how + it trigged. We did check that the trigged bits match what the BP is + configured for though. */ + if (rw_bits == 0x1) { + /* read */ + strncpy(ptr, "rwatch", 6); + ptr += 6; + } else if (rw_bits == 0x2) { + /* write */ + strncpy(ptr, "watch", 5); + ptr += 5; + } else if (rw_bits == 0x3) { + /* access */ + strncpy(ptr, "awatch", 6); + ptr += 6; + } else { + panic("Invalid r/w bits for this BP."); + } + + *ptr++ = ':'; + /* Note that we don't read_register(EDA, ...) */ + ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]); + *ptr++ = ';'; + } + } + /* Only send PC, frame and stack pointer. */ + read_register(PC, ®_cont); + ptr = hex_byte_pack(ptr, PC); + *ptr++ = ':'; + ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[PC]); + *ptr++ = ';'; + + read_register(R8, ®_cont); + ptr = hex_byte_pack(ptr, R8); + *ptr++ = ':'; + ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[R8]); + *ptr++ = ';'; + + read_register(SP, ®_cont); + ptr = hex_byte_pack(ptr, SP); + *ptr++ = ':'; + ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[SP]); + *ptr++ = ';'; + + /* Send ERP as well; this will save us an entire register fetch in some cases. */ + read_register(ERP, ®_cont); + ptr = hex_byte_pack(ptr, ERP); + *ptr++ = ':'; + ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[ERP]); + *ptr++ = ';'; + + /* null-terminate and send it off */ + *ptr = 0; + putpacket(output_buffer); +} + +/* Returns the size of an instruction that has a delay slot. */ + +int insn_size(unsigned long pc) +{ + unsigned short opcode = *(unsigned short *)pc; + int size = 0; + + switch ((opcode & 0x0f00) >> 8) { + case 0x0: + case 0x9: + case 0xb: + size = 2; + break; + case 0xe: + case 0xf: + size = 6; + break; + case 0xd: + /* Could be 4 or 6; check more bits. */ + if ((opcode & 0xff) == 0xff) + size = 4; + else + size = 6; + break; + default: + panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc); + } + + return size; +} + +void register_fixup(int sigval) +{ + /* Compensate for ACR push at the beginning of exception handler. */ + reg.sp += 4; + + /* Standard case. */ + reg.pc = reg.erp; + if (reg.erp & 0x1) { + /* Delay slot bit set. Report as stopped on proper instruction. */ + if (reg.spc) { + /* Rely on SPC if set. */ + reg.pc = reg.spc; + } else { + /* Calculate the PC from the size of the instruction + that the delay slot we're in belongs to. */ + reg.pc += insn_size(reg.erp & ~1) - 1 ; + } + } + + if ((reg.exs & 0x3) == 0x0) { + /* Bits 1 - 0 indicate the type of memory operation performed + by the interrupted instruction. 0 means no memory operation, + and EDA is undefined in that case. We zero it to avoid confusion. */ + reg.eda = 0; + } + + if (sigval == SIGTRAP) { + /* Break 8, single step or hardware breakpoint exception. */ + + /* Check IDX field of EXS. */ + if (((reg.exs & 0xff00) >> 8) == 0x18) { + + /* Break 8. */ + + /* Static (compiled) breakpoints must return to the next instruction + in order to avoid infinite loops (default value of ERP). Dynamic + (gdb-invoked) must subtract the size of the break instruction from + the ERP so that the instruction that was originally in the break + instruction's place will be run when we return from the exception. */ + if (!dynamic_bp) { + /* Assuming that all breakpoints are dynamic from now on. */ + dynamic_bp = 1; + } else { + + /* Only if not in a delay slot. */ + if (!(reg.erp & 0x1)) { + reg.erp -= 2; + reg.pc -= 2; + } + } + + } else if (((reg.exs & 0xff00) >> 8) == 0x3) { + /* Single step. */ + /* Don't fiddle with S1. */ + + } else if (((reg.exs & 0xff00) >> 8) == 0xc) { + + /* Hardware watchpoint exception. */ + + /* SPC has been updated so that we will get a single step exception + when we return, but we don't want that. */ + reg.spc = 0; + + /* Don't fiddle with S1. */ + } + + } else if (sigval == SIGINT) { + /* Nothing special. */ + } +} + +static void insert_watchpoint(char type, int addr, int len) +{ + /* Breakpoint/watchpoint types (GDB terminology): + 0 = memory breakpoint for instructions + (not supported; done via memory write instead) + 1 = hardware breakpoint for instructions (supported) + 2 = write watchpoint (supported) + 3 = read watchpoint (supported) + 4 = access watchpoint (supported) */ + + if (type < '1' || type > '4') { + output_buffer[0] = 0; + return; + } + + /* Read watchpoints are set as access watchpoints, because of GDB's + inability to deal with pure read watchpoints. */ + if (type == '3') + type = '4'; + + if (type == '1') { + /* Hardware (instruction) breakpoint. */ + /* Bit 0 in BP_CTRL holds the configuration for I0. */ + if (sreg.s0_3 & 0x1) { + /* Already in use. */ + gdb_cris_strcpy(output_buffer, error_message[E04]); + return; + } + /* Configure. */ + sreg.s1_3 = addr; + sreg.s2_3 = (addr + len - 1); + sreg.s0_3 |= 1; + } else { + int bp; + unsigned int *bp_d_regs = &sreg.s3_3; + + /* The watchpoint allocation scheme is the simplest possible. + For example, if a region is watched for read and + a write watch is requested, a new watchpoint will + be used. Also, if a watch for a region that is already + covered by one or more existing watchpoints, a new + watchpoint will be used. */ + + /* First, find a free data watchpoint. */ + for (bp = 0; bp < 6; bp++) { + /* Each data watchpoint's control registers occupy 2 bits + (hence the 3), starting at bit 2 for D0 (hence the 2) + with 4 bits between for each watchpoint (yes, the 4). */ + if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) { + break; + } + } + + if (bp > 5) { + /* We're out of watchpoints. */ + gdb_cris_strcpy(output_buffer, error_message[E04]); + return; + } + + /* Configure the control register first. */ + if (type == '3' || type == '4') { + /* Trigger on read. */ + sreg.s0_3 |= (1 << (2 + bp * 4)); + } + if (type == '2' || type == '4') { + /* Trigger on write. */ + sreg.s0_3 |= (2 << (2 + bp * 4)); + } + + /* Ugly pointer arithmetics to configure the watched range. */ + bp_d_regs[bp * 2] = addr; + bp_d_regs[bp * 2 + 1] = (addr + len - 1); + } + + /* Set the S1 flag to enable watchpoints. */ + reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); + gdb_cris_strcpy(output_buffer, "OK"); +} + +static void remove_watchpoint(char type, int addr, int len) +{ + /* Breakpoint/watchpoint types: + 0 = memory breakpoint for instructions + (not supported; done via memory write instead) + 1 = hardware breakpoint for instructions (supported) + 2 = write watchpoint (supported) + 3 = read watchpoint (supported) + 4 = access watchpoint (supported) */ + if (type < '1' || type > '4') { + output_buffer[0] = 0; + return; + } + + /* Read watchpoints are set as access watchpoints, because of GDB's + inability to deal with pure read watchpoints. */ + if (type == '3') + type = '4'; + + if (type == '1') { + /* Hardware breakpoint. */ + /* Bit 0 in BP_CTRL holds the configuration for I0. */ + if (!(sreg.s0_3 & 0x1)) { + /* Not in use. */ + gdb_cris_strcpy(output_buffer, error_message[E04]); + return; + } + /* Deconfigure. */ + sreg.s1_3 = 0; + sreg.s2_3 = 0; + sreg.s0_3 &= ~1; + } else { + int bp; + unsigned int *bp_d_regs = &sreg.s3_3; + /* Try to find a watchpoint that is configured for the + specified range, then check that read/write also matches. */ + + /* Ugly pointer arithmetic, since I cannot rely on a + single switch (addr) as there may be several watchpoints with + the same start address for example. */ + + for (bp = 0; bp < 6; bp++) { + if (bp_d_regs[bp * 2] == addr && + bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { + /* Matching range. */ + int bitpos = 2 + bp * 4; + int rw_bits; + + /* Read/write bits for this BP. */ + rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos; + + if ((type == '3' && rw_bits == 0x1) || + (type == '2' && rw_bits == 0x2) || + (type == '4' && rw_bits == 0x3)) { + /* Read/write matched. */ + break; + } + } + } + + if (bp > 5) { + /* No watchpoint matched. */ + gdb_cris_strcpy(output_buffer, error_message[E04]); + return; + } + + /* Found a matching watchpoint. Now, deconfigure it by + both disabling read/write in bp_ctrl and zeroing its + start/end addresses. */ + sreg.s0_3 &= ~(3 << (2 + (bp * 4))); + bp_d_regs[bp * 2] = 0; + bp_d_regs[bp * 2 + 1] = 0; + } + + /* Note that we don't clear the S1 flag here. It's done when continuing. */ + gdb_cris_strcpy(output_buffer, "OK"); +} + + + +/* All expected commands are sent from remote.c. Send a response according + to the description in remote.c. */ +void +handle_exception(int sigval) +{ + /* Avoid warning of not used. */ + + USEDFUN(handle_exception); + USEDVAR(internal_stack[0]); + + register_fixup(sigval); + + /* Send response. */ + stub_is_stopped(sigval); + + for (;;) { + output_buffer[0] = '\0'; + getpacket(input_buffer); + switch (input_buffer[0]) { + case 'g': + /* Read registers: g + Success: Each byte of register data is described by two hex digits. + Registers are in the internal order for GDB, and the bytes + in a register are in the same order the machine uses. + Failure: void. */ + { + char *buf; + /* General and special registers. */ + buf = mem2hex(output_buffer, (char *)®, sizeof(registers)); + /* Support registers. */ + /* -1 because of the null termination that mem2hex adds. */ + mem2hex(buf, + (char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)), + 16 * sizeof(unsigned int)); + break; + } + case 'G': + /* Write registers. GXX..XX + Each byte of register data is described by two hex digits. + Success: OK + Failure: void. */ + /* General and special registers. */ + hex2mem((char *)®, &input_buffer[1], sizeof(registers)); + /* Support registers. */ + hex2mem((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)), + &input_buffer[1] + sizeof(registers), + 16 * sizeof(unsigned int)); + gdb_cris_strcpy(output_buffer, "OK"); + break; + + case 'P': + /* Write register. Pn...=r... + Write register n..., hex value without 0x, with value r..., + which contains a hex value without 0x and two hex digits + for each byte in the register (target byte order). P1f=11223344 means + set register 31 to 44332211. + Success: OK + Failure: E02, E05 */ + { + char *suffix; + int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16); + int status; + + status = write_register(regno, suffix+1); + + switch (status) { + case E02: + /* Do not support read-only registers. */ + gdb_cris_strcpy(output_buffer, error_message[E02]); + break; + case E05: + /* Do not support non-existing registers. */ + gdb_cris_strcpy(output_buffer, error_message[E05]); + break; + default: + /* Valid register number. */ + gdb_cris_strcpy(output_buffer, "OK"); + break; + } + } + break; + + case 'm': + /* Read from memory. mAA..AA,LLLL + AA..AA is the address and LLLL is the length. + Success: XX..XX is the memory content. Can be fewer bytes than + requested if only part of the data may be read. m6000120a,6c means + retrieve 108 byte from base address 6000120a. + Failure: void. */ + { + char *suffix; + unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1], + &suffix, 16); + int len = gdb_cris_strtol(suffix+1, 0, 16); + + /* Bogus read (i.e. outside the kernel's + segment)? . */ + if (!((unsigned int)addr >= 0xc0000000 && + (unsigned int)addr < 0xd0000000)) + addr = NULL; + + mem2hex(output_buffer, addr, len); + } + break; + + case 'X': + /* Write to memory. XAA..AA,LLLL:XX..XX + AA..AA is the start address, LLLL is the number of bytes, and + XX..XX is the binary data. + Success: OK + Failure: void. */ + case 'M': + /* Write to memory. MAA..AA,LLLL:XX..XX + AA..AA is the start address, LLLL is the number of bytes, and + XX..XX is the hexadecimal data. + Success: OK + Failure: void. */ + { + char *lenptr; + char *dataptr; + unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1], + &lenptr, 16); + int len = gdb_cris_strtol(lenptr+1, &dataptr, 16); + if (*lenptr == ',' && *dataptr == ':') { + if (input_buffer[0] == 'M') { + hex2mem(addr, dataptr + 1, len); + } else /* X */ { + bin2mem(addr, dataptr + 1, len); + } + gdb_cris_strcpy(output_buffer, "OK"); + } + else { + gdb_cris_strcpy(output_buffer, error_message[E06]); + } + } + break; + + case 'c': + /* Continue execution. cAA..AA + AA..AA is the address where execution is resumed. If AA..AA is + omitted, resume at the present address. + Success: return to the executing thread. + Failure: will never know. */ + + if (input_buffer[1] != '\0') { + /* FIXME: Doesn't handle address argument. */ + gdb_cris_strcpy(output_buffer, error_message[E04]); + break; + } + + /* Before continuing, make sure everything is set up correctly. */ + + /* Set the SPC to some unlikely value. */ + reg.spc = 0; + /* Set the S1 flag to 0 unless some watchpoint is enabled (since setting + S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL + are reserved, so don't check against those). */ + if ((sreg.s0_3 & 0x3fff) == 0) { + reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT)); + } + + return; + + case 's': + /* Step. sAA..AA + AA..AA is the address where execution is resumed. If AA..AA is + omitted, resume at the present address. Success: return to the + executing thread. Failure: will never know. */ + + if (input_buffer[1] != '\0') { + /* FIXME: Doesn't handle address argument. */ + gdb_cris_strcpy(output_buffer, error_message[E04]); + break; + } + + /* Set the SPC to PC, which is where we'll return + (deduced previously). */ + reg.spc = reg.pc; + + /* Set the S1 (first stacked, not current) flag, which will + kick into action when we rfe. */ + reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); + return; + + case 'Z': + + /* Insert breakpoint or watchpoint, Ztype,addr,length. + Remote protocol says: A remote target shall return an empty string + for an unrecognized breakpoint or watchpoint packet type. */ + { + char *lenptr; + char *dataptr; + int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16); + int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16); + char type = input_buffer[1]; + + insert_watchpoint(type, addr, len); + break; + } + + case 'z': + /* Remove breakpoint or watchpoint, Ztype,addr,length. + Remote protocol says: A remote target shall return an empty string + for an unrecognized breakpoint or watchpoint packet type. */ + { + char *lenptr; + char *dataptr; + int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16); + int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16); + char type = input_buffer[1]; + + remove_watchpoint(type, addr, len); + break; + } + + + case '?': + /* The last signal which caused a stop. ? + Success: SAA, where AA is the signal number. + Failure: void. */ + output_buffer[0] = 'S'; + output_buffer[1] = hex_asc_hi(sigval); + output_buffer[2] = hex_asc_lo(sigval); + output_buffer[3] = 0; + break; + + case 'D': + /* Detach from host. D + Success: OK, and return to the executing thread. + Failure: will never know */ + putpacket("OK"); + return; + + case 'k': + case 'r': + /* kill request or reset request. + Success: restart of target. + Failure: will never know. */ + kill_restart(); + break; + + case 'C': + case 'S': + case '!': + case 'R': + case 'd': + /* Continue with signal sig. Csig;AA..AA + Step with signal sig. Ssig;AA..AA + Use the extended remote protocol. ! + Restart the target system. R0 + Toggle debug flag. d + Search backwards. tAA:PP,MM + Not supported: E04 */ + + /* FIXME: What's the difference between not supported + and ignored (below)? */ + gdb_cris_strcpy(output_buffer, error_message[E04]); + break; + + default: + /* The stub should ignore other request and send an empty + response ($#). This way we can extend the protocol and GDB + can tell whether the stub it is talking to uses the old or the new. */ + output_buffer[0] = 0; + break; + } + putpacket(output_buffer); + } +} + +void +kgdb_init(void) +{ + reg_intr_vect_rw_mask intr_mask; + reg_ser_rw_intr_mask ser_intr_mask; + + /* Configure the kgdb serial port. */ +#if defined(CONFIG_ETRAX_KGDB_PORT0) + /* Note: no shortcut registered (not handled by multiple_interrupt). + See entry.S. */ + set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception); + /* Enable the ser irq in the global config. */ + intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); + intr_mask.ser0 = 1; + REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); + + ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask); + ser_intr_mask.dav = regk_ser_yes; + REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask); +#elif defined(CONFIG_ETRAX_KGDB_PORT1) + /* Note: no shortcut registered (not handled by multiple_interrupt). + See entry.S. */ + set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception); + /* Enable the ser irq in the global config. */ + intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); + intr_mask.ser1 = 1; + REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); + + ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask); + ser_intr_mask.dav = regk_ser_yes; + REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask); +#elif defined(CONFIG_ETRAX_KGDB_PORT2) + /* Note: no shortcut registered (not handled by multiple_interrupt). + See entry.S. */ + set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception); + /* Enable the ser irq in the global config. */ + intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); + intr_mask.ser2 = 1; + REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); + + ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask); + ser_intr_mask.dav = regk_ser_yes; + REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask); +#elif defined(CONFIG_ETRAX_KGDB_PORT3) + /* Note: no shortcut registered (not handled by multiple_interrupt). + See entry.S. */ + set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception); + /* Enable the ser irq in the global config. */ + intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); + intr_mask.ser3 = 1; + REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); + + ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask); + ser_intr_mask.dav = regk_ser_yes; + REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask); +#endif + +} +/* Performs a complete re-start from scratch. */ +static void +kill_restart(void) +{ + machine_restart(""); +} + +/* Use this static breakpoint in the start-up only. */ + +void +breakpoint(void) +{ + kgdb_started = 1; + dynamic_bp = 0; /* This is a static, not a dynamic breakpoint. */ + __asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */ +} + +/****************************** End of file **********************************/ diff --git a/kernel/arch/cris/arch-v32/kernel/kgdb_asm.S b/kernel/arch/cris/arch-v32/kernel/kgdb_asm.S new file mode 100644 index 000000000..f3a476059 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/kgdb_asm.S @@ -0,0 +1,551 @@ +/* + * Copyright (C) 2004 Axis Communications AB + * + * Code for handling break 8, hardware breakpoint, single step, and serial + * port exceptions for kernel debugging purposes. + */ + +#include + + ;; Exported functions. + .globl kgdb_handle_exception + +kgdb_handle_exception: + +;; Create a register image of the caller. +;; +;; First of all, save the ACR on the stack since we need it for address calculations. +;; We put it into the register struct later. + + subq 4, $sp + move.d $acr, [$sp] + +;; Now we are free to use ACR all we want. +;; If we were running this handler with interrupts on, we would have to be careful +;; to save and restore CCS manually, but since we aren't we treat it like every other +;; register. + + move.d reg, $acr + move.d $r0, [$acr] ; Save R0 (start of register struct) + addq 4, $acr + move.d $r1, [$acr] ; Save R1 + addq 4, $acr + move.d $r2, [$acr] ; Save R2 + addq 4, $acr + move.d $r3, [$acr] ; Save R3 + addq 4, $acr + move.d $r4, [$acr] ; Save R4 + addq 4, $acr + move.d $r5, [$acr] ; Save R5 + addq 4, $acr + move.d $r6, [$acr] ; Save R6 + addq 4, $acr + move.d $r7, [$acr] ; Save R7 + addq 4, $acr + move.d $r8, [$acr] ; Save R8 + addq 4, $acr + move.d $r9, [$acr] ; Save R9 + addq 4, $acr + move.d $r10, [$acr] ; Save R10 + addq 4, $acr + move.d $r11, [$acr] ; Save R11 + addq 4, $acr + move.d $r12, [$acr] ; Save R12 + addq 4, $acr + move.d $r13, [$acr] ; Save R13 + addq 4, $acr + move.d $sp, [$acr] ; Save SP (R14) + addq 4, $acr + + ;; The ACR register is already saved on the stack, so pop it from there. + move.d [$sp],$r0 + move.d $r0, [$acr] + addq 4, $acr + + move $bz, [$acr] + addq 1, $acr + move $vr, [$acr] + addq 1, $acr + move $pid, [$acr] + addq 4, $acr + move $srs, [$acr] + addq 1, $acr + move $wz, [$acr] + addq 2, $acr + move $exs, [$acr] + addq 4, $acr + move $eda, [$acr] + addq 4, $acr + move $mof, [$acr] + addq 4, $acr + move $dz, [$acr] + addq 4, $acr + move $ebp, [$acr] + addq 4, $acr + move $erp, [$acr] + addq 4, $acr + move $srp, [$acr] + addq 4, $acr + move $nrp, [$acr] + addq 4, $acr + move $ccs, [$acr] + addq 4, $acr + move $usp, [$acr] + addq 4, $acr + move $spc, [$acr] + addq 4, $acr + +;; Skip the pseudo-PC. + addq 4, $acr + +;; Save the support registers in bank 0 - 3. + clear.d $r1 ; Bank counter + move.d sreg, $acr + +;; Bank 0 + move $r1, $srs + nop + nop + nop + move $s0, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s1, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s2, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s3, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s4, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s5, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s6, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s7, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s8, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s9, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s10, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s11, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s12, $r0 + move.d $r0, [$acr] + addq 4, $acr + + ;; Nothing in S13 - S15, bank 0 + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + +;; Bank 1 and bank 2 have the same layout, hence the loop. + addq 1, $r1 +1: + move $r1, $srs + nop + nop + nop + move $s0, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s1, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s2, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s3, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s4, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s5, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s6, $r0 + move.d $r0, [$acr] + addq 4, $acr + + ;; Nothing in S7 - S15, bank 1 and 2 + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + clear.d [$acr] + addq 4, $acr + + addq 1, $r1 + cmpq 3, $r1 + bne 1b + nop + +;; Bank 3 + move $r1, $srs + nop + nop + nop + move $s0, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s1, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s2, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s3, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s4, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s5, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s6, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s7, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s8, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s9, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s10, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s11, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s12, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s13, $r0 + move.d $r0, [$acr] + addq 4, $acr + move $s14, $r0 + move.d $r0, [$acr] + addq 4, $acr +;; Nothing in S15, bank 3 + clear.d [$acr] + addq 4, $acr + +;; Check what got us here: get IDX field of EXS. + move $exs, $r10 + and.d 0xff00, $r10 + lsrq 8, $r10 +#if defined(CONFIG_ETRAX_KGDB_PORT0) + cmp.d SER0_INTR_VECT, $r10 ; IRQ for serial port 0 + beq sigint + nop +#elif defined(CONFIG_ETRAX_KGDB_PORT1) + cmp.d SER1_INTR_VECT, $r10 ; IRQ for serial port 1 + beq sigint + nop +#elif defined(CONFIG_ETRAX_KGDB_PORT2) + cmp.d SER2_INTR_VECT, $r10 ; IRQ for serial port 2 + beq sigint + nop +#elif defined(CONFIG_ETRAX_KGDB_PORT3) + cmp.d SER3_INTR_VECT, $r10 ; IRQ for serial port 3 + beq sigint + nop +#endif +;; Multiple interrupt must be due to serial break. + cmp.d 0x30, $r10 ; Multiple interrupt + beq sigint + nop +;; Neither of those? Then it's a sigtrap. + ba handle_comm + moveq 5, $r10 ; Set SIGTRAP (delay slot) + +sigint: + ;; Serial interrupt; get character + jsr getDebugChar + nop ; Delay slot + cmp.b 3, $r10 ; \003 (Ctrl-C)? + bne return ; No, get out of here + nop + moveq 2, $r10 ; Set SIGINT + +;; +;; Handle the communication +;; +handle_comm: + move.d internal_stack+1020, $sp ; Use the internal stack which grows upwards + jsr handle_exception ; Interactive routine + nop + +;; +;; Return to the caller +;; +return: + +;; First of all, write the support registers. + clear.d $r1 ; Bank counter + move.d sreg, $acr + +;; Bank 0 + move $r1, $srs + nop + nop + nop + move.d [$acr], $r0 + move $r0, $s0 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s1 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s2 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s3 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s4 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s5 + addq 4, $acr + +;; Nothing in S6 - S7, bank 0. + addq 4, $acr + addq 4, $acr + + move.d [$acr], $r0 + move $r0, $s8 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s9 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s10 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s11 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s12 + addq 4, $acr + +;; Nothing in S13 - S15, bank 0 + addq 4, $acr + addq 4, $acr + addq 4, $acr + +;; Bank 1 and bank 2 have the same layout, hence the loop. + addq 1, $r1 +2: + move $r1, $srs + nop + nop + nop + move.d [$acr], $r0 + move $r0, $s0 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s1 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s2 + addq 4, $acr + +;; S3 (MM_CAUSE) is read-only. + addq 4, $acr + + move.d [$acr], $r0 + move $r0, $s4 + addq 4, $acr + +;; FIXME: Actually write S5/S6? (Affects MM_CAUSE.) + addq 4, $acr + addq 4, $acr + +;; Nothing in S7 - S15, bank 1 and 2 + addq 4, $acr + addq 4, $acr + addq 4, $acr + addq 4, $acr + addq 4, $acr + addq 4, $acr + addq 4, $acr + addq 4, $acr + addq 4, $acr + + addq 1, $r1 + cmpq 3, $r1 + bne 2b + nop + +;; Bank 3 + move $r1, $srs + nop + nop + nop + move.d [$acr], $r0 + move $r0, $s0 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s1 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s2 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s3 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s4 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s5 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s6 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s7 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s8 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s9 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s10 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s11 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s12 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s13 + addq 4, $acr + move.d [$acr], $r0 + move $r0, $s14 + addq 4, $acr + +;; Nothing in S15, bank 3 + addq 4, $acr + +;; Now, move on to the regular register restoration process. + + move.d reg, $acr ; Reset ACR to point at the beginning of the register image + move.d [$acr], $r0 ; Restore R0 + addq 4, $acr + move.d [$acr], $r1 ; Restore R1 + addq 4, $acr + move.d [$acr], $r2 ; Restore R2 + addq 4, $acr + move.d [$acr], $r3 ; Restore R3 + addq 4, $acr + move.d [$acr], $r4 ; Restore R4 + addq 4, $acr + move.d [$acr], $r5 ; Restore R5 + addq 4, $acr + move.d [$acr], $r6 ; Restore R6 + addq 4, $acr + move.d [$acr], $r7 ; Restore R7 + addq 4, $acr + move.d [$acr], $r8 ; Restore R8 + addq 4, $acr + move.d [$acr], $r9 ; Restore R9 + addq 4, $acr + move.d [$acr], $r10 ; Restore R10 + addq 4, $acr + move.d [$acr], $r11 ; Restore R11 + addq 4, $acr + move.d [$acr], $r12 ; Restore R12 + addq 4, $acr + move.d [$acr], $r13 ; Restore R13 + +;; +;; We restore all registers, even though some of them probably haven't changed. +;; + + addq 4, $acr + move.d [$acr], $sp ; Restore SP (R14) + + ;; ACR cannot be restored just yet. + addq 8, $acr + + ;; Skip BZ, VR. + addq 2, $acr + + move [$acr], $pid ; Restore PID + addq 4, $acr + move [$acr], $srs ; Restore SRS + nop + nop + nop + addq 1, $acr + + ;; Skip WZ. + addq 2, $acr + + move [$acr], $exs ; Restore EXS. + addq 4, $acr + move [$acr], $eda ; Restore EDA. + addq 4, $acr + move [$acr], $mof ; Restore MOF. + + ;; Skip DZ. + addq 8, $acr + + move [$acr], $ebp ; Restore EBP. + addq 4, $acr + move [$acr], $erp ; Restore ERP. + addq 4, $acr + move [$acr], $srp ; Restore SRP. + addq 4, $acr + move [$acr], $nrp ; Restore NRP. + addq 4, $acr + move [$acr], $ccs ; Restore CCS like an ordinary register. + addq 4, $acr + move [$acr], $usp ; Restore USP + addq 4, $acr + move [$acr], $spc ; Restore SPC + ; No restoration of pseudo-PC of course. + + move.d reg, $acr ; Reset ACR to point at the beginning of the register image + add.d 15*4, $acr + move.d [$acr], $acr ; Finally, restore ACR. + rete ; Same as jump ERP + rfe ; Shifts CCS diff --git a/kernel/arch/cris/arch-v32/kernel/process.c b/kernel/arch/cris/arch-v32/kernel/process.c new file mode 100644 index 000000000..cebd32e2a --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/process.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2000-2003 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * Mikael Starvik (starvik@axis.com) + * Tobias Anderberg (tobiasa@axis.com), CRISv32 port. + * + * This file handles the architecture-dependent parts of process handling.. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void stop_watchdog(void); + +/* We use this if we don't have any better idle routine. */ +void default_idle(void) +{ + /* Halt until exception. */ + __asm__ volatile("ei \n\t" + "halt "); +} + +/* + * Free current thread data structures etc.. + */ + +extern void deconfigure_bp(long pid); +void exit_thread(void) +{ + deconfigure_bp(current->pid); +} + +/* + * If the watchdog is enabled, disable interrupts and enter an infinite loop. + * The watchdog will reset the CPU after 0.1s. If the watchdog isn't enabled + * then enable it and wait. + */ +extern void arch_enable_nmi(void); + +void +hard_reset_now(void) +{ + /* + * Don't declare this variable elsewhere. We don't want any other + * code to know about it than the watchdog handler in entry.S and + * this code, implementing hard reset through the watchdog. + */ +#if defined(CONFIG_ETRAX_WATCHDOG) + extern int cause_of_death; +#endif + + printk("*** HARD RESET ***\n"); + local_irq_disable(); + +#if defined(CONFIG_ETRAX_WATCHDOG) + cause_of_death = 0xbedead; +#else +{ + reg_timer_rw_wd_ctrl wd_ctrl = {0}; + + stop_watchdog(); + + wd_ctrl.key = 16; /* Arbitrary key. */ + wd_ctrl.cnt = 1; /* Minimum time. */ + wd_ctrl.cmd = regk_timer_start; + + arch_enable_nmi(); + REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); +} +#endif + + while (1) + ; /* Wait for reset. */ +} + +/* + * Return saved PC of a blocked thread. + */ +unsigned long thread_saved_pc(struct task_struct *t) +{ + return task_pt_regs(t)->erp; +} + +/* + * Setup the child's kernel stack with a pt_regs and call switch_stack() on it. + * It will be unnested during _resume and _ret_from_sys_call when the new thread + * is scheduled. + * + * Also setup the thread switching structure which is used to keep + * thread-specific data during _resumes. + */ + +extern asmlinkage void ret_from_fork(void); +extern asmlinkage void ret_from_kernel_thread(void); + +int +copy_thread(unsigned long clone_flags, unsigned long usp, + unsigned long arg, struct task_struct *p) +{ + struct pt_regs *childregs = task_pt_regs(p); + struct switch_stack *swstack = ((struct switch_stack *) childregs) - 1; + + /* + * Put the pt_regs structure at the end of the new kernel stack page and + * fix it up. Note: the task_struct doubles as the kernel stack for the + * task. + */ + if (unlikely(p->flags & PF_KTHREAD)) { + memset(swstack, 0, + sizeof(struct switch_stack) + sizeof(struct pt_regs)); + swstack->r1 = usp; + swstack->r2 = arg; + childregs->ccs = 1 << (I_CCS_BITNR + CCS_SHIFT); + swstack->return_ip = (unsigned long) ret_from_kernel_thread; + p->thread.ksp = (unsigned long) swstack; + p->thread.usp = 0; + return 0; + } + *childregs = *current_pt_regs(); /* Struct copy of pt_regs. */ + childregs->r10 = 0; /* Child returns 0 after a fork/clone. */ + + /* Set a new TLS ? + * The TLS is in $mof because it is the 5th argument to sys_clone. + */ + if (p->mm && (clone_flags & CLONE_SETTLS)) { + task_thread_info(p)->tls = childregs->mof; + } + + /* Put the switch stack right below the pt_regs. */ + + /* Parameter to ret_from_sys_call. 0 is don't restart the syscall. */ + swstack->r9 = 0; + + /* + * We want to return into ret_from_sys_call after the _resume. + * ret_from_fork will call ret_from_sys_call. + */ + swstack->return_ip = (unsigned long) ret_from_fork; + + /* Fix the user-mode and kernel-mode stackpointer. */ + p->thread.usp = usp ?: rdusp(); + p->thread.ksp = (unsigned long) swstack; + + return 0; +} + +unsigned long +get_wchan(struct task_struct *p) +{ + /* TODO */ + return 0; +} +#undef last_sched +#undef first_sched + +void show_regs(struct pt_regs * regs) +{ + unsigned long usp = rdusp(); + + show_regs_print_info(KERN_DEFAULT); + + printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n", + regs->erp, regs->srp, regs->ccs, usp, regs->mof); + + printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", + regs->r0, regs->r1, regs->r2, regs->r3); + + printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", + regs->r4, regs->r5, regs->r6, regs->r7); + + printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", + regs->r8, regs->r9, regs->r10, regs->r11); + + printk("r12: %08lx r13: %08lx oR10: %08lx\n", + regs->r12, regs->r13, regs->orig_r10); +} diff --git a/kernel/arch/cris/arch-v32/kernel/ptrace.c b/kernel/arch/cris/arch-v32/kernel/ptrace.c new file mode 100644 index 000000000..f085229cf --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/ptrace.c @@ -0,0 +1,490 @@ +/* + * Copyright (C) 2000-2007, Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* + * Determines which bits in CCS the user has access to. + * 1 = access, 0 = no access. + */ +#define CCS_MASK 0x00087c00 /* SXNZVC */ + +#define SBIT_USER (1 << (S_CCS_BITNR + CCS_SHIFT)) + +static int put_debugreg(long pid, unsigned int regno, long data); +static long get_debugreg(long pid, unsigned int regno); +static unsigned long get_pseudo_pc(struct task_struct *child); +void deconfigure_bp(long pid); + +extern unsigned long cris_signal_return_page; + +/* + * Get contents of register REGNO in task TASK. + */ +long get_reg(struct task_struct *task, unsigned int regno) +{ + /* USP is a special case, it's not in the pt_regs struct but + * in the tasks thread struct + */ + unsigned long ret; + + if (regno <= PT_EDA) + ret = ((unsigned long *)task_pt_regs(task))[regno]; + else if (regno == PT_USP) + ret = task->thread.usp; + else if (regno == PT_PPC) + ret = get_pseudo_pc(task); + else if (regno <= PT_MAX) + ret = get_debugreg(task->pid, regno); + else + ret = 0; + + return ret; +} + +/* + * Write contents of register REGNO in task TASK. + */ +int put_reg(struct task_struct *task, unsigned int regno, unsigned long data) +{ + if (regno <= PT_EDA) + ((unsigned long *)task_pt_regs(task))[regno] = data; + else if (regno == PT_USP) + task->thread.usp = data; + else if (regno == PT_PPC) { + /* Write pseudo-PC to ERP only if changed. */ + if (data != get_pseudo_pc(task)) + task_pt_regs(task)->erp = data; + } else if (regno <= PT_MAX) + return put_debugreg(task->pid, regno, data); + else + return -1; + return 0; +} + +void user_enable_single_step(struct task_struct *child) +{ + unsigned long tmp; + + /* + * Set up SPC if not set already (in which case we have no other + * choice but to trust it). + */ + if (!get_reg(child, PT_SPC)) { + /* In case we're stopped in a delay slot. */ + tmp = get_reg(child, PT_ERP) & ~1; + put_reg(child, PT_SPC, tmp); + } + tmp = get_reg(child, PT_CCS) | SBIT_USER; + put_reg(child, PT_CCS, tmp); +} + +void user_disable_single_step(struct task_struct *child) +{ + put_reg(child, PT_SPC, 0); + + if (!get_debugreg(child->pid, PT_BP_CTRL)) { + unsigned long tmp; + /* If no h/w bp configured, disable S bit. */ + tmp = get_reg(child, PT_CCS) & ~SBIT_USER; + put_reg(child, PT_CCS, tmp); + } +} + +/* + * Called by kernel/ptrace.c when detaching. + * + * Make sure the single step bit is not set. + */ +void +ptrace_disable(struct task_struct *child) +{ + /* Deconfigure SPC and S-bit. */ + user_disable_single_step(child); + put_reg(child, PT_SPC, 0); + + /* Deconfigure any watchpoints associated with the child. */ + deconfigure_bp(child->pid); +} + + +long arch_ptrace(struct task_struct *child, long request, + unsigned long addr, unsigned long data) +{ + int ret; + unsigned int regno = addr >> 2; + unsigned long __user *datap = (unsigned long __user *)data; + + switch (request) { + /* Read word at location address. */ + case PTRACE_PEEKTEXT: + case PTRACE_PEEKDATA: { + unsigned long tmp; + int copied; + + ret = -EIO; + + /* The signal trampoline page is outside the normal user-addressable + * space but still accessible. This is hack to make it possible to + * access the signal handler code in GDB. + */ + if ((addr & PAGE_MASK) == cris_signal_return_page) { + /* The trampoline page is globally mapped, no page table to traverse.*/ + tmp = *(unsigned long*)addr; + } else { + copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); + + if (copied != sizeof(tmp)) + break; + } + + ret = put_user(tmp,datap); + break; + } + + /* Read the word at location address in the USER area. */ + case PTRACE_PEEKUSR: { + unsigned long tmp; + + ret = -EIO; + if ((addr & 3) || regno > PT_MAX) + break; + + tmp = get_reg(child, regno); + ret = put_user(tmp, datap); + break; + } + + /* Write the word at location address. */ + case PTRACE_POKETEXT: + case PTRACE_POKEDATA: + ret = generic_ptrace_pokedata(child, addr, data); + break; + + /* Write the word at location address in the USER area. */ + case PTRACE_POKEUSR: + ret = -EIO; + if ((addr & 3) || regno > PT_MAX) + break; + + if (regno == PT_CCS) { + /* don't allow the tracing process to change stuff like + * interrupt enable, kernel/user bit, dma enables etc. + */ + data &= CCS_MASK; + data |= get_reg(child, PT_CCS) & ~CCS_MASK; + } + if (put_reg(child, regno, data)) + break; + ret = 0; + break; + + /* Get all GP registers from the child. */ + case PTRACE_GETREGS: { + int i; + unsigned long tmp; + + for (i = 0; i <= PT_MAX; i++) { + tmp = get_reg(child, i); + + if (put_user(tmp, datap)) { + ret = -EFAULT; + goto out_tsk; + } + + datap++; + } + + ret = 0; + break; + } + + /* Set all GP registers in the child. */ + case PTRACE_SETREGS: { + int i; + unsigned long tmp; + + for (i = 0; i <= PT_MAX; i++) { + if (get_user(tmp, datap)) { + ret = -EFAULT; + goto out_tsk; + } + + if (i == PT_CCS) { + tmp &= CCS_MASK; + tmp |= get_reg(child, PT_CCS) & ~CCS_MASK; + } + + put_reg(child, i, tmp); + datap++; + } + + ret = 0; + break; + } + + default: + ret = ptrace_request(child, request, addr, data); + break; + } + +out_tsk: + return ret; +} + +void do_syscall_trace(void) +{ + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + return; + + if (!(current->ptrace & PT_PTRACED)) + return; + + /* the 0x80 provides a way for the tracing parent to distinguish + between a syscall stop and SIGTRAP delivery */ + ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) + ? 0x80 : 0)); + + /* + * This isn't the same as continuing with a signal, but it will do for + * normal use. + */ + if (current->exit_code) { + send_sig(current->exit_code, current, 1); + current->exit_code = 0; + } +} + +/* Returns the size of an instruction that has a delay slot. */ + +static int insn_size(struct task_struct *child, unsigned long pc) +{ + unsigned long opcode; + int copied; + int opsize = 0; + + /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */ + copied = access_process_vm(child, pc, &opcode, sizeof(opcode), 0); + if (copied != sizeof(opcode)) + return 0; + + switch ((opcode & 0x0f00) >> 8) { + case 0x0: + case 0x9: + case 0xb: + opsize = 2; + break; + case 0xe: + case 0xf: + opsize = 6; + break; + case 0xd: + /* Could be 4 or 6; check more bits. */ + if ((opcode & 0xff) == 0xff) + opsize = 4; + else + opsize = 6; + break; + default: + panic("ERROR: Couldn't find size of opcode 0x%lx at 0x%lx\n", + opcode, pc); + } + + return opsize; +} + +static unsigned long get_pseudo_pc(struct task_struct *child) +{ + /* Default value for PC is ERP. */ + unsigned long pc = get_reg(child, PT_ERP); + + if (pc & 0x1) { + unsigned long spc = get_reg(child, PT_SPC); + /* Delay slot bit set. Report as stopped on proper + instruction. */ + if (spc) { + /* Rely on SPC if set. FIXME: We might want to check + that EXS indicates we stopped due to a single-step + exception. */ + pc = spc; + } else { + /* Calculate the PC from the size of the instruction + that the delay slot we're in belongs to. */ + pc += insn_size(child, pc & ~1) - 1; + } + } + return pc; +} + +static long bp_owner = 0; + +/* Reachable from exit_thread in signal.c, so not static. */ +void deconfigure_bp(long pid) +{ + int bp; + + /* Only deconfigure if the pid is the owner. */ + if (bp_owner != pid) + return; + + for (bp = 0; bp < 6; bp++) { + unsigned long tmp; + /* Deconfigure start and end address (also gets rid of ownership). */ + put_debugreg(pid, PT_BP + 3 + (bp * 2), 0); + put_debugreg(pid, PT_BP + 4 + (bp * 2), 0); + + /* Deconfigure relevant bits in control register. */ + tmp = get_debugreg(pid, PT_BP_CTRL) & ~(3 << (2 + (bp * 4))); + put_debugreg(pid, PT_BP_CTRL, tmp); + } + /* No owner now. */ + bp_owner = 0; +} + +static int put_debugreg(long pid, unsigned int regno, long data) +{ + int ret = 0; + register int old_srs; + +#ifdef CONFIG_ETRAX_KGDB + /* Ignore write, but pretend it was ok if value is 0 + (we don't want POKEUSR/SETREGS failing unnessecarily). */ + return (data == 0) ? ret : -1; +#endif + + /* Simple owner management. */ + if (!bp_owner) + bp_owner = pid; + else if (bp_owner != pid) { + /* Ignore write, but pretend it was ok if value is 0 + (we don't want POKEUSR/SETREGS failing unnessecarily). */ + return (data == 0) ? ret : -1; + } + + /* Remember old SRS. */ + SPEC_REG_RD(SPEC_REG_SRS, old_srs); + /* Switch to BP bank. */ + SUPP_BANK_SEL(BANK_BP); + + switch (regno - PT_BP) { + case 0: + SUPP_REG_WR(0, data); break; + case 1: + case 2: + if (data) + ret = -1; + break; + case 3: + SUPP_REG_WR(3, data); break; + case 4: + SUPP_REG_WR(4, data); break; + case 5: + SUPP_REG_WR(5, data); break; + case 6: + SUPP_REG_WR(6, data); break; + case 7: + SUPP_REG_WR(7, data); break; + case 8: + SUPP_REG_WR(8, data); break; + case 9: + SUPP_REG_WR(9, data); break; + case 10: + SUPP_REG_WR(10, data); break; + case 11: + SUPP_REG_WR(11, data); break; + case 12: + SUPP_REG_WR(12, data); break; + case 13: + SUPP_REG_WR(13, data); break; + case 14: + SUPP_REG_WR(14, data); break; + default: + ret = -1; + break; + } + + /* Restore SRS. */ + SPEC_REG_WR(SPEC_REG_SRS, old_srs); + /* Just for show. */ + NOP(); + NOP(); + NOP(); + + return ret; +} + +static long get_debugreg(long pid, unsigned int regno) +{ + register int old_srs; + register long data; + + if (pid != bp_owner) { + return 0; + } + + /* Remember old SRS. */ + SPEC_REG_RD(SPEC_REG_SRS, old_srs); + /* Switch to BP bank. */ + SUPP_BANK_SEL(BANK_BP); + + switch (regno - PT_BP) { + case 0: + SUPP_REG_RD(0, data); break; + case 1: + case 2: + /* error return value? */ + data = 0; + break; + case 3: + SUPP_REG_RD(3, data); break; + case 4: + SUPP_REG_RD(4, data); break; + case 5: + SUPP_REG_RD(5, data); break; + case 6: + SUPP_REG_RD(6, data); break; + case 7: + SUPP_REG_RD(7, data); break; + case 8: + SUPP_REG_RD(8, data); break; + case 9: + SUPP_REG_RD(9, data); break; + case 10: + SUPP_REG_RD(10, data); break; + case 11: + SUPP_REG_RD(11, data); break; + case 12: + SUPP_REG_RD(12, data); break; + case 13: + SUPP_REG_RD(13, data); break; + case 14: + SUPP_REG_RD(14, data); break; + default: + /* error return value? */ + data = 0; + } + + /* Restore SRS. */ + SPEC_REG_WR(SPEC_REG_SRS, old_srs); + /* Just for show. */ + NOP(); + NOP(); + NOP(); + + return data; +} diff --git a/kernel/arch/cris/arch-v32/kernel/setup.c b/kernel/arch/cris/arch-v32/kernel/setup.c new file mode 100644 index 000000000..cd1865d68 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/setup.c @@ -0,0 +1,170 @@ +/* + * Display CPU info in /proc/cpuinfo. + * + * Copyright (C) 2003, Axis Communications AB. + */ + +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_PROC_FS + +#define HAS_FPU 0x0001 +#define HAS_MMU 0x0002 +#define HAS_ETHERNET100 0x0004 +#define HAS_TOKENRING 0x0008 +#define HAS_SCSI 0x0010 +#define HAS_ATA 0x0020 +#define HAS_USB 0x0040 +#define HAS_IRQ_BUG 0x0080 +#define HAS_MMU_BUG 0x0100 + +struct cpu_info { + char *cpu_model; + unsigned short rev; + unsigned short cache_size; + unsigned short flags; +}; + +/* Some of these model are here for historical reasons only. */ +static struct cpu_info cpinfo[] = { + {"ETRAX 1", 0, 0, 0}, + {"ETRAX 2", 1, 0, 0}, + {"ETRAX 3", 2, 0, 0}, + {"ETRAX 4", 3, 0, 0}, + {"Simulator", 7, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA}, + {"ETRAX 100", 8, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG}, + {"ETRAX 100", 9, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA}, + + {"ETRAX 100LX", 10, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB + | HAS_MMU | HAS_MMU_BUG}, + + {"ETRAX 100LX v2", 11, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB + | HAS_MMU}, +#ifdef CONFIG_ETRAXFS + {"ETRAX FS", 32, 32, HAS_ETHERNET100 | HAS_ATA | HAS_MMU}, +#else + {"ARTPEC-3", 32, 32, HAS_ETHERNET100 | HAS_MMU}, +#endif + {"Unknown", 0, 0, 0} +}; + +int show_cpuinfo(struct seq_file *m, void *v) +{ + int i; + int cpu = (int)v - 1; + unsigned long revision; + struct cpu_info *info; + + info = &cpinfo[ARRAY_SIZE(cpinfo) - 1]; + + revision = rdvr(); + + for (i = 0; i < ARRAY_SIZE(cpinfo); i++) { + if (cpinfo[i].rev == revision) { + info = &cpinfo[i]; + break; + } + } + + seq_printf(m, + "processor\t: %d\n" + "cpu\t\t: CRIS\n" + "cpu revision\t: %lu\n" + "cpu model\t: %s\n" + "cache size\t: %d KB\n" + "fpu\t\t: %s\n" + "mmu\t\t: %s\n" + "mmu DMA bug\t: %s\n" + "ethernet\t: %s Mbps\n" + "token ring\t: %s\n" + "scsi\t\t: %s\n" + "ata\t\t: %s\n" + "usb\t\t: %s\n" + "bogomips\t: %lu.%02lu\n\n", + + cpu, + revision, + info->cpu_model, + info->cache_size, + info->flags & HAS_FPU ? "yes" : "no", + info->flags & HAS_MMU ? "yes" : "no", + info->flags & HAS_MMU_BUG ? "yes" : "no", + info->flags & HAS_ETHERNET100 ? "10/100" : "10", + info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no", + info->flags & HAS_SCSI ? "yes" : "no", + info->flags & HAS_ATA ? "yes" : "no", + info->flags & HAS_USB ? "yes" : "no", + (loops_per_jiffy * HZ + 500) / 500000, + ((loops_per_jiffy * HZ + 500) / 5000) % 100); + + return 0; +} + +#endif /* CONFIG_PROC_FS */ + +void show_etrax_copyright(void) +{ +#ifdef CONFIG_ETRAXFS + printk(KERN_INFO "Linux/CRISv32 port on ETRAX FS " + "(C) 2003, 2004 Axis Communications AB\n"); +#else + printk(KERN_INFO "Linux/CRISv32 port on ARTPEC-3 " + "(C) 2003-2009 Axis Communications AB\n"); +#endif +} + +static struct i2c_board_info __initdata i2c_info[] = { + {I2C_BOARD_INFO("camblock", 0x43)}, + {I2C_BOARD_INFO("tmp100", 0x48)}, + {I2C_BOARD_INFO("tmp100", 0x4A)}, + {I2C_BOARD_INFO("tmp100", 0x4C)}, + {I2C_BOARD_INFO("tmp100", 0x4D)}, + {I2C_BOARD_INFO("tmp100", 0x4E)}, +#ifdef CONFIG_RTC_DRV_PCF8563 + {I2C_BOARD_INFO("pcf8563", 0x51)}, +#endif +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + {I2C_BOARD_INFO("vgpio", 0x20)}, + {I2C_BOARD_INFO("vgpio", 0x21)}, +#endif + {I2C_BOARD_INFO("pca9536", 0x41)}, + {I2C_BOARD_INFO("fnp300", 0x40)}, + {I2C_BOARD_INFO("fnp300", 0x42)}, + {I2C_BOARD_INFO("adc101", 0x54)}, +}; + +static struct i2c_board_info __initdata i2c_info2[] = { + {I2C_BOARD_INFO("camblock", 0x43)}, + {I2C_BOARD_INFO("tmp100", 0x48)}, + {I2C_BOARD_INFO("tmp100", 0x4A)}, + {I2C_BOARD_INFO("tmp100", 0x4C)}, + {I2C_BOARD_INFO("tmp100", 0x4D)}, + {I2C_BOARD_INFO("tmp100", 0x4E)}, +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO + {I2C_BOARD_INFO("vgpio", 0x20)}, + {I2C_BOARD_INFO("vgpio", 0x21)}, +#endif + {I2C_BOARD_INFO("pca9536", 0x41)}, + {I2C_BOARD_INFO("fnp300", 0x40)}, + {I2C_BOARD_INFO("fnp300", 0x42)}, + {I2C_BOARD_INFO("adc101", 0x54)}, +}; + +static struct i2c_board_info __initdata i2c_info3[] = { + {I2C_BOARD_INFO("adc101", 0x54)}, +}; + +static int __init etrax_init(void) +{ + i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info)); + i2c_register_board_info(1, i2c_info2, ARRAY_SIZE(i2c_info2)); + i2c_register_board_info(2, i2c_info3, ARRAY_SIZE(i2c_info3)); + return 0; +} +arch_initcall(etrax_init); diff --git a/kernel/arch/cris/arch-v32/kernel/signal.c b/kernel/arch/cris/arch-v32/kernel/signal.c new file mode 100644 index 000000000..3a36ae6b7 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/signal.c @@ -0,0 +1,540 @@ +/* + * Copyright (C) 2003, Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +extern unsigned long cris_signal_return_page; + +/* + * A syscall in CRIS is really a "break 13" instruction, which is 2 + * bytes. The registers is manipulated so upon return the instruction + * will be executed again. + * + * This relies on that PC points to the instruction after the break call. + */ +#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->erp -= 2; + +/* Signal frames. */ +struct signal_frame { + struct sigcontext sc; + unsigned long extramask[_NSIG_WORDS - 1]; + unsigned char retcode[8]; /* Trampoline code. */ +}; + +struct rt_signal_frame { + struct siginfo *pinfo; + void *puc; + struct siginfo info; + struct ucontext uc; + unsigned char retcode[8]; /* Trampoline code. */ +}; + +void do_signal(int restart, struct pt_regs *regs); +void keep_debug_flags(unsigned long oldccs, unsigned long oldspc, + struct pt_regs *regs); + +static int +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) +{ + unsigned int err = 0; + unsigned long old_usp; + + /* Always make any pending restarted system calls return -EINTR */ + current->restart_block.fn = do_no_restart_syscall; + + /* + * Restore the registers from &sc->regs. sc is already checked + * for VERIFY_READ since the signal_frame was previously + * checked in sys_sigreturn(). + */ + if (__copy_from_user(regs, sc, sizeof(struct pt_regs))) + goto badframe; + + /* Make that the user-mode flag is set. */ + regs->ccs |= (1 << (U_CCS_BITNR + CCS_SHIFT)); + + /* Don't perform syscall restarting */ + regs->exs = -1; + + /* Restore the old USP. */ + err |= __get_user(old_usp, &sc->usp); + wrusp(old_usp); + + return err; + +badframe: + return 1; +} + +asmlinkage int sys_sigreturn(void) +{ + struct pt_regs *regs = current_pt_regs(); + sigset_t set; + struct signal_frame __user *frame; + unsigned long oldspc = regs->spc; + unsigned long oldccs = regs->ccs; + + frame = (struct signal_frame *) rdusp(); + + /* + * Since the signal is stacked on a dword boundary, the frame + * should be dword aligned here as well. It it's not, then the + * user is trying some funny business. + */ + if (((long)frame) & 3) + goto badframe; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + + if (__get_user(set.sig[0], &frame->sc.oldmask) || + (_NSIG_WORDS > 1 && __copy_from_user(&set.sig[1], + frame->extramask, + sizeof(frame->extramask)))) + goto badframe; + + set_current_blocked(&set); + + if (restore_sigcontext(regs, &frame->sc)) + goto badframe; + + keep_debug_flags(oldccs, oldspc, regs); + + return regs->r10; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +asmlinkage int sys_rt_sigreturn(void) +{ + struct pt_regs *regs = current_pt_regs(); + sigset_t set; + struct rt_signal_frame __user *frame; + unsigned long oldspc = regs->spc; + unsigned long oldccs = regs->ccs; + + frame = (struct rt_signal_frame *) rdusp(); + + /* + * Since the signal is stacked on a dword boundary, the frame + * should be dword aligned here as well. It it's not, then the + * user is trying some funny business. + */ + if (((long)frame) & 3) + goto badframe; + + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) + goto badframe; + + if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) + goto badframe; + + set_current_blocked(&set); + + if (restore_sigcontext(regs, &frame->uc.uc_mcontext)) + goto badframe; + + if (restore_altstack(&frame->uc.uc_stack)) + goto badframe; + + keep_debug_flags(oldccs, oldspc, regs); + + return regs->r10; + +badframe: + force_sig(SIGSEGV, current); + return 0; +} + +/* Setup a signal frame. */ +static int +setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, + unsigned long mask) +{ + int err; + unsigned long usp; + + err = 0; + usp = rdusp(); + + /* + * Copy the registers. They are located first in sc, so it's + * possible to use sc directly. + */ + err |= __copy_to_user(sc, regs, sizeof(struct pt_regs)); + + err |= __put_user(mask, &sc->oldmask); + err |= __put_user(usp, &sc->usp); + + return err; +} + +/* Figure out where to put the new signal frame - usually on the stack. */ +static inline void __user * +get_sigframe(struct ksignal *ksig, size_t frame_size) +{ + unsigned long sp = sigsp(rdusp(), ksig); + + /* Make sure the frame is dword-aligned. */ + sp &= ~3; + + return (void __user *)(sp - frame_size); +} + +/* Grab and setup a signal frame. + * + * Basically a lot of state-info is stacked, and arranged for the + * user-mode program to return to the kernel using either a trampiline + * which performs the syscall sigreturn(), or a provided user-mode + * trampoline. + */ +static int +setup_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) +{ + int err; + unsigned long return_ip; + struct signal_frame __user *frame; + + err = 0; + frame = get_sigframe(ksig, sizeof(*frame)); + + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + return -EFAULT; + + err |= setup_sigcontext(&frame->sc, regs, set->sig[0]); + + if (err) + return -EFAULT; + + if (_NSIG_WORDS > 1) { + err |= __copy_to_user(frame->extramask, &set->sig[1], + sizeof(frame->extramask)); + } + + if (err) + return -EFAULT; + + /* + * Set up to return from user-space. If provided, use a stub + * already located in user-space. + */ + if (ksig->ka.sa.sa_flags & SA_RESTORER) { + return_ip = (unsigned long)ksig->ka.sa.sa_restorer; + } else { + /* Trampoline - the desired return ip is in the signal return page. */ + return_ip = cris_signal_return_page; + + /* + * This is movu.w __NR_sigreturn, r9; break 13; + * + * WE DO NOT USE IT ANY MORE! It's only left here for historical + * reasons and because gdb uses it as a signature to notice + * signal handler stack frames. + */ + err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0)); + err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2)); + err |= __put_user(0xe93d, (short __user*)(frame->retcode+4)); + } + + if (err) + return -EFAULT; + + /* + * Set up registers for signal handler. + * + * Where the code enters now. + * Where the code enter later. + * First argument, signo. + */ + regs->erp = (unsigned long) ksig->ka.sa.sa_handler; + regs->srp = return_ip; + regs->r10 = ksig->sig; + + /* Actually move the USP to reflect the stacked frame. */ + wrusp((unsigned long)frame); + + return 0; +} + +static int +setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) +{ + int err; + unsigned long return_ip; + struct rt_signal_frame __user *frame; + + err = 0; + frame = get_sigframe(ksig, sizeof(*frame)); + + if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) + return -EFAULT; + + err |= __put_user(&frame->info, &frame->pinfo); + err |= __put_user(&frame->uc, &frame->puc); + err |= copy_siginfo_to_user(&frame->info, &ksig->info); + + if (err) + return -EFAULT; + + /* Clear all the bits of the ucontext we don't use. */ + err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext)); + err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]); + err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); + err |= __save_altstack(&frame->uc.uc_stack, rdusp()); + + if (err) + return -EFAULT; + + /* + * Set up to return from user-space. If provided, use a stub + * already located in user-space. + */ + if (ksig->ka.sa.sa_flags & SA_RESTORER) { + return_ip = (unsigned long) ksig->ka.sa.sa_restorer; + } else { + /* Trampoline - the desired return ip is in the signal return page. */ + return_ip = cris_signal_return_page + 6; + + /* + * This is movu.w __NR_rt_sigreturn, r9; break 13; + * + * WE DO NOT USE IT ANY MORE! It's only left here for historical + * reasons and because gdb uses it as a signature to notice + * signal handler stack frames. + */ + err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0)); + + err |= __put_user(__NR_rt_sigreturn, + (short __user*)(frame->retcode+2)); + + err |= __put_user(0xe93d, (short __user*)(frame->retcode+4)); + } + + if (err) + return -EFAULT; + + /* + * Set up registers for signal handler. + * + * Where the code enters now. + * Where the code enters later. + * First argument is signo. + * Second argument is (siginfo_t *). + * Third argument is unused. + */ + regs->erp = (unsigned long) ksig->ka.sa.sa_handler; + regs->srp = return_ip; + regs->r10 = ksig->sig; + regs->r11 = (unsigned long) &frame->info; + regs->r12 = 0; + + /* Actually move the usp to reflect the stacked frame. */ + wrusp((unsigned long)frame); + + return 0; +} + +/* Invoke a signal handler to, well, handle the signal. */ +static inline void +handle_signal(int canrestart, struct ksignal *ksig, struct pt_regs *regs) +{ + sigset_t *oldset = sigmask_to_save(); + int ret; + + /* Check if this got called from a system call. */ + if (canrestart) { + /* If so, check system call restarting. */ + switch (regs->r10) { + case -ERESTART_RESTARTBLOCK: + case -ERESTARTNOHAND: + /* + * This means that the syscall should + * only be restarted if there was no + * handler for the signal, and since + * this point isn't reached unless + * there is a handler, there's no need + * to restart. + */ + regs->r10 = -EINTR; + break; + + case -ERESTARTSYS: + /* + * This means restart the syscall if + * there is no handler, or the handler + * was registered with SA_RESTART. + */ + if (!(ksig->ka.sa.sa_flags & SA_RESTART)) { + regs->r10 = -EINTR; + break; + } + + /* Fall through. */ + + case -ERESTARTNOINTR: + /* + * This means that the syscall should + * be called again after the signal + * handler returns. + */ + RESTART_CRIS_SYS(regs); + break; + } + } + + /* Set up the stack frame. */ + if (ksig->ka.sa.sa_flags & SA_SIGINFO) + ret = setup_rt_frame(ksig, oldset, regs); + else + ret = setup_frame(ksig, oldset, regs); + + signal_setup_done(ret, ksig, 0); +} + +/* + * Note that 'init' is a special process: it doesn't get signals it doesn't + * want to handle. Thus you cannot kill init even with a SIGKILL even by + * mistake. + * + * Also note that the regs structure given here as an argument, is the latest + * pushed pt_regs. It may or may not be the same as the first pushed registers + * when the initial usermode->kernelmode transition took place. Therefore + * we can use user_mode(regs) to see if we came directly from kernel or user + * mode below. + */ +void +do_signal(int canrestart, struct pt_regs *regs) +{ + struct ksignal ksig; + + canrestart = canrestart && ((int)regs->exs >= 0); + + /* + * The common case should go fast, which is why this point is + * reached from kernel-mode. If that's the case, just return + * without doing anything. + */ + if (!user_mode(regs)) + return; + + if (get_signal(&ksig)) { + /* Whee! Actually deliver the signal. */ + handle_signal(canrestart, &ksig, regs); + return; + } + + /* Got here from a system call? */ + if (canrestart) { + /* Restart the system call - no handlers present. */ + if (regs->r10 == -ERESTARTNOHAND || + regs->r10 == -ERESTARTSYS || + regs->r10 == -ERESTARTNOINTR) { + RESTART_CRIS_SYS(regs); + } + + if (regs->r10 == -ERESTART_RESTARTBLOCK){ + regs->r9 = __NR_restart_syscall; + regs->erp -= 2; + } + } + + /* if there's no signal to deliver, we just put the saved sigmask + * back */ + restore_saved_sigmask(); +} + +asmlinkage void +ugdb_trap_user(struct thread_info *ti, int sig) +{ + if (((user_regs(ti)->exs & 0xff00) >> 8) != SINGLE_STEP_INTR_VECT) { + /* Zero single-step PC if the reason we stopped wasn't a single + step exception. This is to avoid relying on it when it isn't + reliable. */ + user_regs(ti)->spc = 0; + } + /* FIXME: Filter out false h/w breakpoint hits (i.e. EDA + not within any configured h/w breakpoint range). Synchronize with + what already exists for kernel debugging. */ + if (((user_regs(ti)->exs & 0xff00) >> 8) == BREAK_8_INTR_VECT) { + /* Break 8: subtract 2 from ERP unless in a delay slot. */ + if (!(user_regs(ti)->erp & 0x1)) + user_regs(ti)->erp -= 2; + } + sys_kill(ti->task->pid, sig); +} + +void +keep_debug_flags(unsigned long oldccs, unsigned long oldspc, + struct pt_regs *regs) +{ + if (oldccs & (1 << Q_CCS_BITNR)) { + /* Pending single step due to single-stepping the break 13 + in the signal trampoline: keep the Q flag. */ + regs->ccs |= (1 << Q_CCS_BITNR); + /* S flag should be set - complain if it's not. */ + if (!(oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT)))) { + printk("Q flag but no S flag?"); + } + regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); + /* Assume the SPC is valid and interesting. */ + regs->spc = oldspc; + + } else if (oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT))) { + /* If a h/w bp was set in the signal handler we need + to keep the S flag. */ + regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); + /* Don't keep the old SPC though; if we got here due to + a single-step, the Q flag should have been set. */ + } else if (regs->spc) { + /* If we were single-stepping *before* the signal was taken, + we don't want to restore that state now, because GDB will + have forgotten all about it. */ + regs->spc = 0; + regs->ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT)); + } +} + +/* Set up the trampolines on the signal return page. */ +int __init +cris_init_signal(void) +{ + u16* data = kmalloc(PAGE_SIZE, GFP_KERNEL); + + /* This is movu.w __NR_sigreturn, r9; break 13; */ + data[0] = 0x9c5f; + data[1] = __NR_sigreturn; + data[2] = 0xe93d; + /* This is movu.w __NR_rt_sigreturn, r9; break 13; */ + data[3] = 0x9c5f; + data[4] = __NR_rt_sigreturn; + data[5] = 0xe93d; + + /* Map to userspace with appropriate permissions (no write access...) */ + cris_signal_return_page = (unsigned long) + __ioremap_prot(virt_to_phys(data), PAGE_SIZE, PAGE_SIGNAL_TRAMPOLINE); + + return 0; +} + +__initcall(cris_init_signal); diff --git a/kernel/arch/cris/arch-v32/kernel/time.c b/kernel/arch/cris/arch-v32/kernel/time.c new file mode 100644 index 000000000..4fce9f1f7 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/time.c @@ -0,0 +1,342 @@ +/* + * linux/arch/cris/arch-v32/kernel/time.c + * + * Copyright (C) 2003-2010 Axis Communications AB + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#ifdef CONFIG_CRIS_MACH_ARTPEC3 +#include +#endif + +/* Watchdog defines */ +#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */ +#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */ +/* Number of 763 counts before watchdog bites */ +#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) + +#define CRISV32_TIMER_FREQ (100000000lu) + +unsigned long timer_regs[NR_CPUS] = +{ + regi_timer0, +}; + +extern int set_rtc_mmss(unsigned long nowtime); + +#ifdef CONFIG_CPU_FREQ +static int cris_time_freq_notifier(struct notifier_block *nb, + unsigned long val, void *data); + +static struct notifier_block cris_time_freq_notifier_block = { + .notifier_call = cris_time_freq_notifier, +}; +#endif + +unsigned long get_ns_in_jiffie(void) +{ + reg_timer_r_tmr0_data data; + unsigned long ns; + + data = REG_RD(timer, regi_timer0, r_tmr0_data); + ns = (TIMER0_DIV - data) * 10; + return ns; +} + +/* From timer MDS describing the hardware watchdog: + * 4.3.1 Watchdog Operation + * The watchdog timer is an 8-bit timer with a configurable start value. + * Once started the watchdog counts downwards with a frequency of 763 Hz + * (100/131072 MHz). When the watchdog counts down to 1, it generates an + * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the + * chip. + */ +/* This gives us 1.3 ms to do something useful when the NMI comes */ + +/* Right now, starting the watchdog is the same as resetting it */ +#define start_watchdog reset_watchdog + +#if defined(CONFIG_ETRAX_WATCHDOG) +static short int watchdog_key = 42; /* arbitrary 7 bit number */ +#endif + +/* Number of pages to consider "out of memory". It is normal that the memory + * is used though, so set this really low. */ +#define WATCHDOG_MIN_FREE_PAGES 8 + +#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY) +/* for reliable NICE_DOGGY behaviour */ +static int bite_in_progress; +#endif + +void reset_watchdog(void) +{ +#if defined(CONFIG_ETRAX_WATCHDOG) + reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; + +#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY) + if (unlikely(bite_in_progress)) + return; +#endif + /* Only keep watchdog happy as long as we have memory left! */ + if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { + /* Reset the watchdog with the inverse of the old key */ + /* Invert key, which is 7 bits */ + watchdog_key ^= ETRAX_WD_KEY_MASK; + wd_ctrl.cnt = ETRAX_WD_CNT; + wd_ctrl.cmd = regk_timer_start; + wd_ctrl.key = watchdog_key; + REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); + } +#endif +} + +/* stop the watchdog - we still need the correct key */ + +void stop_watchdog(void) +{ +#if defined(CONFIG_ETRAX_WATCHDOG) + reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; + watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */ + wd_ctrl.cnt = ETRAX_WD_CNT; + wd_ctrl.cmd = regk_timer_stop; + wd_ctrl.key = watchdog_key; + REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); +#endif +} + +extern void show_registers(struct pt_regs *regs); + +void handle_watchdog_bite(struct pt_regs *regs) +{ +#if defined(CONFIG_ETRAX_WATCHDOG) + extern int cause_of_death; + + nmi_enter(); + oops_in_progress = 1; +#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY) + bite_in_progress = 1; +#endif + printk(KERN_WARNING "Watchdog bite\n"); + + /* Check if forced restart or unexpected watchdog */ + if (cause_of_death == 0xbedead) { +#ifdef CONFIG_CRIS_MACH_ARTPEC3 + /* There is a bug in Artpec-3 (voodoo TR 78) that requires + * us to go to lower frequency for the reset to be reliable + */ + reg_clkgen_rw_clk_ctrl ctrl = + REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); + ctrl.pll = 0; + REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl); +#endif + while(1); + } + + /* Unexpected watchdog, stop the watchdog and dump registers. */ + stop_watchdog(); + printk(KERN_WARNING "Oops: bitten by watchdog\n"); + show_registers(regs); + oops_in_progress = 0; + printk("\n"); /* Flush mtdoops. */ +#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY + reset_watchdog(); +#endif + while(1) /* nothing */; +#endif +} + +extern void cris_profile_sample(struct pt_regs *regs); +static void __iomem *timer_base; + +static void crisv32_clkevt_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ + reg_timer_rw_tmr0_ctrl ctrl = { + .op = regk_timer_hold, + .freq = regk_timer_f100, + }; + + REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); +} + +static int crisv32_clkevt_next_event(unsigned long evt, + struct clock_event_device *dev) +{ + reg_timer_rw_tmr0_ctrl ctrl = { + .op = regk_timer_ld, + .freq = regk_timer_f100, + }; + + REG_WR(timer, timer_base, rw_tmr0_div, evt); + REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); + + ctrl.op = regk_timer_run; + REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); + + return 0; +} + +static irqreturn_t crisv32_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + reg_timer_rw_tmr0_ctrl ctrl = { + .op = regk_timer_hold, + .freq = regk_timer_f100, + }; + reg_timer_rw_ack_intr ack = { .tmr0 = 1 }; + reg_timer_r_masked_intr intr; + + intr = REG_RD(timer, timer_base, r_masked_intr); + if (!intr.tmr0) + return IRQ_NONE; + + REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); + REG_WR(timer, timer_base, rw_ack_intr, ack); + + reset_watchdog(); +#ifdef CONFIG_SYSTEM_PROFILER + cris_profile_sample(get_irq_regs()); +#endif + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct clock_event_device crisv32_clockevent = { + .name = "crisv32-timer", + .rating = 300, + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_mode = crisv32_clkevt_mode, + .set_next_event = crisv32_clkevt_next_event, +}; + +/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */ +static struct irqaction irq_timer = { + .handler = crisv32_timer_interrupt, + .flags = IRQF_TIMER | IRQF_SHARED, + .name = "crisv32-timer", + .dev_id = &crisv32_clockevent, +}; + +static u64 notrace crisv32_timer_sched_clock(void) +{ + return REG_RD(timer, timer_base, r_time); +} + +static void __init crisv32_timer_init(void) +{ + reg_timer_rw_intr_mask timer_intr_mask; + reg_timer_rw_tmr0_ctrl ctrl = { + .op = regk_timer_hold, + .freq = regk_timer_f100, + }; + + REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); + + timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask); + timer_intr_mask.tmr0 = 1; + REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask); +} + +void __init time_init(void) +{ + int irq; + int ret; + + /* Probe for the RTC and read it if it exists. + * Before the RTC can be probed the loops_per_usec variable needs + * to be initialized to make usleep work. A better value for + * loops_per_usec is calculated by the kernel later once the + * clock has started. + */ + loops_per_usec = 50; + + irq = TIMER0_INTR_VECT; + timer_base = (void __iomem *) regi_timer0; + + crisv32_timer_init(); + + sched_clock_register(crisv32_timer_sched_clock, 32, + CRISV32_TIMER_FREQ); + + clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time, + "crisv32-timer", CRISV32_TIMER_FREQ, + 300, 32, clocksource_mmio_readl_up); + + crisv32_clockevent.cpumask = cpu_possible_mask; + crisv32_clockevent.irq = irq; + + ret = setup_irq(irq, &irq_timer); + if (ret) + pr_warn("failed to setup irq %d\n", irq); + + clockevents_config_and_register(&crisv32_clockevent, + CRISV32_TIMER_FREQ, + 2, 0xffffffff); + + /* Enable watchdog if we should use one. */ + +#if defined(CONFIG_ETRAX_WATCHDOG) + printk(KERN_INFO "Enabling watchdog...\n"); + start_watchdog(); + + /* If we use the hardware watchdog, we want to trap it as an NMI + * and dump registers before it resets us. For this to happen, we + * must set the "m" NMI enable flag (which once set, is unset only + * when an NMI is taken). */ + { + unsigned long flags; + local_save_flags(flags); + flags |= (1<<30); /* NMI M flag is at bit 30 */ + local_irq_restore(flags); + } +#endif + +#ifdef CONFIG_CPU_FREQ + cpufreq_register_notifier(&cris_time_freq_notifier_block, + CPUFREQ_TRANSITION_NOTIFIER); +#endif +} + +#ifdef CONFIG_CPU_FREQ +static int cris_time_freq_notifier(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct cpufreq_freqs *freqs = data; + if (val == CPUFREQ_POSTCHANGE) { + reg_timer_r_tmr0_data data; + reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ; + do { + data = REG_RD(timer, timer_regs[freqs->cpu], + r_tmr0_data); + } while (data > 20); + REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div); + } + return 0; +} +#endif diff --git a/kernel/arch/cris/arch-v32/kernel/traps.c b/kernel/arch/cris/arch-v32/kernel/traps.c new file mode 100644 index 000000000..8bbe09c93 --- /dev/null +++ b/kernel/arch/cris/arch-v32/kernel/traps.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2003-2006, Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include + +void show_registers(struct pt_regs *regs) +{ + /* + * It's possible to use either the USP register or current->thread.usp. + * USP might not correspond to the current process for all cases this + * function is called, and current->thread.usp isn't up to date for the + * current process. Experience shows that using USP is the way to go. + */ + unsigned long usp = rdusp(); + unsigned long d_mmu_cause; + unsigned long i_mmu_cause; + + printk("CPU: %d\n", smp_processor_id()); + + printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n", + regs->erp, regs->srp, regs->ccs, usp, regs->mof); + + printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", + regs->r0, regs->r1, regs->r2, regs->r3); + + printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", + regs->r4, regs->r5, regs->r6, regs->r7); + + printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", + regs->r8, regs->r9, regs->r10, regs->r11); + + printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n", + regs->r12, regs->r13, regs->orig_r10, regs->acr); + + printk(" sp: %08lx\n", (unsigned long)regs); + + SUPP_BANK_SEL(BANK_IM); + SUPP_REG_RD(RW_MM_CAUSE, i_mmu_cause); + + SUPP_BANK_SEL(BANK_DM); + SUPP_REG_RD(RW_MM_CAUSE, d_mmu_cause); + + printk(" Data MMU Cause: %08lx\n", d_mmu_cause); + printk("Instruction MMU Cause: %08lx\n", i_mmu_cause); + + printk("Process %s (pid: %d, stackpage=%08lx)\n", + current->comm, current->pid, (unsigned long)current); + + /* + * When in-kernel, we also print out the stack and code at the + * time of the fault.. + */ + if (!user_mode(regs)) { + int i; + + show_stack(NULL, (unsigned long *)usp); + + /* + * If the previous stack-dump wasn't a kernel one, dump the + * kernel stack now. + */ + if (usp != 0) + show_stack(NULL, NULL); + + printk("\nCode: "); + + if (regs->erp < PAGE_OFFSET) + goto bad_value; + + /* + * Quite often the value at regs->erp doesn't point to the + * interesting instruction, which often is the previous + * instruction. So dump at an offset large enough that the + * instruction decoding should be in sync at the interesting + * point, but small enough to fit on a row. The regs->erp + * location is pointed out in a ksymoops-friendly way by + * wrapping the byte for that address in parenthesises. + */ + for (i = -12; i < 12; i++) { + unsigned char c; + + if (__get_user(c, &((unsigned char *)regs->erp)[i])) { +bad_value: + printk(" Bad IP value."); + break; + } + + if (i == 0) + printk("(%02x) ", c); + else + printk("%02x ", c); + } + printk("\n"); + } +} + +void arch_enable_nmi(void) +{ + unsigned long flags; + + local_save_flags(flags); + flags |= (1 << 30); /* NMI M flag is at bit 30 */ + local_irq_restore(flags); +} + +extern void (*nmi_handler)(struct pt_regs *); +void handle_nmi(struct pt_regs *regs) +{ +#ifdef CONFIG_ETRAXFS + reg_intr_vect_r_nmi r; +#endif + + if (nmi_handler) + nmi_handler(regs); + +#ifdef CONFIG_ETRAXFS + /* Wait until nmi is no longer active. */ + do { + r = REG_RD(intr_vect, regi_irq, r_nmi); + } while (r.ext == regk_intr_vect_on); +#endif +} + + +#ifdef CONFIG_BUG +extern void die_if_kernel(const char *str, struct pt_regs *regs, long err); + +/* Copy of the regs at BUG() time. */ +struct pt_regs BUG_regs; + +void do_BUG(char *file, unsigned int line) +{ + printk("kernel BUG at %s:%d!\n", file, line); + die_if_kernel("Oops", &BUG_regs, 0); +} +EXPORT_SYMBOL(do_BUG); + +void fixup_BUG(struct pt_regs *regs) +{ + BUG_regs = *regs; + +#ifdef CONFIG_DEBUG_BUGVERBOSE + /* + * Fixup the BUG arguments through exception handlers. + */ + { + const struct exception_table_entry *fixup; + + /* + * ERP points at the "break 14" + 2, compensate for the 2 + * bytes. + */ + fixup = search_exception_tables(instruction_pointer(regs) - 2); + if (fixup) { + /* Adjust the instruction pointer in the stackframe. */ + instruction_pointer(regs) = fixup->fixup; + arch_fixup(regs); + } + } +#else + /* Dont try to lookup the filename + line, just dump regs. */ + do_BUG("unknown", 0); +#endif +} + +/* + * Break 14 handler. Save regs and jump into the fixup_BUG. + */ +__asm__ ( ".text\n\t" + ".global breakh_BUG\n\t" + "breakh_BUG:\n\t" + SAVE_ALL + KGDB_FIXUP + "move.d $sp, $r10\n\t" + "jsr fixup_BUG\n\t" + "nop\n\t" + "jump ret_from_intr\n\t" + "nop\n\t"); + + +#ifdef CONFIG_DEBUG_BUGVERBOSE +void +handle_BUG(struct pt_regs *regs) +{ +} +#endif +#endif diff --git a/kernel/arch/cris/arch-v32/lib/Makefile b/kernel/arch/cris/arch-v32/lib/Makefile new file mode 100644 index 000000000..e91cf02f6 --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for Etrax-specific library files.. +# + +lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \ + csumcpfruser.o delay.o strcmp.o + diff --git a/kernel/arch/cris/arch-v32/lib/checksum.S b/kernel/arch/cris/arch-v32/lib/checksum.S new file mode 100644 index 000000000..4a72a94a4 --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/checksum.S @@ -0,0 +1,88 @@ +/* + * A fast checksum routine using movem + * Copyright (c) 1998-2007 Axis Communications AB + * + * csum_partial(const unsigned char * buff, int len, unsigned int sum) + */ + + .globl csum_partial + .type csum_partial,@function +csum_partial: + + ;; r10 - src + ;; r11 - length + ;; r12 - checksum + + ;; Optimized for large packets + subq 10*4, $r11 + blt _word_loop + move.d $r11, $acr + + subq 9*4,$sp + clearf c + movem $r8,[$sp] + + ;; do a movem checksum + +_mloop: movem [$r10+],$r9 ; read 10 longwords + ;; Loop count without touching the c flag. + addoq -10*4, $acr, $acr + ;; perform dword checksumming on the 10 longwords + + addc $r0,$r12 + addc $r1,$r12 + addc $r2,$r12 + addc $r3,$r12 + addc $r4,$r12 + addc $r5,$r12 + addc $r6,$r12 + addc $r7,$r12 + addc $r8,$r12 + addc $r9,$r12 + + ;; test $acr without trashing carry. + move.d $acr, $acr + bpl _mloop + ;; r11 <= acr is not really needed in the mloop, just using the dslot + ;; to prepare for what is needed after mloop. + move.d $acr, $r11 + + ;; fold the last carry into r13 + addc 0, $r12 + movem [$sp+],$r8 ; restore regs + +_word_loop: + addq 10*4,$r11 ; compensate for last loop underflowing length + + moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9 + lsrq 16,$r9 + + move.d $r12,$r13 + lsrq 16,$r13 ; r13 = checksum >> 16 + and.d $r9,$r12 ; checksum = checksum & 0xffff + +_no_fold: + subq 2,$r11 + blt _no_words + add.d $r13,$r12 ; checksum += r13 + + ;; checksum the rest of the words +_wloop: subq 2,$r11 + bge _wloop + addu.w [$r10+],$r12 + +_no_words: + addq 2,$r11 + ;; see if we have one odd byte more + bne _do_byte + nop + ret + move.d $r12,$r10 + +_do_byte: + ;; copy and checksum the last byte + addu.b [$r10],$r12 + ret + move.d $r12,$r10 + + .size csum_partial, .-csum_partial diff --git a/kernel/arch/cris/arch-v32/lib/checksumcopy.S b/kernel/arch/cris/arch-v32/lib/checksumcopy.S new file mode 100644 index 000000000..54e209f18 --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/checksumcopy.S @@ -0,0 +1,94 @@ +/* + * A fast checksum+copy routine using movem + * Copyright (c) 1998-2007 Axis Communications AB + * + * Authors: Bjorn Wesen + * + * csum_partial_copy_nocheck(const char *src, char *dst, + * int len, unsigned int sum) + */ + + .globl csum_partial_copy_nocheck + .type csum_partial_copy_nocheck,@function +csum_partial_copy_nocheck: + + ;; r10 - src + ;; r11 - dst + ;; r12 - length + ;; r13 - checksum + + ;; Optimized for large packets + subq 10*4, $r12 + blt _word_loop + move.d $r12, $acr + + subq 9*4,$sp + clearf c + movem $r8,[$sp] + + ;; do a movem copy and checksum +1: ;; A failing userspace access (the read) will have this as PC. +_mloop: movem [$r10+],$r9 ; read 10 longwords + addoq -10*4, $acr, $acr ; loop counter in latency cycle + movem $r9,[$r11+] ; write 10 longwords + + ;; perform dword checksumming on the 10 longwords + addc $r0,$r13 + addc $r1,$r13 + addc $r2,$r13 + addc $r3,$r13 + addc $r4,$r13 + addc $r5,$r13 + addc $r6,$r13 + addc $r7,$r13 + addc $r8,$r13 + addc $r9,$r13 + + ;; test $acr, without trashing carry. + move.d $acr, $acr + bpl _mloop + ;; r12 <= acr is needed after mloop and in the exception handlers. + move.d $acr, $r12 + + ;; fold the last carry into r13 + addc 0, $r13 + movem [$sp+],$r8 ; restore regs + +_word_loop: + addq 10*4,$r12 ; compensate for last loop underflowing length + + ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below + ;; r9 can be used as temporary. + move.d $r13,$r9 + lsrq 16,$r9 ; r0 = checksum >> 16 + and.d 0xffff,$r13 ; checksum = checksum & 0xffff + + subq 2, $r12 + blt _no_words + add.d $r9,$r13 ; checksum += r0 + + ;; copy and checksum the rest of the words +2: ;; A failing userspace access for the read below will have this as PC. +_wloop: move.w [$r10+],$r9 + addu.w $r9,$r13 + subq 2,$r12 + bge _wloop + move.w $r9,[$r11+] + +_no_words: + addq 2,$r12 + bne _do_byte + nop + ret + move.d $r13,$r10 + +_do_byte: + ;; copy and checksum the last byte +3: ;; A failing userspace access for the read below will have this as PC. + move.b [$r10],$r9 + addu.b $r9,$r13 + move.b $r9,[$r11] + ret + move.d $r13,$r10 + + .size csum_partial_copy_nocheck, . - csum_partial_copy_nocheck diff --git a/kernel/arch/cris/arch-v32/lib/csumcpfruser.S b/kernel/arch/cris/arch-v32/lib/csumcpfruser.S new file mode 100644 index 000000000..600ec16b9 --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/csumcpfruser.S @@ -0,0 +1,69 @@ +/* + * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into + * csum_partial_copy_from_user by adding exception records. + * + * Copyright (C) 2001, 2003 Axis Communications AB. + * + * Author: Hans-Peter Nilsson. + */ + +#include + +/* Same function body, but a different name. If we just added exception + records to _csum_partial_copy_nocheck and made it generic, we wouldn't + know a user fault from a kernel fault and we would have overhead in + each kernel caller for the error-pointer argument. + + unsigned int csum_partial_copy_from_user + (const char *src, char *dst, int len, unsigned int sum, int *errptr); + + Note that the errptr argument is only set if we encounter an error. + It is conveniently located on the stack, so the normal function body + does not have to handle it. */ + +#define csum_partial_copy_nocheck csum_partial_copy_from_user + +/* There are local labels numbered 1, 2 and 3 present to mark the + different from-user accesses. */ +#include "checksumcopy.S" + + .section .fixup,"ax" + +;; Here from the movem loop; restore stack. +4: + movem [$sp+],$r8 +;; r12 is already decremented. Add back chunk_size-2. + addq 40-2,$r12 + +;; Here from the word loop; r12 is off by 2; add it back. +5: + addq 2,$r12 + +;; Here from a failing single byte. +6: + +;; Signal in *errptr that we had a failing access. + move.d [$sp],$acr + moveq -EFAULT,$r9 + subq 4,$sp + move.d $r9,[$acr] + +;; Clear the rest of the destination area using memset. Preserve the +;; checksum for the readable bytes. + move.d $r13,[$sp] + subq 4,$sp + move.d $r11,$r10 + move $srp,[$sp] + jsr memset + clear.d $r11 + + move [$sp+],$srp + ret + move.d [$sp+],$r10 + + .previous + .section __ex_table,"a" + .dword 1b,4b + .dword 2b,5b + .dword 3b,6b + .previous diff --git a/kernel/arch/cris/arch-v32/lib/delay.c b/kernel/arch/cris/arch-v32/lib/delay.c new file mode 100644 index 000000000..39f1ac999 --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/delay.c @@ -0,0 +1,28 @@ +/* + * Precise Delay Loops for ETRAX FS + * + * Copyright (C) 2006 Axis Communications AB. + * + */ + +#include +#include +#include +#include +#include +#include + +/* + * On ETRAX FS, we can check the free-running read-only 100MHz timer + * getting 32-bit 10ns precision, theoretically good for 42.94967295 + * seconds. Unsigned arithmetic and careful expression handles + * wrapping. + */ + +void cris_delay10ns(u32 n10ns) +{ + u32 t0 = REG_RD(timer, regi_timer0, r_time); + while (REG_RD(timer, regi_timer0, r_time) - t0 < n10ns) + ; +} +EXPORT_SYMBOL(cris_delay10ns); diff --git a/kernel/arch/cris/arch-v32/lib/memset.c b/kernel/arch/cris/arch-v32/lib/memset.c new file mode 100644 index 000000000..c94ea9b3e --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/memset.c @@ -0,0 +1,259 @@ +/* A memset for CRIS. + Copyright (C) 1999-2005 Axis Communications. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Neither the name of Axis Communications nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS + ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS + COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* FIXME: This file should really only be used for reference, as the + result is somewhat depending on gcc generating what we expect rather + than what we describe. An assembly file should be used instead. */ + +/* Note the multiple occurrence of the expression "12*4", including the + asm. It is hard to get it into the asm in a good way. Thus better to + expose the problem everywhere: no macro. */ + +/* Assuming one cycle per dword written or read (ok, not really true; the + world is not ideal), and one cycle per instruction, then 43+3*(n/48-1) + <= 24+24*(n/48-1) so n >= 45.7; n >= 0.9; we win on the first full + 48-byte block to set. */ + +#define MEMSET_BY_BLOCK_THRESHOLD (1 * 48) + +/* No name ambiguities in this file. */ +__asm__ (".syntax no_register_prefix"); + +void *memset(void *pdst, int c, unsigned int plen) +{ + /* Now we want the parameters in special registers. Make sure the + compiler does something usable with this. */ + + register char *return_dst __asm__ ("r10") = pdst; + register int n __asm__ ("r12") = plen; + register int lc __asm__ ("r11") = c; + + /* Most apps use memset sanely. Memsetting about 3..4 bytes or less get + penalized here compared to the generic implementation. */ + + /* This is fragile performancewise at best. Check with newer GCC + releases, if they compile cascaded "x |= x << 8" to sane code. */ + __asm__("movu.b %0,r13 \n\ + lslq 8,r13 \n\ + move.b %0,r13 \n\ + move.d r13,%0 \n\ + lslq 16,r13 \n\ + or.d r13,%0" + : "=r" (lc) /* Inputs. */ + : "0" (lc) /* Outputs. */ + : "r13"); /* Trash. */ + + { + register char *dst __asm__ ("r13") = pdst; + + if (((unsigned long) pdst & 3) != 0 + /* Oops! n = 0 must be a valid call, regardless of alignment. */ + && n >= 3) + { + if ((unsigned long) dst & 1) + { + *dst = (char) lc; + n--; + dst++; + } + + if ((unsigned long) dst & 2) + { + *(short *) dst = lc; + n -= 2; + dst += 2; + } + } + + /* Decide which setting method to use. */ + if (n >= MEMSET_BY_BLOCK_THRESHOLD) + { + /* It is not optimal to tell the compiler about clobbering any + registers; that will move the saving/restoring of those registers + to the function prologue/epilogue, and make non-block sizes + suboptimal. */ + __asm__ volatile + ("\ + ;; GCC does promise correct register allocations, but let's \n\ + ;; make sure it keeps its promises. \n\ + .ifnc %0-%1-%4,$r13-$r12-$r11 \n\ + .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\ + .endif \n\ + \n\ + ;; Save the registers we'll clobber in the movem process \n\ + ;; on the stack. Don't mention them to gcc, it will only be \n\ + ;; upset. \n\ + subq 11*4,sp \n\ + movem r10,[sp] \n\ + \n\ + move.d r11,r0 \n\ + move.d r11,r1 \n\ + move.d r11,r2 \n\ + move.d r11,r3 \n\ + move.d r11,r4 \n\ + move.d r11,r5 \n\ + move.d r11,r6 \n\ + move.d r11,r7 \n\ + move.d r11,r8 \n\ + move.d r11,r9 \n\ + move.d r11,r10 \n\ + \n\ + ;; Now we've got this: \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop \n\ + subq 12*4,r12 \n\ +0: \n\ +" +#ifdef __arch_common_v10_v32 + /* Cater to branch offset difference between v32 and v10. We + assume the branch below has an 8-bit offset. */ +" setf\n" +#endif +" subq 12*4,r12 \n\ + bge 0b \n\ + movem r11,[r13+] \n\ + \n\ + ;; Compensate for last loop underflowing n. \n\ + addq 12*4,r12 \n\ + \n\ + ;; Restore registers from stack. \n\ + movem [sp+],r10" + + /* Outputs. */ + : "=r" (dst), "=r" (n) + + /* Inputs. */ + : "0" (dst), "1" (n), "r" (lc)); + } + + /* An ad-hoc unroll, used for 4*12-1..16 bytes. */ + while (n >= 16) + { + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + n -= 16; + } + + switch (n) + { + case 0: + break; + + case 1: + *dst = (char) lc; + break; + + case 2: + *(short *) dst = (short) lc; + break; + + case 3: + *(short *) dst = (short) lc; dst += 2; + *dst = (char) lc; + break; + + case 4: + *(long *) dst = lc; + break; + + case 5: + *(long *) dst = lc; dst += 4; + *dst = (char) lc; + break; + + case 6: + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; + break; + + case 7: + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; dst += 2; + *dst = (char) lc; + break; + + case 8: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; + break; + + case 9: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *dst = (char) lc; + break; + + case 10: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; + break; + + case 11: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; dst += 2; + *dst = (char) lc; + break; + + case 12: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; + break; + + case 13: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *dst = (char) lc; + break; + + case 14: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; + break; + + case 15: + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(long *) dst = lc; dst += 4; + *(short *) dst = (short) lc; dst += 2; + *dst = (char) lc; + break; + } + } + + return return_dst; +} diff --git a/kernel/arch/cris/arch-v32/lib/strcmp.S b/kernel/arch/cris/arch-v32/lib/strcmp.S new file mode 100644 index 000000000..8f7a1ee62 --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/strcmp.S @@ -0,0 +1,21 @@ +; strcmp.S -- CRISv32 version. +; Copyright (C) 2008 AXIS Communications AB +; Written by Edgar E. Iglesias +; +; This source code is licensed under the GNU General Public License, +; Version 2. See the file COPYING for more details. + + .global strcmp + .type strcmp,@function +strcmp: +1: + move.b [$r10+], $r12 + seq $r13 + sub.b [$r11+], $r12 + or.b $r12, $r13 + beq 1b + nop + + ret + movs.b $r12, $r10 + .size strcmp, . - strcmp diff --git a/kernel/arch/cris/arch-v32/lib/string.c b/kernel/arch/cris/arch-v32/lib/string.c new file mode 100644 index 000000000..c7bd6ebdc --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/string.c @@ -0,0 +1,236 @@ +/* A memcpy for CRIS. + Copyright (C) 1994-2005 Axis Communications. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. Neither the name of Axis Communications nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS + ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS + COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* FIXME: This file should really only be used for reference, as the + result is somewhat depending on gcc generating what we expect rather + than what we describe. An assembly file should be used instead. */ + +#include + +/* Break even between movem and move16 is really at 38.7 * 2, but + modulo 44, so up to the next multiple of 44, we use ordinary code. */ +#define MEMCPY_BY_BLOCK_THRESHOLD (44 * 2) + +/* No name ambiguities in this file. */ +__asm__ (".syntax no_register_prefix"); + +void * +memcpy(void *pdst, const void *psrc, size_t pn) +{ + /* Now we want the parameters put in special registers. + Make sure the compiler is able to make something useful of this. + As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). + + If gcc was allright, it really would need no temporaries, and no + stack space to save stuff on. */ + + register void *return_dst __asm__ ("r10") = pdst; + register unsigned char *dst __asm__ ("r13") = pdst; + register unsigned const char *src __asm__ ("r11") = psrc; + register int n __asm__ ("r12") = pn; + + /* When src is aligned but not dst, this makes a few extra needless + cycles. I believe it would take as many to check that the + re-alignment was unnecessary. */ + if (((unsigned long) dst & 3) != 0 + /* Don't align if we wouldn't copy more than a few bytes; so we + don't have to check further for overflows. */ + && n >= 3) + { + if ((unsigned long) dst & 1) + { + n--; + *dst = *src; + src++; + dst++; + } + + if ((unsigned long) dst & 2) + { + n -= 2; + *(short *) dst = *(short *) src; + src += 2; + dst += 2; + } + } + + /* Decide which copying method to use. */ + if (n >= MEMCPY_BY_BLOCK_THRESHOLD) + { + /* It is not optimal to tell the compiler about clobbering any + registers; that will move the saving/restoring of those registers + to the function prologue/epilogue, and make non-movem sizes + suboptimal. */ + __asm__ volatile + ("\ + ;; GCC does promise correct register allocations, but let's \n\ + ;; make sure it keeps its promises. \n\ + .ifnc %0-%1-%2,$r13-$r11-$r12 \n\ + .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\ + .endif \n\ + \n\ + ;; Save the registers we'll use in the movem process \n\ + ;; on the stack. \n\ + subq 11*4,sp \n\ + movem r10,[sp] \n\ + \n\ + ;; Now we've got this: \n\ + ;; r11 - src \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop. \n\ + subq 44,r12 \n\ +0: \n\ +" +#ifdef __arch_common_v10_v32 + /* Cater to branch offset difference between v32 and v10. We + assume the branch below has an 8-bit offset. */ +" setf\n" +#endif +" movem [r11+],r10 \n\ + subq 44,r12 \n\ + bge 0b \n\ + movem r10,[r13+] \n\ + \n\ + ;; Compensate for last loop underflowing n. \n\ + addq 44,r12 \n\ + \n\ + ;; Restore registers from stack. \n\ + movem [sp+],r10" + + /* Outputs. */ + : "=r" (dst), "=r" (src), "=r" (n) + + /* Inputs. */ + : "0" (dst), "1" (src), "2" (n)); + } + + while (n >= 16) + { + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + + n -= 16; + } + + switch (n) + { + case 0: + break; + + case 1: + *dst = *src; + break; + + case 2: + *(short *) dst = *(short *) src; + break; + + case 3: + *(short *) dst = *(short *) src; dst += 2; src += 2; + *dst = *src; + break; + + case 4: + *(long *) dst = *(long *) src; + break; + + case 5: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *dst = *src; + break; + + case 6: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; + break; + + case 7: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; dst += 2; src += 2; + *dst = *src; + break; + + case 8: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; + break; + + case 9: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *dst = *src; + break; + + case 10: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; + break; + + case 11: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; dst += 2; src += 2; + *dst = *src; + break; + + case 12: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; + break; + + case 13: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *dst = *src; + break; + + case 14: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; + break; + + case 15: + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(long *) dst = *(long *) src; dst += 4; src += 4; + *(short *) dst = *(short *) src; dst += 2; src += 2; + *dst = *src; + break; + } + + return return_dst; +} diff --git a/kernel/arch/cris/arch-v32/lib/usercopy.c b/kernel/arch/cris/arch-v32/lib/usercopy.c new file mode 100644 index 000000000..f0f335d8a --- /dev/null +++ b/kernel/arch/cris/arch-v32/lib/usercopy.c @@ -0,0 +1,469 @@ +/* + * User address space access functions. + * The non-inlined parts of asm-cris/uaccess.h are here. + * + * Copyright (C) 2000, 2003 Axis Communications AB. + * + * Written by Hans-Peter Nilsson. + * Pieces used from memcpy, originally by Kenny Ranerup long time ago. + */ + +#include + +/* Asm:s have been tweaked (within the domain of correctness) to give + satisfactory results for "gcc version 3.2.1 Axis release R53/1.53-v32". + + Check regularly... + + Note that for CRISv32, the PC saved at a bus-fault is the address + *at* the faulting instruction, with a special case for instructions + in delay slots: then it's the address of the branch. Note also that + in contrast to v10, a postincrement in the instruction is *not* + performed at a bus-fault; the register is seen having the original + value in fault handlers. */ + + +/* Copy to userspace. This is based on the memcpy used for + kernel-to-kernel copying; see "string.c". */ + +unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn) +{ + /* We want the parameters put in special registers. + Make sure the compiler is able to make something useful of this. + As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). + + FIXME: Comment for old gcc version. Check. + If gcc was alright, it really would need no temporaries, and no + stack space to save stuff on. */ + + register char *dst __asm__ ("r13") = pdst; + register const char *src __asm__ ("r11") = psrc; + register int n __asm__ ("r12") = pn; + register int retn __asm__ ("r10") = 0; + + + /* When src is aligned but not dst, this makes a few extra needless + cycles. I believe it would take as many to check that the + re-alignment was unnecessary. */ + if (((unsigned long) dst & 3) != 0 + /* Don't align if we wouldn't copy more than a few bytes; so we + don't have to check further for overflows. */ + && n >= 3) + { + if ((unsigned long) dst & 1) + { + __asm_copy_to_user_1 (dst, src, retn); + n--; + } + + if ((unsigned long) dst & 2) + { + __asm_copy_to_user_2 (dst, src, retn); + n -= 2; + } + } + + /* Movem is dirt cheap. The overheap is low enough to always use the + minimum possible block size as the threshold. */ + if (n >= 44) + { + /* For large copies we use 'movem'. */ + + /* It is not optimal to tell the compiler about clobbering any + registers; that will move the saving/restoring of those registers + to the function prologue/epilogue, and make non-movem sizes + suboptimal. */ + __asm__ volatile ("\ + ;; Check that the register asm declaration got right. \n\ + ;; The GCC manual explicitly says TRT will happen. \n\ + .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ + .err \n\ + .endif \n\ + \n\ + ;; Save the registers we'll use in the movem process \n\ + ;; on the stack. \n\ + subq 11*4,$sp \n\ + movem $r10,[$sp] \n\ + \n\ + ;; Now we've got this: \n\ + ;; r11 - src \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop \n\ + subq 44,$r12 \n\ +0: \n\ + movem [$r11+],$r10 \n\ + subq 44,$r12 \n\ +1: bge 0b \n\ + movem $r10,[$r13+] \n\ +3: \n\ + addq 44,$r12 ;; compensate for last loop underflowing n \n\ + \n\ + ;; Restore registers from stack \n\ + movem [$sp+],$r10 \n\ +2: \n\ + .section .fixup,\"ax\" \n\ +4: \n\ +; When failing on any of the 1..44 bytes in a chunk, we adjust back the \n\ +; source pointer and just drop through to the by-16 and by-4 loops to \n\ +; get the correct number of failing bytes. This necessarily means a \n\ +; few extra exceptions, but invalid user pointers shouldn't happen in \n\ +; time-critical code anyway. \n\ + jump 3b \n\ + subq 44,$r11 \n\ + \n\ + .previous \n\ + .section __ex_table,\"a\" \n\ + .dword 1b,4b \n\ + .previous" + + /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) + /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); + + } + + while (n >= 16) + { + __asm_copy_to_user_16 (dst, src, retn); + n -= 16; + } + + /* Having a separate by-four loops cuts down on cache footprint. + FIXME: Test with and without; increasing switch to be 0..15. */ + while (n >= 4) + { + __asm_copy_to_user_4 (dst, src, retn); + n -= 4; + } + + switch (n) + { + case 0: + break; + case 1: + __asm_copy_to_user_1 (dst, src, retn); + break; + case 2: + __asm_copy_to_user_2 (dst, src, retn); + break; + case 3: + __asm_copy_to_user_3 (dst, src, retn); + break; + } + + return retn; +} +EXPORT_SYMBOL(__copy_user); + +/* Copy from user to kernel, zeroing the bytes that were inaccessible in + userland. The return-value is the number of bytes that were + inaccessible. */ +unsigned long __copy_user_zeroing(void *pdst, const void __user *psrc, + unsigned long pn) +{ + /* We want the parameters put in special registers. + Make sure the compiler is able to make something useful of this. + As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). + + FIXME: Comment for old gcc version. Check. + If gcc was alright, it really would need no temporaries, and no + stack space to save stuff on. */ + + register char *dst __asm__ ("r13") = pdst; + register const char *src __asm__ ("r11") = psrc; + register int n __asm__ ("r12") = pn; + register int retn __asm__ ("r10") = 0; + + /* The best reason to align src is that we then know that a read-fault + was for aligned bytes; there's no 1..3 remaining good bytes to + pickle. */ + if (((unsigned long) src & 3) != 0) + { + if (((unsigned long) src & 1) && n != 0) + { + __asm_copy_from_user_1 (dst, src, retn); + n--; + } + + if (((unsigned long) src & 2) && n >= 2) + { + __asm_copy_from_user_2 (dst, src, retn); + n -= 2; + } + + /* We only need one check after the unalignment-adjustments, because + if both adjustments were done, either both or neither reference + had an exception. */ + if (retn != 0) + goto copy_exception_bytes; + } + + /* Movem is dirt cheap. The overheap is low enough to always use the + minimum possible block size as the threshold. */ + if (n >= 44) + { + /* It is not optimal to tell the compiler about clobbering any + registers; that will move the saving/restoring of those registers + to the function prologue/epilogue, and make non-movem sizes + suboptimal. */ + __asm__ volatile ("\ + .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ + .err \n\ + .endif \n\ + \n\ + ;; Save the registers we'll use in the movem process \n\ + ;; on the stack. \n\ + subq 11*4,$sp \n\ + movem $r10,[$sp] \n\ + \n\ + ;; Now we've got this: \n\ + ;; r11 - src \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop \n\ + subq 44,$r12 \n\ +0: \n\ + movem [$r11+],$r10 \n\ + \n\ + subq 44,$r12 \n\ + bge 0b \n\ + movem $r10,[$r13+] \n\ + \n\ +4: \n\ + addq 44,$r12 ;; compensate for last loop underflowing n \n\ + \n\ + ;; Restore registers from stack \n\ + movem [$sp+],$r10 \n\ + .section .fixup,\"ax\" \n\ + \n\ +;; Do not jump back into the loop if we fail. For some uses, we get a \n\ +;; page fault somewhere on the line. Without checking for page limits, \n\ +;; we don't know where, but we need to copy accurately and keep an \n\ +;; accurate count; not just clear the whole line. To do that, we fall \n\ +;; down in the code below, proceeding with smaller amounts. It should \n\ +;; be kept in mind that we have to cater to code like what at one time \n\ +;; was in fs/super.c: \n\ +;; i = size - copy_from_user((void *)page, data, size); \n\ +;; which would cause repeated faults while clearing the remainder of \n\ +;; the SIZE bytes at PAGE after the first fault. \n\ +;; A caveat here is that we must not fall through from a failing page \n\ +;; to a valid page. \n\ + \n\ +3: \n\ + jump 4b ;; Fall through, pretending the fault didn't happen. \n\ + nop \n\ + \n\ + .previous \n\ + .section __ex_table,\"a\" \n\ + .dword 0b,3b \n\ + .previous" + + /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) + /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); + } + + /* Either we directly start copying here, using dword copying in a loop, + or we copy as much as possible with 'movem' and then the last block + (<44 bytes) is copied here. This will work since 'movem' will have + updated src, dst and n. (Except with failing src.) + + Since we want to keep src accurate, we can't use + __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and + retn, but not src (by design; it's value is ignored elsewhere). */ + + while (n >= 4) + { + __asm_copy_from_user_4 (dst, src, retn); + n -= 4; + + if (retn) + goto copy_exception_bytes; + } + + /* If we get here, there were no memory read faults. */ + switch (n) + { + /* These copies are at least "naturally aligned" (so we don't have + to check each byte), due to the src alignment code before the + movem loop. The *_3 case *will* get the correct count for retn. */ + case 0: + /* This case deliberately left in (if you have doubts check the + generated assembly code). */ + break; + case 1: + __asm_copy_from_user_1 (dst, src, retn); + break; + case 2: + __asm_copy_from_user_2 (dst, src, retn); + break; + case 3: + __asm_copy_from_user_3 (dst, src, retn); + break; + } + + /* If we get here, retn correctly reflects the number of failing + bytes. */ + return retn; + +copy_exception_bytes: + /* We already have "retn" bytes cleared, and need to clear the + remaining "n" bytes. A non-optimized simple byte-for-byte in-line + memset is preferred here, since this isn't speed-critical code and + we'd rather have this a leaf-function than calling memset. */ + { + char *endp; + for (endp = dst + n; dst < endp; dst++) + *dst = 0; + } + + return retn + n; +} +EXPORT_SYMBOL(__copy_user_zeroing); + +/* Zero userspace. */ +unsigned long __do_clear_user(void __user *pto, unsigned long pn) +{ + /* We want the parameters put in special registers. + Make sure the compiler is able to make something useful of this. + As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). + + FIXME: Comment for old gcc version. Check. + If gcc was alright, it really would need no temporaries, and no + stack space to save stuff on. */ + + register char *dst __asm__ ("r13") = pto; + register int n __asm__ ("r12") = pn; + register int retn __asm__ ("r10") = 0; + + + if (((unsigned long) dst & 3) != 0 + /* Don't align if we wouldn't copy more than a few bytes. */ + && n >= 3) + { + if ((unsigned long) dst & 1) + { + __asm_clear_1 (dst, retn); + n--; + } + + if ((unsigned long) dst & 2) + { + __asm_clear_2 (dst, retn); + n -= 2; + } + } + + /* Decide which copying method to use. + FIXME: This number is from the "ordinary" kernel memset. */ + if (n >= 48) + { + /* For large clears we use 'movem' */ + + /* It is not optimal to tell the compiler about clobbering any + call-saved registers; that will move the saving/restoring of + those registers to the function prologue/epilogue, and make + non-movem sizes suboptimal. + + This method is not foolproof; it assumes that the "asm reg" + declarations at the beginning of the function really are used + here (beware: they may be moved to temporary registers). + This way, we do not have to save/move the registers around into + temporaries; we can safely use them straight away. + + If you want to check that the allocation was right; then + check the equalities in the first comment. It should say + something like "r13=r13, r11=r11, r12=r12". */ + __asm__ volatile ("\ + .ifnc %0%1%2,$r13$r12$r10 \n\ + .err \n\ + .endif \n\ + \n\ + ;; Save the registers we'll clobber in the movem process \n\ + ;; on the stack. Don't mention them to gcc, it will only be \n\ + ;; upset. \n\ + subq 11*4,$sp \n\ + movem $r10,[$sp] \n\ + \n\ + clear.d $r0 \n\ + clear.d $r1 \n\ + clear.d $r2 \n\ + clear.d $r3 \n\ + clear.d $r4 \n\ + clear.d $r5 \n\ + clear.d $r6 \n\ + clear.d $r7 \n\ + clear.d $r8 \n\ + clear.d $r9 \n\ + clear.d $r10 \n\ + clear.d $r11 \n\ + \n\ + ;; Now we've got this: \n\ + ;; r13 - dst \n\ + ;; r12 - n \n\ + \n\ + ;; Update n for the first loop \n\ + subq 12*4,$r12 \n\ +0: \n\ + subq 12*4,$r12 \n\ +1: \n\ + bge 0b \n\ + movem $r11,[$r13+] \n\ + \n\ + addq 12*4,$r12 ;; compensate for last loop underflowing n \n\ + \n\ + ;; Restore registers from stack \n\ + movem [$sp+],$r10 \n\ +2: \n\ + .section .fixup,\"ax\" \n\ +3: \n\ + movem [$sp],$r10 \n\ + addq 12*4,$r10 \n\ + addq 12*4,$r13 \n\ + movem $r10,[$sp] \n\ + jump 0b \n\ + clear.d $r10 \n\ + \n\ + .previous \n\ + .section __ex_table,\"a\" \n\ + .dword 1b,3b \n\ + .previous" + + /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn) + /* Inputs */ : "0" (dst), "1" (n), "2" (retn) + /* Clobber */ : "r11"); + } + + while (n >= 16) + { + __asm_clear_16 (dst, retn); + n -= 16; + } + + /* Having a separate by-four loops cuts down on cache footprint. + FIXME: Test with and without; increasing switch to be 0..15. */ + while (n >= 4) + { + __asm_clear_4 (dst, retn); + n -= 4; + } + + switch (n) + { + case 0: + break; + case 1: + __asm_clear_1 (dst, retn); + break; + case 2: + __asm_clear_2 (dst, retn); + break; + case 3: + __asm_clear_3 (dst, retn); + break; + } + + return retn; +} +EXPORT_SYMBOL(__do_clear_user); diff --git a/kernel/arch/cris/arch-v32/mach-a3/Kconfig b/kernel/arch/cris/arch-v32/mach-a3/Kconfig new file mode 100644 index 000000000..87547271a --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-a3/Kconfig @@ -0,0 +1,110 @@ +if CRIS_MACH_ARTPEC3 + +menu "Artpec-3 options" + depends on CRIS_MACH_ARTPEC3 + +config ETRAX_DRAM_VIRTUAL_BASE + hex + default "c0000000" + +config ETRAX_L2CACHE + bool + default y + +config ETRAX_SERIAL_PORTS + int + default 5 + +config ETRAX_DDR2_MRS + hex "DDR2 MRS" + default "0" + +config ETRAX_DDR2_TIMING + hex "DDR2 SDRAM timing" + default "0" + help + SDRAM timing parameters. + +config ETRAX_DDR2_CONFIG + hex "DDR2 config" + default "0" + +config ETRAX_DDR2_LATENCY + hex "DDR2 latency" + default "0" + +config ETRAX_PIO_CE0_CFG + hex "PIO CE0 configuration" + default "0" + +config ETRAX_PIO_CE1_CFG + hex "PIO CE1 configuration" + default "0" + +config ETRAX_PIO_CE2_CFG + hex "PIO CE2 configuration" + default "0" + +config ETRAX_DEF_GIO_PA_OE + hex "GIO_PA_OE" + default "00000000" + help + Configures the direction of general port A bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PA_OUT + hex "GIO_PA_OUT" + default "00000000" + help + Configures the initial data for the general port A bits. Most + products should use 00 here. + +config ETRAX_DEF_GIO_PB_OE + hex "GIO_PB_OE" + default "000000000" + help + Configures the direction of general port B bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PB_OUT + hex "GIO_PB_OUT" + default "000000000" + help + Configures the initial data for the general port B bits. Most + products should use 00000 here. + +config ETRAX_DEF_GIO_PC_OE + hex "GIO_PC_OE" + default "00000" + help + Configures the direction of general port C bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PC_OUT + hex "GIO_PC_OUT" + default "00000" + help + Configures the initial data for the general port C bits. Most + products should use 00000 here. + +endmenu + +endif diff --git a/kernel/arch/cris/arch-v32/mach-a3/Makefile b/kernel/arch/cris/arch-v32/mach-a3/Makefile new file mode 100644 index 000000000..18a227196 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-a3/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := dma.o pinmux.o io.o arbiter.o + +clean: + diff --git a/kernel/arch/cris/arch-v32/mach-a3/arbiter.c b/kernel/arch/cris/arch-v32/mach-a3/arbiter.c new file mode 100644 index 000000000..ab5c421a4 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-a3/arbiter.c @@ -0,0 +1,634 @@ +/* + * Memory arbiter functions. Allocates bandwidth through the + * arbiter and sets up arbiter breakpoints. + * + * The algorithm first assigns slots to the clients that has specified + * bandwidth (e.g. ethernet) and then the remaining slots are divided + * on all the active clients. + * + * Copyright (c) 2004-2007 Axis Communications AB. + * + * The artpec-3 has two arbiters. The memory hierarchy looks like this: + * + * + * CPU DMAs + * | | + * | | + * -------------- ------------------ + * | foo arbiter|----| Internal memory| + * -------------- ------------------ + * | + * -------------- + * | L2 cache | + * -------------- + * | + * h264 etc | + * | | + * | | + * -------------- + * | bar arbiter| + * -------------- + * | + * --------- + * | SDRAM | + * --------- + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define D(x) + +struct crisv32_watch_entry { + unsigned long instance; + watch_callback *cb; + unsigned long start; + unsigned long end; + int used; +}; + +#define NUMBER_OF_BP 4 +#define SDRAM_BANDWIDTH 400000000 +#define INTMEM_BANDWIDTH 400000000 +#define NBR_OF_SLOTS 64 +#define NBR_OF_REGIONS 2 +#define NBR_OF_CLIENTS 15 +#define ARBITERS 2 +#define UNASSIGNED 100 + +struct arbiter { + unsigned long instance; + int nbr_regions; + int nbr_clients; + int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS]; + int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS]; +}; + +static struct crisv32_watch_entry watches[ARBITERS][NUMBER_OF_BP] = +{ + { + {regi_marb_foo_bp0}, + {regi_marb_foo_bp1}, + {regi_marb_foo_bp2}, + {regi_marb_foo_bp3} + }, + { + {regi_marb_bar_bp0}, + {regi_marb_bar_bp1}, + {regi_marb_bar_bp2}, + {regi_marb_bar_bp3} + } +}; + +struct arbiter arbiters[ARBITERS] = +{ + { /* L2 cache arbiter */ + .instance = regi_marb_foo, + .nbr_regions = 2, + .nbr_clients = 15 + }, + { /* DDR2 arbiter */ + .instance = regi_marb_bar, + .nbr_regions = 1, + .nbr_clients = 9 + } +}; + +static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH}; + +DEFINE_SPINLOCK(arbiter_lock); + +static irqreturn_t +crisv32_foo_arbiter_irq(int irq, void *dev_id); +static irqreturn_t +crisv32_bar_arbiter_irq(int irq, void *dev_id); + +/* + * "I'm the arbiter, I know the score. + * From square one I'll be watching all 64." + * (memory arbiter slots, that is) + * + * Or in other words: + * Program the memory arbiter slots for "region" according to what's + * in requested_slots[] and active_clients[], while minimizing + * latency. A caller may pass a non-zero positive amount for + * "unused_slots", which must then be the unallocated, remaining + * number of slots, free to hand out to any client. + */ + +static void crisv32_arbiter_config(int arbiter, int region, int unused_slots) +{ + int slot; + int client; + int interval = 0; + + /* + * This vector corresponds to the hardware arbiter slots (see + * the hardware documentation for semantics). We initialize + * each slot with a suitable sentinel value outside the valid + * range {0 .. NBR_OF_CLIENTS - 1} and replace them with + * client indexes. Then it's fed to the hardware. + */ + s8 val[NBR_OF_SLOTS]; + + for (slot = 0; slot < NBR_OF_SLOTS; slot++) + val[slot] = -1; + + for (client = 0; client < arbiters[arbiter].nbr_clients; client++) { + int pos; + /* Allocate the requested non-zero number of slots, but + * also give clients with zero-requests one slot each + * while stocks last. We do the latter here, in client + * order. This makes sure zero-request clients are the + * first to get to any spare slots, else those slots + * could, when bandwidth is allocated close to the limit, + * all be allocated to low-index non-zero-request clients + * in the default-fill loop below. Another positive but + * secondary effect is a somewhat better spread of the + * zero-bandwidth clients in the vector, avoiding some of + * the latency that could otherwise be caused by the + * partitioning of non-zero-bandwidth clients at low + * indexes and zero-bandwidth clients at high + * indexes. (Note that this spreading can only affect the + * unallocated bandwidth.) All the above only matters for + * memory-intensive situations, of course. + */ + if (!arbiters[arbiter].requested_slots[region][client]) { + /* + * Skip inactive clients. Also skip zero-slot + * allocations in this pass when there are no known + * free slots. + */ + if (!arbiters[arbiter].active_clients[region][client] || + unused_slots <= 0) + continue; + + unused_slots--; + + /* Only allocate one slot for this client. */ + interval = NBR_OF_SLOTS; + } else + interval = NBR_OF_SLOTS / + arbiters[arbiter].requested_slots[region][client]; + + pos = 0; + while (pos < NBR_OF_SLOTS) { + if (val[pos] >= 0) + pos++; + else { + val[pos] = client; + pos += interval; + } + } + } + + client = 0; + for (slot = 0; slot < NBR_OF_SLOTS; slot++) { + /* + * Allocate remaining slots in round-robin + * client-number order for active clients. For this + * pass, we ignore requested bandwidth and previous + * allocations. + */ + if (val[slot] < 0) { + int first = client; + while (!arbiters[arbiter].active_clients[region][client]) { + client = (client + 1) % + arbiters[arbiter].nbr_clients; + if (client == first) + break; + } + val[slot] = client; + client = (client + 1) % arbiters[arbiter].nbr_clients; + } + if (arbiter == 0) { + if (region == EXT_REGION) + REG_WR_INT_VECT(marb_foo, regi_marb_foo, + rw_l2_slots, slot, val[slot]); + else if (region == INT_REGION) + REG_WR_INT_VECT(marb_foo, regi_marb_foo, + rw_intm_slots, slot, val[slot]); + } else { + REG_WR_INT_VECT(marb_bar, regi_marb_bar, + rw_ddr2_slots, slot, val[slot]); + } + } +} + +extern char _stext, _etext; + +static void crisv32_arbiter_init(void) +{ + static int initialized; + + if (initialized) + return; + + initialized = 1; + + /* + * CPU caches are always set to active, but with zero + * bandwidth allocated. It should be ok to allocate zero + * bandwidth for the caches, because DMA for other channels + * will supposedly finish, once their programmed amount is + * done, and then the caches will get access according to the + * "fixed scheme" for unclaimed slots. Though, if for some + * use-case somewhere, there's a maximum CPU latency for + * e.g. some interrupt, we have to start allocating specific + * bandwidth for the CPU caches too. + */ + arbiters[0].active_clients[EXT_REGION][11] = 1; + arbiters[0].active_clients[EXT_REGION][12] = 1; + crisv32_arbiter_config(0, EXT_REGION, 0); + crisv32_arbiter_config(0, INT_REGION, 0); + crisv32_arbiter_config(1, EXT_REGION, 0); + + if (request_irq(MEMARB_FOO_INTR_VECT, crisv32_foo_arbiter_irq, + 0, "arbiter", NULL)) + printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); + + if (request_irq(MEMARB_BAR_INTR_VECT, crisv32_bar_arbiter_irq, + 0, "arbiter", NULL)) + printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); + +#ifndef CONFIG_ETRAX_KGDB + /* Global watch for writes to kernel text segment. */ + crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext, + MARB_CLIENTS(arbiter_all_clients, arbiter_bar_all_clients), + arbiter_all_write, NULL); +#endif + + /* Set up max burst sizes by default */ + REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_rd_burst, 3); + REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_wr_burst, 3); + REG_WR_INT(marb_bar, regi_marb_bar, rw_ccd_burst, 3); + REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_wr_burst, 3); + REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_rd_burst, 3); + REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_rd_burst, 3); + REG_WR_INT(marb_bar, regi_marb_bar, rw_vout_burst, 3); + REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_fifo_burst, 3); + REG_WR_INT(marb_bar, regi_marb_bar, rw_l2cache_burst, 3); +} + +int crisv32_arbiter_allocate_bandwidth(int client, int region, + unsigned long bandwidth) +{ + int i; + int total_assigned = 0; + int total_clients = 0; + int req; + int arbiter = 0; + + crisv32_arbiter_init(); + + if (client & 0xffff0000) { + arbiter = 1; + client >>= 16; + } + + for (i = 0; i < arbiters[arbiter].nbr_clients; i++) { + total_assigned += arbiters[arbiter].requested_slots[region][i]; + total_clients += arbiters[arbiter].active_clients[region][i]; + } + + /* Avoid division by 0 for 0-bandwidth requests. */ + req = bandwidth == 0 + ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth); + + /* + * We make sure that there are enough slots only for non-zero + * requests. Requesting 0 bandwidth *may* allocate slots, + * though if all bandwidth is allocated, such a client won't + * get any and will have to rely on getting memory access + * according to the fixed scheme that's the default when one + * of the slot-allocated clients doesn't claim their slot. + */ + if (total_assigned + req > NBR_OF_SLOTS) + return -ENOMEM; + + arbiters[arbiter].active_clients[region][client] = 1; + arbiters[arbiter].requested_slots[region][client] = req; + crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned); + + /* Propagate allocation from foo to bar */ + if (arbiter == 0) + crisv32_arbiter_allocate_bandwidth(8 << 16, + EXT_REGION, bandwidth); + return 0; +} + +/* + * Main entry for bandwidth deallocation. + * + * Strictly speaking, for a somewhat constant set of clients where + * each client gets a constant bandwidth and is just enabled or + * disabled (somewhat dynamically), no action is necessary here to + * avoid starvation for non-zero-allocation clients, as the allocated + * slots will just be unused. However, handing out those unused slots + * to active clients avoids needless latency if the "fixed scheme" + * would give unclaimed slots to an eager low-index client. + */ + +void crisv32_arbiter_deallocate_bandwidth(int client, int region) +{ + int i; + int total_assigned = 0; + int arbiter = 0; + + if (client & 0xffff0000) + arbiter = 1; + + arbiters[arbiter].requested_slots[region][client] = 0; + arbiters[arbiter].active_clients[region][client] = 0; + + for (i = 0; i < arbiters[arbiter].nbr_clients; i++) + total_assigned += arbiters[arbiter].requested_slots[region][i]; + + crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned); +} + +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback *cb) +{ + int i; + int arbiter; + int used[2]; + int ret = 0; + + crisv32_arbiter_init(); + + if (start > 0x80000000) { + printk(KERN_ERR "Arbiter: %lX doesn't look like a " + "physical address", start); + return -EFAULT; + } + + spin_lock(&arbiter_lock); + + if (clients & 0xffff) + used[0] = 1; + if (clients & 0xffff0000) + used[1] = 1; + + for (arbiter = 0; arbiter < ARBITERS; arbiter++) { + if (!used[arbiter]) + continue; + + for (i = 0; i < NUMBER_OF_BP; i++) { + if (!watches[arbiter][i].used) { + unsigned intr_mask; + if (arbiter) + intr_mask = REG_RD_INT(marb_bar, + regi_marb_bar, rw_intr_mask); + else + intr_mask = REG_RD_INT(marb_foo, + regi_marb_foo, rw_intr_mask); + + watches[arbiter][i].used = 1; + watches[arbiter][i].start = start; + watches[arbiter][i].end = start + size; + watches[arbiter][i].cb = cb; + + ret |= (i + 1) << (arbiter + 8); + if (arbiter) { + REG_WR_INT(marb_bar_bp, + watches[arbiter][i].instance, + rw_first_addr, + watches[arbiter][i].start); + REG_WR_INT(marb_bar_bp, + watches[arbiter][i].instance, + rw_last_addr, + watches[arbiter][i].end); + REG_WR_INT(marb_bar_bp, + watches[arbiter][i].instance, + rw_op, accesses); + REG_WR_INT(marb_bar_bp, + watches[arbiter][i].instance, + rw_clients, + clients & 0xffff); + } else { + REG_WR_INT(marb_foo_bp, + watches[arbiter][i].instance, + rw_first_addr, + watches[arbiter][i].start); + REG_WR_INT(marb_foo_bp, + watches[arbiter][i].instance, + rw_last_addr, + watches[arbiter][i].end); + REG_WR_INT(marb_foo_bp, + watches[arbiter][i].instance, + rw_op, accesses); + REG_WR_INT(marb_foo_bp, + watches[arbiter][i].instance, + rw_clients, clients >> 16); + } + + if (i == 0) + intr_mask |= 1; + else if (i == 1) + intr_mask |= 2; + else if (i == 2) + intr_mask |= 4; + else if (i == 3) + intr_mask |= 8; + + if (arbiter) + REG_WR_INT(marb_bar, regi_marb_bar, + rw_intr_mask, intr_mask); + else + REG_WR_INT(marb_foo, regi_marb_foo, + rw_intr_mask, intr_mask); + + spin_unlock(&arbiter_lock); + + break; + } + } + } + spin_unlock(&arbiter_lock); + if (ret) + return ret; + else + return -ENOMEM; +} + +int crisv32_arbiter_unwatch(int id) +{ + int arbiter; + int intr_mask; + + crisv32_arbiter_init(); + + spin_lock(&arbiter_lock); + + for (arbiter = 0; arbiter < ARBITERS; arbiter++) { + int id2; + + if (arbiter) + intr_mask = REG_RD_INT(marb_bar, regi_marb_bar, + rw_intr_mask); + else + intr_mask = REG_RD_INT(marb_foo, regi_marb_foo, + rw_intr_mask); + + id2 = (id & (0xff << (arbiter + 8))) >> (arbiter + 8); + if (id2 == 0) + continue; + id2--; + if ((id2 >= NUMBER_OF_BP) || (!watches[arbiter][id2].used)) { + spin_unlock(&arbiter_lock); + return -EINVAL; + } + + memset(&watches[arbiter][id2], 0, + sizeof(struct crisv32_watch_entry)); + + if (id2 == 0) + intr_mask &= ~1; + else if (id2 == 1) + intr_mask &= ~2; + else if (id2 == 2) + intr_mask &= ~4; + else if (id2 == 3) + intr_mask &= ~8; + + if (arbiter) + REG_WR_INT(marb_bar, regi_marb_bar, rw_intr_mask, + intr_mask); + else + REG_WR_INT(marb_foo, regi_marb_foo, rw_intr_mask, + intr_mask); + } + + spin_unlock(&arbiter_lock); + return 0; +} + +extern void show_registers(struct pt_regs *regs); + + +static irqreturn_t +crisv32_foo_arbiter_irq(int irq, void *dev_id) +{ + reg_marb_foo_r_masked_intr masked_intr = + REG_RD(marb_foo, regi_marb_foo, r_masked_intr); + reg_marb_foo_bp_r_brk_clients r_clients; + reg_marb_foo_bp_r_brk_addr r_addr; + reg_marb_foo_bp_r_brk_op r_op; + reg_marb_foo_bp_r_brk_first_client r_first; + reg_marb_foo_bp_r_brk_size r_size; + reg_marb_foo_bp_rw_ack ack = {0}; + reg_marb_foo_rw_ack_intr ack_intr = { + .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1 + }; + struct crisv32_watch_entry *watch; + unsigned arbiter = (unsigned)dev_id; + + masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr); + + if (masked_intr.bp0) + watch = &watches[arbiter][0]; + else if (masked_intr.bp1) + watch = &watches[arbiter][1]; + else if (masked_intr.bp2) + watch = &watches[arbiter][2]; + else if (masked_intr.bp3) + watch = &watches[arbiter][3]; + else + return IRQ_NONE; + + /* Retrieve all useful information and print it. */ + r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients); + r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr); + r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op); + r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client); + r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size); + + printk(KERN_DEBUG "Arbiter IRQ\n"); + printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n", + REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_clients, r_clients), + REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_addr, r_addr), + REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_op, r_op), + REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_first_client, r_first), + REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_size, r_size)); + + REG_WR(marb_foo_bp, watch->instance, rw_ack, ack); + REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr); + + printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()); + + if (watch->cb) + watch->cb(); + + return IRQ_HANDLED; +} + +static irqreturn_t +crisv32_bar_arbiter_irq(int irq, void *dev_id) +{ + reg_marb_bar_r_masked_intr masked_intr = + REG_RD(marb_bar, regi_marb_bar, r_masked_intr); + reg_marb_bar_bp_r_brk_clients r_clients; + reg_marb_bar_bp_r_brk_addr r_addr; + reg_marb_bar_bp_r_brk_op r_op; + reg_marb_bar_bp_r_brk_first_client r_first; + reg_marb_bar_bp_r_brk_size r_size; + reg_marb_bar_bp_rw_ack ack = {0}; + reg_marb_bar_rw_ack_intr ack_intr = { + .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1 + }; + struct crisv32_watch_entry *watch; + unsigned arbiter = (unsigned)dev_id; + + masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr); + + if (masked_intr.bp0) + watch = &watches[arbiter][0]; + else if (masked_intr.bp1) + watch = &watches[arbiter][1]; + else if (masked_intr.bp2) + watch = &watches[arbiter][2]; + else if (masked_intr.bp3) + watch = &watches[arbiter][3]; + else + return IRQ_NONE; + + /* Retrieve all useful information and print it. */ + r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients); + r_addr = REG_RD(marb_bar_bp, watch->instance, r_brk_addr); + r_op = REG_RD(marb_bar_bp, watch->instance, r_brk_op); + r_first = REG_RD(marb_bar_bp, watch->instance, r_brk_first_client); + r_size = REG_RD(marb_bar_bp, watch->instance, r_brk_size); + + printk(KERN_DEBUG "Arbiter IRQ\n"); + printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n", + REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_clients, r_clients), + REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_addr, r_addr), + REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_op, r_op), + REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_first_client, r_first), + REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_size, r_size)); + + REG_WR(marb_bar_bp, watch->instance, rw_ack, ack); + REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr); + + printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()->erp); + + if (watch->cb) + watch->cb(); + + return IRQ_HANDLED; +} + diff --git a/kernel/arch/cris/arch-v32/mach-a3/dma.c b/kernel/arch/cris/arch-v32/mach-a3/dma.c new file mode 100644 index 000000000..47c64bf40 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-a3/dma.c @@ -0,0 +1,184 @@ +/* Wrapper for DMA channel allocator that starts clocks etc */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static char used_dma_channels[MAX_DMA_CHANNELS]; +static const char *used_dma_channels_users[MAX_DMA_CHANNELS]; + +static DEFINE_SPINLOCK(dma_lock); + +int crisv32_request_dma(unsigned int dmanr, const char *device_id, + unsigned options, unsigned int bandwidth, enum dma_owner owner) +{ + unsigned long flags; + reg_clkgen_rw_clk_ctrl clk_ctrl; + reg_strmux_rw_cfg strmux_cfg; + + if (crisv32_arbiter_allocate_bandwidth(dmanr, + options & DMA_INT_MEM ? INT_REGION : EXT_REGION, + bandwidth)) + return -ENOMEM; + + spin_lock_irqsave(&dma_lock, flags); + + if (used_dma_channels[dmanr]) { + spin_unlock_irqrestore(&dma_lock, flags); + if (options & DMA_VERBOSE_ON_ERROR) + printk(KERN_ERR "Failed to request DMA %i for %s, " + "already allocated by %s\n", + dmanr, + device_id, + used_dma_channels_users[dmanr]); + + if (options & DMA_PANIC_ON_ERROR) + panic("request_dma error!"); + spin_unlock_irqrestore(&dma_lock, flags); + return -EBUSY; + } + clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); + strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); + + switch (dmanr) { + case 0: + case 1: + clk_ctrl.dma0_1_eth = 1; + break; + case 2: + case 3: + clk_ctrl.dma2_3_strcop = 1; + break; + case 4: + case 5: + clk_ctrl.dma4_5_iop = 1; + break; + case 6: + case 7: + clk_ctrl.sser_ser_dma6_7 = 1; + break; + case 9: + case 11: + clk_ctrl.dma9_11 = 1; + break; +#if MAX_DMA_CHANNELS-1 != 11 +#error Check dma.c +#endif + default: + spin_unlock_irqrestore(&dma_lock, flags); + if (options & DMA_VERBOSE_ON_ERROR) + printk(KERN_ERR "Failed to request DMA %i for %s, " + "only 0-%i valid)\n", + dmanr, device_id, MAX_DMA_CHANNELS-1); + + if (options & DMA_PANIC_ON_ERROR) + panic("request_dma error!"); + return -EINVAL; + } + + switch (owner) { + case dma_eth: + if (dmanr == 0) + strmux_cfg.dma0 = regk_strmux_eth; + else if (dmanr == 1) + strmux_cfg.dma1 = regk_strmux_eth; + else + panic("Invalid DMA channel for eth\n"); + break; + case dma_ser0: + if (dmanr == 0) + strmux_cfg.dma0 = regk_strmux_ser0; + else if (dmanr == 1) + strmux_cfg.dma1 = regk_strmux_ser0; + else + panic("Invalid DMA channel for ser0\n"); + break; + case dma_ser3: + if (dmanr == 2) + strmux_cfg.dma2 = regk_strmux_ser3; + else if (dmanr == 3) + strmux_cfg.dma3 = regk_strmux_ser3; + else + panic("Invalid DMA channel for ser3\n"); + break; + case dma_strp: + if (dmanr == 2) + strmux_cfg.dma2 = regk_strmux_strcop; + else if (dmanr == 3) + strmux_cfg.dma3 = regk_strmux_strcop; + else + panic("Invalid DMA channel for strp\n"); + break; + case dma_ser1: + if (dmanr == 4) + strmux_cfg.dma4 = regk_strmux_ser1; + else if (dmanr == 5) + strmux_cfg.dma5 = regk_strmux_ser1; + else + panic("Invalid DMA channel for ser1\n"); + break; + case dma_iop: + if (dmanr == 4) + strmux_cfg.dma4 = regk_strmux_iop; + else if (dmanr == 5) + strmux_cfg.dma5 = regk_strmux_iop; + else + panic("Invalid DMA channel for iop\n"); + break; + case dma_ser2: + if (dmanr == 6) + strmux_cfg.dma6 = regk_strmux_ser2; + else if (dmanr == 7) + strmux_cfg.dma7 = regk_strmux_ser2; + else + panic("Invalid DMA channel for ser2\n"); + break; + case dma_sser: + if (dmanr == 6) + strmux_cfg.dma6 = regk_strmux_sser; + else if (dmanr == 7) + strmux_cfg.dma7 = regk_strmux_sser; + else + panic("Invalid DMA channel for sser\n"); + break; + case dma_ser4: + if (dmanr == 9) + strmux_cfg.dma9 = regk_strmux_ser4; + else + panic("Invalid DMA channel for ser4\n"); + break; + case dma_jpeg: + if (dmanr == 9) + strmux_cfg.dma9 = regk_strmux_jpeg; + else + panic("Invalid DMA channel for JPEG\n"); + break; + case dma_h264: + if (dmanr == 11) + strmux_cfg.dma11 = regk_strmux_h264; + else + panic("Invalid DMA channel for H264\n"); + break; + } + + used_dma_channels[dmanr] = 1; + used_dma_channels_users[dmanr] = device_id; + REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); + REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); + spin_unlock_irqrestore(&dma_lock, flags); + return 0; +} + +void crisv32_free_dma(unsigned int dmanr) +{ + spin_lock(&dma_lock); + used_dma_channels[dmanr] = 0; + spin_unlock(&dma_lock); +} diff --git a/kernel/arch/cris/arch-v32/mach-a3/dram_init.S b/kernel/arch/cris/arch-v32/mach-a3/dram_init.S new file mode 100644 index 000000000..ec8648be3 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-a3/dram_init.S @@ -0,0 +1,118 @@ +/* + * DDR SDRAM initialization - alter with care + * This file is intended to be included from other assembler files + * + * Note: This file may not modify r8 or r9 because they are used to + * carry information from the decompresser to the kernel + * + * Copyright (C) 2005-2007 Axis Communications AB + * + * Authors: Mikael Starvik + */ + +/* Just to be certain the config file is included, we include it here + * explicitely instead of depending on it being included in the file that + * uses this code. + */ + +#include +#include + + ;; WARNING! The registers r8 and r9 are used as parameters carrying + ;; information from the decompressor (if the kernel was compressed). + ;; They should not be used in the code below. + + ;; Refer to ddr2 MDS for initialization sequence + + ; 2. Wait 200us + move.d 10000, $r2 +1: bne 1b + subq 1, $r2 + + ; Start clock + move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0 + move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1 + move.d $r1, [$r0] + + ; 2. Wait 200us + move.d 10000, $r2 +1: bne 1b + subq 1, $r2 + + ; Reset phy and start calibration + move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0 + move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \ + REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1 + move.d $r1, [$r0] + move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1 + move.d $r1, [$r0] + + ; 2. Wait 200us + move.d 10000, $r2 +1: bne 1b + subq 1, $r2 + + ; Issue commands + move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0 + move.d sdram_commands_start, $r2 +command_loop: + movu.b [$r2+], $r1 + movu.w [$r2+], $r3 +do_cmd: + lslq 16, $r1 + or.d $r3, $r1 + move.d $r1, [$r0] + ; 2. Wait 200us + move.d 10000, $r4 +1: bne 1b + subq 1, $r4 + cmp.d sdram_commands_end, $r2 + blo command_loop + nop + + ; Set timing + move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0 + move.d CONFIG_ETRAX_DDR2_TIMING, $r1 + move.d $r1, [$r0] + + ; Set latency + move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0 + move.d CONFIG_ETRAX_DDR2_LATENCY, $r1 + move.d $r1, [$r0] + + ; Set configuration + move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0 + move.d CONFIG_ETRAX_DDR2_CONFIG, $r1 + move.d $r1, [$r0] + + ba after_sdram_commands + nop + +sdram_commands_start: + .byte regk_ddr2_deselect + .word 0 + .byte regk_ddr2_pre + .word regk_ddr2_pre_all + .byte regk_ddr2_emrs2 + .word 0 + .byte regk_ddr2_emrs3 + .word 0 + .byte regk_ddr2_emrs + .word regk_ddr2_dll_en + .byte regk_ddr2_mrs + .word regk_ddr2_dll_rst + .byte regk_ddr2_pre + .word regk_ddr2_pre_all + .byte regk_ddr2_ref + .word 0 + .byte regk_ddr2_ref + .word 0 + .byte regk_ddr2_mrs + .word CONFIG_ETRAX_DDR2_MRS & 0xffff + .byte regk_ddr2_emrs + .word regk_ddr2_ocd_default | regk_ddr2_dll_en + .byte regk_ddr2_emrs + .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16) +sdram_commands_end: + .align 1 +after_sdram_commands: diff --git a/kernel/arch/cris/arch-v32/mach-a3/hw_settings.S b/kernel/arch/cris/arch-v32/mach-a3/hw_settings.S new file mode 100644 index 000000000..0145725a1 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-a3/hw_settings.S @@ -0,0 +1,53 @@ +/* + * This table is used by some tools to extract hardware parameters. + * The table should be included in the kernel and the decompressor. + * Don't forget to update the tools if you change this table. + * + * Copyright (C) 2001-2007 Axis Communications AB + * + * Authors: Mikael Starvik + */ + +#include +#include +#include + + .ascii "HW_PARAM_MAGIC" ; Magic number + .dword 0xc0004000 ; Kernel start address + + ; Debug port +#ifdef CONFIG_ETRAX_DEBUG_PORT0 + .dword 0 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1) + .dword 1 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2) + .dword 2 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3) + .dword 3 +#else + .dword 4 ; No debug +#endif + + ; Register values + .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg) + .dword CONFIG_ETRAX_DDR2_CONFIG + .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency) + .dword CONFIG_ETRAX_DDR2_LATENCY + .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing) + .dword CONFIG_ETRAX_DDR2_TIMING + .dword CONFIG_ETRAX_DDR2_MRS + + .dword REG_ADDR(gio, regi_gio, rw_pa_dout) + .dword CONFIG_ETRAX_DEF_GIO_PA_OUT + .dword REG_ADDR(gio, regi_gio, rw_pa_oe) + .dword CONFIG_ETRAX_DEF_GIO_PA_OE + .dword REG_ADDR(gio, regi_gio, rw_pb_dout) + .dword CONFIG_ETRAX_DEF_GIO_PB_OUT + .dword REG_ADDR(gio, regi_gio, rw_pb_oe) + .dword CONFIG_ETRAX_DEF_GIO_PB_OE + .dword REG_ADDR(gio, regi_gio, rw_pc_dout) + .dword CONFIG_ETRAX_DEF_GIO_PC_OUT + .dword REG_ADDR(gio, regi_gio, rw_pc_oe) + .dword CONFIG_ETRAX_DEF_GIO_PC_OE + + .dword 0 ; No more register values diff --git a/kernel/arch/cris/arch-v32/mach-a3/io.c b/kernel/arch/cris/arch-v32/mach-a3/io.c new file mode 100644 index 000000000..090ceb99e --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-a3/io.c @@ -0,0 +1,149 @@ +/* + * Helper functions for I/O pins. + * + * Copyright (c) 2005-2007 Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct crisv32_ioport crisv32_ioports[] = { + { + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe), + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout), + (unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din), + 32 + }, + { + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe), + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout), + (unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din), + 32 + }, + { + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe), + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout), + (unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din), + 16 + }, +}; + +#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports) + +struct crisv32_iopin crisv32_led_net0_green; +struct crisv32_iopin crisv32_led_net0_red; +struct crisv32_iopin crisv32_led2_green; +struct crisv32_iopin crisv32_led2_red; +struct crisv32_iopin crisv32_led3_green; +struct crisv32_iopin crisv32_led3_red; + +/* Dummy port used when green LED and red LED is on the same bit */ +static unsigned long io_dummy; +static struct crisv32_ioport dummy_port = { + &io_dummy, + &io_dummy, + &io_dummy, + 32 +}; +static struct crisv32_iopin dummy_led = { + &dummy_port, + 0 +}; + +static int __init crisv32_io_init(void) +{ + int ret = 0; + + u32 i; + + /* Locks *should* be dynamically initialized. */ + for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++) + spin_lock_init(&crisv32_ioports[i].lock); + spin_lock_init(&dummy_port.lock); + + /* Initialize LEDs */ +#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) + ret += crisv32_io_get_name(&crisv32_led_net0_green, + CONFIG_ETRAX_LED_G_NET0); + crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out); + if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) { + ret += crisv32_io_get_name(&crisv32_led_net0_red, + CONFIG_ETRAX_LED_R_NET0); + crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out); + } else + crisv32_led_net0_red = dummy_led; +#endif + + ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G); + ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R); + ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G); + ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R); + + crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out); + crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out); + crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out); + crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out); + + return ret; +} + +__initcall(crisv32_io_init); + +int crisv32_io_get(struct crisv32_iopin *iopin, + unsigned int port, unsigned int pin) +{ + if (port > NBR_OF_PORTS) + return -EINVAL; + if (port > crisv32_ioports[port].pin_count) + return -EINVAL; + + iopin->bit = 1 << pin; + iopin->port = &crisv32_ioports[port]; + + if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio)) + return -EIO; + + return 0; +} + +int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name) +{ + int port; + int pin; + + if (toupper(*name) == 'P') + name++; + + if (toupper(*name) < 'A' || toupper(*name) > 'E') + return -EINVAL; + + port = toupper(*name) - 'A'; + name++; + pin = simple_strtoul(name, NULL, 10); + + if (pin < 0 || pin > crisv32_ioports[port].pin_count) + return -EINVAL; + + iopin->bit = 1 << pin; + iopin->port = &crisv32_ioports[port]; + + if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio)) + return -EIO; + + return 0; +} + +#ifdef CONFIG_PCI +/* PCI I/O access stuff */ +struct cris_io_operations *cris_iops = NULL; +EXPORT_SYMBOL(cris_iops); +#endif + diff --git a/kernel/arch/cris/arch-v32/mach-a3/pinmux.c b/kernel/arch/cris/arch-v32/mach-a3/pinmux.c new file mode 100644 index 000000000..591f77526 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-a3/pinmux.c @@ -0,0 +1,388 @@ +/* + * Allocator for I/O pins. All pins are allocated to GPIO at bootup. + * Unassigned pins and GPIO pins can be allocated to a fixed interface + * or the I/O processor instead. + * + * Copyright (c) 2005-2007 Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#undef DEBUG + +#define PINS 80 +#define PORT_PINS 32 +#define PORTS 3 + +static char pins[PINS]; +static DEFINE_SPINLOCK(pinmux_lock); + +static void crisv32_pinmux_set(int port); + +int +crisv32_pinmux_init(void) +{ + static int initialized; + + if (!initialized) { + initialized = 1; + REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); + crisv32_pinmux_alloc(PORT_A, 0, 31, pinmux_gpio); + crisv32_pinmux_alloc(PORT_B, 0, 31, pinmux_gpio); + crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_gpio); + } + + return 0; +} + +int +crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode) +{ + int i; + unsigned long flags; + + crisv32_pinmux_init(); + + if (port >= PORTS) + return -EINVAL; + + spin_lock_irqsave(&pinmux_lock, flags); + + for (i = first_pin; i <= last_pin; i++) { + if ((pins[port * PORT_PINS + i] != pinmux_none) && + (pins[port * PORT_PINS + i] != pinmux_gpio) && + (pins[port * PORT_PINS + i] != mode)) { + spin_unlock_irqrestore(&pinmux_lock, flags); +#ifdef DEBUG + panic("Pinmux alloc failed!\n"); +#endif + return -EPERM; + } + } + + for (i = first_pin; i <= last_pin; i++) + pins[port * PORT_PINS + i] = mode; + + crisv32_pinmux_set(port); + + spin_unlock_irqrestore(&pinmux_lock, flags); + + return 0; +} + +int +crisv32_pinmux_alloc_fixed(enum fixed_function function) +{ + int ret = -EINVAL; + char saved[sizeof pins]; + unsigned long flags; + reg_pinmux_rw_hwprot hwprot; + reg_clkgen_rw_clk_ctrl clk_ctrl; + + spin_lock_irqsave(&pinmux_lock, flags); + + /* Save internal data for recovery */ + memcpy(saved, pins, sizeof pins); + + crisv32_pinmux_init(); /* must be done before we read rw_hwprot */ + + hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); + clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); + + switch (function) { + case pinmux_eth: + clk_ctrl.eth = regk_clkgen_yes; + clk_ctrl.dma0_1_eth = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_B, 8, 23, pinmux_fixed); + ret |= crisv32_pinmux_alloc(PORT_B, 24, 25, pinmux_fixed); + hwprot.eth = hwprot.eth_mdio = regk_pinmux_yes; + break; + case pinmux_geth: + ret = crisv32_pinmux_alloc(PORT_B, 0, 7, pinmux_fixed); + hwprot.geth = regk_pinmux_yes; + break; + case pinmux_tg_cmos: + clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_B, 27, 29, pinmux_fixed); + hwprot.tg_clk = regk_pinmux_yes; + break; + case pinmux_tg_ccd: + clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_B, 27, 31, pinmux_fixed); + ret |= crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_fixed); + hwprot.tg = hwprot.tg_clk = regk_pinmux_yes; + break; + case pinmux_vout: + clk_ctrl.strdma0_2_video = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_A, 8, 18, pinmux_fixed); + hwprot.vout = hwprot.vout_sync = regk_pinmux_yes; + break; + case pinmux_ser1: + clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_A, 24, 25, pinmux_fixed); + hwprot.ser1 = regk_pinmux_yes; + break; + case pinmux_ser2: + clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_A, 26, 27, pinmux_fixed); + hwprot.ser2 = regk_pinmux_yes; + break; + case pinmux_ser3: + clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_A, 28, 29, pinmux_fixed); + hwprot.ser3 = regk_pinmux_yes; + break; + case pinmux_ser4: + clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_A, 30, 31, pinmux_fixed); + hwprot.ser4 = regk_pinmux_yes; + break; + case pinmux_sser: + clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; + ret = crisv32_pinmux_alloc(PORT_A, 19, 23, pinmux_fixed); + hwprot.sser = regk_pinmux_yes; + break; + case pinmux_pio: + hwprot.pio = regk_pinmux_yes; + ret = 0; + break; + case pinmux_pwm0: + ret = crisv32_pinmux_alloc(PORT_A, 30, 30, pinmux_fixed); + hwprot.pwm0 = regk_pinmux_yes; + break; + case pinmux_pwm1: + ret = crisv32_pinmux_alloc(PORT_A, 31, 31, pinmux_fixed); + hwprot.pwm1 = regk_pinmux_yes; + break; + case pinmux_pwm2: + ret = crisv32_pinmux_alloc(PORT_B, 26, 26, pinmux_fixed); + hwprot.pwm2 = regk_pinmux_yes; + break; + case pinmux_i2c0: + ret = crisv32_pinmux_alloc(PORT_A, 0, 1, pinmux_fixed); + hwprot.i2c0 = regk_pinmux_yes; + break; + case pinmux_i2c1: + ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); + hwprot.i2c1 = regk_pinmux_yes; + break; + case pinmux_i2c1_3wire: + ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); + ret |= crisv32_pinmux_alloc(PORT_A, 7, 7, pinmux_fixed); + hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_yes; + break; + case pinmux_i2c1_sda1: + ret = crisv32_pinmux_alloc(PORT_A, 2, 4, pinmux_fixed); + hwprot.i2c1 = hwprot.i2c1_sda1 = regk_pinmux_yes; + break; + case pinmux_i2c1_sda2: + ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); + ret |= crisv32_pinmux_alloc(PORT_A, 5, 5, pinmux_fixed); + hwprot.i2c1 = hwprot.i2c1_sda2 = regk_pinmux_yes; + break; + case pinmux_i2c1_sda3: + ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); + ret |= crisv32_pinmux_alloc(PORT_A, 6, 6, pinmux_fixed); + hwprot.i2c1 = hwprot.i2c1_sda3 = regk_pinmux_yes; + break; + default: + ret = -EINVAL; + break; + } + + if (!ret) { + REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); + REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); + } else + memcpy(pins, saved, sizeof pins); + + spin_unlock_irqrestore(&pinmux_lock, flags); + + return ret; +} + +void +crisv32_pinmux_set(int port) +{ + int i; + int gpio_val = 0; + int iop_val = 0; + int pin = port * PORT_PINS; + + for (i = 0; (i < PORT_PINS) && (pin < PINS); i++, pin++) { + if (pins[pin] == pinmux_gpio) + gpio_val |= (1 << i); + else if (pins[pin] == pinmux_iop) + iop_val |= (1 << i); + } + + REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port, + gpio_val); + REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port, + iop_val); + +#ifdef DEBUG + crisv32_pinmux_dump(); +#endif +} + +int +crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) +{ + int i; + unsigned long flags; + + crisv32_pinmux_init(); + + if (port > PORTS || port < 0) + return -EINVAL; + + spin_lock_irqsave(&pinmux_lock, flags); + + for (i = first_pin; i <= last_pin; i++) + pins[port * PORT_PINS + i] = pinmux_none; + + crisv32_pinmux_set(port); + spin_unlock_irqrestore(&pinmux_lock, flags); + + return 0; +} + +int +crisv32_pinmux_dealloc_fixed(enum fixed_function function) +{ + int ret = -EINVAL; + char saved[sizeof pins]; + unsigned long flags; + reg_pinmux_rw_hwprot hwprot; + + spin_lock_irqsave(&pinmux_lock, flags); + + /* Save internal data for recovery */ + memcpy(saved, pins, sizeof pins); + + crisv32_pinmux_init(); /* must be done before we read rw_hwprot */ + + hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); + + switch (function) { + case pinmux_eth: + ret = crisv32_pinmux_dealloc(PORT_B, 8, 23); + ret |= crisv32_pinmux_dealloc(PORT_B, 24, 25); + ret |= crisv32_pinmux_dealloc(PORT_B, 0, 7); + hwprot.eth = hwprot.eth_mdio = hwprot.geth = regk_pinmux_no; + break; + case pinmux_tg_cmos: + ret = crisv32_pinmux_dealloc(PORT_B, 27, 29); + hwprot.tg_clk = regk_pinmux_no; + break; + case pinmux_tg_ccd: + ret = crisv32_pinmux_dealloc(PORT_B, 27, 31); + ret |= crisv32_pinmux_dealloc(PORT_C, 0, 15); + hwprot.tg = hwprot.tg_clk = regk_pinmux_no; + break; + case pinmux_vout: + ret = crisv32_pinmux_dealloc(PORT_A, 8, 18); + hwprot.vout = hwprot.vout_sync = regk_pinmux_no; + break; + case pinmux_ser1: + ret = crisv32_pinmux_dealloc(PORT_A, 24, 25); + hwprot.ser1 = regk_pinmux_no; + break; + case pinmux_ser2: + ret = crisv32_pinmux_dealloc(PORT_A, 26, 27); + hwprot.ser2 = regk_pinmux_no; + break; + case pinmux_ser3: + ret = crisv32_pinmux_dealloc(PORT_A, 28, 29); + hwprot.ser3 = regk_pinmux_no; + break; + case pinmux_ser4: + ret = crisv32_pinmux_dealloc(PORT_A, 30, 31); + hwprot.ser4 = regk_pinmux_no; + break; + case pinmux_sser: + ret = crisv32_pinmux_dealloc(PORT_A, 19, 23); + hwprot.sser = regk_pinmux_no; + break; + case pinmux_pwm0: + ret = crisv32_pinmux_dealloc(PORT_A, 30, 30); + hwprot.pwm0 = regk_pinmux_no; + break; + case pinmux_pwm1: + ret = crisv32_pinmux_dealloc(PORT_A, 31, 31); + hwprot.pwm1 = regk_pinmux_no; + break; + case pinmux_pwm2: + ret = crisv32_pinmux_dealloc(PORT_B, 26, 26); + hwprot.pwm2 = regk_pinmux_no; + break; + case pinmux_i2c0: + ret = crisv32_pinmux_dealloc(PORT_A, 0, 1); + hwprot.i2c0 = regk_pinmux_no; + break; + case pinmux_i2c1: + ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); + hwprot.i2c1 = regk_pinmux_no; + break; + case pinmux_i2c1_3wire: + ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); + ret |= crisv32_pinmux_dealloc(PORT_A, 7, 7); + hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_no; + break; + case pinmux_i2c1_sda1: + ret = crisv32_pinmux_dealloc(PORT_A, 2, 4); + hwprot.i2c1_sda1 = regk_pinmux_no; + break; + case pinmux_i2c1_sda2: + ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); + ret |= crisv32_pinmux_dealloc(PORT_A, 5, 5); + hwprot.i2c1_sda2 = regk_pinmux_no; + break; + case pinmux_i2c1_sda3: + ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); + ret |= crisv32_pinmux_dealloc(PORT_A, 6, 6); + hwprot.i2c1_sda3 = regk_pinmux_no; + break; + default: + ret = -EINVAL; + break; + } + + if (!ret) + REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); + else + memcpy(pins, saved, sizeof pins); + + spin_unlock_irqrestore(&pinmux_lock, flags); + + return ret; +} + +void +crisv32_pinmux_dump(void) +{ + int i, j; + int pin = 0; + + crisv32_pinmux_init(); + + for (i = 0; i < PORTS; i++) { + pin++; + printk(KERN_DEBUG "Port %c\n", 'A'+i); + for (j = 0; (j < PORT_PINS) && (pin < PINS); j++, pin++) + printk(KERN_DEBUG + " Pin %d = %d\n", j, pins[i * PORT_PINS + j]); + } +} + +__initcall(crisv32_pinmux_init); diff --git a/kernel/arch/cris/arch-v32/mach-fs/Kconfig b/kernel/arch/cris/arch-v32/mach-fs/Kconfig new file mode 100644 index 000000000..774de82ab --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-fs/Kconfig @@ -0,0 +1,216 @@ +if ETRAXFS + +menu "ETRAX FS options" + depends on ETRAXFS + +config ETRAX_DRAM_VIRTUAL_BASE + hex + depends on ETRAX_ARCH_V32 + default "c0000000" + +config ETRAX_SERIAL_PORTS + int + default 4 + +config ETRAX_MEM_GRP1_CONFIG + hex "MEM_GRP1_CONFIG" + depends on ETRAX_ARCH_V32 + default "4044a" + help + Waitstates for flash. The default value is suitable for the + standard flashes used in axis products (120 ns). + +config ETRAX_MEM_GRP2_CONFIG + hex "MEM_GRP2_CONFIG" + depends on ETRAX_ARCH_V32 + default "0" + help + Waitstates for SRAM. 0 is a good choice for most Axis products. + +config ETRAX_MEM_GRP3_CONFIG + hex "MEM_GRP3_CONFIG" + depends on ETRAX_ARCH_V32 + default "0" + help + Waitstates for CSP0-3. 0 is a good choice for most Axis products. + It may need to be changed if external devices such as extra + register-mapped LEDs are used. + +config ETRAX_MEM_GRP4_CONFIG + hex "MEM_GRP4_CONFIG" + depends on ETRAX_ARCH_V32 + default "0" + help + Waitstates for CSP4-6. 0 is a good choice for most Axis products. + +config ETRAX_SDRAM_GRP0_CONFIG + hex "SDRAM_GRP0_CONFIG" + depends on ETRAX_ARCH_V32 + default "336" + help + SDRAM configuration for group 0. The value depends on the + hardware configuration. The default value is suitable + for 32 MB organized as two 16 bits chips (e.g. Axis + part number 18550) connected as one 32 bit device (i.e. in + the same group). + +config ETRAX_SDRAM_GRP1_CONFIG + hex "SDRAM_GRP1_CONFIG" + depends on ETRAX_ARCH_V32 + default "0" + help + SDRAM configuration for group 1. The default value is 0 + because group 1 is not used in the default configuration, + described in the help for SDRAM_GRP0_CONFIG. + +config ETRAX_SDRAM_TIMING + hex "SDRAM_TIMING" + depends on ETRAX_ARCH_V32 + default "104a" + help + SDRAM timing parameters. The default value is ok for + most hardwares but large SDRAMs may require a faster + refresh (a.k.a 8K refresh). The default value implies + 100MHz clock and SDR mode. + +config ETRAX_SDRAM_COMMAND + hex "SDRAM_COMMAND" + depends on ETRAX_ARCH_V32 + default "0" + help + SDRAM command. Should be 0 unless you really know what + you are doing (may be != 0 for unusual address line + mappings such as in a MCM).. + +config ETRAX_DEF_GIO_PA_OE + hex "GIO_PA_OE" + depends on ETRAX_ARCH_V32 + default "1c" + help + Configures the direction of general port A bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PA_OUT + hex "GIO_PA_OUT" + depends on ETRAX_ARCH_V32 + default "00" + help + Configures the initial data for the general port A bits. Most + products should use 00 here. + +config ETRAX_DEF_GIO_PB_OE + hex "GIO_PB_OE" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the direction of general port B bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PB_OUT + hex "GIO_PB_OUT" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the initial data for the general port B bits. Most + products should use 00000 here. + +config ETRAX_DEF_GIO_PC_OE + hex "GIO_PC_OE" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the direction of general port C bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PC_OUT + hex "GIO_PC_OUT" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the initial data for the general port C bits. Most + products should use 00000 here. + +config ETRAX_DEF_GIO_PD_OE + hex "GIO_PD_OE" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the direction of general port D bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PD_OUT + hex "GIO_PD_OUT" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the initial data for the general port D bits. Most + products should use 00000 here. + +config ETRAX_DEF_GIO_PE_OE + hex "GIO_PE_OE" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the direction of general port E bits. 1 is out, 0 is in. + This is often totally different depending on the product used. + There are some guidelines though - if you know that only LED's are + connected to port PA, then they are usually connected to bits 2-4 + and you can therefore use 1c. On other boards which don't have the + LED's at the general ports, these bits are used for all kinds of + stuff. If you don't know what to use, it is always safe to put all + as inputs, although floating inputs isn't good. + +config ETRAX_DEF_GIO_PE_OUT + hex "GIO_PE_OUT" + depends on ETRAX_ARCH_V32 + default "00000" + help + Configures the initial data for the general port E bits. Most + products should use 00000 here. + +config ETRAX_DEF_GIO_PV_OE + hex "GIO_PV_OE" + depends on ETRAX_VIRTUAL_GPIO + default "0000" + help + Configures the direction of virtual general port V bits. 1 is out, + 0 is in. This is often totally different depending on the product + used. These bits are used for all kinds of stuff. If you don't know + what to use, it is always safe to put all as inputs, although + floating inputs isn't good. + +config ETRAX_DEF_GIO_PV_OUT + hex "GIO_PV_OUT" + depends on ETRAX_VIRTUAL_GPIO + default "0000" + help + Configures the initial data for the virtual general port V bits. + Most products should use 0000 here. + +endmenu + +endif diff --git a/kernel/arch/cris/arch-v32/mach-fs/Makefile b/kernel/arch/cris/arch-v32/mach-fs/Makefile new file mode 100644 index 000000000..18a227196 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-fs/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# + +obj-y := dma.o pinmux.o io.o arbiter.o + +clean: + diff --git a/kernel/arch/cris/arch-v32/mach-fs/arbiter.c b/kernel/arch/cris/arch-v32/mach-fs/arbiter.c new file mode 100644 index 000000000..c97f4d812 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-fs/arbiter.c @@ -0,0 +1,404 @@ +/* + * Memory arbiter functions. Allocates bandwidth through the + * arbiter and sets up arbiter breakpoints. + * + * The algorithm first assigns slots to the clients that has specified + * bandwidth (e.g. ethernet) and then the remaining slots are divided + * on all the active clients. + * + * Copyright (c) 2004-2007 Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct crisv32_watch_entry { + unsigned long instance; + watch_callback *cb; + unsigned long start; + unsigned long end; + int used; +}; + +#define NUMBER_OF_BP 4 +#define NBR_OF_CLIENTS 14 +#define NBR_OF_SLOTS 64 +#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */ +#define INTMEM_BANDWIDTH 400000000 +#define NBR_OF_REGIONS 2 + +static struct crisv32_watch_entry watches[NUMBER_OF_BP] = { + {regi_marb_bp0}, + {regi_marb_bp1}, + {regi_marb_bp2}, + {regi_marb_bp3} +}; + +static u8 requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS]; +static u8 active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS]; +static int max_bandwidth[NBR_OF_REGIONS] = + { SDRAM_BANDWIDTH, INTMEM_BANDWIDTH }; + +DEFINE_SPINLOCK(arbiter_lock); + +static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id); + +/* + * "I'm the arbiter, I know the score. + * From square one I'll be watching all 64." + * (memory arbiter slots, that is) + * + * Or in other words: + * Program the memory arbiter slots for "region" according to what's + * in requested_slots[] and active_clients[], while minimizing + * latency. A caller may pass a non-zero positive amount for + * "unused_slots", which must then be the unallocated, remaining + * number of slots, free to hand out to any client. + */ + +static void crisv32_arbiter_config(int region, int unused_slots) +{ + int slot; + int client; + int interval = 0; + + /* + * This vector corresponds to the hardware arbiter slots (see + * the hardware documentation for semantics). We initialize + * each slot with a suitable sentinel value outside the valid + * range {0 .. NBR_OF_CLIENTS - 1} and replace them with + * client indexes. Then it's fed to the hardware. + */ + s8 val[NBR_OF_SLOTS]; + + for (slot = 0; slot < NBR_OF_SLOTS; slot++) + val[slot] = -1; + + for (client = 0; client < NBR_OF_CLIENTS; client++) { + int pos; + /* Allocate the requested non-zero number of slots, but + * also give clients with zero-requests one slot each + * while stocks last. We do the latter here, in client + * order. This makes sure zero-request clients are the + * first to get to any spare slots, else those slots + * could, when bandwidth is allocated close to the limit, + * all be allocated to low-index non-zero-request clients + * in the default-fill loop below. Another positive but + * secondary effect is a somewhat better spread of the + * zero-bandwidth clients in the vector, avoiding some of + * the latency that could otherwise be caused by the + * partitioning of non-zero-bandwidth clients at low + * indexes and zero-bandwidth clients at high + * indexes. (Note that this spreading can only affect the + * unallocated bandwidth.) All the above only matters for + * memory-intensive situations, of course. + */ + if (!requested_slots[region][client]) { + /* + * Skip inactive clients. Also skip zero-slot + * allocations in this pass when there are no known + * free slots. + */ + if (!active_clients[region][client] + || unused_slots <= 0) + continue; + + unused_slots--; + + /* Only allocate one slot for this client. */ + interval = NBR_OF_SLOTS; + } else + interval = + NBR_OF_SLOTS / requested_slots[region][client]; + + pos = 0; + while (pos < NBR_OF_SLOTS) { + if (val[pos] >= 0) + pos++; + else { + val[pos] = client; + pos += interval; + } + } + } + + client = 0; + for (slot = 0; slot < NBR_OF_SLOTS; slot++) { + /* + * Allocate remaining slots in round-robin + * client-number order for active clients. For this + * pass, we ignore requested bandwidth and previous + * allocations. + */ + if (val[slot] < 0) { + int first = client; + while (!active_clients[region][client]) { + client = (client + 1) % NBR_OF_CLIENTS; + if (client == first) + break; + } + val[slot] = client; + client = (client + 1) % NBR_OF_CLIENTS; + } + if (region == EXT_REGION) + REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot, + val[slot]); + else if (region == INT_REGION) + REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot, + val[slot]); + } +} + +extern char _stext, _etext; + +static void crisv32_arbiter_init(void) +{ + static int initialized; + + if (initialized) + return; + + initialized = 1; + + /* + * CPU caches are always set to active, but with zero + * bandwidth allocated. It should be ok to allocate zero + * bandwidth for the caches, because DMA for other channels + * will supposedly finish, once their programmed amount is + * done, and then the caches will get access according to the + * "fixed scheme" for unclaimed slots. Though, if for some + * use-case somewhere, there's a maximum CPU latency for + * e.g. some interrupt, we have to start allocating specific + * bandwidth for the CPU caches too. + */ + active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1; + crisv32_arbiter_config(EXT_REGION, 0); + crisv32_arbiter_config(INT_REGION, 0); + + if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, 0, + "arbiter", NULL)) + printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); + +#ifndef CONFIG_ETRAX_KGDB + /* Global watch for writes to kernel text segment. */ + crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext, + arbiter_all_clients, arbiter_all_write, NULL); +#endif +} + +/* Main entry for bandwidth allocation. */ + +int crisv32_arbiter_allocate_bandwidth(int client, int region, + unsigned long bandwidth) +{ + int i; + int total_assigned = 0; + int total_clients = 0; + int req; + + crisv32_arbiter_init(); + + for (i = 0; i < NBR_OF_CLIENTS; i++) { + total_assigned += requested_slots[region][i]; + total_clients += active_clients[region][i]; + } + + /* Avoid division by 0 for 0-bandwidth requests. */ + req = bandwidth == 0 + ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth); + + /* + * We make sure that there are enough slots only for non-zero + * requests. Requesting 0 bandwidth *may* allocate slots, + * though if all bandwidth is allocated, such a client won't + * get any and will have to rely on getting memory access + * according to the fixed scheme that's the default when one + * of the slot-allocated clients doesn't claim their slot. + */ + if (total_assigned + req > NBR_OF_SLOTS) + return -ENOMEM; + + active_clients[region][client] = 1; + requested_slots[region][client] = req; + crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned); + + return 0; +} + +/* + * Main entry for bandwidth deallocation. + * + * Strictly speaking, for a somewhat constant set of clients where + * each client gets a constant bandwidth and is just enabled or + * disabled (somewhat dynamically), no action is necessary here to + * avoid starvation for non-zero-allocation clients, as the allocated + * slots will just be unused. However, handing out those unused slots + * to active clients avoids needless latency if the "fixed scheme" + * would give unclaimed slots to an eager low-index client. + */ + +void crisv32_arbiter_deallocate_bandwidth(int client, int region) +{ + int i; + int total_assigned = 0; + + requested_slots[region][client] = 0; + active_clients[region][client] = 0; + + for (i = 0; i < NBR_OF_CLIENTS; i++) + total_assigned += requested_slots[region][i]; + + crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned); +} + +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback *cb) +{ + int i; + + crisv32_arbiter_init(); + + if (start > 0x80000000) { + printk(KERN_ERR "Arbiter: %lX doesn't look like a " + "physical address", start); + return -EFAULT; + } + + spin_lock(&arbiter_lock); + + for (i = 0; i < NUMBER_OF_BP; i++) { + if (!watches[i].used) { + reg_marb_rw_intr_mask intr_mask = + REG_RD(marb, regi_marb, rw_intr_mask); + + watches[i].used = 1; + watches[i].start = start; + watches[i].end = start + size; + watches[i].cb = cb; + + REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr, + watches[i].start); + REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr, + watches[i].end); + REG_WR_INT(marb_bp, watches[i].instance, rw_op, + accesses); + REG_WR_INT(marb_bp, watches[i].instance, rw_clients, + clients); + + if (i == 0) + intr_mask.bp0 = regk_marb_yes; + else if (i == 1) + intr_mask.bp1 = regk_marb_yes; + else if (i == 2) + intr_mask.bp2 = regk_marb_yes; + else if (i == 3) + intr_mask.bp3 = regk_marb_yes; + + REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); + spin_unlock(&arbiter_lock); + + return i; + } + } + spin_unlock(&arbiter_lock); + return -ENOMEM; +} + +int crisv32_arbiter_unwatch(int id) +{ + reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask); + + crisv32_arbiter_init(); + + spin_lock(&arbiter_lock); + + if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) { + spin_unlock(&arbiter_lock); + return -EINVAL; + } + + memset(&watches[id], 0, sizeof(struct crisv32_watch_entry)); + + if (id == 0) + intr_mask.bp0 = regk_marb_no; + else if (id == 1) + intr_mask.bp1 = regk_marb_no; + else if (id == 2) + intr_mask.bp2 = regk_marb_no; + else if (id == 3) + intr_mask.bp3 = regk_marb_no; + + REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); + + spin_unlock(&arbiter_lock); + return 0; +} + +extern void show_registers(struct pt_regs *regs); + +static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id) +{ + reg_marb_r_masked_intr masked_intr = + REG_RD(marb, regi_marb, r_masked_intr); + reg_marb_bp_r_brk_clients r_clients; + reg_marb_bp_r_brk_addr r_addr; + reg_marb_bp_r_brk_op r_op; + reg_marb_bp_r_brk_first_client r_first; + reg_marb_bp_r_brk_size r_size; + reg_marb_bp_rw_ack ack = { 0 }; + reg_marb_rw_ack_intr ack_intr = { + .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1 + }; + struct crisv32_watch_entry *watch; + + if (masked_intr.bp0) { + watch = &watches[0]; + ack_intr.bp0 = regk_marb_yes; + } else if (masked_intr.bp1) { + watch = &watches[1]; + ack_intr.bp1 = regk_marb_yes; + } else if (masked_intr.bp2) { + watch = &watches[2]; + ack_intr.bp2 = regk_marb_yes; + } else if (masked_intr.bp3) { + watch = &watches[3]; + ack_intr.bp3 = regk_marb_yes; + } else { + return IRQ_NONE; + } + + /* Retrieve all useful information and print it. */ + r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients); + r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr); + r_op = REG_RD(marb_bp, watch->instance, r_brk_op); + r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client); + r_size = REG_RD(marb_bp, watch->instance, r_brk_size); + + printk(KERN_INFO "Arbiter IRQ\n"); + printk(KERN_INFO "Clients %X addr %X op %X first %X size %X\n", + REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients), + REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr), + REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op), + REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first), + REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size)); + + REG_WR(marb_bp, watch->instance, rw_ack, ack); + REG_WR(marb, regi_marb, rw_ack_intr, ack_intr); + + printk(KERN_INFO "IRQ occurred at %lX\n", get_irq_regs()->erp); + + if (watch->cb) + watch->cb(); + + return IRQ_HANDLED; +} diff --git a/kernel/arch/cris/arch-v32/mach-fs/dma.c b/kernel/arch/cris/arch-v32/mach-fs/dma.c new file mode 100644 index 000000000..fc6416a67 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-fs/dma.c @@ -0,0 +1,229 @@ +/* Wrapper for DMA channel allocator that starts clocks etc */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static char used_dma_channels[MAX_DMA_CHANNELS]; +static const char *used_dma_channels_users[MAX_DMA_CHANNELS]; + +static DEFINE_SPINLOCK(dma_lock); + +int crisv32_request_dma(unsigned int dmanr, const char *device_id, + unsigned options, unsigned int bandwidth, + enum dma_owner owner) +{ + unsigned long flags; + reg_config_rw_clk_ctrl clk_ctrl; + reg_strmux_rw_cfg strmux_cfg; + + if (crisv32_arbiter_allocate_bandwidth(dmanr, + options & DMA_INT_MEM ? + INT_REGION : EXT_REGION, + bandwidth)) + return -ENOMEM; + + spin_lock_irqsave(&dma_lock, flags); + + if (used_dma_channels[dmanr]) { + spin_unlock_irqrestore(&dma_lock, flags); + if (options & DMA_VERBOSE_ON_ERROR) { + printk(KERN_ERR "Failed to request DMA %i for %s, " + "already allocated by %s\n", + dmanr, + device_id, + used_dma_channels_users[dmanr]); + } + if (options & DMA_PANIC_ON_ERROR) + panic("request_dma error!"); + spin_unlock_irqrestore(&dma_lock, flags); + return -EBUSY; + } + clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); + strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); + + switch (dmanr) { + case 0: + case 1: + clk_ctrl.dma01_eth0 = 1; + break; + case 2: + case 3: + clk_ctrl.dma23 = 1; + break; + case 4: + case 5: + clk_ctrl.dma45 = 1; + break; + case 6: + case 7: + clk_ctrl.dma67 = 1; + break; + case 8: + case 9: + clk_ctrl.dma89_strcop = 1; + break; +#if MAX_DMA_CHANNELS-1 != 9 +#error Check dma.c +#endif + default: + spin_unlock_irqrestore(&dma_lock, flags); + if (options & DMA_VERBOSE_ON_ERROR) { + printk(KERN_ERR "Failed to request DMA %i for %s, " + "only 0-%i valid)\n", + dmanr, device_id, MAX_DMA_CHANNELS - 1); + } + + if (options & DMA_PANIC_ON_ERROR) + panic("request_dma error!"); + return -EINVAL; + } + + switch (owner) { + case dma_eth0: + if (dmanr == 0) + strmux_cfg.dma0 = regk_strmux_eth0; + else if (dmanr == 1) + strmux_cfg.dma1 = regk_strmux_eth0; + else + panic("Invalid DMA channel for eth0\n"); + break; + case dma_eth1: + if (dmanr == 6) + strmux_cfg.dma6 = regk_strmux_eth1; + else if (dmanr == 7) + strmux_cfg.dma7 = regk_strmux_eth1; + else + panic("Invalid DMA channel for eth1\n"); + break; + case dma_iop0: + if (dmanr == 2) + strmux_cfg.dma2 = regk_strmux_iop0; + else if (dmanr == 3) + strmux_cfg.dma3 = regk_strmux_iop0; + else + panic("Invalid DMA channel for iop0\n"); + break; + case dma_iop1: + if (dmanr == 4) + strmux_cfg.dma4 = regk_strmux_iop1; + else if (dmanr == 5) + strmux_cfg.dma5 = regk_strmux_iop1; + else + panic("Invalid DMA channel for iop1\n"); + break; + case dma_ser0: + if (dmanr == 6) + strmux_cfg.dma6 = regk_strmux_ser0; + else if (dmanr == 7) + strmux_cfg.dma7 = regk_strmux_ser0; + else + panic("Invalid DMA channel for ser0\n"); + break; + case dma_ser1: + if (dmanr == 4) + strmux_cfg.dma4 = regk_strmux_ser1; + else if (dmanr == 5) + strmux_cfg.dma5 = regk_strmux_ser1; + else + panic("Invalid DMA channel for ser1\n"); + break; + case dma_ser2: + if (dmanr == 2) + strmux_cfg.dma2 = regk_strmux_ser2; + else if (dmanr == 3) + strmux_cfg.dma3 = regk_strmux_ser2; + else + panic("Invalid DMA channel for ser2\n"); + break; + case dma_ser3: + if (dmanr == 8) + strmux_cfg.dma8 = regk_strmux_ser3; + else if (dmanr == 9) + strmux_cfg.dma9 = regk_strmux_ser3; + else + panic("Invalid DMA channel for ser3\n"); + break; + case dma_sser0: + if (dmanr == 4) + strmux_cfg.dma4 = regk_strmux_sser0; + else if (dmanr == 5) + strmux_cfg.dma5 = regk_strmux_sser0; + else + panic("Invalid DMA channel for sser0\n"); + break; + case dma_sser1: + if (dmanr == 6) + strmux_cfg.dma6 = regk_strmux_sser1; + else if (dmanr == 7) + strmux_cfg.dma7 = regk_strmux_sser1; + else + panic("Invalid DMA channel for sser1\n"); + break; + case dma_ata: + if (dmanr == 2) + strmux_cfg.dma2 = regk_strmux_ata; + else if (dmanr == 3) + strmux_cfg.dma3 = regk_strmux_ata; + else + panic("Invalid DMA channel for ata\n"); + break; + case dma_strp: + if (dmanr == 8) + strmux_cfg.dma8 = regk_strmux_strcop; + else if (dmanr == 9) + strmux_cfg.dma9 = regk_strmux_strcop; + else + panic("Invalid DMA channel for strp\n"); + break; + case dma_ext0: + if (dmanr == 6) + strmux_cfg.dma6 = regk_strmux_ext0; + else + panic("Invalid DMA channel for ext0\n"); + break; + case dma_ext1: + if (dmanr == 7) + strmux_cfg.dma7 = regk_strmux_ext1; + else + panic("Invalid DMA channel for ext1\n"); + break; + case dma_ext2: + if (dmanr == 2) + strmux_cfg.dma2 = regk_strmux_ext2; + else if (dmanr == 8) + strmux_cfg.dma8 = regk_strmux_ext2; + else + panic("Invalid DMA channel for ext2\n"); + break; + case dma_ext3: + if (dmanr == 3) + strmux_cfg.dma3 = regk_strmux_ext3; + else if (dmanr == 9) + strmux_cfg.dma9 = regk_strmux_ext2; + else + panic("Invalid DMA channel for ext2\n"); + break; + } + + used_dma_channels[dmanr] = 1; + used_dma_channels_users[dmanr] = device_id; + REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); + REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); + spin_unlock_irqrestore(&dma_lock, flags); + return 0; +} + +void crisv32_free_dma(unsigned int dmanr) +{ + spin_lock(&dma_lock); + used_dma_channels[dmanr] = 0; + spin_unlock(&dma_lock); +} diff --git a/kernel/arch/cris/arch-v32/mach-fs/dram_init.S b/kernel/arch/cris/arch-v32/mach-fs/dram_init.S new file mode 100644 index 000000000..6fbad3365 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-fs/dram_init.S @@ -0,0 +1,116 @@ +/* + * DRAM/SDRAM initialization - alter with care + * This file is intended to be included from other assembler files + * + * Note: This file may not modify r8 or r9 because they are used to + * carry information from the decompresser to the kernel + * + * Copyright (C) 2000-2007 Axis Communications AB + * + * Authors: Mikael Starvik + */ + +/* Just to be certain the config file is included, we include it here + * explicitely instead of depending on it being included in the file that + * uses this code. + */ + +#include +#include + + ;; WARNING! The registers r8 and r9 are used as parameters carrying + ;; information from the decompressor (if the kernel was compressed). + ;; They should not be used in the code below. + + ; Refer to BIF MDS for a description of SDRAM initialization + + ; Bank configuration + move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0 + move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0 + move.d CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1 + move.d $r1, [$r0] + + ; Calculate value of mrs_data + ; CAS latency = 2 && bus_width = 32 => 0x40 + ; CAS latency = 3 && bus_width = 32 => 0x60 + ; CAS latency = 2 && bus_width = 16 => 0x20 + ; CAS latency = 3 && bus_width = 16 => 0x30 + + ; Check if value is already supplied in kernel config + move.d CONFIG_ETRAX_SDRAM_COMMAND, $r2 + bne _set_timing + nop + + move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2 + move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 + and.d 0x07, $r1 ; Get CAS latency + cmpq 2, $r1 ; CL = 2 ? + beq _bw_check + nop + move.d 0x60, $r4 + +_bw_check: + ; Assume that group 0 width is equal to group 1. This assumption + ; is wrong for a group 1 only hardware (such as the grand old + ; StorPoint+). + move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1 + and.d 0x200, $r1 ; DRAM width is bit 9 + beq _set_timing + lslq 2, $r4 ; mrs_data starts at bit 2 + lsrq 1, $r4 ; 16 bits. Shift down value. + + ; Set timing parameters (refresh off to avoid Guinness TR 83) +_set_timing: + move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 + and.d ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1 + move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0 + move.d $r1, [$r0] + + ; Issue NOP command + move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5 + moveq regk_bif_core_nop, $r1 + move.d $r1, [$r5] + + ; Wait 200us + move.d 10000, $r2 +1: bne 1b + subq 1, $r2 + + ; Issue initialization command sequence + lapc _sdram_commands_start, $r2 + lapc _sdram_commands_end, $r3 +1: clear.d $r6 + move.b [$r2+], $r6 ; Load command + or.d $r4, $r6 ; Add calculated mrs + move.d $r6, [$r5] ; Write rw_sdram_cmd + ; Wait 80 ns between each command + move.d 4000, $r7 +2: bne 2b + subq 1, $r7 + cmp.d $r2, $r3 ; Last command? + bne 1b + nop + + ; Start refresh + move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 + move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0 + move.d $r1, [$r0] + + ; Initialization finished + ba _sdram_commands_end + nop + +_sdram_commands_start: + .byte regk_bif_core_pre ; Precharge + .byte regk_bif_core_ref ; refresh + .byte regk_bif_core_ref ; refresh + .byte regk_bif_core_ref ; refresh + .byte regk_bif_core_ref ; refresh + .byte regk_bif_core_ref ; refresh + .byte regk_bif_core_ref ; refresh + .byte regk_bif_core_ref ; refresh + .byte regk_bif_core_ref ; refresh + .byte regk_bif_core_mrs ; mrs +_sdram_commands_end: diff --git a/kernel/arch/cris/arch-v32/mach-fs/hw_settings.S b/kernel/arch/cris/arch-v32/mach-fs/hw_settings.S new file mode 100644 index 000000000..8bde93c36 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-fs/hw_settings.S @@ -0,0 +1,70 @@ +/* + * This table is used by some tools to extract hardware parameters. + * The table should be included in the kernel and the decompressor. + * Don't forget to update the tools if you change this table. + * + * Copyright (C) 2001-2007 Axis Communications AB + * + * Authors: Mikael Starvik + */ + +#include +#include +#include + + .ascii "HW_PARAM_MAGIC" ; Magic number + .dword 0xc0004000 ; Kernel start address + + ; Debug port +#ifdef CONFIG_ETRAX_DEBUG_PORT0 + .dword 0 +#elif defined(CONFIG_ETRAX_DEBUG_PORT1) + .dword 1 +#elif defined(CONFIG_ETRAX_DEBUG_PORT2) + .dword 2 +#elif defined(CONFIG_ETRAX_DEBUG_PORT3) + .dword 3 +#else + .dword 4 ; No debug +#endif + + ; Register values + .dword REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg) + .dword CONFIG_ETRAX_MEM_GRP1_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg) + .dword CONFIG_ETRAX_MEM_GRP2_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg) + .dword CONFIG_ETRAX_MEM_GRP3_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg) + .dword CONFIG_ETRAX_MEM_GRP4_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0) + .dword CONFIG_ETRAX_SDRAM_GRP0_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1) + .dword CONFIG_ETRAX_SDRAM_GRP1_CONFIG + .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing) + .dword CONFIG_ETRAX_SDRAM_TIMING + .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd) + .dword CONFIG_ETRAX_SDRAM_COMMAND + + .dword REG_ADDR(gio, regi_gio, rw_pa_dout) + .dword CONFIG_ETRAX_DEF_GIO_PA_OUT + .dword REG_ADDR(gio, regi_gio, rw_pa_oe) + .dword CONFIG_ETRAX_DEF_GIO_PA_OE + .dword REG_ADDR(gio, regi_gio, rw_pb_dout) + .dword CONFIG_ETRAX_DEF_GIO_PB_OUT + .dword REG_ADDR(gio, regi_gio, rw_pb_oe) + .dword CONFIG_ETRAX_DEF_GIO_PB_OE + .dword REG_ADDR(gio, regi_gio, rw_pc_dout) + .dword CONFIG_ETRAX_DEF_GIO_PC_OUT + .dword REG_ADDR(gio, regi_gio, rw_pc_oe) + .dword CONFIG_ETRAX_DEF_GIO_PC_OE + .dword REG_ADDR(gio, regi_gio, rw_pd_dout) + .dword CONFIG_ETRAX_DEF_GIO_PD_OUT + .dword REG_ADDR(gio, regi_gio, rw_pd_oe) + .dword CONFIG_ETRAX_DEF_GIO_PD_OE + .dword REG_ADDR(gio, regi_gio, rw_pe_dout) + .dword CONFIG_ETRAX_DEF_GIO_PE_OUT + .dword REG_ADDR(gio, regi_gio, rw_pe_oe) + .dword CONFIG_ETRAX_DEF_GIO_PE_OE + + .dword 0 ; No more register values diff --git a/kernel/arch/cris/arch-v32/mach-fs/io.c b/kernel/arch/cris/arch-v32/mach-fs/io.c new file mode 100644 index 000000000..a6958661f --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-fs/io.c @@ -0,0 +1,191 @@ +/* + * Helper functions for I/O pins. + * + * Copyright (c) 2004-2007 Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef DEBUG +#define DEBUG(x) +#endif + +struct crisv32_ioport crisv32_ioports[] = { + { + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe), + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout), + (unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din), + 8 + }, + { + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe), + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout), + (unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din), + 18 + }, + { + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe), + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout), + (unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din), + 18 + }, + { + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_oe), + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_dout), + (unsigned long *)REG_ADDR(gio, regi_gio, r_pd_din), + 18 + }, + { + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_oe), + (unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_dout), + (unsigned long *)REG_ADDR(gio, regi_gio, r_pe_din), + 18 + } +}; + +#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports) + +struct crisv32_iopin crisv32_led_net0_green; +struct crisv32_iopin crisv32_led_net0_red; +struct crisv32_iopin crisv32_led_net1_green; +struct crisv32_iopin crisv32_led_net1_red; +struct crisv32_iopin crisv32_led2_green; +struct crisv32_iopin crisv32_led2_red; +struct crisv32_iopin crisv32_led3_green; +struct crisv32_iopin crisv32_led3_red; + +/* Dummy port used when green LED and red LED is on the same bit */ +static unsigned long io_dummy; +static struct crisv32_ioport dummy_port = { + &io_dummy, + &io_dummy, + &io_dummy, + 18 +}; +static struct crisv32_iopin dummy_led = { + &dummy_port, + 0 +}; + +static int __init crisv32_io_init(void) +{ + int ret = 0; + + u32 i; + + /* Locks *should* be dynamically initialized. */ + for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++) + spin_lock_init(&crisv32_ioports[i].lock); + spin_lock_init(&dummy_port.lock); + + /* Initialize LEDs */ +#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) + ret += + crisv32_io_get_name(&crisv32_led_net0_green, + CONFIG_ETRAX_LED_G_NET0); + crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out); + if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) { + ret += + crisv32_io_get_name(&crisv32_led_net0_red, + CONFIG_ETRAX_LED_R_NET0); + crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out); + } else + crisv32_led_net0_red = dummy_led; +#endif + +#ifdef CONFIG_ETRAX_NBR_LED_GRP_TWO + ret += + crisv32_io_get_name(&crisv32_led_net1_green, + CONFIG_ETRAX_LED_G_NET1); + crisv32_io_set_dir(&crisv32_led_net1_green, crisv32_io_dir_out); + if (strcmp(CONFIG_ETRAX_LED_G_NET1, CONFIG_ETRAX_LED_R_NET1)) { + crisv32_io_get_name(&crisv32_led_net1_red, + CONFIG_ETRAX_LED_R_NET1); + crisv32_io_set_dir(&crisv32_led_net1_red, crisv32_io_dir_out); + } else + crisv32_led_net1_red = dummy_led; +#endif + + ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G); + ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R); + ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G); + ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R); + + crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out); + crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out); + crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out); + crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out); + + return ret; +} + +__initcall(crisv32_io_init); + +int crisv32_io_get(struct crisv32_iopin *iopin, + unsigned int port, unsigned int pin) +{ + if (port > NBR_OF_PORTS) + return -EINVAL; + if (port > crisv32_ioports[port].pin_count) + return -EINVAL; + + iopin->bit = 1 << pin; + iopin->port = &crisv32_ioports[port]; + + /* Only allocate pinmux gpiopins if port != PORT_A (port 0) */ + /* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */ + if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio)) + return -EIO; + DEBUG(printk(KERN_DEBUG "crisv32_io_get: Allocated pin %d on port %d\n", + pin, port)); + + return 0; +} + +int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name) +{ + int port; + int pin; + + if (toupper(*name) == 'P') + name++; + + if (toupper(*name) < 'A' || toupper(*name) > 'E') + return -EINVAL; + + port = toupper(*name) - 'A'; + name++; + pin = simple_strtoul(name, NULL, 10); + + if (pin < 0 || pin > crisv32_ioports[port].pin_count) + return -EINVAL; + + iopin->bit = 1 << pin; + iopin->port = &crisv32_ioports[port]; + + /* Only allocate pinmux gpiopins if port != PORT_A (port 0) */ + /* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */ + if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio)) + return -EIO; + + DEBUG(printk(KERN_DEBUG + "crisv32_io_get_name: Allocated pin %d on port %d\n", + pin, port)); + + return 0; +} + +#ifdef CONFIG_PCI +/* PCI I/O access stuff */ +struct cris_io_operations *cris_iops = NULL; +EXPORT_SYMBOL(cris_iops); +#endif diff --git a/kernel/arch/cris/arch-v32/mach-fs/pinmux.c b/kernel/arch/cris/arch-v32/mach-fs/pinmux.c new file mode 100644 index 000000000..05a04708b --- /dev/null +++ b/kernel/arch/cris/arch-v32/mach-fs/pinmux.c @@ -0,0 +1,323 @@ +/* + * Allocator for I/O pins. All pins are allocated to GPIO at bootup. + * Unassigned pins and GPIO pins can be allocated to a fixed interface + * or the I/O processor instead. + * + * Copyright (c) 2004-2007 Axis Communications AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#undef DEBUG + +#define PORT_PINS 18 +#define PORTS 4 + +static char pins[PORTS][PORT_PINS]; +static DEFINE_SPINLOCK(pinmux_lock); + +static void crisv32_pinmux_set(int port); + +static int __crisv32_pinmux_alloc(int port, int first_pin, int last_pin, + enum pin_mode mode) +{ + int i; + + for (i = first_pin; i <= last_pin; i++) { + if ((pins[port][i] != pinmux_none) + && (pins[port][i] != pinmux_gpio) + && (pins[port][i] != mode)) { +#ifdef DEBUG + panic("Pinmux alloc failed!\n"); +#endif + return -EPERM; + } + } + + for (i = first_pin; i <= last_pin; i++) + pins[port][i] = mode; + + crisv32_pinmux_set(port); +} + +static int crisv32_pinmux_init(void) +{ + static int initialized; + + if (!initialized) { + reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa); + initialized = 1; + REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); + pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 = + pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes; + REG_WR(pinmux, regi_pinmux, rw_pa, pa); + __crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio); + __crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio); + __crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio); + __crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio); + } + + return 0; +} + +int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, + enum pin_mode mode) +{ + unsigned long flags; + int ret; + + crisv32_pinmux_init(); + + if (port > PORTS || port < 0) + return -EINVAL; + + spin_lock_irqsave(&pinmux_lock, flags); + + ret = __crisv32_pinmux_alloc(port, first_pin, last_pin, mode); + + spin_unlock_irqrestore(&pinmux_lock, flags); + + return ret; +} + +int crisv32_pinmux_alloc_fixed(enum fixed_function function) +{ + int ret = -EINVAL; + char saved[sizeof pins]; + unsigned long flags; + + spin_lock_irqsave(&pinmux_lock, flags); + + /* Save internal data for recovery */ + memcpy(saved, pins, sizeof pins); + + crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */ + + reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); + + switch (function) { + case pinmux_ser1: + ret = __crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed); + hwprot.ser1 = regk_pinmux_yes; + break; + case pinmux_ser2: + ret = __crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed); + hwprot.ser2 = regk_pinmux_yes; + break; + case pinmux_ser3: + ret = __crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed); + hwprot.ser3 = regk_pinmux_yes; + break; + case pinmux_sser0: + ret = __crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed); + ret |= __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); + hwprot.sser0 = regk_pinmux_yes; + break; + case pinmux_sser1: + ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); + hwprot.sser1 = regk_pinmux_yes; + break; + case pinmux_ata0: + ret = __crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed); + ret |= __crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed); + hwprot.ata0 = regk_pinmux_yes; + break; + case pinmux_ata1: + ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); + ret |= __crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed); + hwprot.ata1 = regk_pinmux_yes; + break; + case pinmux_ata2: + ret = __crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed); + ret |= __crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed); + hwprot.ata2 = regk_pinmux_yes; + break; + case pinmux_ata3: + ret = __crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed); + ret |= __crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed); + hwprot.ata2 = regk_pinmux_yes; + break; + case pinmux_ata: + ret = __crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed); + ret |= __crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed); + hwprot.ata = regk_pinmux_yes; + break; + case pinmux_eth1: + ret = __crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed); + hwprot.eth1 = regk_pinmux_yes; + hwprot.eth1_mgm = regk_pinmux_yes; + break; + case pinmux_timer: + ret = __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); + hwprot.timer = regk_pinmux_yes; + spin_unlock_irqrestore(&pinmux_lock, flags); + return ret; + } + + if (!ret) + REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); + else + memcpy(pins, saved, sizeof pins); + + spin_unlock_irqrestore(&pinmux_lock, flags); + + return ret; +} + +void crisv32_pinmux_set(int port) +{ + int i; + int gpio_val = 0; + int iop_val = 0; + + for (i = 0; i < PORT_PINS; i++) { + if (pins[port][i] == pinmux_gpio) + gpio_val |= (1 << i); + else if (pins[port][i] == pinmux_iop) + iop_val |= (1 << i); + } + + REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8 * port, + gpio_val); + REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8 * port, + iop_val); + +#ifdef DEBUG + crisv32_pinmux_dump(); +#endif +} + +static int __crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) +{ + int i; + + for (i = first_pin; i <= last_pin; i++) + pins[port][i] = pinmux_none; + + crisv32_pinmux_set(port); + return 0; +} + +int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) +{ + unsigned long flags; + + crisv32_pinmux_init(); + + if (port > PORTS || port < 0) + return -EINVAL; + + spin_lock_irqsave(&pinmux_lock, flags); + __crisv32_pinmux_dealloc(port, first_pin, last_pin); + spin_unlock_irqrestore(&pinmux_lock, flags); + + return 0; +} + +int crisv32_pinmux_dealloc_fixed(enum fixed_function function) +{ + int ret = -EINVAL; + char saved[sizeof pins]; + unsigned long flags; + + spin_lock_irqsave(&pinmux_lock, flags); + + /* Save internal data for recovery */ + memcpy(saved, pins, sizeof pins); + + crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */ + + reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); + + switch (function) { + case pinmux_ser1: + ret = __crisv32_pinmux_dealloc(PORT_C, 4, 7); + hwprot.ser1 = regk_pinmux_no; + break; + case pinmux_ser2: + ret = __crisv32_pinmux_dealloc(PORT_C, 8, 11); + hwprot.ser2 = regk_pinmux_no; + break; + case pinmux_ser3: + ret = __crisv32_pinmux_dealloc(PORT_C, 12, 15); + hwprot.ser3 = regk_pinmux_no; + break; + case pinmux_sser0: + ret = __crisv32_pinmux_dealloc(PORT_C, 0, 3); + ret |= __crisv32_pinmux_dealloc(PORT_C, 16, 16); + hwprot.sser0 = regk_pinmux_no; + break; + case pinmux_sser1: + ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4); + hwprot.sser1 = regk_pinmux_no; + break; + case pinmux_ata0: + ret = __crisv32_pinmux_dealloc(PORT_D, 5, 7); + ret |= __crisv32_pinmux_dealloc(PORT_D, 15, 17); + hwprot.ata0 = regk_pinmux_no; + break; + case pinmux_ata1: + ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4); + ret |= __crisv32_pinmux_dealloc(PORT_E, 17, 17); + hwprot.ata1 = regk_pinmux_no; + break; + case pinmux_ata2: + ret = __crisv32_pinmux_dealloc(PORT_C, 11, 15); + ret |= __crisv32_pinmux_dealloc(PORT_E, 3, 3); + hwprot.ata2 = regk_pinmux_no; + break; + case pinmux_ata3: + ret = __crisv32_pinmux_dealloc(PORT_C, 8, 10); + ret |= __crisv32_pinmux_dealloc(PORT_C, 0, 2); + hwprot.ata2 = regk_pinmux_no; + break; + case pinmux_ata: + ret = __crisv32_pinmux_dealloc(PORT_B, 0, 15); + ret |= __crisv32_pinmux_dealloc(PORT_D, 8, 15); + hwprot.ata = regk_pinmux_no; + break; + case pinmux_eth1: + ret = __crisv32_pinmux_dealloc(PORT_E, 0, 17); + hwprot.eth1 = regk_pinmux_no; + hwprot.eth1_mgm = regk_pinmux_no; + break; + case pinmux_timer: + ret = __crisv32_pinmux_dealloc(PORT_C, 16, 16); + hwprot.timer = regk_pinmux_no; + spin_unlock_irqrestore(&pinmux_lock, flags); + return ret; + } + + if (!ret) + REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); + else + memcpy(pins, saved, sizeof pins); + + spin_unlock_irqrestore(&pinmux_lock, flags); + + return ret; +} + +#ifdef DEBUG +static void crisv32_pinmux_dump(void) +{ + int i, j; + + crisv32_pinmux_init(); + + for (i = 0; i < PORTS; i++) { + printk(KERN_DEBUG "Port %c\n", 'B' + i); + for (j = 0; j < PORT_PINS; j++) + printk(KERN_DEBUG " Pin %d = %d\n", j, pins[i][j]); + } +} +#endif +__initcall(crisv32_pinmux_init); diff --git a/kernel/arch/cris/arch-v32/mm/Makefile b/kernel/arch/cris/arch-v32/mm/Makefile new file mode 100644 index 000000000..0b801f296 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mm/Makefile @@ -0,0 +1,4 @@ +# Makefile for the Linux/cris parts of the memory manager. + +obj-y += mmu.o init.o tlb.o intmem.o +obj-$(CONFIG_ETRAX_L2CACHE) += l2cache.o diff --git a/kernel/arch/cris/arch-v32/mm/init.c b/kernel/arch/cris/arch-v32/mm/init.c new file mode 100644 index 000000000..f5438ca81 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mm/init.c @@ -0,0 +1,162 @@ +/* + * Set up paging and the MMU. + * + * Copyright (C) 2000-2003, Axis Communications AB. + * + * Authors: Bjorn Wesen + * Tobias Anderberg , CRISv32 port. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void tlb_init(void); + +/* + * The kernel is already mapped with linear mapping at kseg_c so there's no + * need to map it with a page table. However, head.S also temporarily mapped it + * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various + * other paging stuff. + */ +void __init cris_mmu_init(void) +{ + unsigned long mmu_config; + unsigned long mmu_kbase_hi; + unsigned long mmu_kbase_lo; + unsigned short mmu_page_id; + + /* + * Make sure the current pgd table points to something sane, even if it + * is most probably not used until the next switch_mm. + */ + per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd; + + /* Initialise the TLB. Function found in tlb.c. */ + tlb_init(); + + /* + * Enable exceptions and initialize the kernel segments. + * See head.S for differences between ARTPEC-3 and ETRAX FS. + */ + mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on) | + REG_STATE(mmu, rw_mm_cfg, acc, on) | + REG_STATE(mmu, rw_mm_cfg, ex, on) | + REG_STATE(mmu, rw_mm_cfg, inv, on) | +#ifdef CONFIG_CRIS_MACH_ARTPEC3 + REG_STATE(mmu, rw_mm_cfg, seg_f, page) | + REG_STATE(mmu, rw_mm_cfg, seg_e, page) | + REG_STATE(mmu, rw_mm_cfg, seg_d, linear) | +#else + REG_STATE(mmu, rw_mm_cfg, seg_f, linear) | + REG_STATE(mmu, rw_mm_cfg, seg_e, linear) | + REG_STATE(mmu, rw_mm_cfg, seg_d, page) | +#endif + REG_STATE(mmu, rw_mm_cfg, seg_c, linear) | + REG_STATE(mmu, rw_mm_cfg, seg_b, linear) | + REG_STATE(mmu, rw_mm_cfg, seg_a, page) | + REG_STATE(mmu, rw_mm_cfg, seg_9, page) | + REG_STATE(mmu, rw_mm_cfg, seg_8, page) | + REG_STATE(mmu, rw_mm_cfg, seg_7, page) | + REG_STATE(mmu, rw_mm_cfg, seg_6, page) | + REG_STATE(mmu, rw_mm_cfg, seg_5, page) | + REG_STATE(mmu, rw_mm_cfg, seg_4, page) | + REG_STATE(mmu, rw_mm_cfg, seg_3, page) | + REG_STATE(mmu, rw_mm_cfg, seg_2, page) | + REG_STATE(mmu, rw_mm_cfg, seg_1, page) | + REG_STATE(mmu, rw_mm_cfg, seg_0, page)); + + /* See head.S for differences between ARTPEC-3 and ETRAX FS. */ + mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) | +#ifdef CONFIG_CRIS_MACH_ARTPEC3 + REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x5) | +#else + REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) | + REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) | +#endif + REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) | + REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) | + REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0)); + + mmu_kbase_lo = ( REG_FIELD(mmu, rw_mm_kbase_lo, base_7, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_lo, base_6, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_lo, base_5, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_lo, base_3, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_lo, base_2, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_lo, base_1, 0x0) | + REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0x0)); + + mmu_page_id = REG_FIELD(mmu, rw_mm_tlb_hi, pid, 0); + + /* Update the instruction MMU. */ + SUPP_BANK_SEL(BANK_IM); + SUPP_REG_WR(RW_MM_CFG, mmu_config); + SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi); + SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo); + SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id); + + /* Update the data MMU. */ + SUPP_BANK_SEL(BANK_DM); + SUPP_REG_WR(RW_MM_CFG, mmu_config); + SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi); + SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo); + SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id); + + SPEC_REG_WR(SPEC_REG_PID, 0); + + /* + * The MMU has been enabled ever since head.S but just to make it + * totally obvious enable it here as well. + */ + SUPP_BANK_SEL(BANK_GC); + SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */ +} + +void __init paging_init(void) +{ + int i; + unsigned long zones_size[MAX_NR_ZONES]; + + printk("Setting up paging and the MMU.\n"); + + /* Clear out the init_mm.pgd that will contain the kernel's mappings. */ + for(i = 0; i < PTRS_PER_PGD; i++) + swapper_pg_dir[i] = __pgd(0); + + cris_mmu_init(); + + /* + * Initialize the bad page table and bad page to point to a couple of + * allocated pages. + */ + empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); + memset((void *) empty_zero_page, 0, PAGE_SIZE); + + /* All pages are DMA'able in Etrax, so put all in the DMA'able zone. */ + zones_size[0] = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT; + + for (i = 1; i < MAX_NR_ZONES; i++) + zones_size[i] = 0; + + /* + * Use free_area_init_node instead of free_area_init, because it is + * designed for systems where the DRAM starts at an address + * substantially higher than 0, like us (we start at PAGE_OFFSET). This + * saves space in the mem_map page array. + */ + free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); + + mem_map = contig_page_data.node_mem_map; +} diff --git a/kernel/arch/cris/arch-v32/mm/intmem.c b/kernel/arch/cris/arch-v32/mm/intmem.c new file mode 100644 index 000000000..1b17d92ce --- /dev/null +++ b/kernel/arch/cris/arch-v32/mm/intmem.c @@ -0,0 +1,150 @@ +/* + * Simple allocator for internal RAM in ETRAX FS + * + * Copyright (c) 2004 Axis Communications AB. + */ + +#include +#include +#include +#include + +#define STATUS_FREE 0 +#define STATUS_ALLOCATED 1 + +#ifdef CONFIG_ETRAX_L2CACHE +#define RESERVED_SIZE 66*1024 +#else +#define RESERVED_SIZE 0 +#endif + +struct intmem_allocation { + struct list_head entry; + unsigned int size; + unsigned offset; + char status; +}; + + +static struct list_head intmem_allocations; +static void* intmem_virtual; + +static void crisv32_intmem_init(void) +{ + static int initiated = 0; + if (!initiated) { + struct intmem_allocation* alloc; + alloc = kmalloc(sizeof *alloc, GFP_KERNEL); + INIT_LIST_HEAD(&intmem_allocations); + intmem_virtual = ioremap(MEM_INTMEM_START + RESERVED_SIZE, + MEM_INTMEM_SIZE - RESERVED_SIZE); + initiated = 1; + alloc->size = MEM_INTMEM_SIZE - RESERVED_SIZE; + alloc->offset = 0; + alloc->status = STATUS_FREE; + list_add_tail(&alloc->entry, &intmem_allocations); + } +} + +void* crisv32_intmem_alloc(unsigned size, unsigned align) +{ + struct intmem_allocation* allocation; + struct intmem_allocation* tmp; + void* ret = NULL; + + preempt_disable(); + crisv32_intmem_init(); + + list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) { + int alignment = allocation->offset % align; + alignment = alignment ? align - alignment : alignment; + + if (allocation->status == STATUS_FREE && + allocation->size >= size + alignment) { + if (allocation->size > size + alignment) { + struct intmem_allocation* alloc; + alloc = kmalloc(sizeof *alloc, GFP_ATOMIC); + alloc->status = STATUS_FREE; + alloc->size = allocation->size - size - + alignment; + alloc->offset = allocation->offset + size + + alignment; + list_add(&alloc->entry, &allocation->entry); + + if (alignment) { + struct intmem_allocation *tmp; + tmp = kmalloc(sizeof *tmp, GFP_ATOMIC); + tmp->offset = allocation->offset; + tmp->size = alignment; + tmp->status = STATUS_FREE; + allocation->offset += alignment; + list_add_tail(&tmp->entry, + &allocation->entry); + } + } + allocation->status = STATUS_ALLOCATED; + allocation->size = size; + ret = (void*)((int)intmem_virtual + allocation->offset); + } + } + preempt_enable(); + return ret; +} + +void crisv32_intmem_free(void* addr) +{ + struct intmem_allocation* allocation; + struct intmem_allocation* tmp; + + if (addr == NULL) + return; + + preempt_disable(); + crisv32_intmem_init(); + + list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) { + if (allocation->offset == (int)(addr - intmem_virtual)) { + struct intmem_allocation *prev = + list_entry(allocation->entry.prev, + struct intmem_allocation, entry); + struct intmem_allocation *next = + list_entry(allocation->entry.next, + struct intmem_allocation, entry); + + allocation->status = STATUS_FREE; + /* Join with prev and/or next if also free */ + if ((prev != &intmem_allocations) && + (prev->status == STATUS_FREE)) { + prev->size += allocation->size; + list_del(&allocation->entry); + kfree(allocation); + allocation = prev; + } + if ((next != &intmem_allocations) && + (next->status == STATUS_FREE)) { + allocation->size += next->size; + list_del(&next->entry); + kfree(next); + } + preempt_enable(); + return; + } + } + preempt_enable(); +} + +void* crisv32_intmem_phys_to_virt(unsigned long addr) +{ + return (void *)(addr - (MEM_INTMEM_START + RESERVED_SIZE) + + (unsigned long)intmem_virtual); +} + +unsigned long crisv32_intmem_virt_to_phys(void* addr) +{ + return (unsigned long)((unsigned long )addr - + (unsigned long)intmem_virtual + MEM_INTMEM_START + + RESERVED_SIZE); +} + +module_init(crisv32_intmem_init); + diff --git a/kernel/arch/cris/arch-v32/mm/l2cache.c b/kernel/arch/cris/arch-v32/mm/l2cache.c new file mode 100644 index 000000000..332ff10dc --- /dev/null +++ b/kernel/arch/cris/arch-v32/mm/l2cache.c @@ -0,0 +1,29 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#define L2CACHE_SIZE 64 + +int __init l2cache_init(void) +{ + reg_l2cache_rw_ctrl ctrl = {0}; + reg_l2cache_rw_cfg cfg = {.en = regk_l2cache_yes}; + + ctrl.csize = L2CACHE_SIZE; + ctrl.cbase = L2CACHE_SIZE / 4 + (L2CACHE_SIZE % 4 ? 1 : 0); + REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl); + + /* Flush the tag memory */ + memset((void *)(MEM_INTMEM_START | MEM_NON_CACHEABLE), 0, 2*1024); + + /* Enable the cache */ + REG_WR(l2cache, regi_l2cache, rw_cfg, cfg); + + return 0; +} + diff --git a/kernel/arch/cris/arch-v32/mm/mmu.S b/kernel/arch/cris/arch-v32/mm/mmu.S new file mode 100644 index 000000000..c0981044e --- /dev/null +++ b/kernel/arch/cris/arch-v32/mm/mmu.S @@ -0,0 +1,210 @@ +; WARNING : The refill handler has been modified, see below !!! + +/* + * Copyright (C) 2003 Axis Communications AB + * + * Authors: Mikael Starvik (starvik@axis.com) + * + * Code for the fault low-level handling routines. + * + */ + +#include +#include + +; Save all register. Must save in same order as struct pt_regs. +.macro SAVE_ALL + subq 12, $sp + move $erp, [$sp] + subq 4, $sp + move $srp, [$sp] + subq 4, $sp + move $ccs, [$sp] + subq 4, $sp + move $spc, [$sp] + subq 4, $sp + move $mof, [$sp] + subq 4, $sp + move $srs, [$sp] + subq 4, $sp + move.d $acr, [$sp] + subq 14*4, $sp + movem $r13, [$sp] + subq 4, $sp + move.d $r10, [$sp] +.endm + +; Bus fault handler. Extracts relevant information and calls mm subsystem +; to handle the fault. +.macro MMU_BUS_FAULT_HANDLER handler, mmu, we, ex + .globl \handler + .type \handler,"function" +\handler: + SAVE_ALL + move \mmu, $srs ; Select MMU support register bank + move.d $sp, $r11 ; regs + moveq 1, $r12 ; protection fault + moveq \we, $r13 ; write exception? + orq \ex << 1, $r13 ; execute? + move $s3, $r10 ; rw_mm_cause + and.d ~8191, $r10 ; Get faulting page start address + + jsr do_page_fault + nop + ba ret_from_intr + nop + .size \handler, . - \handler +.endm + +; Refill handler. Three cases may occur: +; 1. PMD and PTE exists in mm subsystem but not in TLB +; 2. PMD exists but not PTE +; 3. PMD doesn't exist +; The code below handles case 1 and calls the mm subsystem for case 2 and 3. +; Do not touch this code without very good reasons and extensive testing. +; Note that the code is optimized to minimize stalls (makes the code harder +; to read). +; +; WARNING !!! +; Modified by Mikael Asker 060725: added a workaround for strange TLB +; behavior. If the same PTE is present in more than one set, the TLB +; doesn't recognize it and we get stuck in a loop of refill exceptions. +; The workaround detects such loops and exits them by flushing +; the TLB contents. The problem and workaround were verified +; in VCS by Mikael Starvik. +; +; Each page is 8 KB. Each PMD holds 8192/4 PTEs (each PTE is 4 bytes) so each +; PMD holds 16 MB of virtual memory. +; Bits 0-12 : Offset within a page +; Bits 13-23 : PTE offset within a PMD +; Bits 24-31 : PMD offset within the PGD + +.macro MMU_REFILL_HANDLER handler, mmu + .data +1: .dword 0 ; refill_count + ; == 0 <=> last_refill_cause is invalid +2: .dword 0 ; last_refill_cause + .text + .globl \handler + .type \handler, "function" +\handler: + subq 4, $sp +; (The pipeline stalls for one cycle; $sp used as address in the next cycle.) + move $srs, [$sp] + subq 4, $sp + move \mmu, $srs ; Select MMU support register bank + move.d $acr, [$sp] + subq 12, $sp + move.d 1b, $acr ; Point to refill_count + movem $r2, [$sp] + + test.d [$acr] ; refill_count == 0 ? + beq 5f ; yes, last_refill_cause is invalid + move.d $acr, $r1 + + ; last_refill_cause is valid, investigate cause + addq 4, $r1 ; Point to last_refill_cause + move $s3, $r0 ; Get rw_mm_cause + move.d [$r1], $r2 ; Get last_refill_cause + cmp.d $r0, $r2 ; rw_mm_cause == last_refill_cause ? + beq 6f ; yes, increment count + moveq 1, $r2 + + ; rw_mm_cause != last_refill_cause + move.d $r2, [$acr] ; refill_count = 1 + move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause + +3: ; Probably not in a loop, continue normal processing + move.d current_pgd, $acr ; PGD + ; Look up PMD in PGD + lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31) + move.d [$acr], $acr ; PGD for the current process + addi $r0.d, $acr, $acr + move $s3, $r0 ; rw_mm_cause + move.d [$acr], $acr ; Get PMD + beq 8f + ; Look up PTE in PMD + lsrq PAGE_SHIFT, $r0 + and.w PAGE_MASK, $acr ; Remove PMD flags + and.d 0x7ff, $r0 ; Get PTE index into PMD (bit 13-23) + addi $r0.d, $acr, $acr + move.d [$acr], $acr ; Get PTE + beq 9f + movem [$sp], $r2 ; Restore r0-r2 in delay slot + addq 12, $sp + ; Store in TLB + move $acr, $s5 +4: ; Return + move.d [$sp+], $acr + move [$sp], $srs + addq 4, $sp + rete + rfe + +5: ; last_refill_cause is invalid + moveq 1, $r2 + addq 4, $r1 ; Point to last_refill_cause + move.d $r2, [$acr] ; refill_count = 1 + move $s3, $r0 ; Get rw_mm_cause + ba 3b ; Continue normal processing + move.d $r0,[$r1] ; last_refill_cause = rw_mm_cause + +6: ; rw_mm_cause == last_refill_cause + move.d [$acr], $r2 ; Get refill_count + cmpq 4, $r2 ; refill_count > 4 ? + bhi 7f ; yes + addq 1, $r2 ; refill_count++ + ba 3b ; Continue normal processing + move.d $r2, [$acr] + +7: ; refill_count > 4, error + move.d $acr, $r0 ; Save pointer to refill_count + clear.d [$r0] ; refill_count = 0 + + ;; rewind the short stack + movem [$sp], $r2 ; Restore r0-r2 + addq 12, $sp + move.d [$sp+], $acr + move [$sp], $srs + addq 4, $sp + ;; Keep it simple (slow), save all the regs. + SAVE_ALL + jsr __flush_tlb_all + nop + ba ret_from_intr ; Return + nop + +8: ; PMD missing, let the mm subsystem fix it up. + movem [$sp], $r2 ; Restore r0-r2 +9: ; PTE missing, let the mm subsystem fix it up. + addq 12, $sp + move.d [$sp+], $acr + move [$sp], $srs + addq 4, $sp + SAVE_ALL + move \mmu, $srs + move.d $sp, $r11 ; regs + clear.d $r12 ; Not a protection fault + move.w PAGE_MASK, $acr + move $s3, $r10 ; rw_mm_cause + btstq 9, $r10 ; Check if write access + smi $r13 + and.w PAGE_MASK, $r10 ; Get VPN (virtual address) + jsr do_page_fault + and.w $acr, $r10 + ; Return + ba ret_from_intr + nop + .size \handler, . - \handler +.endm + + ; This is the MMU bus fault handlers. + +MMU_REFILL_HANDLER i_mmu_refill, 1 +MMU_BUS_FAULT_HANDLER i_mmu_invalid, 1, 0, 0 +MMU_BUS_FAULT_HANDLER i_mmu_access, 1, 0, 0 +MMU_BUS_FAULT_HANDLER i_mmu_execute, 1, 0, 1 +MMU_REFILL_HANDLER d_mmu_refill, 2 +MMU_BUS_FAULT_HANDLER d_mmu_invalid, 2, 0, 0 +MMU_BUS_FAULT_HANDLER d_mmu_access, 2, 0, 0 +MMU_BUS_FAULT_HANDLER d_mmu_write, 2, 1, 0 diff --git a/kernel/arch/cris/arch-v32/mm/tlb.c b/kernel/arch/cris/arch-v32/mm/tlb.c new file mode 100644 index 000000000..c030d0206 --- /dev/null +++ b/kernel/arch/cris/arch-v32/mm/tlb.c @@ -0,0 +1,207 @@ +/* + * Low level TLB handling. + * + * Copyright (C) 2000-2003, Axis Communications AB. + * + * Authors: Bjorn Wesen + * Tobias Anderberg , CRISv32 port. + */ + +#include +#include +#include +#include + +#define UPDATE_TLB_SEL_IDX(val) \ +do { \ + unsigned long tlb_sel; \ + \ + tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val); \ + SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel); \ +} while(0) + +#define UPDATE_TLB_HILO(tlb_hi, tlb_lo) \ +do { \ + SUPP_REG_WR(RW_MM_TLB_HI, tlb_hi); \ + SUPP_REG_WR(RW_MM_TLB_LO, tlb_lo); \ +} while(0) + +/* + * The TLB can host up to 256 different mm contexts at the same time. The running + * context is found in the PID register. Each TLB entry contains a page_id that + * has to match the PID register to give a hit. page_id_map keeps track of which + * mm's is assigned to which page_id's, making sure it's known when to + * invalidate TLB entries. + * + * The last page_id is never running, it is used as an invalid page_id so that + * it's possible to make TLB entries that will nerver match. + * + * Note; the flushes needs to be atomic otherwise an interrupt hander that uses + * vmalloc'ed memory might cause a TLB load in the middle of a flush. + */ + +/* Flush all TLB entries. */ +void +__flush_tlb_all(void) +{ + int i; + int mmu; + unsigned long flags; + unsigned long mmu_tlb_hi; + unsigned long mmu_tlb_sel; + + /* + * Mask with 0xf so similar TLB entries aren't written in the same 4-way + * entry group. + */ + local_irq_save(flags); + + for (mmu = 1; mmu <= 2; mmu++) { + SUPP_BANK_SEL(mmu); /* Select the MMU */ + for (i = 0; i < NUM_TLB_ENTRIES; i++) { + /* Store invalid entry */ + mmu_tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, i); + + mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, INVALID_PAGEID) + | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, i & 0xf)); + + SUPP_REG_WR(RW_MM_TLB_SEL, mmu_tlb_sel); + SUPP_REG_WR(RW_MM_TLB_HI, mmu_tlb_hi); + SUPP_REG_WR(RW_MM_TLB_LO, 0); + } + } + + local_irq_restore(flags); +} + +/* Flush an entire user address space. */ +void +__flush_tlb_mm(struct mm_struct *mm) +{ + int i; + int mmu; + unsigned long flags; + unsigned long page_id; + unsigned long tlb_hi; + unsigned long mmu_tlb_hi; + + page_id = mm->context.page_id; + + if (page_id == NO_CONTEXT) + return; + + /* Mark the TLB entries that match the page_id as invalid. */ + local_irq_save(flags); + + for (mmu = 1; mmu <= 2; mmu++) { + SUPP_BANK_SEL(mmu); + for (i = 0; i < NUM_TLB_ENTRIES; i++) { + UPDATE_TLB_SEL_IDX(i); + + /* Get the page_id */ + SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi); + + /* Check if the page_id match. */ + if ((tlb_hi & 0xff) == page_id) { + mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, + INVALID_PAGEID) + | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, + i & 0xf)); + + UPDATE_TLB_HILO(mmu_tlb_hi, 0); + } + } + } + + local_irq_restore(flags); +} + +/* Invalidate a single page. */ +void +__flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) +{ + int i; + int mmu; + unsigned long page_id; + unsigned long flags; + unsigned long tlb_hi; + unsigned long mmu_tlb_hi; + + page_id = vma->vm_mm->context.page_id; + + if (page_id == NO_CONTEXT) + return; + + addr &= PAGE_MASK; + + /* + * Invalidate those TLB entries that match both the mm context and the + * requested virtual address. + */ + local_irq_save(flags); + + for (mmu = 1; mmu <= 2; mmu++) { + SUPP_BANK_SEL(mmu); + for (i = 0; i < NUM_TLB_ENTRIES; i++) { + UPDATE_TLB_SEL_IDX(i); + SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi); + + /* Check if page_id and address matches */ + if (((tlb_hi & 0xff) == page_id) && + ((tlb_hi & PAGE_MASK) == addr)) { + mmu_tlb_hi = REG_FIELD(mmu, rw_mm_tlb_hi, pid, + INVALID_PAGEID) | addr; + + UPDATE_TLB_HILO(mmu_tlb_hi, 0); + } + } + } + + local_irq_restore(flags); +} + +/* + * Initialize the context related info for a new mm_struct + * instance. + */ + +int +init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ + mm->context.page_id = NO_CONTEXT; + return 0; +} + +static DEFINE_SPINLOCK(mmu_context_lock); + +/* Called in schedule() just before actually doing the switch_to. */ +void +switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk) +{ + if (prev != next) { + int cpu = smp_processor_id(); + + /* Make sure there is a MMU context. */ + spin_lock(&mmu_context_lock); + get_mmu_context(next); + cpumask_set_cpu(cpu, mm_cpumask(next)); + spin_unlock(&mmu_context_lock); + + /* + * Remember the pgd for the fault handlers. Keep a separate + * copy of it because current and active_mm might be invalid + * at points where * there's still a need to derefer the pgd. + */ + per_cpu(current_pgd, cpu) = next->pgd; + + /* Switch context in the MMU. */ + if (tsk && task_thread_info(tsk)) { + SPEC_REG_WR(SPEC_REG_PID, next->context.page_id | + task_thread_info(tsk)->tls); + } else { + SPEC_REG_WR(SPEC_REG_PID, next->context.page_id); + } + } +} + diff --git a/kernel/arch/cris/arch-v32/output_arch.ld b/kernel/arch/cris/arch-v32/output_arch.ld new file mode 100644 index 000000000..d60a57db0 --- /dev/null +++ b/kernel/arch/cris/arch-v32/output_arch.ld @@ -0,0 +1,2 @@ +/* At the time of this writing, there's no equivalent ld option. */ +OUTPUT_ARCH (crisv32) diff --git a/kernel/arch/cris/boot/.gitignore b/kernel/arch/cris/boot/.gitignore new file mode 100644 index 000000000..171a0853c --- /dev/null +++ b/kernel/arch/cris/boot/.gitignore @@ -0,0 +1,2 @@ +Image +zImage diff --git a/kernel/arch/cris/boot/Makefile b/kernel/arch/cris/boot/Makefile new file mode 100644 index 000000000..6e3b509fd --- /dev/null +++ b/kernel/arch/cris/boot/Makefile @@ -0,0 +1,24 @@ +# +# arch/cris/boot/Makefile +# + +objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment +objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss --remove-section=.note.gnu.build-id + +OBJCOPYFLAGS = -O binary $(objcopyflags-y) + + +subdir- := compressed rescue +targets := Image + +$(obj)/Image: vmlinux FORCE + $(call if_changed,objcopy) + @echo ' Kernel: $@ is ready' + +$(obj)/compressed/vmlinux: $(obj)/Image FORCE + $(Q)$(MAKE) $(build)=$(obj)/compressed $@ + $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin + +$(obj)/zImage: $(obj)/compressed/vmlinux + @cp $< $@ + @echo ' Kernel: $@ is ready' diff --git a/kernel/arch/cris/boot/compressed/Makefile b/kernel/arch/cris/boot/compressed/Makefile new file mode 100644 index 000000000..8fe9338c1 --- /dev/null +++ b/kernel/arch/cris/boot/compressed/Makefile @@ -0,0 +1,38 @@ +# +# arch/cris/boot/compressed/Makefile +# + +asflags-y += $(LINUXINCLUDE) +ccflags-y += -O2 $(LINUXINCLUDE) + +# asflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/mach \ +# -I$(srctree)/include/asm/arch +# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -O2 -I$(srctree)/include/asm/mach +# -I$(srctree)/include/asm/arch + +arch-$(CONFIG_ETRAX_ARCH_V10) = v10 +arch-$(CONFIG_ETRAX_ARCH_V32) = v32 + +ldflags-y += -T $(srctree)/$(src)/decompress_$(arch-y).lds + +OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o +OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o +OBJECTS= $(OBJECTS-y) $(obj)/misc.o +OBJCOPYFLAGS = -O binary --remove-section=.bss + +quiet_cmd_image = BUILD $@ +cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@ + +targets := vmlinux piggy.gz decompress.o decompress.bin + +$(obj)/decompress.o: $(OBJECTS) FORCE + $(call if_changed,ld) + +$(obj)/decompress.bin: $(obj)/decompress.o FORCE + $(call if_changed,objcopy) + +$(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE + $(call if_changed,image) + +$(obj)/piggy.gz: $(obj)/../Image FORCE + $(call if_changed,gzip) diff --git a/kernel/arch/cris/boot/compressed/README b/kernel/arch/cris/boot/compressed/README new file mode 100644 index 000000000..182c5d757 --- /dev/null +++ b/kernel/arch/cris/boot/compressed/README @@ -0,0 +1,24 @@ +Creation of the self-extracting compressed kernel image (vmlinuz) +----------------------------------------------------------------- + +This can be slightly confusing because it's a process with many steps. + +The kernel object built by the arch/etrax100/Makefile, vmlinux, is split +by that makefile into text and data binary files, vmlinux.text and +vmlinux.data. + +Those files together with a ROM filesystem can be catted together and +burned into a flash or executed directly at the DRAM origin. + +They can also be catted together and compressed with gzip, which is what +happens in this makefile. Together they make up piggy.img. + +The decompressor is built into the file decompress.o. It is turned into +the binary file decompress.bin, which is catted together with piggy.img +into the file vmlinuz. It can be executed in an arbitrary place in flash. + +Be careful - it assumes some things about free locations in DRAM. It +assumes the DRAM starts at 0x40000000 and that it is at least 8 MB, +so it puts its code at 0x40700000, and initial stack at 0x40800000. + +-Bjorn diff --git a/kernel/arch/cris/boot/compressed/decompress_v10.lds b/kernel/arch/cris/boot/compressed/decompress_v10.lds new file mode 100644 index 000000000..e80f4594d --- /dev/null +++ b/kernel/arch/cris/boot/compressed/decompress_v10.lds @@ -0,0 +1,30 @@ +/* OUTPUT_FORMAT(elf32-us-cris) */ +OUTPUT_FORMAT(elf32-cris) + +MEMORY + { + dram : ORIGIN = 0x40700000, + LENGTH = 0x00100000 + } + +SECTIONS +{ + .text : + { + _stext = . ; + *(.text) + *(.rodata) + *(.rodata.*) + _etext = . ; + } > dram + .data : + { + *(.data) + _edata = . ; + } > dram + .bss : + { + *(.bss) + _end = ALIGN( 0x10 ) ; + } > dram +} diff --git a/kernel/arch/cris/boot/compressed/decompress_v32.lds b/kernel/arch/cris/boot/compressed/decompress_v32.lds new file mode 100644 index 000000000..3c837feca --- /dev/null +++ b/kernel/arch/cris/boot/compressed/decompress_v32.lds @@ -0,0 +1,30 @@ +/*#OUTPUT_FORMAT(elf32-us-cris) */ +OUTPUT_ARCH (crisv32) + +MEMORY + { + dram : ORIGIN = 0x40700000, + LENGTH = 0x00100000 + } + +SECTIONS +{ + .text : + { + _stext = . ; + *(.text) + *(.rodata) + *(.rodata.*) + _etext = . ; + } > dram + .data : + { + *(.data) + _edata = . ; + } > dram + .bss : + { + *(.bss) + _end = ALIGN( 0x10 ) ; + } > dram +} diff --git a/kernel/arch/cris/boot/compressed/head_v10.S b/kernel/arch/cris/boot/compressed/head_v10.S new file mode 100644 index 000000000..9edb8ade7 --- /dev/null +++ b/kernel/arch/cris/boot/compressed/head_v10.S @@ -0,0 +1,126 @@ +/* + * arch/cris/boot/compressed/head.S + * + * Copyright (C) 1999, 2001 Axis Communications AB + * + * Code that sets up the DRAM registers, calls the + * decompressor to unpack the piggybacked kernel, and jumps. + * + */ + +#define ASSEMBLER_MACROS_ONLY +#include + +#define RAM_INIT_MAGIC 0x56902387 +#define COMMAND_LINE_MAGIC 0x87109563 + + ;; Exported symbols + + .globl input_data + + + .text + + nop + di + +;; We need to initialze DRAM registers before we start using the DRAM + + cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? + beq dram_init_finished + nop + +#include "../../arch-v10/lib/dram_init.S" + +dram_init_finished: + + ;; Initiate the PA and PB ports + + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0 + move.b $r0, [R_PORT_PA_DATA] + + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0 + move.b $r0, [R_PORT_PA_DIR] + + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0 + move.b $r0, [R_PORT_PB_DATA] + + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0 + move.b $r0, [R_PORT_PB_DIR] + + ;; Setup the stack to a suitably high address. + ;; We assume 8 MB is the minimum DRAM in an eLinux + ;; product and put the sp at the top for now. + + move.d 0x40800000, $sp + + ;; Figure out where the compressed piggyback image is + ;; in the flash (since we wont try to copy it to DRAM + ;; before unpacking). It is at _edata, but in flash. + ;; Use (_edata - basse) as offset to the current PC. + +basse: move.d $pc, $r5 + and.d 0x7fffffff, $r5 ; strip any non-cache bit + subq 2, $r5 ; compensate for the move.d $pc instr + move.d $r5, $r0 ; save for later - flash address of 'basse' + add.d _edata, $r5 + sub.d basse, $r5 ; $r5 = flash address of '_edata' + + ;; Copy text+data to DRAM + + move.d basse, $r1 ; destination + move.d _edata, $r2 ; end destination +1: move.w [$r0+], $r3 + move.w $r3, [$r1+] + cmp.d $r2, $r1 + bcs 1b + nop + + move.d $r5, [input_data] ; for the decompressor + + + ;; Clear the decompressors BSS (between _edata and _end) + + moveq 0, $r0 + move.d _edata, $r1 + move.d _end, $r2 +1: move.w $r0, [$r1+] + cmp.d $r2, $r1 + bcs 1b + nop + + ;; Save command line magic and address. + move.d _cmd_line_magic, $r12 + move.d $r10, [$r12] + move.d _cmd_line_addr, $r12 + move.d $r11, [$r12] + + ;; Do the decompression and save compressed size in inptr + + jsr decompress_kernel + + ;; Put start address of root partition in $r9 so the kernel can use it + ;; when mounting from flash + + move.d [input_data], $r9 ; flash address of compressed kernel + add.d [inptr], $r9 ; size of compressed kernel + + ;; Restore command line magic and address. + move.d _cmd_line_magic, $r10 + move.d [$r10], $r10 + move.d _cmd_line_addr, $r11 + move.d [$r11], $r11 + + ;; Enter the decompressed kernel + move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized + jump 0x40004000 ; kernel is linked to this address + + .data + +input_data: + .dword 0 ; used by the decompressor +_cmd_line_magic: + .dword 0 +_cmd_line_addr: + .dword 0 +#include "../../arch-v10/lib/hw_settings.S" diff --git a/kernel/arch/cris/boot/compressed/head_v32.S b/kernel/arch/cris/boot/compressed/head_v32.S new file mode 100644 index 000000000..f483005f3 --- /dev/null +++ b/kernel/arch/cris/boot/compressed/head_v32.S @@ -0,0 +1,145 @@ +/* + * Code that sets up the DRAM registers, calls the + * decompressor to unpack the piggybacked kernel, and jumps. + * + * Copyright (C) 1999 - 2006, Axis Communications AB + */ + +#define ASSEMBLER_MACROS_ONLY +#include +#include + +#define RAM_INIT_MAGIC 0x56902387 +#define COMMAND_LINE_MAGIC 0x87109563 + + ;; Exported symbols + + .globl input_data + + .text +start: + di + + ;; Start clocks for used blocks. + START_CLOCKS + + ;; Initialize the DRAM registers. + cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? + beq dram_init_finished + nop + +#if defined CONFIG_ETRAXFS +#include "../../arch-v32/mach-fs/dram_init.S" +#elif defined CONFIG_CRIS_MACH_ARTPEC3 +#include "../../arch-v32/mach-a3/dram_init.S" +#else +#error Only ETRAXFS and ARTPEC-3 supported! +#endif + +dram_init_finished: + + GIO_INIT + ;; Setup the stack to a suitably high address. + ;; We assume 8 MB is the minimum DRAM and put + ;; the SP at the top for now. + + move.d 0x40800000, $sp + + ;; Figure out where the compressed piggyback image is. + ;; It is either in [NOR] flash (we don't want to copy it + ;; to DRAM before unpacking), or copied to DRAM + ;; by the [NAND] flash boot loader. + ;; The piggyback image is at _edata, but relative to where the + ;; image is actually located in memory, not where it is linked + ;; (the decompressor is linked at 0x40700000+ and runs there). + ;; Use (_edata - herami) as offset to the current PC. + +hereami: + lapcq ., $r5 ; get PC + and.d 0x7fffffff, $r5 ; strip any non-cache bit + move.d $r5, $r0 ; source address of 'herami' + add.d _edata, $r5 + sub.d hereami, $r5 ; r5 = flash address of '_edata' + move.d hereami, $r1 ; destination + + ;; Copy text+data to DRAM + + move.d _edata, $r2 ; end destination +1: move.w [$r0+], $r3 ; from herami+ source + move.w $r3, [$r1+] ; to hereami+ destination (linked address) + cmp.d $r2, $r1 ; finish when destination == _edata + bcs 1b + nop + move.d input_data, $r0 ; for the decompressor + move.d $r5, [$r0] ; for the decompressor + + ;; Clear the decompressors BSS (between _edata and _end) + + moveq 0, $r0 + move.d _edata, $r1 + move.d _end, $r2 +1: move.w $r0, [$r1+] + cmp.d $r2, $r1 + bcs 1b + nop + + ;; Save command line magic and address. + move.d _cmd_line_magic, $r0 + move.d $r10, [$r0] + move.d _cmd_line_addr, $r0 + move.d $r11, [$r0] + + ;; Save boot source indicator + move.d _boot_source, $r0 + move.d $r12, [$r0] + + ;; Do the decompression and save compressed size in _inptr + + jsr decompress_kernel + nop + + ;; Restore boot source indicator + move.d _boot_source, $r12 + move.d [$r12], $r12 + + ;; Restore command line magic and address. + move.d _cmd_line_magic, $r10 + move.d [$r10], $r10 + move.d _cmd_line_addr, $r11 + move.d [$r11], $r11 + + ;; Put start address of root partition in r9 so the kernel can use it + ;; when mounting from flash + move.d input_data, $r0 + move.d [$r0], $r9 ; flash address of compressed kernel + move.d inptr, $r0 + add.d [$r0], $r9 ; size of compressed kernel + cmp.d 0x40000000, $r9 ; image in DRAM ? + blo enter_kernel ; no, must be [NOR] flash, jump + nop ; delay slot + and.d 0x001fffff, $r9 ; assume compressed kernel was < 2M + +enter_kernel: + ;; Enter the decompressed kernel + move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized + jump 0x40004000 ; kernel is linked to this address + nop + + .data + +input_data: + .dword 0 ; used by the decompressor +_cmd_line_magic: + .dword 0 +_cmd_line_addr: + .dword 0 +_boot_source: + .dword 0 + +#if defined CONFIG_ETRAXFS +#include "../../arch-v32/mach-fs/hw_settings.S" +#elif defined CONFIG_CRIS_MACH_ARTPEC3 +#include "../../arch-v32/mach-a3/hw_settings.S" +#else +#error Only ETRAXFS and ARTPEC-3 supported! +#endif diff --git a/kernel/arch/cris/boot/compressed/misc.c b/kernel/arch/cris/boot/compressed/misc.c new file mode 100644 index 000000000..548d886b0 --- /dev/null +++ b/kernel/arch/cris/boot/compressed/misc.c @@ -0,0 +1,376 @@ +/* + * misc.c + * + * This is a collection of several routines from gzip-1.0.3 + * adapted for Linux. + * + * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 + * puts by Nick Holloway 1993, better puts by Martin Mares 1995 + * adaptation for Linux/CRIS Axis Communications AB, 1999 + * + */ + +/* where the piggybacked kernel image expects itself to live. + * it is the same address we use when we network load an uncompressed + * image into DRAM, and it is the address the kernel is linked to live + * at by vmlinux.lds.S + */ + +#define KERNEL_LOAD_ADR 0x40004000 + +#include + +#ifdef CONFIG_ETRAX_ARCH_V32 +#include +#include +#include +#include +#ifdef CONFIG_CRIS_MACH_ARTPEC3 +#include +#endif +#else +#include +#endif + +/* + * gzip declarations + */ + +#define OF(args) args +#define STATIC static + +void *memset(void *s, int c, size_t n); +void *memcpy(void *__dest, __const void *__src, size_t __n); + +#define memzero(s, n) memset((s), 0, (n)) + +typedef unsigned char uch; +typedef unsigned short ush; +typedef unsigned long ulg; + +#define WSIZE 0x8000 /* Window size must be at least 32k, */ + /* and a power of two */ + +static uch *inbuf; /* input buffer */ +static uch window[WSIZE]; /* Sliding window buffer */ + +unsigned inptr = 0; /* index of next byte to be processed in inbuf + * After decompression it will contain the + * compressed size, and head.S will read it. + */ + +static unsigned outcnt = 0; /* bytes in output buffer */ + +/* gzip flag byte */ +#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */ +#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ +#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ +#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ +#define COMMENT 0x10 /* bit 4 set: file comment present */ +#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ +#define RESERVED 0xC0 /* bit 6,7: reserved */ + +#define get_byte() (inbuf[inptr++]) + +/* Diagnostic functions */ +#ifdef DEBUG +# define Assert(cond, msg) do { \ + if (!(cond)) \ + error(msg); \ + } while (0) +# define Trace(x) fprintf x +# define Tracev(x) do { \ + if (verbose) \ + fprintf x; \ + } while (0) +# define Tracevv(x) do { \ + if (verbose > 1) \ + fprintf x; \ + } while (0) +# define Tracec(c, x) do { \ + if (verbose && (c)) \ + fprintf x; \ + } while (0) +# define Tracecv(c, x) do { \ + if (verbose > 1 && (c)) \ + fprintf x; \ + } while (0) +#else +# define Assert(cond, msg) +# define Trace(x) +# define Tracev(x) +# define Tracevv(x) +# define Tracec(c, x) +# define Tracecv(c, x) +#endif + +static void flush_window(void); +static void error(char *m); +static void aputs(const char *s); + +extern char *input_data; /* lives in head.S */ + +static long bytes_out; +static uch *output_data; +static unsigned long output_ptr; + +/* the "heap" is put directly after the BSS ends, at end */ + +extern int _end; +static long free_mem_ptr = (long)&_end; +static long free_mem_end_ptr; + +#include "../../../../../lib/inflate.c" + +/* decompressor info and error messages to serial console */ + +#ifdef CONFIG_ETRAX_ARCH_V32 +static inline void serout(const char *s, reg_scope_instances regi_ser) +{ + reg_ser_rs_stat_din rs; + reg_ser_rw_dout dout = {.data = *s}; + + do { + rs = REG_RD(ser, regi_ser, rs_stat_din); + } + while (!rs.tr_rdy);/* Wait for transceiver. */ + + REG_WR(ser, regi_ser, rw_dout, dout); +} +#define SEROUT(S, N) \ + do { \ + serout(S, regi_ser ## N); \ + s++; \ + } while (0) +#else +#define SEROUT(S, N) do { \ + while (!(*R_SERIAL ## N ## _STATUS & (1 << 5))) \ + ; \ + *R_SERIAL ## N ## _TR_DATA = *s++; \ + } while (0) +#endif + +static void aputs(const char *s) +{ +#ifndef CONFIG_ETRAX_DEBUG_PORT_NULL + while (*s) { +#ifdef CONFIG_ETRAX_DEBUG_PORT0 + SEROUT(s, 0); +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT1 + SEROUT(s, 1); +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT2 + SEROUT(s, 2); +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT3 + SEROUT(s, 3); +#endif + } +#endif /* CONFIG_ETRAX_DEBUG_PORT_NULL */ +} + +void *memset(void *s, int c, size_t n) +{ + int i; + char *ss = (char*)s; + + for (i=0;i> 8); + } + crc = c; + bytes_out += (ulg)outcnt; + output_ptr += (ulg)outcnt; + outcnt = 0; +} + +static void error(char *x) +{ + aputs("\n\n"); + aputs(x); + aputs("\n\n -- System halted\n"); + + while(1); /* Halt */ +} + +void setup_normal_output_buffer(void) +{ + output_data = (char *)KERNEL_LOAD_ADR; +} + +#ifdef CONFIG_ETRAX_ARCH_V32 +static inline void serial_setup(reg_scope_instances regi_ser) +{ + reg_ser_rw_xoff xoff; + reg_ser_rw_tr_ctrl tr_ctrl; + reg_ser_rw_rec_ctrl rec_ctrl; + reg_ser_rw_tr_baud_div tr_baud; + reg_ser_rw_rec_baud_div rec_baud; + + /* Turn off XOFF. */ + xoff = REG_RD(ser, regi_ser, rw_xoff); + + xoff.chr = 0; + xoff.automatic = regk_ser_no; + + REG_WR(ser, regi_ser, rw_xoff, xoff); + + /* Set baudrate and stopbits. */ + tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); + rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); + tr_baud = REG_RD(ser, regi_ser, rw_tr_baud_div); + rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div); + + tr_ctrl.stop_bits = 1; /* 2 stop bits. */ + tr_ctrl.en = 1; /* enable transmitter */ + rec_ctrl.en = 1; /* enabler receiver */ + + /* + * The baudrate setup used to be a bit fishy, but now transmitter and + * receiver are both set to the intended baud rate, 115200. + * The magic value is 29.493 MHz. + */ + tr_ctrl.base_freq = regk_ser_f29_493; + rec_ctrl.base_freq = regk_ser_f29_493; + tr_baud.div = (29493000 / 8) / 115200; + rec_baud.div = (29493000 / 8) / 115200; + + REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); + REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud); + REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); + REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud); +} +#endif + +void decompress_kernel(void) +{ + char revision; + char compile_rev; + +#ifdef CONFIG_ETRAX_ARCH_V32 + /* Need at least a CRISv32 to run. */ + compile_rev = 32; +#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \ + defined(CONFIG_ETRAX_DEBUG_PORT2) || \ + defined(CONFIG_ETRAX_DEBUG_PORT3) + reg_pinmux_rw_hwprot hwprot; + +#ifdef CONFIG_CRIS_MACH_ARTPEC3 + reg_clkgen_rw_clk_ctrl clk_ctrl; + + /* Enable corresponding clock region when serial 1..3 selected */ + + clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); + clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; + REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); +#endif + + /* pinmux setup for ports 1..3 */ + hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); +#endif + + +#ifdef CONFIG_ETRAX_DEBUG_PORT0 + serial_setup(regi_ser0); +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT1 + hwprot.ser1 = regk_pinmux_yes; + serial_setup(regi_ser1); +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT2 + hwprot.ser2 = regk_pinmux_yes; + serial_setup(regi_ser2); +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT3 + hwprot.ser3 = regk_pinmux_yes; + serial_setup(regi_ser3); +#endif +#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \ + defined(CONFIG_ETRAX_DEBUG_PORT2) || \ + defined(CONFIG_ETRAX_DEBUG_PORT3) + REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); +#endif + + /* input_data is set in head.S */ + inbuf = input_data; +#else /* CRISv10 */ + /* Need at least a crisv10 to run. */ + compile_rev = 10; + + /* input_data is set in head.S */ + inbuf = input_data; + +#ifdef CONFIG_ETRAX_DEBUG_PORT0 + *R_SERIAL0_XOFF = 0; + *R_SERIAL0_BAUD = 0x99; + *R_SERIAL0_TR_CTRL = 0x40; +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT1 + *R_SERIAL1_XOFF = 0; + *R_SERIAL1_BAUD = 0x99; + *R_SERIAL1_TR_CTRL = 0x40; +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT2 + *R_GEN_CONFIG = 0x08; + *R_SERIAL2_XOFF = 0; + *R_SERIAL2_BAUD = 0x99; + *R_SERIAL2_TR_CTRL = 0x40; +#endif +#ifdef CONFIG_ETRAX_DEBUG_PORT3 + *R_GEN_CONFIG = 0x100; + *R_SERIAL3_XOFF = 0; + *R_SERIAL3_BAUD = 0x99; + *R_SERIAL3_TR_CTRL = 0x40; +#endif +#endif + + setup_normal_output_buffer(); + + makecrc(); + + __asm__ volatile ("move $vr,%0" : "=rm" (revision)); + if (revision < compile_rev) { +#ifdef CONFIG_ETRAX_ARCH_V32 + aputs("You need at least ETRAX FS to run Linux 2.6/crisv32\n"); +#else + aputs("You need an ETRAX 100LX to run linux 2.6/crisv10\n"); +#endif + while(1); + } + + aputs("Uncompressing Linux...\n"); + gunzip(); + aputs("Done. Now booting the kernel\n"); +} diff --git a/kernel/arch/cris/boot/dts/Makefile b/kernel/arch/cris/boot/dts/Makefile new file mode 100644 index 000000000..faf69fb99 --- /dev/null +++ b/kernel/arch/cris/boot/dts/Makefile @@ -0,0 +1,6 @@ +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o +ifneq ($(CONFIG_BUILTIN_DTB),"") +obj-$(CONFIG_OF) += $(BUILTIN_DTB) +endif + +clean-files := *.dtb.S diff --git a/kernel/arch/cris/boot/dts/dev88.dts b/kernel/arch/cris/boot/dts/dev88.dts new file mode 100644 index 000000000..4fa5a3f9d --- /dev/null +++ b/kernel/arch/cris/boot/dts/dev88.dts @@ -0,0 +1,18 @@ +/dts-v1/; + +/include/ "etraxfs.dtsi" + +/ { + model = "Axis 88 Developer Board"; + compatible = "axis,dev88"; + + aliases { + serial0 = &uart0; + }; + + soc { + uart0: serial@b00260000 { + status = "okay"; + }; + }; +}; diff --git a/kernel/arch/cris/boot/dts/etraxfs.dtsi b/kernel/arch/cris/boot/dts/etraxfs.dtsi new file mode 100644 index 000000000..909bcedc3 --- /dev/null +++ b/kernel/arch/cris/boot/dts/etraxfs.dtsi @@ -0,0 +1,38 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "axis,crisv32"; + reg = <0>; + }; + }; + + soc { + compatible = "simple-bus"; + model = "etraxfs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller { + compatible = "axis,crisv32-intc"; + reg = <0xb001c000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + serial@b00260000 { + compatible = "axis,etraxfs-uart"; + reg = <0xb0026000 0x1000>; + interrupts = <68>; + status = "disabled"; + }; + }; +}; diff --git a/kernel/arch/cris/boot/rescue/Makefile b/kernel/arch/cris/boot/rescue/Makefile new file mode 100644 index 000000000..52bd0bd1d --- /dev/null +++ b/kernel/arch/cris/boot/rescue/Makefile @@ -0,0 +1,47 @@ +# +# Makefile for rescue (bootstrap) code +# + +# CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE) +# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/arch/mach/ \ +# -I$(srctree)/include/asm/arch +# asflags-y += -I $(srctree)/include/asm/arch/mach/ -I $(srctree)/include/asm/arch +# LD = gcc-cris -mlinux -march=v32 -nostdlib + +asflags-y += $(LINUXINCLUDE) +ccflags-y += -O2 $(LINUXINCLUDE) +arch-$(CONFIG_ETRAX_ARCH_V10) = v10 +arch-$(CONFIG_ETRAX_ARCH_V32) = v32 + +ldflags-y += -T $(srctree)/$(src)/rescue_$(arch-y).lds +OBJCOPYFLAGS = -O binary --remove-section=.bss +obj-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o +obj-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o +OBJECTS := $(obj-y) + +targets := rescue.o rescue.bin + +$(obj)/rescue.o: $(OBJECTS) FORCE + $(call if_changed,ld) + +$(obj)/rescue.bin: $(obj)/rescue.o FORCE + $(call if_changed,objcopy) + cp -p $(obj)/rescue.bin $(objtree) + +$(obj)/testrescue.bin: $(obj)/testrescue.o + $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/testrescue.o tr.bin +# Pad it to 784 bytes + dd if=/dev/zero of=tmp2423 bs=1 count=784 + cat tr.bin tmp2423 >testrescue_tmp.bin + dd if=testrescue_tmp.bin of=$(obj)/testrescue.bin bs=1 count=784 + rm tr.bin tmp2423 testrescue_tmp.bin + + +$(obj)/kimagerescue.bin: $(obj)/kimagerescue.o + $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/kimagerescue.o ktr.bin +# Pad it to 784 bytes, that's what the rescue loader expects + dd if=/dev/zero of=tmp2423 bs=1 count=784 + cat ktr.bin tmp2423 >kimagerescue_tmp.bin + dd if=kimagerescue_tmp.bin of=$(obj)/kimagerescue.bin bs=1 count=784 + rm ktr.bin tmp2423 kimagerescue_tmp.bin + diff --git a/kernel/arch/cris/boot/rescue/head_v10.S b/kernel/arch/cris/boot/rescue/head_v10.S new file mode 100644 index 000000000..af55df099 --- /dev/null +++ b/kernel/arch/cris/boot/rescue/head_v10.S @@ -0,0 +1,360 @@ +/* + * Rescue code, made to reside at the beginning of the + * flash-memory. when it starts, it checks a partition + * table at the first sector after the rescue sector. + * the partition table was generated by the product builder + * script and contains offsets, lengths, types and checksums + * for each partition that this code should check. + * + * If any of the checksums fail, we assume the flash is so + * corrupt that we can't use it to boot into the ftp flash + * loader, and instead we initialize the serial port to + * receive a flash-loader and new flash image. we dont include + * any flash code here, but just accept a certain amount of + * bytes from the serial port and jump into it. the downloaded + * code is put in the cache. + * + * The partitiontable is designed so that it is transparent to + * code execution - it has a relative branch opcode in the + * beginning that jumps over it. each entry contains extra + * data so we can add stuff later. + * + * Partition table format: + * + * Code transparency: + * + * 2 bytes [opcode 'nop'] + * 2 bytes [opcode 'di'] + * 4 bytes [opcode 'ba ', 8-bit or 16-bit version] + * 2 bytes [opcode 'nop', delay slot] + * + * Table validation (at +10): + * + * 2 bytes [magic/version word for partitiontable - 0xef, 0xbe] + * 2 bytes [length of all entries plus the end marker] + * 4 bytes [checksum for the partitiontable itself] + * + * Entries, each with the following format, last has offset -1: + * + * 4 bytes [offset in bytes, from start of flash] + * 4 bytes [length in bytes of partition] + * 4 bytes [checksum, simple longword sum] + * 2 bytes [partition type] + * 2 bytes [flags, only bit 0 used, ro/rw = 1/0] + * 16 bytes [reserved for future use] + * + * End marker + * + * 4 bytes [-1] + * + * 10 bytes [0, padding] + * + * Bit 0 in flags signifies RW or RO. The rescue code only bothers + * to check the checksum for RO partitions, since the others will + * change their data without updating the checksums. A 1 in bit 0 + * means RO, 0 means RW. That way, it is possible to set a partition + * in RO mode initially, and later mark it as RW, since you can always + * write 0's to the flash. + * + * During the wait for serial input, the status LED will flash so the + * user knows something went wrong. + * + * Copyright (C) 1999-2007 Axis Communications AB + */ + +#ifdef CONFIG_ETRAX_AXISFLASHMAP + +#define ASSEMBLER_MACROS_ONLY +#include + + ;; The partitiontable is looked for at the first sector after the boot + ;; sector. Sector size is 65536 bytes in all flashes we use. + +#define PTABLE_START CONFIG_ETRAX_PTABLE_SECTOR +#define PTABLE_MAGIC 0xbeef + + ;; The normal Etrax100 on-chip boot ROM does serial boot at 0x380000f0. + ;; That is not where we put our downloaded serial boot-code. + ;; The length is enough for downloading code that loads the rest + ;; of itself (after having setup the DRAM etc). + ;; It is the same length as the on-chip ROM loads, so the same + ;; host loader can be used to load a rescued product as well as + ;; one booted through the Etrax serial boot code. + +#define CODE_START 0x40000000 +#define CODE_LENGTH 784 + +#ifdef CONFIG_ETRAX_RESCUE_SER0 +#define SERXOFF R_SERIAL0_XOFF +#define SERBAUD R_SERIAL0_BAUD +#define SERRECC R_SERIAL0_REC_CTRL +#define SERRDAT R_SERIAL0_REC_DATA +#define SERSTAT R_SERIAL0_STATUS +#endif +#ifdef CONFIG_ETRAX_RESCUE_SER1 +#define SERXOFF R_SERIAL1_XOFF +#define SERBAUD R_SERIAL1_BAUD +#define SERRECC R_SERIAL1_REC_CTRL +#define SERRDAT R_SERIAL1_REC_DATA +#define SERSTAT R_SERIAL1_STATUS +#endif +#ifdef CONFIG_ETRAX_RESCUE_SER2 +#define SERXOFF R_SERIAL2_XOFF +#define SERBAUD R_SERIAL2_BAUD +#define SERRECC R_SERIAL2_REC_CTRL +#define SERRDAT R_SERIAL2_REC_DATA +#define SERSTAT R_SERIAL2_STATUS +#endif +#ifdef CONFIG_ETRAX_RESCUE_SER3 +#define SERXOFF R_SERIAL3_XOFF +#define SERBAUD R_SERIAL3_BAUD +#define SERRECC R_SERIAL3_REC_CTRL +#define SERRDAT R_SERIAL3_REC_DATA +#define SERSTAT R_SERIAL3_STATUS +#endif + +#define NOP_DI 0xf025050f +#define RAM_INIT_MAGIC 0x56902387 + + .text + + ;; This is the entry point of the rescue code + ;; 0x80000000 if loaded in flash (as it should be) + ;; Since etrax actually starts at address 2 when booting from flash, we + ;; put a nop (2 bytes) here first so we dont accidentally skip the di + + nop + di + + jump in_cache ; enter cached area instead +in_cache: + + + ;; First put a jump test to give a possibility of upgrading the + ;; rescue code without erasing/reflashing the sector. + ;; We put a longword of -1 here and if it is not -1, we jump using + ;; the value as jump target. Since we can always change 1's to 0's + ;; without erasing the sector, it is possible to add new + ;; code after this and altering the jumptarget in an upgrade. + +jtcd: move.d [jumptarget], $r0 + cmp.d 0xffffffff, $r0 + beq no_newjump + nop + + jump [$r0] + +jumptarget: + .dword 0xffffffff ; can be overwritten later to insert new code + +no_newjump: +#ifdef CONFIG_ETRAX_ETHERNET + ;; Start MII clock to make sure it is running when tranceiver is reset + move.d 0x3, $r0 ; enable = on, phy = mii_clk + move.d $r0, [R_NETWORK_GEN_CONFIG] +#endif + + ;; We need to setup the bus registers before we start using the DRAM +#include "../../../arch-v10/lib/dram_init.S" + + ;; we now should go through the checksum-table and check the listed + ;; partitions for errors. + + move.d PTABLE_START, $r3 + move.d [$r3], $r0 + cmp.d NOP_DI, $r0 ; make sure the nop/di is there... + bne do_rescue + nop + + ;; skip the code transparency block (10 bytes). + + addq 10, $r3 + + ;; check for correct magic + + move.w [$r3+], $r0 + cmp.w PTABLE_MAGIC, $r0 + bne do_rescue ; didn't recognize - trig rescue + nop + + ;; check for correct ptable checksum + + movu.w [$r3+], $r2 ; ptable length + move.d $r2, $r8 ; save for later, length of total ptable + addq 28, $r8 ; account for the rest + move.d [$r3+], $r4 ; ptable checksum + move.d $r3, $r1 + jsr checksum ; r1 source, r2 length, returns in r0 + + cmp.d $r0, $r4 + bne do_rescue ; didn't match - trig rescue + nop + + ;; ptable is ok. validate each entry. + + moveq -1, $r7 + +ploop: move.d [$r3+], $r1 ; partition offset (from ptable start) + bne notfirst ; check if it is the partition containing ptable + nop ; yes.. + move.d $r8, $r1 ; for its checksum check, skip the ptable + move.d [$r3+], $r2 ; partition length + sub.d $r8, $r2 ; minus the ptable length + ba bosse + nop +notfirst: + cmp.d -1, $r1 ; the end of the ptable ? + beq flash_ok ; if so, the flash is validated + move.d [$r3+], $r2 ; partition length +bosse: move.d [$r3+], $r5 ; checksum + move.d [$r3+], $r4 ; type and flags + addq 16, $r3 ; skip the reserved bytes + btstq 16, $r4 ; check ro flag + bpl ploop ; rw partition, skip validation + nop + btstq 17, $r4 ; check bootable flag + bpl 1f + nop + move.d $r1, $r7 ; remember boot partition offset +1: + add.d PTABLE_START, $r1 + + jsr checksum ; checksum the partition + + cmp.d $r0, $r5 + beq ploop ; checksums matched, go to next entry + nop + + ;; otherwise fall through to the rescue code. + +do_rescue: + ;; setup port PA and PB default initial directions and data + ;; (so we can flash LEDs, and so that DTR and others are set) + + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0 + move.b $r0, [R_PORT_PA_DIR] + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0 + move.b $r0, [R_PORT_PA_DATA] + + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0 + move.b $r0, [R_PORT_PB_DIR] + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0 + move.b $r0, [R_PORT_PB_DATA] + + ;; setup the serial port at 115200 baud + + moveq 0, $r0 + move.d $r0, [SERXOFF] + + move.b 0x99, $r0 + move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit and receive + + move.b 0x40, $r0 ; rec enable + move.b $r0, [SERRECC] + + moveq 0, $r1 ; "timer" to clock out a LED red flash + move.d CODE_START, $r3 ; destination counter + movu.w CODE_LENGTH, $r4; length + +wait_ser: + addq 1, $r1 +#ifndef CONFIG_ETRAX_NO_LEDS +#ifdef CONFIG_ETRAX_PA_LEDS + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2 +#endif +#ifdef CONFIG_ETRAX_PB_LEDS + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2 +#endif + move.d (1 << CONFIG_ETRAX_LED1R) | (1 << CONFIG_ETRAX_LED2R), $r0 + btstq 16, $r1 + bpl 1f + nop + or.d $r0, $r2 ; set bit + ba 2f + nop +1: not $r0 ; clear bit + and.d $r0, $r2 +2: +#ifdef CONFIG_ETRAX_PA_LEDS + move.b $r2, [R_PORT_PA_DATA] +#endif +#ifdef CONFIG_ETRAX_PB_LEDS + move.b $r2, [R_PORT_PB_DATA] +#endif +#ifdef CONFIG_ETRAX_90000000_LEDS + move.b $r2, [0x90000000] +#endif +#endif + + ;; check if we got something on the serial port + + move.b [SERSTAT], $r0 + btstq 0, $r0 ; data_avail + bpl wait_ser + nop + + ;; got something - copy the byte and loop + + move.b [SERRDAT], $r0 + move.b $r0, [$r3+] + + subq 1, $r4 ; decrease length + bne wait_ser + nop + + ;; jump into downloaded code + + move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is + ; initialized + jump CODE_START + +flash_ok: + ;; check r7, which contains either -1 or the partition to boot from + + cmp.d -1, $r7 + bne 1f + nop + move.d PTABLE_START, $r7; otherwise use the ptable start +1: + move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is + ; initialized + jump $r7 ; boot! + + + ;; Helper subroutines + + ;; Will checksum by simple addition + ;; r1 - source + ;; r2 - length in bytes + ;; result will be in r0 +checksum: + moveq 0, $r0 + moveq CONFIG_ETRAX_FLASH1_SIZE, $r6 + + ;; If the first physical flash memory is exceeded wrap to the + ;; second one + btstq 26, $r1 ; Are we addressing first flash? + bpl 1f + nop + clear.d $r6 + +1: test.d $r6 ; 0 = no wrapping + beq 2f + nop + lslq 20, $r6 ; Convert MB to bytes + sub.d $r1, $r6 + +2: addu.b [$r1+], $r0 + subq 1, $r6 ; Flash memory left + beq 3f + subq 1, $r2 ; Length left + bne 2b + nop + ret + nop + +3: move.d MEM_CSE1_START, $r1 ; wrap to second flash + ba 2b + nop + +#endif diff --git a/kernel/arch/cris/boot/rescue/head_v32.S b/kernel/arch/cris/boot/rescue/head_v32.S new file mode 100644 index 000000000..5f846b770 --- /dev/null +++ b/kernel/arch/cris/boot/rescue/head_v32.S @@ -0,0 +1,26 @@ +/* + * Just get started by jumping to CONFIG_ETRAX_PTABLE_SECTOR to start + * kernel decompressor. + * + * In practice, this only works for NOR flash (or some convoluted RAM boot) + * and hence is not really useful for Artpec-3, so it's Etrax FS / NOR only. + * + */ + +#include + +#ifdef CONFIG_ETRAX_AXISFLASHMAP + +;; Code + + .text +start: + + ;; Start clocks for used blocks. + START_CLOCKS + + move.d CONFIG_ETRAX_PTABLE_SECTOR, $r10 + jump $r10 ; Jump to decompressor + nop + +#endif diff --git a/kernel/arch/cris/boot/rescue/kimagerescue.S b/kernel/arch/cris/boot/rescue/kimagerescue.S new file mode 100644 index 000000000..655b511fe --- /dev/null +++ b/kernel/arch/cris/boot/rescue/kimagerescue.S @@ -0,0 +1,141 @@ +/* + * Rescue code to be prepended on a kimage and copied to the + * rescue serial port. + * This is called from the rescue code, it will copy received data to + * 4004000 and after a timeout jump to it. + */ + +#define ASSEMBLER_MACROS_ONLY +#include + +#define CODE_START 0x40004000 +#define CODE_LENGTH 784 +#define TIMEOUT_VALUE 1000 + + +#ifdef CONFIG_ETRAX_RESCUE_SER0 +#define SERXOFF R_SERIAL0_XOFF +#define SERBAUD R_SERIAL0_BAUD +#define SERRECC R_SERIAL0_REC_CTRL +#define SERRDAT R_SERIAL0_REC_DATA +#define SERSTAT R_SERIAL0_STATUS +#endif +#ifdef CONFIG_ETRAX_RESCUE_SER1 +#define SERXOFF R_SERIAL1_XOFF +#define SERBAUD R_SERIAL1_BAUD +#define SERRECC R_SERIAL1_REC_CTRL +#define SERRDAT R_SERIAL1_REC_DATA +#define SERSTAT R_SERIAL1_STATUS +#endif +#ifdef CONFIG_ETRAX_RESCUE_SER2 +#define SERXOFF R_SERIAL2_XOFF +#define SERBAUD R_SERIAL2_BAUD +#define SERRECC R_SERIAL2_REC_CTRL +#define SERRDAT R_SERIAL2_REC_DATA +#define SERSTAT R_SERIAL2_STATUS +#endif +#ifdef CONFIG_ETRAX_RESCUE_SER3 +#define SERXOFF R_SERIAL3_XOFF +#define SERBAUD R_SERIAL3_BAUD +#define SERRECC R_SERIAL3_REC_CTRL +#define SERRDAT R_SERIAL3_REC_DATA +#define SERSTAT R_SERIAL3_STATUS +#endif + + .text + ;; This is the entry point of the rescue code + ;; 0x80000000 if loaded in flash (as it should be) + ;; since etrax actually starts at address 2 when booting from flash, we + ;; put a nop (2 bytes) here first so we dont accidentally skip the di + + nop + di + ;; setup port PA and PB default initial directions and data + ;; (so we can flash LEDs, and so that DTR and others are set) + + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0 + move.b $r0, [R_PORT_PA_DIR] + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0 + move.b $r0, [R_PORT_PA_DATA] + + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0 + move.b $r0, [R_PORT_PB_DIR] + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0 + move.b $r0, [R_PORT_PB_DATA] + + ;; We need to setup the bus registers before we start using the DRAM +#include "../../lib/dram_init.S" + + ;; Setup the stack to a suitably high address. + ;; We assume 8 MB is the minimum DRAM in an eLinux + ;; product and put the sp at the top for now. + + move.d 0x40800000, $sp + + ;; setup the serial port at 115200 baud + + moveq 0, $r0 + move.d $r0, [SERXOFF] + + move.b 0x99, $r0 + move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit + ; and receive + + move.b 0x40, $r0 ; rec enable + move.b $r0, [SERRECC] + + + moveq 0, $r1 ; "timer" to clock out a LED red flash + move.d CODE_START, $r3 ; destination counter + move.d CODE_LENGTH, $r4 ; length + move.d TIMEOUT_VALUE, $r5 ; "timeout" until jump + +wait_ser: + addq 1, $r1 + subq 1, $r5 ; decrease timeout + beq jump_start ; timed out + nop +#ifndef CONFIG_ETRAX_NO_LEDS +#ifdef CONFIG_ETRAX_PA_LEDS + move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2 +#endif +#ifdef CONFIG_ETRAX_PB_LEDS + move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2 +#endif + move.d (1 << CONFIG_ETRAX_LED1R) | (1 << CONFIG_ETRAX_LED2R), $r0 + btstq 16, $r1 + bpl 1f + nop + or.d $r0, $r2 ; set bit + ba 2f + nop +1: not $r0 ; clear bit + and.d $r0, $r2 +2: +#ifdef CONFIG_ETRAX_PA_LEDS + move.b $r2, [R_PORT_PA_DATA] +#endif +#ifdef CONFIG_ETRAX_PB_LEDS + move.b $r2, [R_PORT_PB_DATA] +#endif +#endif + + ;; check if we got something on the serial port + + move.b [SERSTAT], $r0 + btstq 0, $r0 ; data_avail + bpl wait_ser + nop + + ;; got something - copy the byte and loop + + move.b [SERRDAT], $r0 + move.b $r0, [$r3+] + move.d TIMEOUT_VALUE, $r5 ; reset "timeout" + subq 1, $r4 ; decrease length + bne wait_ser + nop +jump_start: + ;; jump into downloaded code + + jump CODE_START diff --git a/kernel/arch/cris/boot/rescue/rescue_v10.lds b/kernel/arch/cris/boot/rescue/rescue_v10.lds new file mode 100644 index 000000000..0b52a9490 --- /dev/null +++ b/kernel/arch/cris/boot/rescue/rescue_v10.lds @@ -0,0 +1,20 @@ +MEMORY + { + flash : ORIGIN = 0x00000000, + LENGTH = 0x00100000 + } + +SECTIONS +{ + .text : + { + stext = . ; + *(.text) + etext = . ; + } > flash + .data : + { + *(.data) + edata = . ; + } > flash +} diff --git a/kernel/arch/cris/boot/rescue/rescue_v32.lds b/kernel/arch/cris/boot/rescue/rescue_v32.lds new file mode 100644 index 000000000..8ac646bc1 --- /dev/null +++ b/kernel/arch/cris/boot/rescue/rescue_v32.lds @@ -0,0 +1,43 @@ +/*#OUTPUT_FORMAT(elf32-us-cris) */ +OUTPUT_ARCH (crisv32) +/* Now that NAND support has been stripped, this file could be simplified, + * but it doesn't do any harm on the other hand so why bother. */ + +MEMORY + { + bootblk : ORIGIN = 0x38000000, + LENGTH = 0x00004000 + intmem : ORIGIN = 0x38004000, + LENGTH = 0x00005000 + } + +SECTIONS +{ + .text : + { + _stext = . ; + *(.text) + *(.init.text) + *(.rodata) + *(.rodata.*) + _etext = . ; + } > bootblk + .data : + { + *(.data) + _edata = . ; + } > bootblk + .bss : + { + _bss = . ; + *(.bss) + _end = ALIGN( 0x10 ) ; + } > intmem + + /* Get rid of stuff from EXPORT_SYMBOL(foo). */ + /DISCARD/ : + { + *(__ksymtab_strings) + *(__ksymtab) + } +} diff --git a/kernel/arch/cris/boot/rescue/testrescue.S b/kernel/arch/cris/boot/rescue/testrescue.S new file mode 100644 index 000000000..fc7ec674e --- /dev/null +++ b/kernel/arch/cris/boot/rescue/testrescue.S @@ -0,0 +1,24 @@ +/* + * Simple testcode to download by the rescue block. + * Just lights some LEDs to show it was downloaded correctly. + * + * Copyright (C) 1999 Axis Communications AB + */ + +#define ASSEMBLER_MACROS_ONLY +#include + + .text + + nop + nop + moveq -1, $r2 + move.b $r2, [R_PORT_PA_DIR] + moveq 0, $r2 + move.b $r2, [R_PORT_PA_DATA] + +endless: + nop + ba endless + nop + diff --git a/kernel/arch/cris/boot/tools/build.c b/kernel/arch/cris/boot/tools/build.c new file mode 100644 index 000000000..c8adef364 --- /dev/null +++ b/kernel/arch/cris/boot/tools/build.c @@ -0,0 +1,287 @@ +/* + * linux/tools/build.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* + * This file builds a disk-image from three different files: + * + * - bootsect: exactly 512 bytes of 8086 machine code, loads the rest + * - setup: 8086 machine code, sets up system parm + * - system: 80386 code for actual system + * + * It does some checking that all files are of the correct type, and + * just writes the result to stdout, removing headers and padding to + * the right amount. It also writes some system data to stderr. + */ + +/* + * Changes by tytso to allow root device specification + * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996 + * Cross compiling fixes by Gertjan van Wingerde, July 1996 + */ + +#include /* fprintf */ +#include +#include /* contains exit */ +#include /* unistd.h needs this */ +#include +#include +#include /* contains read/write */ +#include +#include + +#define MINIX_HEADER 32 + +#define N_MAGIC_OFFSET 1024 +#ifndef __BFD__ +static int GCC_HEADER = sizeof(struct exec); +#endif + +#ifdef __BIG_KERNEL__ +#define SYS_SIZE 0xffff +#else +#define SYS_SIZE DEF_SYSSIZE +#endif + +#define DEFAULT_MAJOR_ROOT 0 +#define DEFAULT_MINOR_ROOT 0 + +/* max nr of sectors of setup: don't change unless you also change + * bootsect etc */ +#define SETUP_SECTS 4 + +#define STRINGIFY(x) #x + +typedef union { + int i; + long l; + short s[2]; + char b[4]; +} conv; + +long intel_long(long l) +{ + conv t; + + t.b[0] = l & 0xff; l >>= 8; + t.b[1] = l & 0xff; l >>= 8; + t.b[2] = l & 0xff; l >>= 8; + t.b[3] = l & 0xff; l >>= 8; + return t.l; +} + +int intel_int(int i) +{ + conv t; + + t.b[0] = i & 0xff; i >>= 8; + t.b[1] = i & 0xff; i >>= 8; + t.b[2] = i & 0xff; i >>= 8; + t.b[3] = i & 0xff; i >>= 8; + return t.i; +} + +short intel_short(short l) +{ + conv t; + + t.b[0] = l & 0xff; l >>= 8; + t.b[1] = l & 0xff; l >>= 8; + return t.s[0]; +} + +void die(const char * str) +{ + fprintf(stderr,"%s\n",str); + exit(1); +} + +void usage(void) +{ + die("Usage: build bootsect setup system [rootdev] [> image]"); +} + +int main(int argc, char ** argv) +{ + int i,c,id,sz,tmp_int; + unsigned long sys_size, tmp_long; + char buf[1024]; +#ifndef __BFD__ + struct exec *ex = (struct exec *)buf; +#endif + char major_root, minor_root; + struct stat sb; + unsigned char setup_sectors; + + if ((argc < 4) || (argc > 5)) + usage(); + if (argc > 4) { + if (!strcmp(argv[4], "CURRENT")) { + if (stat("/", &sb)) { + perror("/"); + die("Couldn't stat /"); + } + major_root = major(sb.st_dev); + minor_root = minor(sb.st_dev); + } else if (strcmp(argv[4], "FLOPPY")) { + if (stat(argv[4], &sb)) { + perror(argv[4]); + die("Couldn't stat root device."); + } + major_root = major(sb.st_rdev); + minor_root = minor(sb.st_rdev); + } else { + major_root = 0; + minor_root = 0; + } + } else { + major_root = DEFAULT_MAJOR_ROOT; + minor_root = DEFAULT_MINOR_ROOT; + } + fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root); + for (i=0;i0 ; i+=c ) +#ifdef __BIG_KERNEL__ + { + if (!i) { + /* Working with memcpy because of alignment constraints + on Sparc - Gertjan */ + memcpy(&tmp_long, &buf[2], sizeof(long)); + if (tmp_long != intel_long(0x53726448) ) + die("Wrong magic in loader header of 'setup'"); + memcpy(&tmp_int, &buf[6], sizeof(int)); + if (tmp_int < intel_int(0x200)) + die("Wrong version of loader header of 'setup'"); + buf[0x11] = 1; /* LOADED_HIGH */ + tmp_long = intel_long(0x100000); + memcpy(&buf[0x14], &tmp_long, sizeof(long)); /* code32_start */ + } +#endif + if (write(1,buf,c)!=c) + die("Write call failed"); +#ifdef __BIG_KERNEL__ + } +#endif + if (c != 0) + die("read-error on 'setup'"); + close (id); + setup_sectors = (unsigned char)((i + 511) / 512); + /* for compatibility with LILO */ + if (setup_sectors < SETUP_SECTS) + setup_sectors = SETUP_SECTS; + fprintf(stderr,"Setup is %d bytes.\n",i); + for (c=0 ; c sizeof(buf)) + c = sizeof(buf); + if (write(1,buf,c) != c) + die("Write call failed"); + i += c; + } + + if ((id=open(argv[3],O_RDONLY,0))<0) + die("Unable to open 'system'"); +#ifndef __BFD__ + if (read(id,buf,GCC_HEADER) != GCC_HEADER) + die("Unable to read header of 'system'"); + if (N_MAGIC(*ex) == ZMAGIC) { + GCC_HEADER = N_MAGIC_OFFSET; + lseek(id, GCC_HEADER, SEEK_SET); + } else if (N_MAGIC(*ex) != QMAGIC) + die("Non-GCC header of 'system'"); + fprintf(stderr,"System is %d kB (%d kB code, %d kB data and %d kB bss)\n", + (ex->a_text+ex->a_data+ex->a_bss)/1024, + ex->a_text /1024, + ex->a_data /1024, + ex->a_bss /1024); + sz = N_SYMOFF(*ex) - GCC_HEADER + 4; +#else + if (fstat (id, &sb)) { + perror ("fstat"); + die ("Unable to stat 'system'"); + } + sz = sb.st_size; + fprintf (stderr, "System is %d kB\n", sz/1024); +#endif + sys_size = (sz + 15) / 16; + if (sys_size > SYS_SIZE) + die("System is too big"); + while (sz > 0) { + int l, n; + + l = sz; + if (l > sizeof(buf)) + l = sizeof(buf); + if ((n=read(id, buf, l)) != l) { + if (n == -1) + perror(argv[1]); + else + fprintf(stderr, "Unexpected EOF\n"); + die("Can't read 'system'"); + } + if (write(1, buf, l) != l) + die("Write failed"); + sz -= l; + } + close(id); + if (lseek(1, 497, 0) == 497) { + if (write(1, &setup_sectors, 1) != 1) + die("Write of setup sectors failed"); + } + if (lseek(1,500,0) == 500) { + buf[0] = (sys_size & 0xff); + buf[1] = ((sys_size >> 8) & 0xff); + if (write(1, buf, 2) != 2) + die("Write failed"); + } + return(0); +} diff --git a/kernel/arch/cris/configs/artpec_3_defconfig b/kernel/arch/cris/configs/artpec_3_defconfig new file mode 100644 index 000000000..71854d41c --- /dev/null +++ b/kernel/arch/cris/configs/artpec_3_defconfig @@ -0,0 +1,44 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_SWAP is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc" +CONFIG_ETRAX_FAST_TIMER=y +CONFIG_CRIS_MACH_ARTPEC3=y +CONFIG_ETRAX_DRAM_SIZE=32 +CONFIG_ETRAX_FLASH1_SIZE=4 +CONFIG_ETRAX_DEF_GIO_PA_OE=1c +CONFIG_ETRAX_DEF_GIO_PA_OUT=00 +CONFIG_ETRAX_DEF_GIO_PB_OE=00000 +CONFIG_ETRAX_DEF_GIO_PB_OUT=00000 +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_ETRAX_ETHERNET=y +CONFIG_ETRAX_AXISFLASHMAP=y +CONFIG_MTD_RAM=y +CONFIG_MTD_MTDRAM=y +CONFIG_MTDRAM_TOTAL_SIZE=0 +CONFIG_MTDRAM_ERASE_SIZE=64 +CONFIG_MTDRAM_ABS_POS=0x0 +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +# CONFIG_INPUT is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y diff --git a/kernel/arch/cris/configs/etrax-100lx_defconfig b/kernel/arch/cris/configs/etrax-100lx_defconfig new file mode 100644 index 000000000..cbbcefeaa --- /dev/null +++ b/kernel/arch/cris/configs/etrax-100lx_defconfig @@ -0,0 +1,23 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_ETRAX_LED1R=2 +CONFIG_ETRAX_LED2G=2 +CONFIG_ETRAX_LED2R=2 +CONFIG_ETRAX_DEF_R_PORT_PA_DIR=1d +CONFIG_ETRAX_DEF_R_PORT_PA_DATA=f0 +CONFIG_ETRAX_DEF_R_PORT_PB_DIR=1e +CONFIG_ETRAX_DEF_R_PORT_PB_DATA=f3 +CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IPV6 is not set +CONFIG_ETRAX_ETHERNET=y +CONFIG_ETRAX_SERIAL=y +CONFIG_ETRAX_SERIAL_PORT0=y +CONFIG_ETRAX_SERIAL_PORT1=y +CONFIG_ETRAX_I2C=y +CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C=y +CONFIG_ETRAX_GPIO=y +CONFIG_ETRAX_AXISFLASHMAP=y +CONFIG_NETDEVICES=y +CONFIG_CRAMFS=y diff --git a/kernel/arch/cris/configs/etrax-100lx_v2_defconfig b/kernel/arch/cris/configs/etrax-100lx_v2_defconfig new file mode 100644 index 000000000..a85aabf92 --- /dev/null +++ b/kernel/arch/cris/configs/etrax-100lx_v2_defconfig @@ -0,0 +1,43 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_SWAP is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc" +CONFIG_ETRAX_FAST_TIMER=y +CONFIG_ETRAX100LX_V2=y +CONFIG_ETRAX_DRAM_SIZE=32 +CONFIG_ETRAX_FLASH1_SIZE=4 +CONFIG_ETRAX_DEBUG_PORT_NULL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_ETRAX_ETHERNET=y +CONFIG_ETRAX_SERIAL=y +CONFIG_ETRAX_AXISFLASHMAP=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_RAM=y +CONFIG_MTD_MTDRAM=y +CONFIG_MTDRAM_TOTAL_SIZE=0 +CONFIG_MTDRAM_ERASE_SIZE=64 +CONFIG_MTDRAM_ABS_POS=0x0 +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +# CONFIG_INPUT is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y diff --git a/kernel/arch/cris/configs/etraxfs_defconfig b/kernel/arch/cris/configs/etraxfs_defconfig new file mode 100644 index 000000000..87c7227fe --- /dev/null +++ b/kernel/arch/cris/configs/etraxfs_defconfig @@ -0,0 +1,40 @@ +CONFIG_EXPERIMENTAL=y +# CONFIG_SWAP is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_EXPERT=y +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc" +CONFIG_ETRAX_FAST_TIMER=y +CONFIG_ETRAXFS=y +CONFIG_ETRAX_DRAM_SIZE=32 +CONFIG_ETRAX_FLASH1_SIZE=4 +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_ETRAX_ETHERNET=y +CONFIG_ETRAX_AXISFLASHMAP=y +CONFIG_MTD_RAM=y +CONFIG_MTD_MTDRAM=y +CONFIG_MTDRAM_TOTAL_SIZE=0 +CONFIG_MTDRAM_ERASE_SIZE=64 +CONFIG_MTDRAM_ABS_POS=0x0 +CONFIG_BLK_DEV_RAM=y +CONFIG_NETDEVICES=y +# CONFIG_INPUT is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y diff --git a/kernel/arch/cris/include/arch-v10/arch/Kbuild b/kernel/arch/cris/include/arch-v10/arch/Kbuild new file mode 100644 index 000000000..1f0fc7a66 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/Kbuild @@ -0,0 +1 @@ +# CRISv10 arch diff --git a/kernel/arch/cris/include/arch-v10/arch/bitops.h b/kernel/arch/cris/include/arch-v10/arch/bitops.h new file mode 100644 index 000000000..03d9cfd92 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/bitops.h @@ -0,0 +1,73 @@ +/* asm/arch/bitops.h for Linux/CRISv10 */ + +#ifndef _CRIS_ARCH_BITOPS_H +#define _CRIS_ARCH_BITOPS_H + +/* + * Helper functions for the core of the ff[sz] functions, wrapping the + * syntactically awkward asms. The asms compute the number of leading + * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped + * number. They differ in that the first function also inverts all bits + * in the input. + */ +static inline unsigned long cris_swapnwbrlz(unsigned long w) +{ + /* Let's just say we return the result in the same register as the + input. Saying we clobber the input but can return the result + in another register: + ! __asm__ ("swapnwbr %2\n\tlz %2,%0" + ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w)); + confuses gcc (core.c, gcc from cris-dist-1.14). */ + + unsigned long res; + __asm__ ("swapnwbr %0 \n\t" + "lz %0,%0" + : "=r" (res) : "0" (w)); + return res; +} + +static inline unsigned long cris_swapwbrlz(unsigned long w) +{ + unsigned res; + __asm__ ("swapwbr %0 \n\t" + "lz %0,%0" + : "=r" (res) + : "0" (w)); + return res; +} + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long w) +{ + return cris_swapnwbrlz(w); +} + +/** + * __ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline unsigned long __ffs(unsigned long word) +{ + return cris_swapnwbrlz(~word); +} + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +static inline unsigned long kernel_ffs(unsigned long w) +{ + return w ? cris_swapwbrlz (w) + 1 : 0; +} + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/bug.h b/kernel/arch/cris/include/arch-v10/arch/bug.h new file mode 100644 index 000000000..3485d6b34 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/bug.h @@ -0,0 +1,66 @@ +#ifndef __ASM_CRISv10_ARCH_BUG_H +#define __ASM_CRISv10_ARCH_BUG_H + +#include + +#ifdef CONFIG_BUG +#ifdef CONFIG_DEBUG_BUGVERBOSE +/* The BUG() macro is used for marking obviously incorrect code paths. + * It will cause a message with the file name and line number to be printed, + * and then cause an oops. The message is actually printed by handle_BUG() + * in arch/cris/kernel/traps.c, and the reason we use this method of storing + * the file name and line number is that we do not want to affect the registers + * by calling printk() before causing the oops. + */ + +#define BUG_PREFIX 0x0D7F +#define BUG_MAGIC 0x00001234 + +struct bug_frame { + unsigned short prefix; + unsigned int magic; + unsigned short clear; + unsigned short movu; + unsigned short line; + unsigned short jump; + unsigned char *filename; +}; + +#if 0 +/* Unfortunately this version of the macro does not work due to a problem + * with the compiler (aka a bug) when compiling with -O2, which sometimes + * erroneously causes the second input to be stored in a register... + */ +#define BUG() \ + __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ + "movu.w %0,$r0\n\t" \ + "jump %1\n\t" \ + : : "i" (__LINE__), "i" (__FILE__)) +#else +/* This version will have to do for now, until the compiler is fixed. + * The drawbacks of this version are that the file name will appear multiple + * times in the .rodata section, and that __LINE__ and __FILE__ can probably + * not be used like this with newer versions of gcc. + */ +#define BUG() \ + __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ + "movu.w " __stringify(__LINE__) ",$r0\n\t"\ + "jump 0f\n\t" \ + ".section .rodata\n" \ + "0:\t.string \"" __FILE__ "\"\n\t" \ + ".previous") +#endif + +#else + +/* This just causes an oops. */ +#define BUG() (*(int *)0 = 0) + +#endif + +#define HAVE_ARCH_BUG +#endif + +#include + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/cache.h b/kernel/arch/cris/include/arch-v10/arch/cache.h new file mode 100644 index 000000000..aea27184d --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/cache.h @@ -0,0 +1,8 @@ +#ifndef _ASM_ARCH_CACHE_H +#define _ASM_ARCH_CACHE_H + +/* Etrax 100LX have 32-byte cache-lines. */ +#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 + +#endif /* _ASM_ARCH_CACHE_H */ diff --git a/kernel/arch/cris/include/arch-v10/arch/checksum.h b/kernel/arch/cris/include/arch-v10/arch/checksum.h new file mode 100644 index 000000000..b8000c5d7 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/checksum.h @@ -0,0 +1,29 @@ +#ifndef _CRIS_ARCH_CHECKSUM_H +#define _CRIS_ARCH_CHECKSUM_H + +/* Checksum some values used in TCP/UDP headers. + * + * The gain by doing this in asm is that C will not generate carry-additions + * for the 32-bit components of the checksum, so otherwise we would have had + * to split all of those into 16-bit components, then add. + */ + +static inline __wsum +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + __wsum res; + __asm__ ("add.d %2, %0\n\t" + "ax\n\t" + "add.d %3, %0\n\t" + "ax\n\t" + "add.d %4, %0\n\t" + "ax\n\t" + "addq 0, %0\n" + : "=r" (res) + : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8)); + + return res; +} + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/delay.h b/kernel/arch/cris/include/arch-v10/arch/delay.h new file mode 100644 index 000000000..39481f6e0 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/delay.h @@ -0,0 +1,20 @@ +#ifndef _CRIS_ARCH_DELAY_H +#define _CRIS_ARCH_DELAY_H + +static inline void __delay(int loops) +{ + __asm__ __volatile__ ( + "move.d %0,$r9\n\t" + "beq 2f\n\t" + "subq 1,$r9\n\t" + "1:\n\t" + "bne 1b\n\t" + "subq 1,$r9\n" + "2:" + : : "g" (loops) : "r9"); +} + +#endif /* defined(_CRIS_ARCH_DELAY_H) */ + + + diff --git a/kernel/arch/cris/include/arch-v10/arch/dma.h b/kernel/arch/cris/include/arch-v10/arch/dma.h new file mode 100644 index 000000000..ecb9dba6f --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/dma.h @@ -0,0 +1,74 @@ +/* Defines for using and allocating dma channels. */ + +#ifndef _ASM_ARCH_DMA_H +#define _ASM_ARCH_DMA_H + +#define MAX_DMA_CHANNELS 10 + +/* dma0 and dma1 used for network (ethernet) */ +#define NETWORK_TX_DMA_NBR 0 +#define NETWORK_RX_DMA_NBR 1 + +/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */ +#define PAR0_TX_DMA_NBR 2 +#define PAR0_RX_DMA_NBR 3 +#define SCSI0_TX_DMA_NBR 2 +#define SCSI0_RX_DMA_NBR 3 +#define SER2_TX_DMA_NBR 2 +#define SER2_RX_DMA_NBR 3 +#define ATA_TX_DMA_NBR 2 +#define ATA_RX_DMA_NBR 3 + +/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ +#define PAR1_TX_DMA_NBR 4 +#define PAR1_RX_DMA_NBR 5 +#define SCSI1_TX_DMA_NBR 4 +#define SCSI1_RX_DMA_NBR 5 +#define SER3_TX_DMA_NBR 4 +#define SER3_RX_DMA_NBR 5 +#define EXTDMA0_TX_DMA_NBR 4 +#define EXTDMA0_RX_DMA_NBR 5 + +/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */ +#define SER0_TX_DMA_NBR 6 +#define SER0_RX_DMA_NBR 7 +#define EXTDMA1_TX_DMA_NBR 6 +#define EXTDMA1_RX_DMA_NBR 7 +#define MEM2MEM_TX_DMA_NBR 6 +#define MEM2MEM_RX_DMA_NBR 7 + +/* dma8 and dma9 shared by ser1 and usb */ +#define SER1_TX_DMA_NBR 8 +#define SER1_RX_DMA_NBR 9 +#define USB_TX_DMA_NBR 8 +#define USB_RX_DMA_NBR 9 + +#endif + +enum dma_owner +{ + dma_eth, + dma_ser0, + dma_ser1, /* Async and sync */ + dma_ser2, + dma_ser3, /* Async and sync */ + dma_ata, + dma_par0, + dma_par1, + dma_ext0, + dma_ext1, + dma_int6, + dma_int7, + dma_usb, + dma_scsi0, + dma_scsi1 +}; + +/* Masks used by cris_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR (1<<0) +#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR) + +int cris_request_dma(unsigned int dmanr, const char * device_id, + unsigned options, enum dma_owner owner); + +void cris_free_dma(unsigned int dmanr, const char * device_id); diff --git a/kernel/arch/cris/include/arch-v10/arch/elf.h b/kernel/arch/cris/include/arch-v10/arch/elf.h new file mode 100644 index 000000000..1eb638aed --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/elf.h @@ -0,0 +1,83 @@ +#ifndef __ASMCRIS_ARCH_ELF_H +#define __ASMCRIS_ARCH_ELF_H + +#include + +#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) \ + ((x)->e_machine == EM_CRIS \ + && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ + || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) + +/* + * ELF register definitions.. + */ + +#include + +/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program + starts (a register; assume first param register for CRIS) + contains a pointer to a function which might be + registered using `atexit'. This provides a mean for the + dynamic linker to call DT_FINI functions for shared libraries + that have been loaded before the code runs. + + A value of 0 tells we have no such handler. */ + +/* Explicitly set registers to 0 to increase determinism. */ +#define ELF_PLAT_INIT(_r, load_addr) do { \ + (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ + (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ + (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ + (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ +} while (0) + +/* The additional layer below is because the stack pointer is missing in + the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t, + and should be filled in according to the layout of the user_regs_struct + struct; regs is a pt_regs struct. We dump all registers, though several are + obviously unnecessary. That way there's less need for intelligence at + the receiving end (i.e. gdb). */ +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ + pr_reg[0] = regs->r0; \ + pr_reg[1] = regs->r1; \ + pr_reg[2] = regs->r2; \ + pr_reg[3] = regs->r3; \ + pr_reg[4] = regs->r4; \ + pr_reg[5] = regs->r5; \ + pr_reg[6] = regs->r6; \ + pr_reg[7] = regs->r7; \ + pr_reg[8] = regs->r8; \ + pr_reg[9] = regs->r9; \ + pr_reg[10] = regs->r10; \ + pr_reg[11] = regs->r11; \ + pr_reg[12] = regs->r12; \ + pr_reg[13] = regs->r13; \ + pr_reg[14] = rdusp(); /* sp */ \ + pr_reg[15] = regs->irp; /* pc */ \ + pr_reg[16] = 0; /* p0 */ \ + pr_reg[17] = rdvr(); /* vr */ \ + pr_reg[18] = 0; /* p2 */ \ + pr_reg[19] = 0; /* p3 */ \ + pr_reg[20] = 0; /* p4 */ \ + pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \ + pr_reg[22] = 0; /* p6 */ \ + pr_reg[23] = regs->mof; /* mof */ \ + pr_reg[24] = 0; /* p8 */ \ + pr_reg[25] = 0; /* ibr */ \ + pr_reg[26] = 0; /* irp */ \ + pr_reg[27] = regs->srp; /* srp */ \ + pr_reg[28] = 0; /* bar */ \ + pr_reg[29] = regs->dccr; /* dccr */ \ + pr_reg[30] = 0; /* brp */ \ + pr_reg[31] = rdusp(); /* usp */ \ + pr_reg[32] = 0; /* csrinstr */ \ + pr_reg[33] = 0; /* csraddr */ \ + pr_reg[34] = 0; /* csrdata */ + + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/io.h b/kernel/arch/cris/include/arch-v10/arch/io.h new file mode 100644 index 000000000..4a7241728 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/io.h @@ -0,0 +1,172 @@ +#ifndef _ASM_ARCH_CRIS_IO_H +#define _ASM_ARCH_CRIS_IO_H + +/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ + +extern unsigned long gen_config_ii_shadow; +extern unsigned long port_g_data_shadow; +extern unsigned char port_pa_dir_shadow; +extern unsigned char port_pa_data_shadow; +extern unsigned char port_pb_i2c_shadow; +extern unsigned char port_pb_config_shadow; +extern unsigned char port_pb_dir_shadow; +extern unsigned char port_pb_data_shadow; +extern unsigned long r_timer_ctrl_shadow; + +extern unsigned long port_cse1_shadow; +extern unsigned long port_csp0_shadow; +extern unsigned long port_csp4_shadow; + +extern volatile unsigned long *port_cse1_addr; +extern volatile unsigned long *port_csp0_addr; +extern volatile unsigned long *port_csp4_addr; + +/* macro for setting regs through a shadow - + * r = register name (like R_PORT_PA_DATA) + * s = shadow name (like port_pa_data_shadow) + * b = bit number + * v = value (0 or 1) + */ + +#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b)) + +/* The LED's on various Etrax-based products are set differently. */ + +#if defined(CONFIG_ETRAX_NO_LEDS) +#undef CONFIG_ETRAX_PA_LEDS +#undef CONFIG_ETRAX_PB_LEDS +#undef CONFIG_ETRAX_CSP0_LEDS +#define CRIS_LED_NETWORK_SET_G(x) +#define CRIS_LED_NETWORK_SET_R(x) +#define CRIS_LED_ACTIVE_SET_G(x) +#define CRIS_LED_ACTIVE_SET_R(x) +#define CRIS_LED_DISK_WRITE(x) +#define CRIS_LED_DISK_READ(x) +#endif + +#if !defined(CONFIG_ETRAX_CSP0_LEDS) +#define CRIS_LED_BIT_SET(x) +#define CRIS_LED_BIT_CLR(x) +#endif + +#define CRIS_LED_OFF 0x00 +#define CRIS_LED_GREEN 0x01 +#define CRIS_LED_RED 0x02 +#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) + +#if defined(CONFIG_ETRAX_NO_LEDS) +#define CRIS_LED_NETWORK_SET(x) +#else +#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R +#define CRIS_LED_NETWORK_SET(x) \ + do { \ + CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ + } while (0) +#else +#define CRIS_LED_NETWORK_SET(x) \ + do { \ + CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#endif +#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R +#define CRIS_LED_ACTIVE_SET(x) \ + do { \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ + } while (0) +#else +#define CRIS_LED_ACTIVE_SET(x) \ + do { \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#endif +#endif + +#ifdef CONFIG_ETRAX_PA_LEDS +#define CRIS_LED_NETWORK_SET_G(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) +#define CRIS_LED_NETWORK_SET_R(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) +#define CRIS_LED_ACTIVE_SET_G(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) +#define CRIS_LED_ACTIVE_SET_R(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) +#define CRIS_LED_DISK_WRITE(x) \ + do{\ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ + }while(0) +#define CRIS_LED_DISK_READ(x) \ + REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \ + CONFIG_ETRAX_LED3G, !(x)) +#endif + +#ifdef CONFIG_ETRAX_PB_LEDS +#define CRIS_LED_NETWORK_SET_G(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) +#define CRIS_LED_NETWORK_SET_R(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) +#define CRIS_LED_ACTIVE_SET_G(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) +#define CRIS_LED_ACTIVE_SET_R(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) +#define CRIS_LED_DISK_WRITE(x) \ + do{\ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ + }while(0) +#define CRIS_LED_DISK_READ(x) \ + REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \ + CONFIG_ETRAX_LED3G, !(x)) +#endif + +#ifdef CONFIG_ETRAX_CSP0_LEDS +#define CONFIGURABLE_LEDS\ + ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\ + (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\ + (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\ + (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\ + (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\ + (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\ + (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\ + (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\ + (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ + (1 << CONFIG_ETRAX_LED12R )) + +#define CRIS_LED_NETWORK_SET_G(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) +#define CRIS_LED_NETWORK_SET_R(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) +#define CRIS_LED_ACTIVE_SET_G(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) +#define CRIS_LED_ACTIVE_SET_R(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) +#define CRIS_LED_DISK_WRITE(x) \ + do{\ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ + }while(0) +#define CRIS_LED_DISK_READ(x) \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) +#define CRIS_LED_BIT_SET(x)\ + do{\ + if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ + }while(0) +#define CRIS_LED_BIT_CLR(x)\ + do{\ + if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ + }while(0) +#endif + +# +#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN +#define SOFT_SHUTDOWN() \ + REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1) +#else +#define SOFT_SHUTDOWN() +#endif + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/io_interface_mux.h b/kernel/arch/cris/include/arch-v10/arch/io_interface_mux.h new file mode 100644 index 000000000..d92500080 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/io_interface_mux.h @@ -0,0 +1,75 @@ +/* IO interface mux allocator for ETRAX100LX. + * Copyright 2004, Axis Communications AB + * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $ + */ + + +#ifndef _IO_INTERFACE_MUX_H +#define _IO_INTERFACE_MUX_H + + +/* C.f. ETRAX100LX Designer's Reference 20.9 */ + +/* The order in enum must match the order of interfaces[] in + * io_interface_mux.c */ +enum cris_io_interface { + /* Begin Non-multiplexed interfaces */ + if_eth = 0, + if_serial_0, + /* End Non-multiplexed interfaces */ + if_serial_1, + if_serial_2, + if_serial_3, + if_sync_serial_1, + if_sync_serial_3, + if_shared_ram, + if_shared_ram_w, + if_par_0, + if_par_1, + if_par_w, + if_scsi8_0, + if_scsi8_1, + if_scsi_w, + if_ata, + if_csp, + if_i2c, + if_usb_1, + if_usb_2, + /* GPIO pins */ + if_gpio_grp_a, + if_gpio_grp_b, + if_gpio_grp_c, + if_gpio_grp_d, + if_gpio_grp_e, + if_gpio_grp_f, + if_max_interfaces, + if_unclaimed +}; + +int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id); + +void cris_free_io_interface(enum cris_io_interface ioif); + +/* port can be 'a', 'b' or 'g' */ +int cris_io_interface_allocate_pins(const enum cris_io_interface ioif, + const char port, + const unsigned start_bit, + const unsigned stop_bit); + +/* port can be 'a', 'b' or 'g' */ +int cris_io_interface_free_pins(const enum cris_io_interface ioif, + const char port, + const unsigned start_bit, + const unsigned stop_bit); + +int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available)); + +void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, + const unsigned int gpio_out_available, + const unsigned char pa_available, + const unsigned char pb_available)); + +#endif /* _IO_INTERFACE_MUX_H */ diff --git a/kernel/arch/cris/include/arch-v10/arch/irq.h b/kernel/arch/cris/include/arch-v10/arch/irq.h new file mode 100644 index 000000000..6aecb8350 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/irq.h @@ -0,0 +1,161 @@ +/* + * Interrupt handling assembler and defines for Linux/CRISv10 + */ + +#ifndef _ASM_ARCH_IRQ_H +#define _ASM_ARCH_IRQ_H + +#include + +#define NR_IRQS 32 + +/* The first vector number used for IRQs in v10 is really 0x20 */ +/* but all the code and constants are offseted to make 0 the first */ +#define FIRST_IRQ 0 + +#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */ +#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */ +#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */ +#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */ +/* mio, ata, par0, scsi0 on 4 */ +/* par1, scsi1 on 5 */ +#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */ + +#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */ +#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */ +/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */ +#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0) +#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1) + +/* dma0-9 is irq 16..25 */ +/* 16,17: network */ +#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0) +#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1) +#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR +#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR + +/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */ +#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2) +#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3) +#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR +#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR + +/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ +#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4) +#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5) +#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR +#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR + +/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */ +#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6) +#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7) +#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR +#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR +#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR +#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR + +/* 24,25: dma8 and dma9 shared by ser1 and usb */ +#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8) +#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9) +#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR +#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR +#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR +#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR + +/* usb: controller at irq 31 + uses DMA8 and DMA9 */ +#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb) + +/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */ + +typedef void (*irqvectptr)(void); + +struct etrax_interrupt_vector { + irqvectptr v[256]; +}; + +extern struct etrax_interrupt_vector *etrax_irv; +void set_int_vector(int n, irqvectptr addr); +void set_break_vector(int n, irqvectptr addr); + +#define __STR(x) #x +#define STR(x) __STR(x) + +/* SAVE_ALL saves registers so they match pt_regs */ + +#define SAVE_ALL \ + "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \ + "push $srp\n\t" /* push subroutine return pointer */ \ + "push $dccr\n\t" /* push condition codes */ \ + "push $mof\n\t" /* push multiply overflow reg */ \ + "di\n\t" /* need to disable irq's at this point */\ + "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \ + "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \ + "push $r10\n\t" /* push orig_r10 */ \ + "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */ + +/* BLOCK_IRQ and UNBLOCK_IRQ do the same as + * crisv10_mask_irq and crisv10_unmask_irq */ + +#define BLOCK_IRQ(mask,nr) \ + "move.d " #mask ",$r0\n\t" \ + "move.d $r0,[0xb00000d8]\n\t" + +#define UNBLOCK_IRQ(mask) \ + "move.d " #mask ",$r0\n\t" \ + "move.d $r0,[0xb00000dc]\n\t" + +#define IRQ_NAME2(nr) nr##_interrupt(void) +#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) +#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr) +#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr) + + /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls + * do_IRQ (with irq disabled still). after that it unblocks and jumps to + * ret_from_intr (entry.S) + * + * The reason the IRQ is blocked is to allow an sti() before the handler which + * will acknowledge the interrupt is run. + */ + +#define BUILD_IRQ(nr,mask) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ + "moveq "#nr",$r10\n\t" \ + "move.d $sp,$r11\n\t" \ + "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ + UNBLOCK_IRQ(mask) \ + "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ + "jump ret_from_intr\n\t"); + +/* This is subtle. The timer interrupt is crucial and it should not be disabled for + * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would + * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK. + * If the softirq's take too much time to run, the timer irq won't run and the + * watchdog will kill us. + * + * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq + * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed + * it here, we would not get the multiple_irq at all. + * + * The non-blocking here is based on the knowledge that the timer interrupt runs + * with interrupts disabled, and therefore there will not be an sti() before the + * timer irq handler is run to acknowledge the interrupt. + */ + +#define BUILD_TIMER_IRQ(nr,mask) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + "moveq "#nr",$r10\n\t" \ + "move.d $sp,$r11\n\t" \ + "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ + "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ + "jump ret_from_intr\n\t"); + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/irqflags.h b/kernel/arch/cris/include/arch-v10/arch/irqflags.h new file mode 100644 index 000000000..75ef18991 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/irqflags.h @@ -0,0 +1,45 @@ +#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H +#define __ASM_CRIS_ARCH_IRQFLAGS_H + +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("move $ccr,%0" : "=rm" (flags) : : "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + asm volatile("di" : : : "memory"); +} + +static inline void arch_local_irq_enable(void) +{ + asm volatile("ei" : : : "memory"); +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = arch_local_save_flags(); + arch_local_irq_disable(); + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile("move %0,$ccr" : : "rm" (flags) : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return !(flags & (1 << 5)); +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */ diff --git a/kernel/arch/cris/include/arch-v10/arch/memmap.h b/kernel/arch/cris/include/arch-v10/arch/memmap.h new file mode 100644 index 000000000..13f3b9714 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/memmap.h @@ -0,0 +1,22 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/mmu.h b/kernel/arch/cris/include/arch-v10/arch/mmu.h new file mode 100644 index 000000000..47a5dd217 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/mmu.h @@ -0,0 +1,107 @@ +/* + * CRIS MMU constants and PTE layout + */ + +#ifndef _CRIS_ARCH_MMU_H +#define _CRIS_ARCH_MMU_H + +/* type used in struct mm to couple an MMU context to an active mm */ + +typedef struct +{ + unsigned int page_id; +} mm_context_t; + +/* kernel memory segments */ + +#define KSEG_F 0xf0000000UL +#define KSEG_E 0xe0000000UL +#define KSEG_D 0xd0000000UL +#define KSEG_C 0xc0000000UL +#define KSEG_B 0xb0000000UL +#define KSEG_A 0xa0000000UL +#define KSEG_9 0x90000000UL +#define KSEG_8 0x80000000UL +#define KSEG_7 0x70000000UL +#define KSEG_6 0x60000000UL +#define KSEG_5 0x50000000UL +#define KSEG_4 0x40000000UL +#define KSEG_3 0x30000000UL +#define KSEG_2 0x20000000UL +#define KSEG_1 0x10000000UL +#define KSEG_0 0x00000000UL + +/* CRIS PTE bits (see R_TLB_LO in the register description) + * + * Bit: 31 30-13 12-------4 3 2 1 0 + * _______________________________________________________ + * | cache |pfn | reserved | global | valid | kernel | we | + * |_______|____|__________|________|_______|________|_____| + * + * (pfn = physical frame number) + */ + +/* Real HW-based PTE bits. We use some synonym names so that + * things become less confusing in combination with the SW-based + * bits further below. + * + */ + +#define _PAGE_WE (1<<0) /* page is write-enabled */ +#define _PAGE_SILENT_WRITE (1<<0) /* synonym */ +#define _PAGE_KERNEL (1<<1) /* page is kernel only */ +#define _PAGE_VALID (1<<2) /* page is valid */ +#define _PAGE_SILENT_READ (1<<2) /* synonym */ +#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ +#define _PAGE_NO_CACHE (1<<31) /* part of the uncached memory map */ + +/* Bits the HW doesn't care about but the kernel uses them in SW */ + +#define _PAGE_PRESENT (1<<4) /* page present in memory */ +#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */ +#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */ +#define _PAGE_READ (1<<7) /* read-enabled */ +#define _PAGE_WRITE (1<<8) /* write-enabled */ + +/* Define some higher level generic page attributes. */ + +#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) + +#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) + +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ + _PAGE_ACCESSED) +#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) +#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ + _PAGE_PRESENT | __READABLE | __WRITEABLE) +#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) + +/* + * CRIS can't do page protection for execute, and considers read the same. + * Also, write permissions imply read permissions. This is the closest we can + * get.. + */ + +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY +#define __P101 PAGE_READONLY +#define __P110 PAGE_COPY +#define __P111 PAGE_COPY + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY +#define __S101 PAGE_READONLY +#define __S110 PAGE_SHARED +#define __S111 PAGE_SHARED + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/offset.h b/kernel/arch/cris/include/arch-v10/arch/offset.h new file mode 100644 index 000000000..675b51d85 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/offset.h @@ -0,0 +1,33 @@ +#ifndef __ASM_OFFSETS_H__ +#define __ASM_OFFSETS_H__ +/* + * DO NOT MODIFY. + * + * This file was generated by arch/cris/Makefile + * + */ + +#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */ +#define PT_r13 8 /* offsetof(struct pt_regs, r13) */ +#define PT_r12 12 /* offsetof(struct pt_regs, r12) */ +#define PT_r11 16 /* offsetof(struct pt_regs, r11) */ +#define PT_r10 20 /* offsetof(struct pt_regs, r10) */ +#define PT_r9 24 /* offsetof(struct pt_regs, r9) */ +#define PT_mof 64 /* offsetof(struct pt_regs, mof) */ +#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */ +#define PT_srp 72 /* offsetof(struct pt_regs, srp) */ + +#define TI_task 0 /* offsetof(struct thread_info, task) */ +#define TI_flags 8 /* offsetof(struct thread_info, flags) */ +#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ + +#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ +#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ +#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ + +#define TASK_pid 141 /* offsetof(struct task_struct, pid) */ + +#define LCLONE_VM 256 /* CLONE_VM */ +#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/page.h b/kernel/arch/cris/include/arch-v10/arch/page.h new file mode 100644 index 000000000..ffafc99c3 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/page.h @@ -0,0 +1,30 @@ +#ifndef _CRIS_ARCH_PAGE_H +#define _CRIS_ARCH_PAGE_H + + +#ifdef __KERNEL__ + +/* This handles the memory map.. */ +#ifdef CONFIG_CRIS_LOW_MAP +#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */ +#else +#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */ +#endif + +/* macros to convert between really physical and virtual addresses + * by stripping a selected bit, we can convert between KSEG_x and + * 0x40000000 where the DRAM really resides + */ + +#ifdef CONFIG_CRIS_LOW_MAP +/* we have DRAM virtually at 0x6 */ +#define __pa(x) ((unsigned long)(x) & 0xdfffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0x20000000)) +#else +/* we have DRAM virtually at 0xc */ +#define __pa(x) ((unsigned long)(x) & 0x7fffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) +#endif + +#endif +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/pgtable.h b/kernel/arch/cris/include/arch-v10/arch/pgtable.h new file mode 100644 index 000000000..2a2576d1f --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/pgtable.h @@ -0,0 +1,17 @@ +#ifndef _CRIS_ARCH_PGTABLE_H +#define _CRIS_ARCH_PGTABLE_H + +/* + * Kernels own virtual memory area. + */ + +#ifdef CONFIG_CRIS_LOW_MAP +#define VMALLOC_START KSEG_7 +#define VMALLOC_END KSEG_8 +#else +#define VMALLOC_START KSEG_D +#define VMALLOC_END KSEG_E +#endif + +#endif + diff --git a/kernel/arch/cris/include/arch-v10/arch/processor.h b/kernel/arch/cris/include/arch-v10/arch/processor.h new file mode 100644 index 000000000..93feb2a48 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/processor.h @@ -0,0 +1,69 @@ +#ifndef __ASM_CRIS_ARCH_PROCESSOR_H +#define __ASM_CRIS_ARCH_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; }) + +/* CRIS has no problems with write protection */ +#define wp_works_ok 1 + +/* CRIS thread_struct. this really has nothing to do with the processor itself, since + * CRIS does not do any hardware task-switching, but it's here for legacy reasons. + * The thread_struct here is used when task-switching using _resume defined in entry.S. + * The offsets here are hardcoded into _resume - if you change this struct, you need to + * change them as well!!! +*/ + +struct thread_struct { + unsigned long ksp; /* kernel stack pointer */ + unsigned long usp; /* user stack pointer */ + unsigned long dccr; /* saved flag register */ +}; + +/* + * User space process size. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. + */ + +#ifdef CONFIG_CRIS_LOW_MAP +#define TASK_SIZE (0x50000000UL) /* 1.25 GB */ +#else +#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */ +#endif + +#define INIT_THREAD { \ + 0, 0, 0x20 } /* ccr = int enable, nothing else */ + +#define KSTK_EIP(tsk) \ +({ \ + unsigned long eip = 0; \ + unsigned long regs = (unsigned long)task_pt_regs(tsk); \ + if (regs > PAGE_SIZE && \ + virt_addr_valid(regs)) \ + eip = ((struct pt_regs *)regs)->irp; \ + eip; \ +}) + +/* give the thread a program location + * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8) + * switch user-stackpointer + */ + +#define start_thread(regs, ip, usp) do { \ + regs->irp = ip; \ + regs->dccr |= 1 << U_DCCR_BITNR; \ + wrusp(usp); \ +} while(0) + +/* Called when handling a kernel bus fault fixup. + * + * After a fixup we do not want to return by restoring the CPU-state + * anymore, so switch frame-types (see ptrace.h) + */ +#define arch_fixup(regs) \ + regs->frametype = CRIS_FRAME_NORMAL; + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/ptrace.h b/kernel/arch/cris/include/arch-v10/arch/ptrace.h new file mode 100644 index 000000000..1a2327395 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/ptrace.h @@ -0,0 +1,118 @@ +#ifndef _CRIS_ARCH_PTRACE_H +#define _CRIS_ARCH_PTRACE_H + +/* Frame types */ + +#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */ +#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return + path */ + +/* Register numbers in the ptrace system call interface */ + +#define PT_FRAMETYPE 0 +#define PT_ORIG_R10 1 +#define PT_R13 2 +#define PT_R12 3 +#define PT_R11 4 +#define PT_R10 5 +#define PT_R9 6 +#define PT_R8 7 +#define PT_R7 8 +#define PT_R6 9 +#define PT_R5 10 +#define PT_R4 11 +#define PT_R3 12 +#define PT_R2 13 +#define PT_R1 14 +#define PT_R0 15 +#define PT_MOF 16 +#define PT_DCCR 17 +#define PT_SRP 18 +#define PT_IRP 19 /* This is actually the debugged process' PC */ +#define PT_CSRINSTR 20 /* CPU Status record remnants - + valid if frametype == busfault */ +#define PT_CSRADDR 21 +#define PT_CSRDATA 22 +#define PT_USP 23 /* special case - USP is not in the pt_regs */ +#define PT_MAX 23 + +/* Condition code bit numbers. The same numbers apply to CCR of course, + but we use DCCR everywhere else, so let's try and be consistent. */ +#define C_DCCR_BITNR 0 +#define V_DCCR_BITNR 1 +#define Z_DCCR_BITNR 2 +#define N_DCCR_BITNR 3 +#define X_DCCR_BITNR 4 +#define I_DCCR_BITNR 5 +#define B_DCCR_BITNR 6 +#define M_DCCR_BITNR 7 +#define U_DCCR_BITNR 8 +#define P_DCCR_BITNR 9 +#define F_DCCR_BITNR 10 + +/* pt_regs not only specifices the format in the user-struct during + * ptrace but is also the frame format used in the kernel prologue/epilogues + * themselves + */ + +struct pt_regs { + unsigned long frametype; /* type of stackframe */ + unsigned long orig_r10; + /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */ + unsigned long r13; + unsigned long r12; + unsigned long r11; + unsigned long r10; + unsigned long r9; + unsigned long r8; + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; + unsigned long mof; + unsigned long dccr; + unsigned long srp; + unsigned long irp; /* This is actually the debugged process' PC */ + unsigned long csrinstr; + unsigned long csraddr; + unsigned long csrdata; +}; + +/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) + * when doing a context-switch. it is used (apart from in resume) when a new + * thread is made and we need to make _resume (which is starting it for the + * first time) realise what is going on. + * + * Actually, the use is very close to the thread struct (TSS) in that both the + * switch_stack and the TSS are used to keep thread stuff when switching in + * _resume. + */ + +struct switch_stack { + unsigned long r9; + unsigned long r8; + unsigned long r7; + unsigned long r6; + unsigned long r5; + unsigned long r4; + unsigned long r3; + unsigned long r2; + unsigned long r1; + unsigned long r0; + unsigned long return_ip; /* ip that _resume will return to */ +}; + +#ifdef __KERNEL__ + +/* bit 8 is user-mode flag */ +#define user_mode(regs) (((regs)->dccr & 0x100) != 0) +#define instruction_pointer(regs) ((regs)->irp) +#define profile_pc(regs) instruction_pointer(regs) + +#endif /* __KERNEL__ */ + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/swab.h b/kernel/arch/cris/include/arch-v10/arch/swab.h new file mode 100644 index 000000000..e4e847d8a --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/swab.h @@ -0,0 +1,30 @@ +#ifndef _CRIS_ARCH_SWAB_H +#define _CRIS_ARCH_SWAB_H + +#include +#include + +#define __SWAB_64_THRU_32__ + +/* we just define these two (as we can do the swap in a single + * asm instruction in CRIS) and the arch-independent files will put + * them together into ntohl etc. + */ + +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) +{ + __asm__ ("swapwb %0" : "=r" (x) : "0" (x)); + + return(x); +} +#define __arch_swab32 __arch_swab32 + +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) +{ + __asm__ ("swapb %0" : "=r" (x) : "0" (x)); + + return(x); +} +#define __arch_swab16 __arch_swab16 + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/system.h b/kernel/arch/cris/include/arch-v10/arch/system.h new file mode 100644 index 000000000..9b5580f58 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/system.h @@ -0,0 +1,39 @@ +#ifndef __ASM_CRIS_ARCH_SYSTEM_H +#define __ASM_CRIS_ARCH_SYSTEM_H + + +/* read the CPU version register */ + +static inline unsigned long rdvr(void) { + unsigned char vr; + __asm__ volatile ("move $vr,%0" : "=rm" (vr)); + return vr; +} + +#define cris_machine_name "cris" + +/* read/write the user-mode stackpointer */ + +static inline unsigned long rdusp(void) { + unsigned long usp; + __asm__ __volatile__("move $usp,%0" : "=rm" (usp)); + return usp; +} + +#define wrusp(usp) \ + __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp)) + +/* read the current stackpointer */ + +static inline unsigned long rdsp(void) { + unsigned long sp; + __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp)); + return sp; +} + +static inline unsigned long _get_base(char * addr) +{ + return 0; +} + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/thread_info.h b/kernel/arch/cris/include/arch-v10/arch/thread_info.h new file mode 100644 index 000000000..218f4152d --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/thread_info.h @@ -0,0 +1,12 @@ +#ifndef _ASM_ARCH_THREAD_INFO_H +#define _ASM_ARCH_THREAD_INFO_H + +/* how to get the thread information struct from C */ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL)); + return ti; +} + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/timex.h b/kernel/arch/cris/include/arch-v10/arch/timex.h new file mode 100644 index 000000000..e48447d94 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/timex.h @@ -0,0 +1,30 @@ +/* + * Use prescale timer at 25000 Hz instead of the baudrate timer at + * 19200 to get rid of the 64ppm to fast timer (and we get better + * resolution within a jiffie as well. + */ +#ifndef _ASM_CRIS_ARCH_TIMEX_H +#define _ASM_CRIS_ARCH_TIMEX_H + +/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */ +/* If you change anything here you must check time.c as well... */ +#define PRESCALE_FREQ 25000000 +#define PRESCALE_VALUE 1000 +#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */ +/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/ +#define TIMER0_FREQ (CLOCK_TICK_RATE) +#define TIMER0_CLKSEL flexible +#define TIMER0_DIV (TIMER0_FREQ/(HZ)) + + +#define GET_JIFFIES_USEC() \ + ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV ) + +unsigned long get_ns_in_jiffie(void); + +static inline unsigned long get_us_in_jiffie_highres(void) +{ + return get_ns_in_jiffie()/1000; +} + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/tlb.h b/kernel/arch/cris/include/arch-v10/arch/tlb.h new file mode 100644 index 000000000..31525bbe7 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/tlb.h @@ -0,0 +1,13 @@ +#ifndef _CRIS_ARCH_TLB_H +#define _CRIS_ARCH_TLB_H + +/* The TLB can host up to 64 different mm contexts at the same time. + * The last page_id is never running - it is used as an invalid page_id + * so we can make TLB entries that will never match. + */ +#define NUM_TLB_ENTRIES 64 +#define NUM_PAGEID 64 +#define INVALID_PAGEID 63 +#define NO_CONTEXT -1 + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/uaccess.h b/kernel/arch/cris/include/arch-v10/arch/uaccess.h new file mode 100644 index 000000000..65b02d9b6 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/uaccess.h @@ -0,0 +1,660 @@ +/* + * Authors: Bjorn Wesen (bjornw@axis.com) + * Hans-Peter Nilsson (hp@axis.com) + * + */ +#ifndef _CRIS_ARCH_UACCESS_H +#define _CRIS_ARCH_UACCESS_H + +/* + * We don't tell gcc that we are accessing memory, but this is OK + * because we do not write to any memory gcc knows about, so there + * are no aliasing issues. + * + * Note that PC at a fault is the address *after* the faulting + * instruction. + */ +#define __put_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + " "op" %1,[%2]\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err) \ + : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __put_user_asm_64(x, addr, err) \ + __asm__ __volatile__( \ + " move.d %M1,[%2]\n" \ + "2: move.d %H1,[%2+4]\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 4b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err) \ + : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) + +/* See comment before __put_user_asm. */ + +#define __get_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + " "op" [%2],%1\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " moveq 0,%1\n" \ + " jump 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x) \ + : "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __get_user_asm_64(x, addr, err) \ + __asm__ __volatile__( \ + " move.d [%2],%M1\n" \ + "2: move.d [%2+4],%H1\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " moveq 0,%1\n" \ + " jump 4b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x) \ + : "r" (addr), "g" (-EFAULT), "0" (err)) + +/* + * Copy a null terminated string from userspace. + * + * Must return: + * -EFAULT for an exception + * count if we hit the buffer limit + * bytes copied if we hit a null byte + * (without the null byte) + */ +static inline long +__do_strncpy_from_user(char *dst, const char *src, long count) +{ + long res; + + if (count == 0) + return 0; + + /* + * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. + * So do we. + * + * This code is deduced from: + * + * char tmp2; + * long tmp1, tmp3 + * tmp1 = count; + * while ((*dst++ = (tmp2 = *src++)) != 0 + * && --tmp1) + * ; + * + * res = count - tmp1; + * + * with tweaks. + */ + + __asm__ __volatile__ ( + " move.d %3,%0\n" + " move.b [%2+],$r9\n" + "1: beq 2f\n" + " move.b $r9,[%1+]\n" + + " subq 1,%0\n" + " bne 1b\n" + " move.b [%2+],$r9\n" + + "2: sub.d %3,%0\n" + " neg.d %0,%0\n" + "3:\n" + " .section .fixup,\"ax\"\n" + "4: move.d %7,%0\n" + " jump 3b\n" + + /* There's one address for a fault at the first move, and + two possible PC values for a fault at the second move, + being a delay-slot filler. However, the branch-target + for the second move is the same as the first address. + Just so you don't get confused... */ + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 1b,4b\n" + " .dword 2b,4b\n" + " .previous" + : "=r" (res), "=r" (dst), "=r" (src), "=r" (count) + : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) + : "r9"); + + return res; +} + +/* A few copy asms to build up the more complex ones from. + + Note again, a post-increment is performed regardless of whether a bus + fault occurred in that instruction, and PC for a faulted insn is the + address *after* the insn. */ + +#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + COPY \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " jump 1b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous\n" \ + : "=r" (to), "=r" (from), "=r" (ret) \ + : "0" (to), "1" (from), "2" (ret) \ + : "r9", "memory") + +#define __asm_copy_from_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "2: move.b $r9,[%0+]\n", \ + "3: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + "2: move.w $r9,[%0+]\n" COPY, \ + "3: addq 2,%2\n" \ + " clear.w [%0+]\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_copy_from_user_2(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_3(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "4: move.b $r9,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "2: move.d $r9,[%0+]\n" COPY, \ + "3: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_copy_from_user_4(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_5(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "4: move.b $r9,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + "4: move.w $r9,[%0+]\n" COPY, \ + "5: addq 2,%2\n" \ + " clear.w [%0+]\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_copy_from_user_6(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_7(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "6: move.b $r9,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "4: move.d $r9,[%0+]\n" COPY, \ + "5: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_copy_from_user_8(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_9(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "6: move.b $r9,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + "6: move.w $r9,[%0+]\n" COPY, \ + "7: addq 2,%2\n" \ + " clear.w [%0+]\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_copy_from_user_10(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_11(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "8: move.b $r9,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "6: move.d $r9,[%0+]\n" COPY, \ + "7: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_copy_from_user_12(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_13(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "8: move.b $r9,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + "8: move.w $r9,[%0+]\n" COPY, \ + "9: addq 2,%2\n" \ + " clear.w [%0+]\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_copy_from_user_14(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_15(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + "10: move.b $r9,[%0+]\n", \ + "11: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "8: move.d $r9,[%0+]\n" COPY, \ + "9: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_copy_from_user_16(to, from, ret) \ + __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_16x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "10: move.d $r9,[%0+]\n" COPY, \ + "11: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 10b,11b\n" TENTRY) + +#define __asm_copy_from_user_20(to, from, ret) \ + __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_20x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + "12: move.d $r9,[%0+]\n" COPY, \ + "13: addq 4,%2\n" \ + " clear.d [%0+]\n" FIXUP, \ + " .dword 12b,13b\n" TENTRY) + +#define __asm_copy_from_user_24(to, from, ret) \ + __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") + +/* And now, the to-user ones. */ + +#define __asm_copy_to_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n2:\n", \ + "3: addq 1,%2\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + " move.w $r9,[%0+]\n2:\n" COPY, \ + "3: addq 2,%2\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_copy_to_user_2(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_3(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n4:\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n2:\n" COPY, \ + "3: addq 4,%2\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_copy_to_user_4(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_5(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n4:\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + " move.w $r9,[%0+]\n4:\n" COPY, \ + "5: addq 2,%2\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_copy_to_user_6(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_7(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n6:\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n4:\n" COPY, \ + "5: addq 4,%2\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_copy_to_user_8(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_9(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n6:\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + " move.w $r9,[%0+]\n6:\n" COPY, \ + "7: addq 2,%2\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_copy_to_user_10(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_11(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n8:\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n6:\n" COPY, \ + "7: addq 4,%2\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_copy_to_user_12(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_13(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n8:\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.w [%1+],$r9\n" \ + " move.w $r9,[%0+]\n8:\n" COPY, \ + "9: addq 2,%2\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_copy_to_user_14(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_15(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, \ + " move.b [%1+],$r9\n" \ + " move.b $r9,[%0+]\n10:\n", \ + "11: addq 1,%2\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n8:\n" COPY, \ + "9: addq 4,%2\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_copy_to_user_16(to, from, ret) \ + __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_16x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n10:\n" COPY, \ + "11: addq 4,%2\n" FIXUP, \ + " .dword 10b,11b\n" TENTRY) + +#define __asm_copy_to_user_20(to, from, ret) \ + __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_20x_cont(to, from, ret, \ + " move.d [%1+],$r9\n" \ + " move.d $r9,[%0+]\n12:\n" COPY, \ + "13: addq 4,%2\n" FIXUP, \ + " .dword 12b,13b\n" TENTRY) + +#define __asm_copy_to_user_24(to, from, ret) \ + __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") + +/* Define a few clearing asms with exception handlers. */ + +/* This frame-asm is like the __asm_copy_user_cont one, but has one less + input. */ + +#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + CLEAR \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " jump 1b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous" \ + : "=r" (to), "=r" (ret) \ + : "0" (to), "1" (ret) \ + : "memory") + +#define __asm_clear_1(to, ret) \ + __asm_clear(to, ret, \ + " clear.b [%0+]\n2:\n", \ + "3: addq 1,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_2(to, ret) \ + __asm_clear(to, ret, \ + " clear.w [%0+]\n2:\n", \ + "3: addq 2,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_3(to, ret) \ + __asm_clear(to, ret, \ + " clear.w [%0+]\n" \ + "2: clear.b [%0+]\n3:\n", \ + "4: addq 2,%1\n" \ + "5: addq 1,%1\n", \ + " .dword 2b,4b\n" \ + " .dword 3b,5b\n") + +#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear(to, ret, \ + " clear.d [%0+]\n2:\n" CLEAR, \ + "3: addq 4,%1\n" FIXUP, \ + " .dword 2b,3b\n" TENTRY) + +#define __asm_clear_4(to, ret) \ + __asm_clear_4x_cont(to, ret, "", "", "") + +#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_4x_cont(to, ret, \ + " clear.d [%0+]\n4:\n" CLEAR, \ + "5: addq 4,%1\n" FIXUP, \ + " .dword 4b,5b\n" TENTRY) + +#define __asm_clear_8(to, ret) \ + __asm_clear_8x_cont(to, ret, "", "", "") + +#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_8x_cont(to, ret, \ + " clear.d [%0+]\n6:\n" CLEAR, \ + "7: addq 4,%1\n" FIXUP, \ + " .dword 6b,7b\n" TENTRY) + +#define __asm_clear_12(to, ret) \ + __asm_clear_12x_cont(to, ret, "", "", "") + +#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_12x_cont(to, ret, \ + " clear.d [%0+]\n8:\n" CLEAR, \ + "9: addq 4,%1\n" FIXUP, \ + " .dword 8b,9b\n" TENTRY) + +#define __asm_clear_16(to, ret) \ + __asm_clear_16x_cont(to, ret, "", "", "") + +#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_16x_cont(to, ret, \ + " clear.d [%0+]\n10:\n" CLEAR, \ + "11: addq 4,%1\n" FIXUP, \ + " .dword 10b,11b\n" TENTRY) + +#define __asm_clear_20(to, ret) \ + __asm_clear_20x_cont(to, ret, "", "", "") + +#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_20x_cont(to, ret, \ + " clear.d [%0+]\n12:\n" CLEAR, \ + "13: addq 4,%1\n" FIXUP, \ + " .dword 12b,13b\n" TENTRY) + +#define __asm_clear_24(to, ret) \ + __asm_clear_24x_cont(to, ret, "", "", "") + +/* + * Return the size of a string (including the ending 0) + * + * Return length of string in userspace including terminating 0 + * or 0 for error. Return a value greater than N if too long. + */ + +static inline long +strnlen_user(const char *s, long n) +{ + long res, tmp1; + + if (!access_ok(VERIFY_READ, s, 0)) + return 0; + + /* + * This code is deduced from: + * + * tmp1 = n; + * while (tmp1-- > 0 && *s++) + * ; + * + * res = n - tmp1; + * + * (with tweaks). + */ + + __asm__ __volatile__ ( + " move.d %1,$r9\n" + "0:\n" + " ble 1f\n" + " subq 1,$r9\n" + + " test.b [%0+]\n" + " bne 0b\n" + " test.d $r9\n" + "1:\n" + " move.d %1,%0\n" + " sub.d $r9,%0\n" + "2:\n" + " .section .fixup,\"ax\"\n" + + "3: clear.d %0\n" + " jump 2b\n" + + /* There's one address for a fault at the first move, and + two possible PC values for a fault at the second move, + being a delay-slot filler. However, the branch-target + for the second move is the same as the first address. + Just so you don't get confused... */ + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 0b,3b\n" + " .dword 1b,3b\n" + " .previous\n" + : "=r" (res), "=r" (tmp1) + : "0" (s), "1" (n) + : "r9"); + + return res; +} + +#endif diff --git a/kernel/arch/cris/include/arch-v10/arch/unistd.h b/kernel/arch/cris/include/arch-v10/arch/unistd.h new file mode 100644 index 000000000..d1a38b9e6 --- /dev/null +++ b/kernel/arch/cris/include/arch-v10/arch/unistd.h @@ -0,0 +1,148 @@ +#ifndef _ASM_CRIS_ARCH_UNISTD_H_ +#define _ASM_CRIS_ARCH_UNISTD_H_ + +/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ +/* + * Don't remove the .ifnc tests; they are an insurance against + * any hard-to-spot gcc register allocation bugs. + */ +#define _syscall0(type,name) \ +type name(void) \ +{ \ + register long __a __asm__ ("r10"); \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall1(type,name,type1,arg1) \ +type name(type1 arg1) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall2(type,name,type1,arg1,type2,arg2) \ +type name(type1 arg1,type2 arg2) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ +type name(type1 arg1,type2 arg2,type3 arg3) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ +type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "move %6,$mof\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "g" (arg5)); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5,type6,arg6) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "move %6,$mof\n\tmove %7,$srp\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\ + : "srp"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/Kbuild b/kernel/arch/cris/include/arch-v32/arch/Kbuild new file mode 100644 index 000000000..2fd65c7e1 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/Kbuild @@ -0,0 +1 @@ +# CRISv32 arch diff --git a/kernel/arch/cris/include/arch-v32/arch/bitops.h b/kernel/arch/cris/include/arch-v32/arch/bitops.h new file mode 100644 index 000000000..147689d6b --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/bitops.h @@ -0,0 +1,64 @@ +#ifndef _ASM_CRIS_ARCH_BITOPS_H +#define _ASM_CRIS_ARCH_BITOPS_H + +/* + * Helper functions for the core of the ff[sz] functions. They compute the + * number of leading zeroes of a bits-in-byte, byte-in-word and + * word-in-dword-swapped number. They differ in that the first function also + * inverts all bits in the input. + */ + +static inline unsigned long +cris_swapnwbrlz(unsigned long w) +{ + unsigned long res; + + __asm__ __volatile__ ("swapnwbr %0\n\t" + "lz %0,%0" + : "=r" (res) : "0" (w)); + + return res; +} + +static inline unsigned long +cris_swapwbrlz(unsigned long w) +{ + unsigned long res; + + __asm__ __volatile__ ("swapwbr %0\n\t" + "lz %0,%0" + : "=r" (res) : "0" (w)); + + return res; +} + +/* + * Find First Zero in word. Undefined if no zero exist, so the caller should + * check against ~0 first. + */ +static inline unsigned long +ffz(unsigned long w) +{ + return cris_swapnwbrlz(w); +} + +/* + * Find First Set bit in word. Undefined if no 1 exist, so the caller + * should check against 0 first. + */ +static inline unsigned long +__ffs(unsigned long w) +{ + return cris_swapnwbrlz(~w); +} + +/* + * Find First Bit that is set. + */ +static inline unsigned long +kernel_ffs(unsigned long w) +{ + return w ? cris_swapwbrlz (w) + 1 : 0; +} + +#endif /* _ASM_CRIS_ARCH_BITOPS_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/bug.h b/kernel/arch/cris/include/arch-v32/arch/bug.h new file mode 100644 index 000000000..0f211e135 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/bug.h @@ -0,0 +1,33 @@ +#ifndef __ASM_CRISv32_ARCH_BUG_H +#define __ASM_CRISv32_ARCH_BUG_H + +#include + +#ifdef CONFIG_BUG +#ifdef CONFIG_DEBUG_BUGVERBOSE +/* + * The penalty for the in-band code path will be the size of break 14. + * All other stuff is done out-of-band with exception handlers. + */ +#define BUG() \ + __asm__ __volatile__ ("0: break 14\n\t" \ + ".section .fixup,\"ax\"\n" \ + "1:\n\t" \ + "move.d %0, $r10\n\t" \ + "move.d %1, $r11\n\t" \ + "jump do_BUG\n\t" \ + "nop\n\t" \ + ".previous\n\t" \ + ".section __ex_table,\"a\"\n\t" \ + ".dword 0b, 1b\n\t" \ + ".previous\n\t" \ + : : "ri" (__FILE__), "i" (__LINE__)) +#else +#define BUG() __asm__ __volatile__ ("break 14\n\t") +#endif + +#define HAVE_ARCH_BUG +#endif + +#include +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/cache.h b/kernel/arch/cris/include/arch-v32/arch/cache.h new file mode 100644 index 000000000..7caf25d58 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/cache.h @@ -0,0 +1,21 @@ +#ifndef _ASM_CRIS_ARCH_CACHE_H +#define _ASM_CRIS_ARCH_CACHE_H + +#include + +/* A cache-line is 32 bytes. */ +#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 + +#define __read_mostly __attribute__((__section__(".data..read_mostly"))) + +void flush_dma_list(dma_descr_data *descr); +void flush_dma_descr(dma_descr_data *descr, int flush_buf); + +#define flush_dma_context(c) \ + flush_dma_list(phys_to_virt((c)->saved_data)); + +void cris_flush_cache_range(void *buf, unsigned long len); +void cris_flush_cache(void); + +#endif /* _ASM_CRIS_ARCH_CACHE_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/checksum.h b/kernel/arch/cris/include/arch-v32/arch/checksum.h new file mode 100644 index 000000000..e5dcfce6e --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/checksum.h @@ -0,0 +1,29 @@ +#ifndef _ASM_CRIS_ARCH_CHECKSUM_H +#define _ASM_CRIS_ARCH_CHECKSUM_H + +/* + * Check values used in TCP/UDP headers. + * + * The gain of doing this in assembler instead of C, is that C doesn't + * generate carry-additions for the 32-bit components of the + * checksum. Which means it would be necessary to split all those into + * 16-bit components and then add. + */ +static inline __wsum +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, + unsigned short len, unsigned short proto, __wsum sum) +{ + __wsum res; + + __asm__ __volatile__ ("add.d %2, %0\n\t" + "addc %3, %0\n\t" + "addc %4, %0\n\t" + "addc 0, %0\n\t" + : "=r" (res) + : "0" (sum), "r" (daddr), "r" (saddr), \ + "r" ((len + proto) << 8)); + + return res; +} + +#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/cryptocop.h b/kernel/arch/cris/include/arch-v32/arch/cryptocop.h new file mode 100644 index 000000000..716e434e9 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/cryptocop.h @@ -0,0 +1,158 @@ +/* + * The device /dev/cryptocop is accessible using this driver using + * CRYPTOCOP_MAJOR (254) and minor number 0. + */ +#ifndef CRYPTOCOP_H +#define CRYPTOCOP_H + +#include + + +/********** The API to use from inside the kernel. ************/ + +#include + +typedef enum { + cryptocop_alg_csum = 0, + cryptocop_alg_mem2mem, + cryptocop_alg_md5, + cryptocop_alg_sha1, + cryptocop_alg_des, + cryptocop_alg_3des, + cryptocop_alg_aes, + cryptocop_no_alg, +} cryptocop_algorithm; + +typedef u8 cryptocop_tfrm_id; + + +struct cryptocop_operation; + +typedef void (cryptocop_callback)(struct cryptocop_operation*, void*); + +struct cryptocop_transform_init { + cryptocop_algorithm alg; + /* Keydata for ciphers. */ + unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH]; + unsigned int keylen; + cryptocop_cipher_mode cipher_mode; + cryptocop_3des_mode tdes_mode; + cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */ + + cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */ + struct cryptocop_transform_init *next; +}; + + +typedef enum { + cryptocop_source_dma = 0, + cryptocop_source_des, + cryptocop_source_3des, + cryptocop_source_aes, + cryptocop_source_md5, + cryptocop_source_sha1, + cryptocop_source_csum, + cryptocop_source_none, +} cryptocop_source; + + +struct cryptocop_desc_cfg { + cryptocop_tfrm_id tid; + cryptocop_source src; + unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */ + struct cryptocop_desc_cfg *next; +}; + +struct cryptocop_desc { + size_t length; + struct cryptocop_desc_cfg *cfg; + struct cryptocop_desc *next; +}; + + +/* Flags for cryptocop_tfrm_cfg */ +#define CRYPTOCOP_NO_FLAG (0x00) +#define CRYPTOCOP_ENCRYPT (0x01) +#define CRYPTOCOP_DECRYPT (0x02) +#define CRYPTOCOP_EXPLICIT_IV (0x04) + +struct cryptocop_tfrm_cfg { + cryptocop_tfrm_id tid; + + unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */ + + /* CBC initialisation vector for cihers. */ + u8 iv[CRYPTOCOP_MAX_IV_LENGTH]; + + /* The position in output where to write the transform output. The order + in which the driver writes the output is unspecified, hence if several + transforms write on the same positions in the output the result is + unspecified. */ + size_t inject_ix; + + struct cryptocop_tfrm_cfg *next; +}; + + + +struct cryptocop_dma_list_operation{ + /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in + struct cryptocop_operation must be set for the driver to use them. outlist, + out_data_buf, inlist and in_data_buf must all be physical addresses since they will + be loaded to DMA . */ + dma_descr_data *outlist; /* Out from memory to the co-processor. */ + char *out_data_buf; + dma_descr_data *inlist; /* In from the co-processor to memory. */ + char *in_data_buf; + + cryptocop_3des_mode tdes_mode; + cryptocop_csum_type csum_mode; +}; + + +struct cryptocop_tfrm_operation{ + /* Operation configuration, if not 'use_dmalists' is set. */ + struct cryptocop_tfrm_cfg *tfrm_cfg; + struct cryptocop_desc *desc; + + struct iovec *indata; + size_t incount; + size_t inlen; /* Total inlength. */ + + struct iovec *outdata; + size_t outcount; + size_t outlen; /* Total outlength. */ +}; + + +struct cryptocop_operation { + cryptocop_callback *cb; + void *cb_data; + + cryptocop_session_id sid; + + /* The status of the operation when returned to consumer. */ + int operation_status; /* 0, -EAGAIN */ + + /* Flags */ + unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */ + unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */ + unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */ + + union{ + struct cryptocop_dma_list_operation list_op; + struct cryptocop_tfrm_operation tfrm_op; + }; +}; + + +int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag); +int cryptocop_free_session(cryptocop_session_id sid); + +int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation); + +int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); + +int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); + +#endif /* CRYPTOCOP_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/delay.h b/kernel/arch/cris/include/arch-v32/arch/delay.h new file mode 100644 index 000000000..e9fda0381 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/delay.h @@ -0,0 +1,28 @@ +#ifndef _ASM_CRIS_ARCH_DELAY_H +#define _ASM_CRIS_ARCH_DELAY_H + +extern void cris_delay10ns(u32 n10ns); +#define udelay(u) cris_delay10ns((u)*100) +#define ndelay(n) cris_delay10ns(((n)+9)/10) + +/* + * Not used anymore for udelay or ndelay. Referenced by + * e.g. init/calibrate.c. All other references are likely bugs; + * should be replaced by mdelay, udelay or ndelay. + */ + +static inline void +__delay(int loops) +{ + __asm__ __volatile__ ( + "move.d %0, $r9\n\t" + "beq 2f\n\t" + "subq 1, $r9\n\t" + "1:\n\t" + "bne 1b\n\t" + "subq 1, $r9\n" + "2:" + : : "g" (loops) : "r9"); +} + +#endif /* _ASM_CRIS_ARCH_DELAY_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/dma.h b/kernel/arch/cris/include/arch-v32/arch/dma.h new file mode 100644 index 000000000..6f92f4f23 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/dma.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/arch-v32/arch/elf.h b/kernel/arch/cris/include/arch-v32/arch/elf.h new file mode 100644 index 000000000..c46d58291 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/elf.h @@ -0,0 +1,75 @@ +#ifndef _ASM_CRIS_ELF_H +#define _ASM_CRIS_ELF_H + +#include + +#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) \ + ((x)->e_machine == EM_CRIS \ + && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ + || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) + +/* CRISv32 ELF register definitions. */ + +#include + +/* Explicitly zero out registers to increase determinism. */ +#define ELF_PLAT_INIT(_r, load_addr) do { \ + (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ + (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ + (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ + (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ + (_r)->acr = 0; \ +} while (0) + +/* + * An executable for which elf_read_implies_exec() returns TRUE will + * have the READ_IMPLIES_EXEC personality flag set automatically. + */ +#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) + +/* + * This is basically a pt_regs with the additional definition + * of the stack pointer since it's needed in a core dump. + * pr_regs is a elf_gregset_t and should be filled according + * to the layout of user_regs_struct. + */ +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ + pr_reg[0] = regs->r0; \ + pr_reg[1] = regs->r1; \ + pr_reg[2] = regs->r2; \ + pr_reg[3] = regs->r3; \ + pr_reg[4] = regs->r4; \ + pr_reg[5] = regs->r5; \ + pr_reg[6] = regs->r6; \ + pr_reg[7] = regs->r7; \ + pr_reg[8] = regs->r8; \ + pr_reg[9] = regs->r9; \ + pr_reg[10] = regs->r10; \ + pr_reg[11] = regs->r11; \ + pr_reg[12] = regs->r12; \ + pr_reg[13] = regs->r13; \ + pr_reg[14] = rdusp(); /* SP */ \ + pr_reg[15] = regs->acr; /* ACR */ \ + pr_reg[16] = 0; /* BZ */ \ + pr_reg[17] = rdvr(); /* VR */ \ + pr_reg[18] = 0; /* PID */ \ + pr_reg[19] = regs->srs; /* SRS */ \ + pr_reg[20] = 0; /* WZ */ \ + pr_reg[21] = regs->exs; /* EXS */ \ + pr_reg[22] = regs->eda; /* EDA */ \ + pr_reg[23] = regs->mof; /* MOF */ \ + pr_reg[24] = 0; /* DZ */ \ + pr_reg[25] = 0; /* EBP */ \ + pr_reg[26] = regs->erp; /* ERP */ \ + pr_reg[27] = regs->srp; /* SRP */ \ + pr_reg[28] = 0; /* NRP */ \ + pr_reg[29] = regs->ccs; /* CCS */ \ + pr_reg[30] = rdusp(); /* USP */ \ + pr_reg[31] = regs->spc; /* SPC */ \ + +#endif /* _ASM_CRIS_ELF_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/Makefile b/kernel/arch/cris/include/arch-v32/arch/hwregs/Makefile new file mode 100644 index 000000000..b8b3f8d66 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/Makefile @@ -0,0 +1,186 @@ +# Makefile to generate or copy the latest register definitions +# and related datastructures and helpermacros. +# The official place for these files is at: +RELEASE ?= r1_alfa5 +OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ + +# which is updated on each new release. +INCL_ASMFILES = +INCL_FILES = ata_defs.h +INCL_FILES += bif_core_defs.h +INCL_ASMFILES += bif_core_defs_asm.h +INCL_FILES += bif_slave_defs.h +#INCL_FILES += bif_slave_ext_defs.h +INCL_FILES += config_defs.h +INCL_ASMFILES += config_defs_asm.h +INCL_FILES += cpu_vect.h +#INCL_FILES += cris_defs.h +#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h +INCL_FILES += dma.h +INCL_FILES += dma_defs.h +INCL_FILES += eth_defs.h +INCL_FILES += extmem_defs.h +INCL_FILES += gio_defs.h +INCL_ASMFILES += gio_defs_asm.h +INCL_FILES += intr_vect.h +INCL_FILES += intr_vect_defs.h +INCL_ASMFILES += intr_vect_defs_asm.h +INCL_FILES += marb_bp_defs.h +INCL_FILES += marb_defs.h +INCL_ASMFILES += mmu_defs_asm.h +#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h +#INCL_FILES += par_defs.h # No useful content +INCL_FILES += pinmux_defs.h +INCL_FILES += reg_map.h +INCL_ASMFILES += reg_map_asm.h +INCL_FILES += reg_rdwr.h +INCL_FILES += ser_defs.h +#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h +INCL_FILES += sser_defs.h +INCL_FILES += strcop_defs.h +#INCL_FILES += strcop.h # Where is this? +INCL_FILES += strmux_defs.h +#INCL_FILES += supp_reg.h # Handcrafted instead +INCL_FILES += timer_defs.h + +REGDESC = +REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r +REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r +REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r +#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r +REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r +REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r +REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r +REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r +REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r +REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r +REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r +REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r +#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r +REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r +REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r +REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r +REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r +REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r +#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r + + +BASEDIR = /n/asic/design +DESIGNDIR = /n/asic/projects/guinness/design +RDES2C = /n/asic/bin/rdes2c +RDES2C = /n/asic/design/tools/rdesc/rdes2c +RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr +RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt + +## all - Just print help - you probably want to do 'make gen' +all: help + +# Disable implicit rule that may generate deleted files from RCS/ directory. +%.r: + +%.h: + +## help - This help +help: + @grep '^## ' Makefile + +## gen - Generate include files +gen: $(INCL_FILES) $(INCL_ASMFILES) + +ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r + $(RDES2C) $< +config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r + $(RDES2C) $< +config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r + $(RDES2C) -asm $< +# Can't generate cpu_vect.h yet +#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ???? +# $(RDES2INTR) $< +cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r + $(RDES2C) $< +$(BASEDIR)/core/dma/sw/dma.h: +dma.h: $(BASEDIR)/core/dma/sw/dma.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r + $(RDES2C) $< +extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r + $(RDES2C) $< +gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r + $(RDES2C) $< +intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r + $(RDES2C) $< +intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r + $(RDES2C) -asm $< +# Can't generate intr_vect.h yet +#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r +# $(RDES2INTR) $< +intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r + $(RDES2C) -asm $< +par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r + $(RDES2C) $< + +# From /n/asic/projects/guinness/design/ +reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap + $(RDES2C) -base 0xb0000000 $^ +reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap + $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^ + +reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ + +ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r + $(RDES2C) $< +strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r + $(RDES2C) $< +strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r + $(RDES2C) $< +timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r + $(RDES2C) $< +usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r + $(RDES2C) $< + +## copy - Copy files from official location +copy: + @for HFILE in $(INCL_FILES); do \ + echo " $$HFILE"; \ + cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @for HFILE in $(INCL_ASMFILES); do \ + echo " $$HFILE"; \ + cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done +## ls_official - List official location +ls_official: + (cd $(OFFICIAL_INCDIR); ls -l *.h ) + +## diff_official - Diff current directory with official location +diff_official: + diff . $(OFFICIAL_INCDIR) + +## doc - Generate .axw files from register description. +doc: $(REGDESC) + for RDES in $^; do \ + $(RDES2TXT) $$RDES; \ + done + +.PHONY: axw +## %.axw - Generate the specified .axw file (doesn't work for all files +## due to inconsistent naming ir .r files. +%.axw: axw + @for RDES in $(REGDESC); do \ + if echo "$$RDES" | grep $* ; then \ + $(RDES2TXT) $$RDES; \ + fi \ + done + +.PHONY: clean +## clean - Remove .h files and .axw files. +clean: + rm -rf $(INCL_FILES) *.axw + diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h new file mode 100644 index 000000000..866191418 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h @@ -0,0 +1,222 @@ +#ifndef __ata_defs_asm_h +#define __ata_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/ata/rtl/ata_regs.r + * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp + * last modfied: Mon Apr 11 16:06:25 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r + * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ctrl0, scope ata, type rw */ +#define reg_ata_rw_ctrl0___pio_hold___lsb 0 +#define reg_ata_rw_ctrl0___pio_hold___width 6 +#define reg_ata_rw_ctrl0___pio_strb___lsb 6 +#define reg_ata_rw_ctrl0___pio_strb___width 6 +#define reg_ata_rw_ctrl0___pio_setup___lsb 12 +#define reg_ata_rw_ctrl0___pio_setup___width 6 +#define reg_ata_rw_ctrl0___dma_hold___lsb 18 +#define reg_ata_rw_ctrl0___dma_hold___width 6 +#define reg_ata_rw_ctrl0___dma_strb___lsb 24 +#define reg_ata_rw_ctrl0___dma_strb___width 6 +#define reg_ata_rw_ctrl0___rst___lsb 30 +#define reg_ata_rw_ctrl0___rst___width 1 +#define reg_ata_rw_ctrl0___rst___bit 30 +#define reg_ata_rw_ctrl0___en___lsb 31 +#define reg_ata_rw_ctrl0___en___width 1 +#define reg_ata_rw_ctrl0___en___bit 31 +#define reg_ata_rw_ctrl0_offset 12 + +/* Register rw_ctrl1, scope ata, type rw */ +#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0 +#define reg_ata_rw_ctrl1___udma_tcyc___width 4 +#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4 +#define reg_ata_rw_ctrl1___udma_tdvs___width 4 +#define reg_ata_rw_ctrl1_offset 16 + +/* Register rw_ctrl2, scope ata, type rw */ +#define reg_ata_rw_ctrl2___data___lsb 0 +#define reg_ata_rw_ctrl2___data___width 16 +#define reg_ata_rw_ctrl2___dma_size___lsb 19 +#define reg_ata_rw_ctrl2___dma_size___width 1 +#define reg_ata_rw_ctrl2___dma_size___bit 19 +#define reg_ata_rw_ctrl2___multi___lsb 20 +#define reg_ata_rw_ctrl2___multi___width 1 +#define reg_ata_rw_ctrl2___multi___bit 20 +#define reg_ata_rw_ctrl2___hsh___lsb 21 +#define reg_ata_rw_ctrl2___hsh___width 2 +#define reg_ata_rw_ctrl2___trf_mode___lsb 23 +#define reg_ata_rw_ctrl2___trf_mode___width 1 +#define reg_ata_rw_ctrl2___trf_mode___bit 23 +#define reg_ata_rw_ctrl2___rw___lsb 24 +#define reg_ata_rw_ctrl2___rw___width 1 +#define reg_ata_rw_ctrl2___rw___bit 24 +#define reg_ata_rw_ctrl2___addr___lsb 25 +#define reg_ata_rw_ctrl2___addr___width 3 +#define reg_ata_rw_ctrl2___cs0___lsb 28 +#define reg_ata_rw_ctrl2___cs0___width 1 +#define reg_ata_rw_ctrl2___cs0___bit 28 +#define reg_ata_rw_ctrl2___cs1___lsb 29 +#define reg_ata_rw_ctrl2___cs1___width 1 +#define reg_ata_rw_ctrl2___cs1___bit 29 +#define reg_ata_rw_ctrl2___sel___lsb 30 +#define reg_ata_rw_ctrl2___sel___width 2 +#define reg_ata_rw_ctrl2_offset 0 + +/* Register rs_stat_data, scope ata, type rs */ +#define reg_ata_rs_stat_data___data___lsb 0 +#define reg_ata_rs_stat_data___data___width 16 +#define reg_ata_rs_stat_data___dav___lsb 16 +#define reg_ata_rs_stat_data___dav___width 1 +#define reg_ata_rs_stat_data___dav___bit 16 +#define reg_ata_rs_stat_data___busy___lsb 17 +#define reg_ata_rs_stat_data___busy___width 1 +#define reg_ata_rs_stat_data___busy___bit 17 +#define reg_ata_rs_stat_data_offset 4 + +/* Register r_stat_data, scope ata, type r */ +#define reg_ata_r_stat_data___data___lsb 0 +#define reg_ata_r_stat_data___data___width 16 +#define reg_ata_r_stat_data___dav___lsb 16 +#define reg_ata_r_stat_data___dav___width 1 +#define reg_ata_r_stat_data___dav___bit 16 +#define reg_ata_r_stat_data___busy___lsb 17 +#define reg_ata_r_stat_data___busy___width 1 +#define reg_ata_r_stat_data___busy___bit 17 +#define reg_ata_r_stat_data_offset 8 + +/* Register rw_trf_cnt, scope ata, type rw */ +#define reg_ata_rw_trf_cnt___cnt___lsb 0 +#define reg_ata_rw_trf_cnt___cnt___width 17 +#define reg_ata_rw_trf_cnt_offset 20 + +/* Register r_stat_misc, scope ata, type r */ +#define reg_ata_r_stat_misc___crc___lsb 0 +#define reg_ata_r_stat_misc___crc___width 16 +#define reg_ata_r_stat_misc_offset 24 + +/* Register rw_intr_mask, scope ata, type rw */ +#define reg_ata_rw_intr_mask___bus0___lsb 0 +#define reg_ata_rw_intr_mask___bus0___width 1 +#define reg_ata_rw_intr_mask___bus0___bit 0 +#define reg_ata_rw_intr_mask___bus1___lsb 1 +#define reg_ata_rw_intr_mask___bus1___width 1 +#define reg_ata_rw_intr_mask___bus1___bit 1 +#define reg_ata_rw_intr_mask___bus2___lsb 2 +#define reg_ata_rw_intr_mask___bus2___width 1 +#define reg_ata_rw_intr_mask___bus2___bit 2 +#define reg_ata_rw_intr_mask___bus3___lsb 3 +#define reg_ata_rw_intr_mask___bus3___width 1 +#define reg_ata_rw_intr_mask___bus3___bit 3 +#define reg_ata_rw_intr_mask_offset 28 + +/* Register rw_ack_intr, scope ata, type rw */ +#define reg_ata_rw_ack_intr___bus0___lsb 0 +#define reg_ata_rw_ack_intr___bus0___width 1 +#define reg_ata_rw_ack_intr___bus0___bit 0 +#define reg_ata_rw_ack_intr___bus1___lsb 1 +#define reg_ata_rw_ack_intr___bus1___width 1 +#define reg_ata_rw_ack_intr___bus1___bit 1 +#define reg_ata_rw_ack_intr___bus2___lsb 2 +#define reg_ata_rw_ack_intr___bus2___width 1 +#define reg_ata_rw_ack_intr___bus2___bit 2 +#define reg_ata_rw_ack_intr___bus3___lsb 3 +#define reg_ata_rw_ack_intr___bus3___width 1 +#define reg_ata_rw_ack_intr___bus3___bit 3 +#define reg_ata_rw_ack_intr_offset 32 + +/* Register r_intr, scope ata, type r */ +#define reg_ata_r_intr___bus0___lsb 0 +#define reg_ata_r_intr___bus0___width 1 +#define reg_ata_r_intr___bus0___bit 0 +#define reg_ata_r_intr___bus1___lsb 1 +#define reg_ata_r_intr___bus1___width 1 +#define reg_ata_r_intr___bus1___bit 1 +#define reg_ata_r_intr___bus2___lsb 2 +#define reg_ata_r_intr___bus2___width 1 +#define reg_ata_r_intr___bus2___bit 2 +#define reg_ata_r_intr___bus3___lsb 3 +#define reg_ata_r_intr___bus3___width 1 +#define reg_ata_r_intr___bus3___bit 3 +#define reg_ata_r_intr_offset 36 + +/* Register r_masked_intr, scope ata, type r */ +#define reg_ata_r_masked_intr___bus0___lsb 0 +#define reg_ata_r_masked_intr___bus0___width 1 +#define reg_ata_r_masked_intr___bus0___bit 0 +#define reg_ata_r_masked_intr___bus1___lsb 1 +#define reg_ata_r_masked_intr___bus1___width 1 +#define reg_ata_r_masked_intr___bus1___bit 1 +#define reg_ata_r_masked_intr___bus2___lsb 2 +#define reg_ata_r_masked_intr___bus2___width 1 +#define reg_ata_r_masked_intr___bus2___bit 2 +#define reg_ata_r_masked_intr___bus3___lsb 3 +#define reg_ata_r_masked_intr___bus3___width 1 +#define reg_ata_r_masked_intr___bus3___bit 3 +#define reg_ata_r_masked_intr_offset 40 + + +/* Constants */ +#define regk_ata_active 0x00000001 +#define regk_ata_byte 0x00000001 +#define regk_ata_data 0x00000001 +#define regk_ata_dma 0x00000001 +#define regk_ata_inactive 0x00000000 +#define regk_ata_no 0x00000000 +#define regk_ata_nodata 0x00000000 +#define regk_ata_pio 0x00000000 +#define regk_ata_rd 0x00000001 +#define regk_ata_reg 0x00000000 +#define regk_ata_rw_ctrl0_default 0x00000000 +#define regk_ata_rw_ctrl2_default 0x00000000 +#define regk_ata_rw_intr_mask_default 0x00000000 +#define regk_ata_udma 0x00000002 +#define regk_ata_word 0x00000000 +#define regk_ata_wr 0x00000000 +#define regk_ata_yes 0x00000001 +#endif /* __ata_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h new file mode 100644 index 000000000..c686cb335 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h @@ -0,0 +1,319 @@ +#ifndef __bif_core_defs_asm_h +#define __bif_core_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp1_cfg___lw___width 6 +#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp1_cfg___ew___width 3 +#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp1_cfg___zw___width 3 +#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp1_cfg___aw___width 2 +#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp1_cfg___dw___width 2 +#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp1_cfg___ewb___width 2 +#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp1_cfg___bw___width 1 +#define reg_bif_core_rw_grp1_cfg___bw___bit 18 +#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp1_cfg___mode___width 1 +#define reg_bif_core_rw_grp1_cfg___mode___bit 21 +#define reg_bif_core_rw_grp1_cfg_offset 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp2_cfg___lw___width 6 +#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp2_cfg___ew___width 3 +#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp2_cfg___zw___width 3 +#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp2_cfg___aw___width 2 +#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp2_cfg___dw___width 2 +#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp2_cfg___ewb___width 2 +#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp2_cfg___bw___width 1 +#define reg_bif_core_rw_grp2_cfg___bw___bit 18 +#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp2_cfg___mode___width 1 +#define reg_bif_core_rw_grp2_cfg___mode___bit 21 +#define reg_bif_core_rw_grp2_cfg_offset 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp3_cfg___lw___width 6 +#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp3_cfg___ew___width 3 +#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp3_cfg___zw___width 3 +#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp3_cfg___aw___width 2 +#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp3_cfg___dw___width 2 +#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp3_cfg___ewb___width 2 +#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp3_cfg___bw___width 1 +#define reg_bif_core_rw_grp3_cfg___bw___bit 18 +#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp3_cfg___mode___width 1 +#define reg_bif_core_rw_grp3_cfg___mode___bit 21 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 +#define reg_bif_core_rw_grp3_cfg_offset 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp4_cfg___lw___width 6 +#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp4_cfg___ew___width 3 +#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp4_cfg___zw___width 3 +#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp4_cfg___aw___width 2 +#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp4_cfg___dw___width 2 +#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp4_cfg___ewb___width 2 +#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp4_cfg___bw___width 1 +#define reg_bif_core_rw_grp4_cfg___bw___bit 18 +#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp4_cfg___mode___width 1 +#define reg_bif_core_rw_grp4_cfg___mode___bit 21 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 +#define reg_bif_core_rw_grp4_cfg_offset 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_timing___cl___lsb 0 +#define reg_bif_core_rw_sdram_timing___cl___width 3 +#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 +#define reg_bif_core_rw_sdram_timing___rcd___width 3 +#define reg_bif_core_rw_sdram_timing___rp___lsb 6 +#define reg_bif_core_rw_sdram_timing___rp___width 3 +#define reg_bif_core_rw_sdram_timing___rc___lsb 9 +#define reg_bif_core_rw_sdram_timing___rc___width 2 +#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 +#define reg_bif_core_rw_sdram_timing___dpl___width 2 +#define reg_bif_core_rw_sdram_timing___pde___lsb 13 +#define reg_bif_core_rw_sdram_timing___pde___width 1 +#define reg_bif_core_rw_sdram_timing___pde___bit 13 +#define reg_bif_core_rw_sdram_timing___ref___lsb 14 +#define reg_bif_core_rw_sdram_timing___ref___width 2 +#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 +#define reg_bif_core_rw_sdram_timing___cpd___width 1 +#define reg_bif_core_rw_sdram_timing___cpd___bit 16 +#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 +#define reg_bif_core_rw_sdram_timing___sdcke___width 1 +#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 +#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 +#define reg_bif_core_rw_sdram_timing___sdclk___width 1 +#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 +#define reg_bif_core_rw_sdram_timing_offset 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 +#define reg_bif_core_rw_sdram_cmd___cmd___width 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 +#define reg_bif_core_rw_sdram_cmd_offset 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 +#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_rs_sdram_ref_stat_offset 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_r_sdram_ref_stat___ok___width 1 +#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_r_sdram_ref_stat_offset 36 + + +/* Constants */ +#define regk_bif_core_bank2 0x00000000 +#define regk_bif_core_bank4 0x00000001 +#define regk_bif_core_bit10 0x0000000a +#define regk_bif_core_bit11 0x0000000b +#define regk_bif_core_bit12 0x0000000c +#define regk_bif_core_bit13 0x0000000d +#define regk_bif_core_bit14 0x0000000e +#define regk_bif_core_bit15 0x0000000f +#define regk_bif_core_bit16 0x00000010 +#define regk_bif_core_bit17 0x00000011 +#define regk_bif_core_bit18 0x00000012 +#define regk_bif_core_bit19 0x00000013 +#define regk_bif_core_bit20 0x00000014 +#define regk_bif_core_bit21 0x00000015 +#define regk_bif_core_bit22 0x00000016 +#define regk_bif_core_bit23 0x00000017 +#define regk_bif_core_bit24 0x00000018 +#define regk_bif_core_bit25 0x00000019 +#define regk_bif_core_bit26 0x0000001a +#define regk_bif_core_bit27 0x0000001b +#define regk_bif_core_bit28 0x0000001c +#define regk_bif_core_bit29 0x0000001d +#define regk_bif_core_bit9 0x00000009 +#define regk_bif_core_bw16 0x00000001 +#define regk_bif_core_bw32 0x00000000 +#define regk_bif_core_bwe 0x00000000 +#define regk_bif_core_cwe 0x00000001 +#define regk_bif_core_e15us 0x00000001 +#define regk_bif_core_e7800ns 0x00000002 +#define regk_bif_core_grp0 0x00000000 +#define regk_bif_core_grp1 0x00000001 +#define regk_bif_core_mrs 0x00000003 +#define regk_bif_core_no 0x00000000 +#define regk_bif_core_none 0x00000000 +#define regk_bif_core_nop 0x00000000 +#define regk_bif_core_off 0x00000000 +#define regk_bif_core_pre 0x00000002 +#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rd 0x00000002 +#define regk_bif_core_ref 0x00000001 +#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rw_grp1_cfg_default 0x000006cf +#define regk_bif_core_rw_grp2_cfg_default 0x000006cf +#define regk_bif_core_rw_grp3_cfg_default 0x000006cf +#define regk_bif_core_rw_grp4_cfg_default 0x000006cf +#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 +#define regk_bif_core_slf 0x00000004 +#define regk_bif_core_wr 0x00000001 +#define regk_bif_core_yes 0x00000001 +#endif /* __bif_core_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h new file mode 100644 index 000000000..71532aa18 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h @@ -0,0 +1,495 @@ +#ifndef __bif_dma_defs_asm_h +#define __bif_dma_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch0_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch0_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 +#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 +#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 +#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 +#define reg_bif_dma_rw_ch0_ctrl_offset 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch0_addr___addr___width 32 +#define reg_bif_dma_rw_ch0_addr_offset 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_start___run___lsb 0 +#define reg_bif_dma_rw_ch0_start___run___width 1 +#define reg_bif_dma_rw_ch0_start___run___bit 0 +#define reg_bif_dma_rw_ch0_start_offset 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch0_cnt_offset 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch0_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch0_stat___cnt___width 16 +#define reg_bif_dma_r_ch0_stat___run___lsb 31 +#define reg_bif_dma_r_ch0_stat___run___width 1 +#define reg_bif_dma_r_ch0_stat___run___bit 31 +#define reg_bif_dma_r_ch0_stat_offset 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch1_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch1_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 +#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 +#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch1_ctrl_offset 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch1_addr___addr___width 32 +#define reg_bif_dma_rw_ch1_addr_offset 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_start___run___lsb 0 +#define reg_bif_dma_rw_ch1_start___run___width 1 +#define reg_bif_dma_rw_ch1_start___run___bit 0 +#define reg_bif_dma_rw_ch1_start_offset 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch1_cnt_offset 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch1_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch1_stat___cnt___width 16 +#define reg_bif_dma_r_ch1_stat___run___lsb 31 +#define reg_bif_dma_r_ch1_stat___run___width 1 +#define reg_bif_dma_r_ch1_stat___run___bit 31 +#define reg_bif_dma_r_ch1_stat_offset 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch2_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch2_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 +#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 +#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 +#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 +#define reg_bif_dma_rw_ch2_ctrl_offset 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch2_addr___addr___width 32 +#define reg_bif_dma_rw_ch2_addr_offset 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_start___run___lsb 0 +#define reg_bif_dma_rw_ch2_start___run___width 1 +#define reg_bif_dma_rw_ch2_start___run___bit 0 +#define reg_bif_dma_rw_ch2_start_offset 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch2_cnt_offset 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch2_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch2_stat___cnt___width 16 +#define reg_bif_dma_r_ch2_stat___run___lsb 31 +#define reg_bif_dma_r_ch2_stat___run___width 1 +#define reg_bif_dma_r_ch2_stat___run___bit 31 +#define reg_bif_dma_r_ch2_stat_offset 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 +#define reg_bif_dma_rw_ch3_ctrl___bw___width 2 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 +#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 +#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 +#define reg_bif_dma_rw_ch3_ctrl___cont___width 1 +#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 +#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 +#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 +#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 +#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 +#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 +#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 +#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 +#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 +#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 +#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 +#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 +#define reg_bif_dma_rw_ch3_ctrl_offset 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_addr___addr___lsb 0 +#define reg_bif_dma_rw_ch3_addr___addr___width 32 +#define reg_bif_dma_rw_ch3_addr_offset 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_start___run___lsb 0 +#define reg_bif_dma_rw_ch3_start___run___width 1 +#define reg_bif_dma_rw_ch3_start___run___bit 0 +#define reg_bif_dma_rw_ch3_start_offset 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 +#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 +#define reg_bif_dma_rw_ch3_cnt_offset 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_ch3_stat___cnt___lsb 0 +#define reg_bif_dma_r_ch3_stat___cnt___width 16 +#define reg_bif_dma_r_ch3_stat___run___lsb 31 +#define reg_bif_dma_r_ch3_stat___run___width 1 +#define reg_bif_dma_r_ch3_stat___run___bit 31 +#define reg_bif_dma_r_ch3_stat_offset 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 +#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 +#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 +#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 +#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 +#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 +#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 +#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 +#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 +#define reg_bif_dma_rw_intr_mask_offset 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 +#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 +#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 +#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 +#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 +#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 +#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 +#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 +#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 +#define reg_bif_dma_rw_ack_intr_offset 132 + +/* Register r_intr, scope bif_dma, type r */ +#define reg_bif_dma_r_intr___ext_dma0___lsb 0 +#define reg_bif_dma_r_intr___ext_dma0___width 1 +#define reg_bif_dma_r_intr___ext_dma0___bit 0 +#define reg_bif_dma_r_intr___ext_dma1___lsb 1 +#define reg_bif_dma_r_intr___ext_dma1___width 1 +#define reg_bif_dma_r_intr___ext_dma1___bit 1 +#define reg_bif_dma_r_intr___ext_dma2___lsb 2 +#define reg_bif_dma_r_intr___ext_dma2___width 1 +#define reg_bif_dma_r_intr___ext_dma2___bit 2 +#define reg_bif_dma_r_intr___ext_dma3___lsb 3 +#define reg_bif_dma_r_intr___ext_dma3___width 1 +#define reg_bif_dma_r_intr___ext_dma3___bit 3 +#define reg_bif_dma_r_intr_offset 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 +#define reg_bif_dma_r_masked_intr___ext_dma0___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 +#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 +#define reg_bif_dma_r_masked_intr___ext_dma1___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 +#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 +#define reg_bif_dma_r_masked_intr___ext_dma2___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 +#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 +#define reg_bif_dma_r_masked_intr___ext_dma3___width 1 +#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 +#define reg_bif_dma_r_masked_intr_offset 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin0_cfg_offset 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin1_cfg_offset 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin2_cfg_offset 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin3_cfg_offset 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin4_cfg_offset 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin5_cfg_offset 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin6_cfg_offset 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 +#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 +#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 +#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 +#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 +#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 +#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 +#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 +#define reg_bif_dma_rw_pin7_cfg_offset 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +#define reg_bif_dma_r_pin_stat___pin0___lsb 0 +#define reg_bif_dma_r_pin_stat___pin0___width 1 +#define reg_bif_dma_r_pin_stat___pin0___bit 0 +#define reg_bif_dma_r_pin_stat___pin1___lsb 1 +#define reg_bif_dma_r_pin_stat___pin1___width 1 +#define reg_bif_dma_r_pin_stat___pin1___bit 1 +#define reg_bif_dma_r_pin_stat___pin2___lsb 2 +#define reg_bif_dma_r_pin_stat___pin2___width 1 +#define reg_bif_dma_r_pin_stat___pin2___bit 2 +#define reg_bif_dma_r_pin_stat___pin3___lsb 3 +#define reg_bif_dma_r_pin_stat___pin3___width 1 +#define reg_bif_dma_r_pin_stat___pin3___bit 3 +#define reg_bif_dma_r_pin_stat___pin4___lsb 4 +#define reg_bif_dma_r_pin_stat___pin4___width 1 +#define reg_bif_dma_r_pin_stat___pin4___bit 4 +#define reg_bif_dma_r_pin_stat___pin5___lsb 5 +#define reg_bif_dma_r_pin_stat___pin5___width 1 +#define reg_bif_dma_r_pin_stat___pin5___bit 5 +#define reg_bif_dma_r_pin_stat___pin6___lsb 6 +#define reg_bif_dma_r_pin_stat___pin6___width 1 +#define reg_bif_dma_r_pin_stat___pin6___bit 6 +#define reg_bif_dma_r_pin_stat___pin7___lsb 7 +#define reg_bif_dma_r_pin_stat___pin7___width 1 +#define reg_bif_dma_r_pin_stat___pin7___bit 7 +#define reg_bif_dma_r_pin_stat_offset 192 + + +/* Constants */ +#define regk_bif_dma_as_master 0x00000001 +#define regk_bif_dma_as_slave 0x00000001 +#define regk_bif_dma_burst1 0x00000000 +#define regk_bif_dma_burst8 0x00000001 +#define regk_bif_dma_bw16 0x00000001 +#define regk_bif_dma_bw32 0x00000002 +#define regk_bif_dma_bw8 0x00000000 +#define regk_bif_dma_dack 0x00000006 +#define regk_bif_dma_dack_inv 0x00000007 +#define regk_bif_dma_force 0x00000001 +#define regk_bif_dma_hi 0x00000003 +#define regk_bif_dma_inv 0x00000003 +#define regk_bif_dma_lo 0x00000002 +#define regk_bif_dma_master 0x00000001 +#define regk_bif_dma_no 0x00000000 +#define regk_bif_dma_norm 0x00000002 +#define regk_bif_dma_off 0x00000000 +#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch0_start_default 0x00000000 +#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch1_start_default 0x00000000 +#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch2_start_default 0x00000000 +#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 +#define regk_bif_dma_rw_ch3_start_default 0x00000000 +#define regk_bif_dma_rw_intr_mask_default 0x00000000 +#define regk_bif_dma_rw_pin0_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin1_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin2_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin3_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin4_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin5_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin6_cfg_default 0x00000000 +#define regk_bif_dma_rw_pin7_cfg_default 0x00000000 +#define regk_bif_dma_slave 0x00000002 +#define regk_bif_dma_sreq 0x00000006 +#define regk_bif_dma_sreq_inv 0x00000007 +#define regk_bif_dma_tc 0x00000004 +#define regk_bif_dma_tc_inv 0x00000005 +#define regk_bif_dma_yes 0x00000001 +#endif /* __bif_dma_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h new file mode 100644 index 000000000..031f33a36 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_asm_h +#define __bif_slave_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 +#define reg_bif_slave_rw_slave_cfg___slave_id___width 3 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 +#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 +#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 +#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 +#define reg_bif_slave_rw_slave_cfg___loopback___width 1 +#define reg_bif_slave_rw_slave_cfg___loopback___bit 5 +#define reg_bif_slave_rw_slave_cfg___dis___lsb 6 +#define reg_bif_slave_rw_slave_cfg___dis___width 1 +#define reg_bif_slave_rw_slave_cfg___dis___bit 6 +#define reg_bif_slave_rw_slave_cfg_offset 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 +#define reg_bif_slave_r_slave_mode___ch0_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 +#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 +#define reg_bif_slave_r_slave_mode___ch1_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 +#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 +#define reg_bif_slave_r_slave_mode___ch2_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 +#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 +#define reg_bif_slave_r_slave_mode___ch3_mode___width 1 +#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 +#define reg_bif_slave_r_slave_mode_offset 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch0_cfg_offset 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch1_cfg_offset 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch2_cfg_offset 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 +#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 +#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 +#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 +#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 +#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 +#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 +#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 +#define reg_bif_slave_rw_ch3_cfg_offset 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 +#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 +#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 +#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 +#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 +#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 +#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 +#define reg_bif_slave_rw_arb_cfg___release___lsb 7 +#define reg_bif_slave_rw_arb_cfg___release___width 2 +#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 +#define reg_bif_slave_rw_arb_cfg___acquire___width 1 +#define reg_bif_slave_rw_arb_cfg___acquire___bit 9 +#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 +#define reg_bif_slave_rw_arb_cfg___settle_time___width 2 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 +#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 +#define reg_bif_slave_rw_arb_cfg_offset 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +#define reg_bif_slave_r_arb_stat___init_mode___lsb 0 +#define reg_bif_slave_r_arb_stat___init_mode___width 1 +#define reg_bif_slave_r_arb_stat___init_mode___bit 0 +#define reg_bif_slave_r_arb_stat___mode___lsb 1 +#define reg_bif_slave_r_arb_stat___mode___width 1 +#define reg_bif_slave_r_arb_stat___mode___bit 1 +#define reg_bif_slave_r_arb_stat___brin___lsb 2 +#define reg_bif_slave_r_arb_stat___brin___width 1 +#define reg_bif_slave_r_arb_stat___brin___bit 2 +#define reg_bif_slave_r_arb_stat___brout___lsb 3 +#define reg_bif_slave_r_arb_stat___brout___width 1 +#define reg_bif_slave_r_arb_stat___brout___bit 3 +#define reg_bif_slave_r_arb_stat___bg___lsb 4 +#define reg_bif_slave_r_arb_stat___bg___width 1 +#define reg_bif_slave_r_arb_stat___bg___bit 4 +#define reg_bif_slave_r_arb_stat_offset 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 +#define reg_bif_slave_rw_intr_mask___bus_release___width 1 +#define reg_bif_slave_rw_intr_mask___bus_release___bit 0 +#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 +#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 +#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 +#define reg_bif_slave_rw_intr_mask_offset 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 +#define reg_bif_slave_rw_ack_intr___bus_release___width 1 +#define reg_bif_slave_rw_ack_intr___bus_release___bit 0 +#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 +#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 +#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 +#define reg_bif_slave_rw_ack_intr_offset 68 + +/* Register r_intr, scope bif_slave, type r */ +#define reg_bif_slave_r_intr___bus_release___lsb 0 +#define reg_bif_slave_r_intr___bus_release___width 1 +#define reg_bif_slave_r_intr___bus_release___bit 0 +#define reg_bif_slave_r_intr___bus_acquire___lsb 1 +#define reg_bif_slave_r_intr___bus_acquire___width 1 +#define reg_bif_slave_r_intr___bus_acquire___bit 1 +#define reg_bif_slave_r_intr_offset 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +#define reg_bif_slave_r_masked_intr___bus_release___lsb 0 +#define reg_bif_slave_r_masked_intr___bus_release___width 1 +#define reg_bif_slave_r_masked_intr___bus_release___bit 0 +#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 +#define reg_bif_slave_r_masked_intr___bus_acquire___width 1 +#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 +#define reg_bif_slave_r_masked_intr_offset 76 + + +/* Constants */ +#define regk_bif_slave_active_hi 0x00000003 +#define regk_bif_slave_active_lo 0x00000002 +#define regk_bif_slave_addr 0x00000000 +#define regk_bif_slave_always 0x00000001 +#define regk_bif_slave_at_idle 0x00000002 +#define regk_bif_slave_burst_end 0x00000003 +#define regk_bif_slave_dma 0x00000001 +#define regk_bif_slave_hi 0x00000003 +#define regk_bif_slave_inv 0x00000001 +#define regk_bif_slave_lo 0x00000002 +#define regk_bif_slave_local 0x00000001 +#define regk_bif_slave_master 0x00000000 +#define regk_bif_slave_mode_reg 0x00000001 +#define regk_bif_slave_no 0x00000000 +#define regk_bif_slave_norm 0x00000000 +#define regk_bif_slave_on_access 0x00000000 +#define regk_bif_slave_rw_arb_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch0_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch1_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch2_cfg_default 0x00000000 +#define regk_bif_slave_rw_ch3_cfg_default 0x00000000 +#define regk_bif_slave_rw_intr_mask_default 0x00000000 +#define regk_bif_slave_rw_slave_cfg_default 0x00000000 +#define regk_bif_slave_shared 0x00000000 +#define regk_bif_slave_slave 0x00000001 +#define regk_bif_slave_t0ns 0x00000003 +#define regk_bif_slave_t10ns 0x00000002 +#define regk_bif_slave_t20ns 0x00000003 +#define regk_bif_slave_t30ns 0x00000002 +#define regk_bif_slave_t40ns 0x00000001 +#define regk_bif_slave_t50ns 0x00000000 +#define regk_bif_slave_yes 0x00000001 +#define regk_bif_slave_z 0x00000004 +#endif /* __bif_slave_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h new file mode 100644 index 000000000..e98476332 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h @@ -0,0 +1,131 @@ +#ifndef __config_defs_asm_h +#define __config_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r + * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope config, type r */ +#define reg_config_r_bootsel___boot_mode___lsb 0 +#define reg_config_r_bootsel___boot_mode___width 3 +#define reg_config_r_bootsel___full_duplex___lsb 3 +#define reg_config_r_bootsel___full_duplex___width 1 +#define reg_config_r_bootsel___full_duplex___bit 3 +#define reg_config_r_bootsel___user___lsb 4 +#define reg_config_r_bootsel___user___width 1 +#define reg_config_r_bootsel___user___bit 4 +#define reg_config_r_bootsel___pll___lsb 5 +#define reg_config_r_bootsel___pll___width 1 +#define reg_config_r_bootsel___pll___bit 5 +#define reg_config_r_bootsel___flash_bw___lsb 6 +#define reg_config_r_bootsel___flash_bw___width 1 +#define reg_config_r_bootsel___flash_bw___bit 6 +#define reg_config_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +#define reg_config_rw_clk_ctrl___pll___lsb 0 +#define reg_config_rw_clk_ctrl___pll___width 1 +#define reg_config_rw_clk_ctrl___pll___bit 0 +#define reg_config_rw_clk_ctrl___cpu___lsb 1 +#define reg_config_rw_clk_ctrl___cpu___width 1 +#define reg_config_rw_clk_ctrl___cpu___bit 1 +#define reg_config_rw_clk_ctrl___iop___lsb 2 +#define reg_config_rw_clk_ctrl___iop___width 1 +#define reg_config_rw_clk_ctrl___iop___bit 2 +#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 +#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 +#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 +#define reg_config_rw_clk_ctrl___dma23___lsb 4 +#define reg_config_rw_clk_ctrl___dma23___width 1 +#define reg_config_rw_clk_ctrl___dma23___bit 4 +#define reg_config_rw_clk_ctrl___dma45___lsb 5 +#define reg_config_rw_clk_ctrl___dma45___width 1 +#define reg_config_rw_clk_ctrl___dma45___bit 5 +#define reg_config_rw_clk_ctrl___dma67___lsb 6 +#define reg_config_rw_clk_ctrl___dma67___width 1 +#define reg_config_rw_clk_ctrl___dma67___bit 6 +#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 +#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 +#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 +#define reg_config_rw_clk_ctrl___bif___lsb 8 +#define reg_config_rw_clk_ctrl___bif___width 1 +#define reg_config_rw_clk_ctrl___bif___bit 8 +#define reg_config_rw_clk_ctrl___fix_io___lsb 9 +#define reg_config_rw_clk_ctrl___fix_io___width 1 +#define reg_config_rw_clk_ctrl___fix_io___bit 9 +#define reg_config_rw_clk_ctrl_offset 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 +#define reg_config_rw_pad_ctrl___usb_susp___width 1 +#define reg_config_rw_pad_ctrl___usb_susp___bit 0 +#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 +#define reg_config_rw_pad_ctrl___phyrst_n___width 1 +#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 +#define reg_config_rw_pad_ctrl_offset 8 + + +/* Constants */ +#define regk_config_bw16 0x00000000 +#define regk_config_bw32 0x00000001 +#define regk_config_master 0x00000005 +#define regk_config_nand 0x00000003 +#define regk_config_net_rx 0x00000001 +#define regk_config_net_tx_rx 0x00000002 +#define regk_config_no 0x00000000 +#define regk_config_none 0x00000007 +#define regk_config_nor 0x00000000 +#define regk_config_rw_clk_ctrl_default 0x00000002 +#define regk_config_rw_pad_ctrl_default 0x00000000 +#define regk_config_ser 0x00000004 +#define regk_config_slave 0x00000006 +#define regk_config_yes 0x00000001 +#endif /* __config_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h new file mode 100644 index 000000000..8370aee8a --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/crisp/doc/cpu_vect.r +version . */ + +#ifndef _______INST_CRISP_DOC_CPU_VECT_R +#define _______INST_CRISP_DOC_CPU_VECT_R +#define NMI_INTR_VECT 0x00 +#define RESERVED_1_INTR_VECT 0x01 +#define RESERVED_2_INTR_VECT 0x02 +#define SINGLE_STEP_INTR_VECT 0x03 +#define INSTR_TLB_REFILL_INTR_VECT 0x04 +#define INSTR_TLB_INV_INTR_VECT 0x05 +#define INSTR_TLB_ACC_INTR_VECT 0x06 +#define TLB_EX_INTR_VECT 0x07 +#define DATA_TLB_REFILL_INTR_VECT 0x08 +#define DATA_TLB_INV_INTR_VECT 0x09 +#define DATA_TLB_ACC_INTR_VECT 0x0a +#define DATA_TLB_WE_INTR_VECT 0x0b +#define HW_BP_INTR_VECT 0x0c +#define RESERVED_D_INTR_VECT 0x0d +#define RESERVED_E_INTR_VECT 0x0e +#define RESERVED_F_INTR_VECT 0x0f +#define BREAK_0_INTR_VECT 0x10 +#define BREAK_1_INTR_VECT 0x11 +#define BREAK_2_INTR_VECT 0x12 +#define BREAK_3_INTR_VECT 0x13 +#define BREAK_4_INTR_VECT 0x14 +#define BREAK_5_INTR_VECT 0x15 +#define BREAK_6_INTR_VECT 0x16 +#define BREAK_7_INTR_VECT 0x17 +#define BREAK_8_INTR_VECT 0x18 +#define BREAK_9_INTR_VECT 0x19 +#define BREAK_10_INTR_VECT 0x1a +#define BREAK_11_INTR_VECT 0x1b +#define BREAK_12_INTR_VECT 0x1c +#define BREAK_13_INTR_VECT 0x1d +#define BREAK_14_INTR_VECT 0x1e +#define BREAK_15_INTR_VECT 0x1f +#define MULTIPLE_INTR_VECT 0x30 + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h new file mode 100644 index 000000000..7f768db27 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h @@ -0,0 +1,114 @@ +#ifndef __cris_defs_asm_h +#define __cris_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/crisp/doc/cris.r + * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp + * last modfied: Mon Apr 11 16:06:39 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r + * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gc_cfg, scope cris, type rw */ +#define reg_cris_rw_gc_cfg___ic___lsb 0 +#define reg_cris_rw_gc_cfg___ic___width 1 +#define reg_cris_rw_gc_cfg___ic___bit 0 +#define reg_cris_rw_gc_cfg___dc___lsb 1 +#define reg_cris_rw_gc_cfg___dc___width 1 +#define reg_cris_rw_gc_cfg___dc___bit 1 +#define reg_cris_rw_gc_cfg___im___lsb 2 +#define reg_cris_rw_gc_cfg___im___width 1 +#define reg_cris_rw_gc_cfg___im___bit 2 +#define reg_cris_rw_gc_cfg___dm___lsb 3 +#define reg_cris_rw_gc_cfg___dm___width 1 +#define reg_cris_rw_gc_cfg___dm___bit 3 +#define reg_cris_rw_gc_cfg___gb___lsb 4 +#define reg_cris_rw_gc_cfg___gb___width 1 +#define reg_cris_rw_gc_cfg___gb___bit 4 +#define reg_cris_rw_gc_cfg___gk___lsb 5 +#define reg_cris_rw_gc_cfg___gk___width 1 +#define reg_cris_rw_gc_cfg___gk___bit 5 +#define reg_cris_rw_gc_cfg___gp___lsb 6 +#define reg_cris_rw_gc_cfg___gp___width 1 +#define reg_cris_rw_gc_cfg___gp___bit 6 +#define reg_cris_rw_gc_cfg_offset 0 + +/* Register rw_gc_ccs, scope cris, type rw */ +#define reg_cris_rw_gc_ccs_offset 4 + +/* Register rw_gc_srs, scope cris, type rw */ +#define reg_cris_rw_gc_srs___srs___lsb 0 +#define reg_cris_rw_gc_srs___srs___width 8 +#define reg_cris_rw_gc_srs_offset 8 + +/* Register rw_gc_nrp, scope cris, type rw */ +#define reg_cris_rw_gc_nrp_offset 12 + +/* Register rw_gc_exs, scope cris, type rw */ +#define reg_cris_rw_gc_exs_offset 16 + +/* Register rw_gc_eda, scope cris, type rw */ +#define reg_cris_rw_gc_eda_offset 20 + +/* Register rw_gc_r0, scope cris, type rw */ +#define reg_cris_rw_gc_r0_offset 32 + +/* Register rw_gc_r1, scope cris, type rw */ +#define reg_cris_rw_gc_r1_offset 36 + +/* Register rw_gc_r2, scope cris, type rw */ +#define reg_cris_rw_gc_r2_offset 40 + +/* Register rw_gc_r3, scope cris, type rw */ +#define reg_cris_rw_gc_r3_offset 44 + + +/* Constants */ +#define regk_cris_no 0x00000000 +#define regk_cris_rw_gc_cfg_default 0x00000000 +#define regk_cris_yes 0x00000001 +#endif /* __cris_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h new file mode 100644 index 000000000..7d3689a6f --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h @@ -0,0 +1,10 @@ +#define RW_GC_CFG 0 +#define RW_GC_CCS 1 +#define RW_GC_SRS 2 +#define RW_GC_NRP 3 +#define RW_GC_EXS 4 +#define RW_GC_EDA 5 +#define RW_GC_R0 8 +#define RW_GC_R1 9 +#define RW_GC_R2 10 +#define RW_GC_R3 11 diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h new file mode 100644 index 000000000..0cb71bc12 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h @@ -0,0 +1,368 @@ +#ifndef __dma_defs_asm_h +#define __dma_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp + * last modfied: Mon Apr 11 16:06:51 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_data, scope dma, type rw */ +#define reg_dma_rw_data_offset 0 + +/* Register rw_data_next, scope dma, type rw */ +#define reg_dma_rw_data_next_offset 4 + +/* Register rw_data_buf, scope dma, type rw */ +#define reg_dma_rw_data_buf_offset 8 + +/* Register rw_data_ctrl, scope dma, type rw */ +#define reg_dma_rw_data_ctrl___eol___lsb 0 +#define reg_dma_rw_data_ctrl___eol___width 1 +#define reg_dma_rw_data_ctrl___eol___bit 0 +#define reg_dma_rw_data_ctrl___out_eop___lsb 3 +#define reg_dma_rw_data_ctrl___out_eop___width 1 +#define reg_dma_rw_data_ctrl___out_eop___bit 3 +#define reg_dma_rw_data_ctrl___intr___lsb 4 +#define reg_dma_rw_data_ctrl___intr___width 1 +#define reg_dma_rw_data_ctrl___intr___bit 4 +#define reg_dma_rw_data_ctrl___wait___lsb 5 +#define reg_dma_rw_data_ctrl___wait___width 1 +#define reg_dma_rw_data_ctrl___wait___bit 5 +#define reg_dma_rw_data_ctrl_offset 12 + +/* Register rw_data_stat, scope dma, type rw */ +#define reg_dma_rw_data_stat___in_eop___lsb 3 +#define reg_dma_rw_data_stat___in_eop___width 1 +#define reg_dma_rw_data_stat___in_eop___bit 3 +#define reg_dma_rw_data_stat_offset 16 + +/* Register rw_data_md, scope dma, type rw */ +#define reg_dma_rw_data_md___md___lsb 0 +#define reg_dma_rw_data_md___md___width 16 +#define reg_dma_rw_data_md_offset 20 + +/* Register rw_data_md_s, scope dma, type rw */ +#define reg_dma_rw_data_md_s___md_s___lsb 0 +#define reg_dma_rw_data_md_s___md_s___width 16 +#define reg_dma_rw_data_md_s_offset 24 + +/* Register rw_data_after, scope dma, type rw */ +#define reg_dma_rw_data_after_offset 28 + +/* Register rw_ctxt, scope dma, type rw */ +#define reg_dma_rw_ctxt_offset 32 + +/* Register rw_ctxt_next, scope dma, type rw */ +#define reg_dma_rw_ctxt_next_offset 36 + +/* Register rw_ctxt_ctrl, scope dma, type rw */ +#define reg_dma_rw_ctxt_ctrl___eol___lsb 0 +#define reg_dma_rw_ctxt_ctrl___eol___width 1 +#define reg_dma_rw_ctxt_ctrl___eol___bit 0 +#define reg_dma_rw_ctxt_ctrl___intr___lsb 4 +#define reg_dma_rw_ctxt_ctrl___intr___width 1 +#define reg_dma_rw_ctxt_ctrl___intr___bit 4 +#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 +#define reg_dma_rw_ctxt_ctrl___store_mode___width 1 +#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 +#define reg_dma_rw_ctxt_ctrl___en___lsb 7 +#define reg_dma_rw_ctxt_ctrl___en___width 1 +#define reg_dma_rw_ctxt_ctrl___en___bit 7 +#define reg_dma_rw_ctxt_ctrl_offset 40 + +/* Register rw_ctxt_stat, scope dma, type rw */ +#define reg_dma_rw_ctxt_stat___dis___lsb 7 +#define reg_dma_rw_ctxt_stat___dis___width 1 +#define reg_dma_rw_ctxt_stat___dis___bit 7 +#define reg_dma_rw_ctxt_stat_offset 44 + +/* Register rw_ctxt_md0, scope dma, type rw */ +#define reg_dma_rw_ctxt_md0___md0___lsb 0 +#define reg_dma_rw_ctxt_md0___md0___width 16 +#define reg_dma_rw_ctxt_md0_offset 48 + +/* Register rw_ctxt_md0_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 +#define reg_dma_rw_ctxt_md0_s___md0_s___width 16 +#define reg_dma_rw_ctxt_md0_s_offset 52 + +/* Register rw_ctxt_md1, scope dma, type rw */ +#define reg_dma_rw_ctxt_md1_offset 56 + +/* Register rw_ctxt_md1_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md1_s_offset 60 + +/* Register rw_ctxt_md2, scope dma, type rw */ +#define reg_dma_rw_ctxt_md2_offset 64 + +/* Register rw_ctxt_md2_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md2_s_offset 68 + +/* Register rw_ctxt_md3, scope dma, type rw */ +#define reg_dma_rw_ctxt_md3_offset 72 + +/* Register rw_ctxt_md3_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md3_s_offset 76 + +/* Register rw_ctxt_md4, scope dma, type rw */ +#define reg_dma_rw_ctxt_md4_offset 80 + +/* Register rw_ctxt_md4_s, scope dma, type rw */ +#define reg_dma_rw_ctxt_md4_s_offset 84 + +/* Register rw_saved_data, scope dma, type rw */ +#define reg_dma_rw_saved_data_offset 88 + +/* Register rw_saved_data_buf, scope dma, type rw */ +#define reg_dma_rw_saved_data_buf_offset 92 + +/* Register rw_group, scope dma, type rw */ +#define reg_dma_rw_group_offset 96 + +/* Register rw_group_next, scope dma, type rw */ +#define reg_dma_rw_group_next_offset 100 + +/* Register rw_group_ctrl, scope dma, type rw */ +#define reg_dma_rw_group_ctrl___eol___lsb 0 +#define reg_dma_rw_group_ctrl___eol___width 1 +#define reg_dma_rw_group_ctrl___eol___bit 0 +#define reg_dma_rw_group_ctrl___tol___lsb 1 +#define reg_dma_rw_group_ctrl___tol___width 1 +#define reg_dma_rw_group_ctrl___tol___bit 1 +#define reg_dma_rw_group_ctrl___bol___lsb 2 +#define reg_dma_rw_group_ctrl___bol___width 1 +#define reg_dma_rw_group_ctrl___bol___bit 2 +#define reg_dma_rw_group_ctrl___intr___lsb 4 +#define reg_dma_rw_group_ctrl___intr___width 1 +#define reg_dma_rw_group_ctrl___intr___bit 4 +#define reg_dma_rw_group_ctrl___en___lsb 7 +#define reg_dma_rw_group_ctrl___en___width 1 +#define reg_dma_rw_group_ctrl___en___bit 7 +#define reg_dma_rw_group_ctrl_offset 104 + +/* Register rw_group_stat, scope dma, type rw */ +#define reg_dma_rw_group_stat___dis___lsb 7 +#define reg_dma_rw_group_stat___dis___width 1 +#define reg_dma_rw_group_stat___dis___bit 7 +#define reg_dma_rw_group_stat_offset 108 + +/* Register rw_group_md, scope dma, type rw */ +#define reg_dma_rw_group_md___md___lsb 0 +#define reg_dma_rw_group_md___md___width 16 +#define reg_dma_rw_group_md_offset 112 + +/* Register rw_group_md_s, scope dma, type rw */ +#define reg_dma_rw_group_md_s___md_s___lsb 0 +#define reg_dma_rw_group_md_s___md_s___width 16 +#define reg_dma_rw_group_md_s_offset 116 + +/* Register rw_group_up, scope dma, type rw */ +#define reg_dma_rw_group_up_offset 120 + +/* Register rw_group_down, scope dma, type rw */ +#define reg_dma_rw_group_down_offset 124 + +/* Register rw_cmd, scope dma, type rw */ +#define reg_dma_rw_cmd___cont_data___lsb 0 +#define reg_dma_rw_cmd___cont_data___width 1 +#define reg_dma_rw_cmd___cont_data___bit 0 +#define reg_dma_rw_cmd_offset 128 + +/* Register rw_cfg, scope dma, type rw */ +#define reg_dma_rw_cfg___en___lsb 0 +#define reg_dma_rw_cfg___en___width 1 +#define reg_dma_rw_cfg___en___bit 0 +#define reg_dma_rw_cfg___stop___lsb 1 +#define reg_dma_rw_cfg___stop___width 1 +#define reg_dma_rw_cfg___stop___bit 1 +#define reg_dma_rw_cfg_offset 132 + +/* Register rw_stat, scope dma, type rw */ +#define reg_dma_rw_stat___mode___lsb 0 +#define reg_dma_rw_stat___mode___width 5 +#define reg_dma_rw_stat___list_state___lsb 5 +#define reg_dma_rw_stat___list_state___width 3 +#define reg_dma_rw_stat___stream_cmd_src___lsb 8 +#define reg_dma_rw_stat___stream_cmd_src___width 8 +#define reg_dma_rw_stat___buf___lsb 24 +#define reg_dma_rw_stat___buf___width 8 +#define reg_dma_rw_stat_offset 136 + +/* Register rw_intr_mask, scope dma, type rw */ +#define reg_dma_rw_intr_mask___group___lsb 0 +#define reg_dma_rw_intr_mask___group___width 1 +#define reg_dma_rw_intr_mask___group___bit 0 +#define reg_dma_rw_intr_mask___ctxt___lsb 1 +#define reg_dma_rw_intr_mask___ctxt___width 1 +#define reg_dma_rw_intr_mask___ctxt___bit 1 +#define reg_dma_rw_intr_mask___data___lsb 2 +#define reg_dma_rw_intr_mask___data___width 1 +#define reg_dma_rw_intr_mask___data___bit 2 +#define reg_dma_rw_intr_mask___in_eop___lsb 3 +#define reg_dma_rw_intr_mask___in_eop___width 1 +#define reg_dma_rw_intr_mask___in_eop___bit 3 +#define reg_dma_rw_intr_mask___stream_cmd___lsb 4 +#define reg_dma_rw_intr_mask___stream_cmd___width 1 +#define reg_dma_rw_intr_mask___stream_cmd___bit 4 +#define reg_dma_rw_intr_mask_offset 140 + +/* Register rw_ack_intr, scope dma, type rw */ +#define reg_dma_rw_ack_intr___group___lsb 0 +#define reg_dma_rw_ack_intr___group___width 1 +#define reg_dma_rw_ack_intr___group___bit 0 +#define reg_dma_rw_ack_intr___ctxt___lsb 1 +#define reg_dma_rw_ack_intr___ctxt___width 1 +#define reg_dma_rw_ack_intr___ctxt___bit 1 +#define reg_dma_rw_ack_intr___data___lsb 2 +#define reg_dma_rw_ack_intr___data___width 1 +#define reg_dma_rw_ack_intr___data___bit 2 +#define reg_dma_rw_ack_intr___in_eop___lsb 3 +#define reg_dma_rw_ack_intr___in_eop___width 1 +#define reg_dma_rw_ack_intr___in_eop___bit 3 +#define reg_dma_rw_ack_intr___stream_cmd___lsb 4 +#define reg_dma_rw_ack_intr___stream_cmd___width 1 +#define reg_dma_rw_ack_intr___stream_cmd___bit 4 +#define reg_dma_rw_ack_intr_offset 144 + +/* Register r_intr, scope dma, type r */ +#define reg_dma_r_intr___group___lsb 0 +#define reg_dma_r_intr___group___width 1 +#define reg_dma_r_intr___group___bit 0 +#define reg_dma_r_intr___ctxt___lsb 1 +#define reg_dma_r_intr___ctxt___width 1 +#define reg_dma_r_intr___ctxt___bit 1 +#define reg_dma_r_intr___data___lsb 2 +#define reg_dma_r_intr___data___width 1 +#define reg_dma_r_intr___data___bit 2 +#define reg_dma_r_intr___in_eop___lsb 3 +#define reg_dma_r_intr___in_eop___width 1 +#define reg_dma_r_intr___in_eop___bit 3 +#define reg_dma_r_intr___stream_cmd___lsb 4 +#define reg_dma_r_intr___stream_cmd___width 1 +#define reg_dma_r_intr___stream_cmd___bit 4 +#define reg_dma_r_intr_offset 148 + +/* Register r_masked_intr, scope dma, type r */ +#define reg_dma_r_masked_intr___group___lsb 0 +#define reg_dma_r_masked_intr___group___width 1 +#define reg_dma_r_masked_intr___group___bit 0 +#define reg_dma_r_masked_intr___ctxt___lsb 1 +#define reg_dma_r_masked_intr___ctxt___width 1 +#define reg_dma_r_masked_intr___ctxt___bit 1 +#define reg_dma_r_masked_intr___data___lsb 2 +#define reg_dma_r_masked_intr___data___width 1 +#define reg_dma_r_masked_intr___data___bit 2 +#define reg_dma_r_masked_intr___in_eop___lsb 3 +#define reg_dma_r_masked_intr___in_eop___width 1 +#define reg_dma_r_masked_intr___in_eop___bit 3 +#define reg_dma_r_masked_intr___stream_cmd___lsb 4 +#define reg_dma_r_masked_intr___stream_cmd___width 1 +#define reg_dma_r_masked_intr___stream_cmd___bit 4 +#define reg_dma_r_masked_intr_offset 152 + +/* Register rw_stream_cmd, scope dma, type rw */ +#define reg_dma_rw_stream_cmd___cmd___lsb 0 +#define reg_dma_rw_stream_cmd___cmd___width 10 +#define reg_dma_rw_stream_cmd___n___lsb 16 +#define reg_dma_rw_stream_cmd___n___width 8 +#define reg_dma_rw_stream_cmd___busy___lsb 31 +#define reg_dma_rw_stream_cmd___busy___width 1 +#define reg_dma_rw_stream_cmd___busy___bit 31 +#define reg_dma_rw_stream_cmd_offset 156 + + +/* Constants */ +#define regk_dma_ack_pkt 0x00000100 +#define regk_dma_anytime 0x00000001 +#define regk_dma_array 0x00000008 +#define regk_dma_burst 0x00000020 +#define regk_dma_client 0x00000002 +#define regk_dma_copy_next 0x00000010 +#define regk_dma_copy_up 0x00000020 +#define regk_dma_data_at_eol 0x00000001 +#define regk_dma_dis_c 0x00000010 +#define regk_dma_dis_g 0x00000020 +#define regk_dma_idle 0x00000001 +#define regk_dma_intern 0x00000004 +#define regk_dma_load_c 0x00000200 +#define regk_dma_load_c_n 0x00000280 +#define regk_dma_load_c_next 0x00000240 +#define regk_dma_load_d 0x00000140 +#define regk_dma_load_g 0x00000300 +#define regk_dma_load_g_down 0x000003c0 +#define regk_dma_load_g_next 0x00000340 +#define regk_dma_load_g_up 0x00000380 +#define regk_dma_next_en 0x00000010 +#define regk_dma_next_pkt 0x00000010 +#define regk_dma_no 0x00000000 +#define regk_dma_only_at_wait 0x00000000 +#define regk_dma_restore 0x00000020 +#define regk_dma_rst 0x00000001 +#define regk_dma_running 0x00000004 +#define regk_dma_rw_cfg_default 0x00000000 +#define regk_dma_rw_cmd_default 0x00000000 +#define regk_dma_rw_intr_mask_default 0x00000000 +#define regk_dma_rw_stat_default 0x00000101 +#define regk_dma_rw_stream_cmd_default 0x00000000 +#define regk_dma_save_down 0x00000020 +#define regk_dma_save_up 0x00000020 +#define regk_dma_set_reg 0x00000050 +#define regk_dma_set_w_size1 0x00000190 +#define regk_dma_set_w_size2 0x000001a0 +#define regk_dma_set_w_size4 0x000001c0 +#define regk_dma_stopped 0x00000002 +#define regk_dma_store_c 0x00000002 +#define regk_dma_store_descr 0x00000000 +#define regk_dma_store_g 0x00000004 +#define regk_dma_store_md 0x00000001 +#define regk_dma_sw 0x00000008 +#define regk_dma_update_down 0x00000020 +#define regk_dma_yes 0x00000001 +#endif /* __dma_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h new file mode 100644 index 000000000..c9f498648 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h @@ -0,0 +1,498 @@ +#ifndef __eth_defs_asm_h +#define __eth_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/eth/rtl/eth_regs.r + * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp + * last modfied: Mon Apr 11 16:07:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r + * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_ma0_lo, scope eth, type rw */ +#define reg_eth_rw_ma0_lo___addr___lsb 0 +#define reg_eth_rw_ma0_lo___addr___width 32 +#define reg_eth_rw_ma0_lo_offset 0 + +/* Register rw_ma0_hi, scope eth, type rw */ +#define reg_eth_rw_ma0_hi___addr___lsb 0 +#define reg_eth_rw_ma0_hi___addr___width 16 +#define reg_eth_rw_ma0_hi_offset 4 + +/* Register rw_ma1_lo, scope eth, type rw */ +#define reg_eth_rw_ma1_lo___addr___lsb 0 +#define reg_eth_rw_ma1_lo___addr___width 32 +#define reg_eth_rw_ma1_lo_offset 8 + +/* Register rw_ma1_hi, scope eth, type rw */ +#define reg_eth_rw_ma1_hi___addr___lsb 0 +#define reg_eth_rw_ma1_hi___addr___width 16 +#define reg_eth_rw_ma1_hi_offset 12 + +/* Register rw_ga_lo, scope eth, type rw */ +#define reg_eth_rw_ga_lo___table___lsb 0 +#define reg_eth_rw_ga_lo___table___width 32 +#define reg_eth_rw_ga_lo_offset 16 + +/* Register rw_ga_hi, scope eth, type rw */ +#define reg_eth_rw_ga_hi___table___lsb 0 +#define reg_eth_rw_ga_hi___table___width 32 +#define reg_eth_rw_ga_hi_offset 20 + +/* Register rw_gen_ctrl, scope eth, type rw */ +#define reg_eth_rw_gen_ctrl___en___lsb 0 +#define reg_eth_rw_gen_ctrl___en___width 1 +#define reg_eth_rw_gen_ctrl___en___bit 0 +#define reg_eth_rw_gen_ctrl___phy___lsb 1 +#define reg_eth_rw_gen_ctrl___phy___width 2 +#define reg_eth_rw_gen_ctrl___protocol___lsb 3 +#define reg_eth_rw_gen_ctrl___protocol___width 1 +#define reg_eth_rw_gen_ctrl___protocol___bit 3 +#define reg_eth_rw_gen_ctrl___loopback___lsb 4 +#define reg_eth_rw_gen_ctrl___loopback___width 1 +#define reg_eth_rw_gen_ctrl___loopback___bit 4 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 +#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 +#define reg_eth_rw_gen_ctrl_offset 24 + +/* Register rw_rec_ctrl, scope eth, type rw */ +#define reg_eth_rw_rec_ctrl___ma0___lsb 0 +#define reg_eth_rw_rec_ctrl___ma0___width 1 +#define reg_eth_rw_rec_ctrl___ma0___bit 0 +#define reg_eth_rw_rec_ctrl___ma1___lsb 1 +#define reg_eth_rw_rec_ctrl___ma1___width 1 +#define reg_eth_rw_rec_ctrl___ma1___bit 1 +#define reg_eth_rw_rec_ctrl___individual___lsb 2 +#define reg_eth_rw_rec_ctrl___individual___width 1 +#define reg_eth_rw_rec_ctrl___individual___bit 2 +#define reg_eth_rw_rec_ctrl___broadcast___lsb 3 +#define reg_eth_rw_rec_ctrl___broadcast___width 1 +#define reg_eth_rw_rec_ctrl___broadcast___bit 3 +#define reg_eth_rw_rec_ctrl___undersize___lsb 4 +#define reg_eth_rw_rec_ctrl___undersize___width 1 +#define reg_eth_rw_rec_ctrl___undersize___bit 4 +#define reg_eth_rw_rec_ctrl___oversize___lsb 5 +#define reg_eth_rw_rec_ctrl___oversize___width 1 +#define reg_eth_rw_rec_ctrl___oversize___bit 5 +#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 +#define reg_eth_rw_rec_ctrl___bad_crc___width 1 +#define reg_eth_rw_rec_ctrl___bad_crc___bit 6 +#define reg_eth_rw_rec_ctrl___duplex___lsb 7 +#define reg_eth_rw_rec_ctrl___duplex___width 1 +#define reg_eth_rw_rec_ctrl___duplex___bit 7 +#define reg_eth_rw_rec_ctrl___max_size___lsb 8 +#define reg_eth_rw_rec_ctrl___max_size___width 1 +#define reg_eth_rw_rec_ctrl___max_size___bit 8 +#define reg_eth_rw_rec_ctrl_offset 28 + +/* Register rw_tr_ctrl, scope eth, type rw */ +#define reg_eth_rw_tr_ctrl___crc___lsb 0 +#define reg_eth_rw_tr_ctrl___crc___width 1 +#define reg_eth_rw_tr_ctrl___crc___bit 0 +#define reg_eth_rw_tr_ctrl___pad___lsb 1 +#define reg_eth_rw_tr_ctrl___pad___width 1 +#define reg_eth_rw_tr_ctrl___pad___bit 1 +#define reg_eth_rw_tr_ctrl___retry___lsb 2 +#define reg_eth_rw_tr_ctrl___retry___width 1 +#define reg_eth_rw_tr_ctrl___retry___bit 2 +#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 +#define reg_eth_rw_tr_ctrl___ignore_col___width 1 +#define reg_eth_rw_tr_ctrl___ignore_col___bit 3 +#define reg_eth_rw_tr_ctrl___cancel___lsb 4 +#define reg_eth_rw_tr_ctrl___cancel___width 1 +#define reg_eth_rw_tr_ctrl___cancel___bit 4 +#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 +#define reg_eth_rw_tr_ctrl___hsh_delay___width 1 +#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 +#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 +#define reg_eth_rw_tr_ctrl___ignore_crs___width 1 +#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 +#define reg_eth_rw_tr_ctrl_offset 32 + +/* Register rw_clr_err, scope eth, type rw */ +#define reg_eth_rw_clr_err___clr___lsb 0 +#define reg_eth_rw_clr_err___clr___width 1 +#define reg_eth_rw_clr_err___clr___bit 0 +#define reg_eth_rw_clr_err_offset 36 + +/* Register rw_mgm_ctrl, scope eth, type rw */ +#define reg_eth_rw_mgm_ctrl___mdio___lsb 0 +#define reg_eth_rw_mgm_ctrl___mdio___width 1 +#define reg_eth_rw_mgm_ctrl___mdio___bit 0 +#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 +#define reg_eth_rw_mgm_ctrl___mdoe___width 1 +#define reg_eth_rw_mgm_ctrl___mdoe___bit 1 +#define reg_eth_rw_mgm_ctrl___mdc___lsb 2 +#define reg_eth_rw_mgm_ctrl___mdc___width 1 +#define reg_eth_rw_mgm_ctrl___mdc___bit 2 +#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 +#define reg_eth_rw_mgm_ctrl___phyclk___width 1 +#define reg_eth_rw_mgm_ctrl___phyclk___bit 3 +#define reg_eth_rw_mgm_ctrl___txdata___lsb 4 +#define reg_eth_rw_mgm_ctrl___txdata___width 4 +#define reg_eth_rw_mgm_ctrl___txen___lsb 8 +#define reg_eth_rw_mgm_ctrl___txen___width 1 +#define reg_eth_rw_mgm_ctrl___txen___bit 8 +#define reg_eth_rw_mgm_ctrl_offset 40 + +/* Register r_stat, scope eth, type r */ +#define reg_eth_r_stat___mdio___lsb 0 +#define reg_eth_r_stat___mdio___width 1 +#define reg_eth_r_stat___mdio___bit 0 +#define reg_eth_r_stat___exc_col___lsb 1 +#define reg_eth_r_stat___exc_col___width 1 +#define reg_eth_r_stat___exc_col___bit 1 +#define reg_eth_r_stat___urun___lsb 2 +#define reg_eth_r_stat___urun___width 1 +#define reg_eth_r_stat___urun___bit 2 +#define reg_eth_r_stat___phyclk___lsb 3 +#define reg_eth_r_stat___phyclk___width 1 +#define reg_eth_r_stat___phyclk___bit 3 +#define reg_eth_r_stat___txdata___lsb 4 +#define reg_eth_r_stat___txdata___width 4 +#define reg_eth_r_stat___txen___lsb 8 +#define reg_eth_r_stat___txen___width 1 +#define reg_eth_r_stat___txen___bit 8 +#define reg_eth_r_stat___col___lsb 9 +#define reg_eth_r_stat___col___width 1 +#define reg_eth_r_stat___col___bit 9 +#define reg_eth_r_stat___crs___lsb 10 +#define reg_eth_r_stat___crs___width 1 +#define reg_eth_r_stat___crs___bit 10 +#define reg_eth_r_stat___txclk___lsb 11 +#define reg_eth_r_stat___txclk___width 1 +#define reg_eth_r_stat___txclk___bit 11 +#define reg_eth_r_stat___rxdata___lsb 12 +#define reg_eth_r_stat___rxdata___width 4 +#define reg_eth_r_stat___rxer___lsb 16 +#define reg_eth_r_stat___rxer___width 1 +#define reg_eth_r_stat___rxer___bit 16 +#define reg_eth_r_stat___rxdv___lsb 17 +#define reg_eth_r_stat___rxdv___width 1 +#define reg_eth_r_stat___rxdv___bit 17 +#define reg_eth_r_stat___rxclk___lsb 18 +#define reg_eth_r_stat___rxclk___width 1 +#define reg_eth_r_stat___rxclk___bit 18 +#define reg_eth_r_stat_offset 44 + +/* Register rs_rec_cnt, scope eth, type rs */ +#define reg_eth_rs_rec_cnt___crc_err___lsb 0 +#define reg_eth_rs_rec_cnt___crc_err___width 8 +#define reg_eth_rs_rec_cnt___align_err___lsb 8 +#define reg_eth_rs_rec_cnt___align_err___width 8 +#define reg_eth_rs_rec_cnt___oversize___lsb 16 +#define reg_eth_rs_rec_cnt___oversize___width 8 +#define reg_eth_rs_rec_cnt___congestion___lsb 24 +#define reg_eth_rs_rec_cnt___congestion___width 8 +#define reg_eth_rs_rec_cnt_offset 48 + +/* Register r_rec_cnt, scope eth, type r */ +#define reg_eth_r_rec_cnt___crc_err___lsb 0 +#define reg_eth_r_rec_cnt___crc_err___width 8 +#define reg_eth_r_rec_cnt___align_err___lsb 8 +#define reg_eth_r_rec_cnt___align_err___width 8 +#define reg_eth_r_rec_cnt___oversize___lsb 16 +#define reg_eth_r_rec_cnt___oversize___width 8 +#define reg_eth_r_rec_cnt___congestion___lsb 24 +#define reg_eth_r_rec_cnt___congestion___width 8 +#define reg_eth_r_rec_cnt_offset 52 + +/* Register rs_tr_cnt, scope eth, type rs */ +#define reg_eth_rs_tr_cnt___single_col___lsb 0 +#define reg_eth_rs_tr_cnt___single_col___width 8 +#define reg_eth_rs_tr_cnt___mult_col___lsb 8 +#define reg_eth_rs_tr_cnt___mult_col___width 8 +#define reg_eth_rs_tr_cnt___late_col___lsb 16 +#define reg_eth_rs_tr_cnt___late_col___width 8 +#define reg_eth_rs_tr_cnt___deferred___lsb 24 +#define reg_eth_rs_tr_cnt___deferred___width 8 +#define reg_eth_rs_tr_cnt_offset 56 + +/* Register r_tr_cnt, scope eth, type r */ +#define reg_eth_r_tr_cnt___single_col___lsb 0 +#define reg_eth_r_tr_cnt___single_col___width 8 +#define reg_eth_r_tr_cnt___mult_col___lsb 8 +#define reg_eth_r_tr_cnt___mult_col___width 8 +#define reg_eth_r_tr_cnt___late_col___lsb 16 +#define reg_eth_r_tr_cnt___late_col___width 8 +#define reg_eth_r_tr_cnt___deferred___lsb 24 +#define reg_eth_r_tr_cnt___deferred___width 8 +#define reg_eth_r_tr_cnt_offset 60 + +/* Register rs_phy_cnt, scope eth, type rs */ +#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 +#define reg_eth_rs_phy_cnt___carrier_loss___width 8 +#define reg_eth_rs_phy_cnt___sqe_err___lsb 8 +#define reg_eth_rs_phy_cnt___sqe_err___width 8 +#define reg_eth_rs_phy_cnt_offset 64 + +/* Register r_phy_cnt, scope eth, type r */ +#define reg_eth_r_phy_cnt___carrier_loss___lsb 0 +#define reg_eth_r_phy_cnt___carrier_loss___width 8 +#define reg_eth_r_phy_cnt___sqe_err___lsb 8 +#define reg_eth_r_phy_cnt___sqe_err___width 8 +#define reg_eth_r_phy_cnt_offset 68 + +/* Register rw_test_ctrl, scope eth, type rw */ +#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 +#define reg_eth_rw_test_ctrl___snmp_inc___width 1 +#define reg_eth_rw_test_ctrl___snmp_inc___bit 0 +#define reg_eth_rw_test_ctrl___snmp___lsb 1 +#define reg_eth_rw_test_ctrl___snmp___width 1 +#define reg_eth_rw_test_ctrl___snmp___bit 1 +#define reg_eth_rw_test_ctrl___backoff___lsb 2 +#define reg_eth_rw_test_ctrl___backoff___width 1 +#define reg_eth_rw_test_ctrl___backoff___bit 2 +#define reg_eth_rw_test_ctrl_offset 72 + +/* Register rw_intr_mask, scope eth, type rw */ +#define reg_eth_rw_intr_mask___crc___lsb 0 +#define reg_eth_rw_intr_mask___crc___width 1 +#define reg_eth_rw_intr_mask___crc___bit 0 +#define reg_eth_rw_intr_mask___align___lsb 1 +#define reg_eth_rw_intr_mask___align___width 1 +#define reg_eth_rw_intr_mask___align___bit 1 +#define reg_eth_rw_intr_mask___oversize___lsb 2 +#define reg_eth_rw_intr_mask___oversize___width 1 +#define reg_eth_rw_intr_mask___oversize___bit 2 +#define reg_eth_rw_intr_mask___congestion___lsb 3 +#define reg_eth_rw_intr_mask___congestion___width 1 +#define reg_eth_rw_intr_mask___congestion___bit 3 +#define reg_eth_rw_intr_mask___single_col___lsb 4 +#define reg_eth_rw_intr_mask___single_col___width 1 +#define reg_eth_rw_intr_mask___single_col___bit 4 +#define reg_eth_rw_intr_mask___mult_col___lsb 5 +#define reg_eth_rw_intr_mask___mult_col___width 1 +#define reg_eth_rw_intr_mask___mult_col___bit 5 +#define reg_eth_rw_intr_mask___late_col___lsb 6 +#define reg_eth_rw_intr_mask___late_col___width 1 +#define reg_eth_rw_intr_mask___late_col___bit 6 +#define reg_eth_rw_intr_mask___deferred___lsb 7 +#define reg_eth_rw_intr_mask___deferred___width 1 +#define reg_eth_rw_intr_mask___deferred___bit 7 +#define reg_eth_rw_intr_mask___carrier_loss___lsb 8 +#define reg_eth_rw_intr_mask___carrier_loss___width 1 +#define reg_eth_rw_intr_mask___carrier_loss___bit 8 +#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 +#define reg_eth_rw_intr_mask___sqe_test_err___width 1 +#define reg_eth_rw_intr_mask___sqe_test_err___bit 9 +#define reg_eth_rw_intr_mask___orun___lsb 10 +#define reg_eth_rw_intr_mask___orun___width 1 +#define reg_eth_rw_intr_mask___orun___bit 10 +#define reg_eth_rw_intr_mask___urun___lsb 11 +#define reg_eth_rw_intr_mask___urun___width 1 +#define reg_eth_rw_intr_mask___urun___bit 11 +#define reg_eth_rw_intr_mask___excessive_col___lsb 12 +#define reg_eth_rw_intr_mask___excessive_col___width 1 +#define reg_eth_rw_intr_mask___excessive_col___bit 12 +#define reg_eth_rw_intr_mask___mdio___lsb 13 +#define reg_eth_rw_intr_mask___mdio___width 1 +#define reg_eth_rw_intr_mask___mdio___bit 13 +#define reg_eth_rw_intr_mask_offset 76 + +/* Register rw_ack_intr, scope eth, type rw */ +#define reg_eth_rw_ack_intr___crc___lsb 0 +#define reg_eth_rw_ack_intr___crc___width 1 +#define reg_eth_rw_ack_intr___crc___bit 0 +#define reg_eth_rw_ack_intr___align___lsb 1 +#define reg_eth_rw_ack_intr___align___width 1 +#define reg_eth_rw_ack_intr___align___bit 1 +#define reg_eth_rw_ack_intr___oversize___lsb 2 +#define reg_eth_rw_ack_intr___oversize___width 1 +#define reg_eth_rw_ack_intr___oversize___bit 2 +#define reg_eth_rw_ack_intr___congestion___lsb 3 +#define reg_eth_rw_ack_intr___congestion___width 1 +#define reg_eth_rw_ack_intr___congestion___bit 3 +#define reg_eth_rw_ack_intr___single_col___lsb 4 +#define reg_eth_rw_ack_intr___single_col___width 1 +#define reg_eth_rw_ack_intr___single_col___bit 4 +#define reg_eth_rw_ack_intr___mult_col___lsb 5 +#define reg_eth_rw_ack_intr___mult_col___width 1 +#define reg_eth_rw_ack_intr___mult_col___bit 5 +#define reg_eth_rw_ack_intr___late_col___lsb 6 +#define reg_eth_rw_ack_intr___late_col___width 1 +#define reg_eth_rw_ack_intr___late_col___bit 6 +#define reg_eth_rw_ack_intr___deferred___lsb 7 +#define reg_eth_rw_ack_intr___deferred___width 1 +#define reg_eth_rw_ack_intr___deferred___bit 7 +#define reg_eth_rw_ack_intr___carrier_loss___lsb 8 +#define reg_eth_rw_ack_intr___carrier_loss___width 1 +#define reg_eth_rw_ack_intr___carrier_loss___bit 8 +#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 +#define reg_eth_rw_ack_intr___sqe_test_err___width 1 +#define reg_eth_rw_ack_intr___sqe_test_err___bit 9 +#define reg_eth_rw_ack_intr___orun___lsb 10 +#define reg_eth_rw_ack_intr___orun___width 1 +#define reg_eth_rw_ack_intr___orun___bit 10 +#define reg_eth_rw_ack_intr___urun___lsb 11 +#define reg_eth_rw_ack_intr___urun___width 1 +#define reg_eth_rw_ack_intr___urun___bit 11 +#define reg_eth_rw_ack_intr___excessive_col___lsb 12 +#define reg_eth_rw_ack_intr___excessive_col___width 1 +#define reg_eth_rw_ack_intr___excessive_col___bit 12 +#define reg_eth_rw_ack_intr___mdio___lsb 13 +#define reg_eth_rw_ack_intr___mdio___width 1 +#define reg_eth_rw_ack_intr___mdio___bit 13 +#define reg_eth_rw_ack_intr_offset 80 + +/* Register r_intr, scope eth, type r */ +#define reg_eth_r_intr___crc___lsb 0 +#define reg_eth_r_intr___crc___width 1 +#define reg_eth_r_intr___crc___bit 0 +#define reg_eth_r_intr___align___lsb 1 +#define reg_eth_r_intr___align___width 1 +#define reg_eth_r_intr___align___bit 1 +#define reg_eth_r_intr___oversize___lsb 2 +#define reg_eth_r_intr___oversize___width 1 +#define reg_eth_r_intr___oversize___bit 2 +#define reg_eth_r_intr___congestion___lsb 3 +#define reg_eth_r_intr___congestion___width 1 +#define reg_eth_r_intr___congestion___bit 3 +#define reg_eth_r_intr___single_col___lsb 4 +#define reg_eth_r_intr___single_col___width 1 +#define reg_eth_r_intr___single_col___bit 4 +#define reg_eth_r_intr___mult_col___lsb 5 +#define reg_eth_r_intr___mult_col___width 1 +#define reg_eth_r_intr___mult_col___bit 5 +#define reg_eth_r_intr___late_col___lsb 6 +#define reg_eth_r_intr___late_col___width 1 +#define reg_eth_r_intr___late_col___bit 6 +#define reg_eth_r_intr___deferred___lsb 7 +#define reg_eth_r_intr___deferred___width 1 +#define reg_eth_r_intr___deferred___bit 7 +#define reg_eth_r_intr___carrier_loss___lsb 8 +#define reg_eth_r_intr___carrier_loss___width 1 +#define reg_eth_r_intr___carrier_loss___bit 8 +#define reg_eth_r_intr___sqe_test_err___lsb 9 +#define reg_eth_r_intr___sqe_test_err___width 1 +#define reg_eth_r_intr___sqe_test_err___bit 9 +#define reg_eth_r_intr___orun___lsb 10 +#define reg_eth_r_intr___orun___width 1 +#define reg_eth_r_intr___orun___bit 10 +#define reg_eth_r_intr___urun___lsb 11 +#define reg_eth_r_intr___urun___width 1 +#define reg_eth_r_intr___urun___bit 11 +#define reg_eth_r_intr___excessive_col___lsb 12 +#define reg_eth_r_intr___excessive_col___width 1 +#define reg_eth_r_intr___excessive_col___bit 12 +#define reg_eth_r_intr___mdio___lsb 13 +#define reg_eth_r_intr___mdio___width 1 +#define reg_eth_r_intr___mdio___bit 13 +#define reg_eth_r_intr_offset 84 + +/* Register r_masked_intr, scope eth, type r */ +#define reg_eth_r_masked_intr___crc___lsb 0 +#define reg_eth_r_masked_intr___crc___width 1 +#define reg_eth_r_masked_intr___crc___bit 0 +#define reg_eth_r_masked_intr___align___lsb 1 +#define reg_eth_r_masked_intr___align___width 1 +#define reg_eth_r_masked_intr___align___bit 1 +#define reg_eth_r_masked_intr___oversize___lsb 2 +#define reg_eth_r_masked_intr___oversize___width 1 +#define reg_eth_r_masked_intr___oversize___bit 2 +#define reg_eth_r_masked_intr___congestion___lsb 3 +#define reg_eth_r_masked_intr___congestion___width 1 +#define reg_eth_r_masked_intr___congestion___bit 3 +#define reg_eth_r_masked_intr___single_col___lsb 4 +#define reg_eth_r_masked_intr___single_col___width 1 +#define reg_eth_r_masked_intr___single_col___bit 4 +#define reg_eth_r_masked_intr___mult_col___lsb 5 +#define reg_eth_r_masked_intr___mult_col___width 1 +#define reg_eth_r_masked_intr___mult_col___bit 5 +#define reg_eth_r_masked_intr___late_col___lsb 6 +#define reg_eth_r_masked_intr___late_col___width 1 +#define reg_eth_r_masked_intr___late_col___bit 6 +#define reg_eth_r_masked_intr___deferred___lsb 7 +#define reg_eth_r_masked_intr___deferred___width 1 +#define reg_eth_r_masked_intr___deferred___bit 7 +#define reg_eth_r_masked_intr___carrier_loss___lsb 8 +#define reg_eth_r_masked_intr___carrier_loss___width 1 +#define reg_eth_r_masked_intr___carrier_loss___bit 8 +#define reg_eth_r_masked_intr___sqe_test_err___lsb 9 +#define reg_eth_r_masked_intr___sqe_test_err___width 1 +#define reg_eth_r_masked_intr___sqe_test_err___bit 9 +#define reg_eth_r_masked_intr___orun___lsb 10 +#define reg_eth_r_masked_intr___orun___width 1 +#define reg_eth_r_masked_intr___orun___bit 10 +#define reg_eth_r_masked_intr___urun___lsb 11 +#define reg_eth_r_masked_intr___urun___width 1 +#define reg_eth_r_masked_intr___urun___bit 11 +#define reg_eth_r_masked_intr___excessive_col___lsb 12 +#define reg_eth_r_masked_intr___excessive_col___width 1 +#define reg_eth_r_masked_intr___excessive_col___bit 12 +#define reg_eth_r_masked_intr___mdio___lsb 13 +#define reg_eth_r_masked_intr___mdio___width 1 +#define reg_eth_r_masked_intr___mdio___bit 13 +#define reg_eth_r_masked_intr_offset 88 + + +/* Constants */ +#define regk_eth_discard 0x00000000 +#define regk_eth_ether 0x00000000 +#define regk_eth_full 0x00000001 +#define regk_eth_half 0x00000000 +#define regk_eth_hsh 0x00000001 +#define regk_eth_mii 0x00000001 +#define regk_eth_mii_clk 0x00000000 +#define regk_eth_mii_rec 0x00000002 +#define regk_eth_no 0x00000000 +#define regk_eth_rec 0x00000001 +#define regk_eth_rw_ga_hi_default 0x00000000 +#define regk_eth_rw_ga_lo_default 0x00000000 +#define regk_eth_rw_gen_ctrl_default 0x00000000 +#define regk_eth_rw_intr_mask_default 0x00000000 +#define regk_eth_rw_ma0_hi_default 0x00000000 +#define regk_eth_rw_ma0_lo_default 0x00000000 +#define regk_eth_rw_ma1_hi_default 0x00000000 +#define regk_eth_rw_ma1_lo_default 0x00000000 +#define regk_eth_rw_mgm_ctrl_default 0x00000000 +#define regk_eth_rw_test_ctrl_default 0x00000000 +#define regk_eth_size1518 0x00000000 +#define regk_eth_size1522 0x00000001 +#define regk_eth_yes 0x00000001 +#endif /* __eth_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000..35356bc08 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 8 +#define reg_gio_rw_pa_dout_offset 0 + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 8 +#define reg_gio_r_pa_din_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 8 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___pa0___lsb 0 +#define reg_gio_rw_intr_cfg___pa0___width 3 +#define reg_gio_rw_intr_cfg___pa1___lsb 3 +#define reg_gio_rw_intr_cfg___pa1___width 3 +#define reg_gio_rw_intr_cfg___pa2___lsb 6 +#define reg_gio_rw_intr_cfg___pa2___width 3 +#define reg_gio_rw_intr_cfg___pa3___lsb 9 +#define reg_gio_rw_intr_cfg___pa3___width 3 +#define reg_gio_rw_intr_cfg___pa4___lsb 12 +#define reg_gio_rw_intr_cfg___pa4___width 3 +#define reg_gio_rw_intr_cfg___pa5___lsb 15 +#define reg_gio_rw_intr_cfg___pa5___width 3 +#define reg_gio_rw_intr_cfg___pa6___lsb 18 +#define reg_gio_rw_intr_cfg___pa6___width 3 +#define reg_gio_rw_intr_cfg___pa7___lsb 21 +#define reg_gio_rw_intr_cfg___pa7___width 3 +#define reg_gio_rw_intr_cfg_offset 12 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___pa0___lsb 0 +#define reg_gio_rw_intr_mask___pa0___width 1 +#define reg_gio_rw_intr_mask___pa0___bit 0 +#define reg_gio_rw_intr_mask___pa1___lsb 1 +#define reg_gio_rw_intr_mask___pa1___width 1 +#define reg_gio_rw_intr_mask___pa1___bit 1 +#define reg_gio_rw_intr_mask___pa2___lsb 2 +#define reg_gio_rw_intr_mask___pa2___width 1 +#define reg_gio_rw_intr_mask___pa2___bit 2 +#define reg_gio_rw_intr_mask___pa3___lsb 3 +#define reg_gio_rw_intr_mask___pa3___width 1 +#define reg_gio_rw_intr_mask___pa3___bit 3 +#define reg_gio_rw_intr_mask___pa4___lsb 4 +#define reg_gio_rw_intr_mask___pa4___width 1 +#define reg_gio_rw_intr_mask___pa4___bit 4 +#define reg_gio_rw_intr_mask___pa5___lsb 5 +#define reg_gio_rw_intr_mask___pa5___width 1 +#define reg_gio_rw_intr_mask___pa5___bit 5 +#define reg_gio_rw_intr_mask___pa6___lsb 6 +#define reg_gio_rw_intr_mask___pa6___width 1 +#define reg_gio_rw_intr_mask___pa6___bit 6 +#define reg_gio_rw_intr_mask___pa7___lsb 7 +#define reg_gio_rw_intr_mask___pa7___width 1 +#define reg_gio_rw_intr_mask___pa7___bit 7 +#define reg_gio_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___pa0___lsb 0 +#define reg_gio_rw_ack_intr___pa0___width 1 +#define reg_gio_rw_ack_intr___pa0___bit 0 +#define reg_gio_rw_ack_intr___pa1___lsb 1 +#define reg_gio_rw_ack_intr___pa1___width 1 +#define reg_gio_rw_ack_intr___pa1___bit 1 +#define reg_gio_rw_ack_intr___pa2___lsb 2 +#define reg_gio_rw_ack_intr___pa2___width 1 +#define reg_gio_rw_ack_intr___pa2___bit 2 +#define reg_gio_rw_ack_intr___pa3___lsb 3 +#define reg_gio_rw_ack_intr___pa3___width 1 +#define reg_gio_rw_ack_intr___pa3___bit 3 +#define reg_gio_rw_ack_intr___pa4___lsb 4 +#define reg_gio_rw_ack_intr___pa4___width 1 +#define reg_gio_rw_ack_intr___pa4___bit 4 +#define reg_gio_rw_ack_intr___pa5___lsb 5 +#define reg_gio_rw_ack_intr___pa5___width 1 +#define reg_gio_rw_ack_intr___pa5___bit 5 +#define reg_gio_rw_ack_intr___pa6___lsb 6 +#define reg_gio_rw_ack_intr___pa6___width 1 +#define reg_gio_rw_ack_intr___pa6___bit 6 +#define reg_gio_rw_ack_intr___pa7___lsb 7 +#define reg_gio_rw_ack_intr___pa7___width 1 +#define reg_gio_rw_ack_intr___pa7___bit 7 +#define reg_gio_rw_ack_intr_offset 20 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___pa0___lsb 0 +#define reg_gio_r_intr___pa0___width 1 +#define reg_gio_r_intr___pa0___bit 0 +#define reg_gio_r_intr___pa1___lsb 1 +#define reg_gio_r_intr___pa1___width 1 +#define reg_gio_r_intr___pa1___bit 1 +#define reg_gio_r_intr___pa2___lsb 2 +#define reg_gio_r_intr___pa2___width 1 +#define reg_gio_r_intr___pa2___bit 2 +#define reg_gio_r_intr___pa3___lsb 3 +#define reg_gio_r_intr___pa3___width 1 +#define reg_gio_r_intr___pa3___bit 3 +#define reg_gio_r_intr___pa4___lsb 4 +#define reg_gio_r_intr___pa4___width 1 +#define reg_gio_r_intr___pa4___bit 4 +#define reg_gio_r_intr___pa5___lsb 5 +#define reg_gio_r_intr___pa5___width 1 +#define reg_gio_r_intr___pa5___bit 5 +#define reg_gio_r_intr___pa6___lsb 6 +#define reg_gio_r_intr___pa6___width 1 +#define reg_gio_r_intr___pa6___bit 6 +#define reg_gio_r_intr___pa7___lsb 7 +#define reg_gio_r_intr___pa7___width 1 +#define reg_gio_r_intr___pa7___bit 7 +#define reg_gio_r_intr_offset 24 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___pa0___lsb 0 +#define reg_gio_r_masked_intr___pa0___width 1 +#define reg_gio_r_masked_intr___pa0___bit 0 +#define reg_gio_r_masked_intr___pa1___lsb 1 +#define reg_gio_r_masked_intr___pa1___width 1 +#define reg_gio_r_masked_intr___pa1___bit 1 +#define reg_gio_r_masked_intr___pa2___lsb 2 +#define reg_gio_r_masked_intr___pa2___width 1 +#define reg_gio_r_masked_intr___pa2___bit 2 +#define reg_gio_r_masked_intr___pa3___lsb 3 +#define reg_gio_r_masked_intr___pa3___width 1 +#define reg_gio_r_masked_intr___pa3___bit 3 +#define reg_gio_r_masked_intr___pa4___lsb 4 +#define reg_gio_r_masked_intr___pa4___width 1 +#define reg_gio_r_masked_intr___pa4___bit 4 +#define reg_gio_r_masked_intr___pa5___lsb 5 +#define reg_gio_r_masked_intr___pa5___width 1 +#define reg_gio_r_masked_intr___pa5___bit 5 +#define reg_gio_r_masked_intr___pa6___lsb 6 +#define reg_gio_r_masked_intr___pa6___width 1 +#define reg_gio_r_masked_intr___pa6___bit 6 +#define reg_gio_r_masked_intr___pa7___lsb 7 +#define reg_gio_r_masked_intr___pa7___width 1 +#define reg_gio_r_masked_intr___pa7___bit 7 +#define reg_gio_r_masked_intr_offset 28 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 18 +#define reg_gio_rw_pb_dout_offset 32 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 18 +#define reg_gio_r_pb_din_offset 36 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 18 +#define reg_gio_rw_pb_oe_offset 40 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 18 +#define reg_gio_rw_pc_dout_offset 48 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 18 +#define reg_gio_r_pc_din_offset 52 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 18 +#define reg_gio_rw_pc_oe_offset 56 + +/* Register rw_pd_dout, scope gio, type rw */ +#define reg_gio_rw_pd_dout___data___lsb 0 +#define reg_gio_rw_pd_dout___data___width 18 +#define reg_gio_rw_pd_dout_offset 64 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 18 +#define reg_gio_r_pd_din_offset 68 + +/* Register rw_pd_oe, scope gio, type rw */ +#define reg_gio_rw_pd_oe___oe___lsb 0 +#define reg_gio_rw_pd_oe___oe___width 18 +#define reg_gio_rw_pd_oe_offset 72 + +/* Register rw_pe_dout, scope gio, type rw */ +#define reg_gio_rw_pe_dout___data___lsb 0 +#define reg_gio_rw_pe_dout___data___width 18 +#define reg_gio_rw_pe_dout_offset 80 + +/* Register r_pe_din, scope gio, type r */ +#define reg_gio_r_pe_din___data___lsb 0 +#define reg_gio_r_pe_din___data___width 18 +#define reg_gio_r_pe_din_offset 84 + +/* Register rw_pe_oe, scope gio, type rw */ +#define reg_gio_rw_pe_oe___oe___lsb 0 +#define reg_gio_rw_pe_oe___oe___width 18 +#define reg_gio_rw_pe_oe_offset 88 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_hi 0x00000001 +#define regk_gio_lo 0x00000002 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_off 0x00000000 +#define regk_gio_posedge 0x00000005 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_pd_oe_default 0x00000000 +#define regk_gio_rw_pe_oe_default 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h new file mode 100644 index 000000000..c8315905c --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h @@ -0,0 +1,38 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/intr_vect/rtl/guinness/ivmask.config.r +version . */ + +#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define MEMARB_INTR_VECT 0x31 +#define GEN_IO_INTR_VECT 0x32 +#define IOP0_INTR_VECT 0x33 +#define IOP1_INTR_VECT 0x34 +#define IOP2_INTR_VECT 0x35 +#define IOP3_INTR_VECT 0x36 +#define DMA0_INTR_VECT 0x37 +#define DMA1_INTR_VECT 0x38 +#define DMA2_INTR_VECT 0x39 +#define DMA3_INTR_VECT 0x3a +#define DMA4_INTR_VECT 0x3b +#define DMA5_INTR_VECT 0x3c +#define DMA6_INTR_VECT 0x3d +#define DMA7_INTR_VECT 0x3e +#define DMA8_INTR_VECT 0x3f +#define DMA9_INTR_VECT 0x40 +#define ATA_INTR_VECT 0x41 +#define SSER0_INTR_VECT 0x42 +#define SSER1_INTR_VECT 0x43 +#define SER0_INTR_VECT 0x44 +#define SER1_INTR_VECT 0x45 +#define SER2_INTR_VECT 0x46 +#define SER3_INTR_VECT 0x47 +#define P21_INTR_VECT 0x48 +#define ETH0_INTR_VECT 0x49 +#define ETH1_INTR_VECT 0x4a +#define TIMER_INTR_VECT 0x4b +#define BIF_ARB_INTR_VECT 0x4c +#define BIF_DMA_INTR_VECT 0x4d +#define EXT_INTR_VECT 0x4e + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h new file mode 100644 index 000000000..6df2a433b --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h @@ -0,0 +1,355 @@ +#ifndef __intr_vect_defs_asm_h +#define __intr_vect_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp + * last modfied: Mon Apr 11 16:08:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mask, scope intr_vect, type rw */ +#define reg_intr_vect_rw_mask___memarb___lsb 0 +#define reg_intr_vect_rw_mask___memarb___width 1 +#define reg_intr_vect_rw_mask___memarb___bit 0 +#define reg_intr_vect_rw_mask___gen_io___lsb 1 +#define reg_intr_vect_rw_mask___gen_io___width 1 +#define reg_intr_vect_rw_mask___gen_io___bit 1 +#define reg_intr_vect_rw_mask___iop0___lsb 2 +#define reg_intr_vect_rw_mask___iop0___width 1 +#define reg_intr_vect_rw_mask___iop0___bit 2 +#define reg_intr_vect_rw_mask___iop1___lsb 3 +#define reg_intr_vect_rw_mask___iop1___width 1 +#define reg_intr_vect_rw_mask___iop1___bit 3 +#define reg_intr_vect_rw_mask___iop2___lsb 4 +#define reg_intr_vect_rw_mask___iop2___width 1 +#define reg_intr_vect_rw_mask___iop2___bit 4 +#define reg_intr_vect_rw_mask___iop3___lsb 5 +#define reg_intr_vect_rw_mask___iop3___width 1 +#define reg_intr_vect_rw_mask___iop3___bit 5 +#define reg_intr_vect_rw_mask___dma0___lsb 6 +#define reg_intr_vect_rw_mask___dma0___width 1 +#define reg_intr_vect_rw_mask___dma0___bit 6 +#define reg_intr_vect_rw_mask___dma1___lsb 7 +#define reg_intr_vect_rw_mask___dma1___width 1 +#define reg_intr_vect_rw_mask___dma1___bit 7 +#define reg_intr_vect_rw_mask___dma2___lsb 8 +#define reg_intr_vect_rw_mask___dma2___width 1 +#define reg_intr_vect_rw_mask___dma2___bit 8 +#define reg_intr_vect_rw_mask___dma3___lsb 9 +#define reg_intr_vect_rw_mask___dma3___width 1 +#define reg_intr_vect_rw_mask___dma3___bit 9 +#define reg_intr_vect_rw_mask___dma4___lsb 10 +#define reg_intr_vect_rw_mask___dma4___width 1 +#define reg_intr_vect_rw_mask___dma4___bit 10 +#define reg_intr_vect_rw_mask___dma5___lsb 11 +#define reg_intr_vect_rw_mask___dma5___width 1 +#define reg_intr_vect_rw_mask___dma5___bit 11 +#define reg_intr_vect_rw_mask___dma6___lsb 12 +#define reg_intr_vect_rw_mask___dma6___width 1 +#define reg_intr_vect_rw_mask___dma6___bit 12 +#define reg_intr_vect_rw_mask___dma7___lsb 13 +#define reg_intr_vect_rw_mask___dma7___width 1 +#define reg_intr_vect_rw_mask___dma7___bit 13 +#define reg_intr_vect_rw_mask___dma8___lsb 14 +#define reg_intr_vect_rw_mask___dma8___width 1 +#define reg_intr_vect_rw_mask___dma8___bit 14 +#define reg_intr_vect_rw_mask___dma9___lsb 15 +#define reg_intr_vect_rw_mask___dma9___width 1 +#define reg_intr_vect_rw_mask___dma9___bit 15 +#define reg_intr_vect_rw_mask___ata___lsb 16 +#define reg_intr_vect_rw_mask___ata___width 1 +#define reg_intr_vect_rw_mask___ata___bit 16 +#define reg_intr_vect_rw_mask___sser0___lsb 17 +#define reg_intr_vect_rw_mask___sser0___width 1 +#define reg_intr_vect_rw_mask___sser0___bit 17 +#define reg_intr_vect_rw_mask___sser1___lsb 18 +#define reg_intr_vect_rw_mask___sser1___width 1 +#define reg_intr_vect_rw_mask___sser1___bit 18 +#define reg_intr_vect_rw_mask___ser0___lsb 19 +#define reg_intr_vect_rw_mask___ser0___width 1 +#define reg_intr_vect_rw_mask___ser0___bit 19 +#define reg_intr_vect_rw_mask___ser1___lsb 20 +#define reg_intr_vect_rw_mask___ser1___width 1 +#define reg_intr_vect_rw_mask___ser1___bit 20 +#define reg_intr_vect_rw_mask___ser2___lsb 21 +#define reg_intr_vect_rw_mask___ser2___width 1 +#define reg_intr_vect_rw_mask___ser2___bit 21 +#define reg_intr_vect_rw_mask___ser3___lsb 22 +#define reg_intr_vect_rw_mask___ser3___width 1 +#define reg_intr_vect_rw_mask___ser3___bit 22 +#define reg_intr_vect_rw_mask___p21___lsb 23 +#define reg_intr_vect_rw_mask___p21___width 1 +#define reg_intr_vect_rw_mask___p21___bit 23 +#define reg_intr_vect_rw_mask___eth0___lsb 24 +#define reg_intr_vect_rw_mask___eth0___width 1 +#define reg_intr_vect_rw_mask___eth0___bit 24 +#define reg_intr_vect_rw_mask___eth1___lsb 25 +#define reg_intr_vect_rw_mask___eth1___width 1 +#define reg_intr_vect_rw_mask___eth1___bit 25 +#define reg_intr_vect_rw_mask___timer___lsb 26 +#define reg_intr_vect_rw_mask___timer___width 1 +#define reg_intr_vect_rw_mask___timer___bit 26 +#define reg_intr_vect_rw_mask___bif_arb___lsb 27 +#define reg_intr_vect_rw_mask___bif_arb___width 1 +#define reg_intr_vect_rw_mask___bif_arb___bit 27 +#define reg_intr_vect_rw_mask___bif_dma___lsb 28 +#define reg_intr_vect_rw_mask___bif_dma___width 1 +#define reg_intr_vect_rw_mask___bif_dma___bit 28 +#define reg_intr_vect_rw_mask___ext___lsb 29 +#define reg_intr_vect_rw_mask___ext___width 1 +#define reg_intr_vect_rw_mask___ext___bit 29 +#define reg_intr_vect_rw_mask_offset 0 + +/* Register r_vect, scope intr_vect, type r */ +#define reg_intr_vect_r_vect___memarb___lsb 0 +#define reg_intr_vect_r_vect___memarb___width 1 +#define reg_intr_vect_r_vect___memarb___bit 0 +#define reg_intr_vect_r_vect___gen_io___lsb 1 +#define reg_intr_vect_r_vect___gen_io___width 1 +#define reg_intr_vect_r_vect___gen_io___bit 1 +#define reg_intr_vect_r_vect___iop0___lsb 2 +#define reg_intr_vect_r_vect___iop0___width 1 +#define reg_intr_vect_r_vect___iop0___bit 2 +#define reg_intr_vect_r_vect___iop1___lsb 3 +#define reg_intr_vect_r_vect___iop1___width 1 +#define reg_intr_vect_r_vect___iop1___bit 3 +#define reg_intr_vect_r_vect___iop2___lsb 4 +#define reg_intr_vect_r_vect___iop2___width 1 +#define reg_intr_vect_r_vect___iop2___bit 4 +#define reg_intr_vect_r_vect___iop3___lsb 5 +#define reg_intr_vect_r_vect___iop3___width 1 +#define reg_intr_vect_r_vect___iop3___bit 5 +#define reg_intr_vect_r_vect___dma0___lsb 6 +#define reg_intr_vect_r_vect___dma0___width 1 +#define reg_intr_vect_r_vect___dma0___bit 6 +#define reg_intr_vect_r_vect___dma1___lsb 7 +#define reg_intr_vect_r_vect___dma1___width 1 +#define reg_intr_vect_r_vect___dma1___bit 7 +#define reg_intr_vect_r_vect___dma2___lsb 8 +#define reg_intr_vect_r_vect___dma2___width 1 +#define reg_intr_vect_r_vect___dma2___bit 8 +#define reg_intr_vect_r_vect___dma3___lsb 9 +#define reg_intr_vect_r_vect___dma3___width 1 +#define reg_intr_vect_r_vect___dma3___bit 9 +#define reg_intr_vect_r_vect___dma4___lsb 10 +#define reg_intr_vect_r_vect___dma4___width 1 +#define reg_intr_vect_r_vect___dma4___bit 10 +#define reg_intr_vect_r_vect___dma5___lsb 11 +#define reg_intr_vect_r_vect___dma5___width 1 +#define reg_intr_vect_r_vect___dma5___bit 11 +#define reg_intr_vect_r_vect___dma6___lsb 12 +#define reg_intr_vect_r_vect___dma6___width 1 +#define reg_intr_vect_r_vect___dma6___bit 12 +#define reg_intr_vect_r_vect___dma7___lsb 13 +#define reg_intr_vect_r_vect___dma7___width 1 +#define reg_intr_vect_r_vect___dma7___bit 13 +#define reg_intr_vect_r_vect___dma8___lsb 14 +#define reg_intr_vect_r_vect___dma8___width 1 +#define reg_intr_vect_r_vect___dma8___bit 14 +#define reg_intr_vect_r_vect___dma9___lsb 15 +#define reg_intr_vect_r_vect___dma9___width 1 +#define reg_intr_vect_r_vect___dma9___bit 15 +#define reg_intr_vect_r_vect___ata___lsb 16 +#define reg_intr_vect_r_vect___ata___width 1 +#define reg_intr_vect_r_vect___ata___bit 16 +#define reg_intr_vect_r_vect___sser0___lsb 17 +#define reg_intr_vect_r_vect___sser0___width 1 +#define reg_intr_vect_r_vect___sser0___bit 17 +#define reg_intr_vect_r_vect___sser1___lsb 18 +#define reg_intr_vect_r_vect___sser1___width 1 +#define reg_intr_vect_r_vect___sser1___bit 18 +#define reg_intr_vect_r_vect___ser0___lsb 19 +#define reg_intr_vect_r_vect___ser0___width 1 +#define reg_intr_vect_r_vect___ser0___bit 19 +#define reg_intr_vect_r_vect___ser1___lsb 20 +#define reg_intr_vect_r_vect___ser1___width 1 +#define reg_intr_vect_r_vect___ser1___bit 20 +#define reg_intr_vect_r_vect___ser2___lsb 21 +#define reg_intr_vect_r_vect___ser2___width 1 +#define reg_intr_vect_r_vect___ser2___bit 21 +#define reg_intr_vect_r_vect___ser3___lsb 22 +#define reg_intr_vect_r_vect___ser3___width 1 +#define reg_intr_vect_r_vect___ser3___bit 22 +#define reg_intr_vect_r_vect___p21___lsb 23 +#define reg_intr_vect_r_vect___p21___width 1 +#define reg_intr_vect_r_vect___p21___bit 23 +#define reg_intr_vect_r_vect___eth0___lsb 24 +#define reg_intr_vect_r_vect___eth0___width 1 +#define reg_intr_vect_r_vect___eth0___bit 24 +#define reg_intr_vect_r_vect___eth1___lsb 25 +#define reg_intr_vect_r_vect___eth1___width 1 +#define reg_intr_vect_r_vect___eth1___bit 25 +#define reg_intr_vect_r_vect___timer___lsb 26 +#define reg_intr_vect_r_vect___timer___width 1 +#define reg_intr_vect_r_vect___timer___bit 26 +#define reg_intr_vect_r_vect___bif_arb___lsb 27 +#define reg_intr_vect_r_vect___bif_arb___width 1 +#define reg_intr_vect_r_vect___bif_arb___bit 27 +#define reg_intr_vect_r_vect___bif_dma___lsb 28 +#define reg_intr_vect_r_vect___bif_dma___width 1 +#define reg_intr_vect_r_vect___bif_dma___bit 28 +#define reg_intr_vect_r_vect___ext___lsb 29 +#define reg_intr_vect_r_vect___ext___width 1 +#define reg_intr_vect_r_vect___ext___bit 29 +#define reg_intr_vect_r_vect_offset 4 + +/* Register r_masked_vect, scope intr_vect, type r */ +#define reg_intr_vect_r_masked_vect___memarb___lsb 0 +#define reg_intr_vect_r_masked_vect___memarb___width 1 +#define reg_intr_vect_r_masked_vect___memarb___bit 0 +#define reg_intr_vect_r_masked_vect___gen_io___lsb 1 +#define reg_intr_vect_r_masked_vect___gen_io___width 1 +#define reg_intr_vect_r_masked_vect___gen_io___bit 1 +#define reg_intr_vect_r_masked_vect___iop0___lsb 2 +#define reg_intr_vect_r_masked_vect___iop0___width 1 +#define reg_intr_vect_r_masked_vect___iop0___bit 2 +#define reg_intr_vect_r_masked_vect___iop1___lsb 3 +#define reg_intr_vect_r_masked_vect___iop1___width 1 +#define reg_intr_vect_r_masked_vect___iop1___bit 3 +#define reg_intr_vect_r_masked_vect___iop2___lsb 4 +#define reg_intr_vect_r_masked_vect___iop2___width 1 +#define reg_intr_vect_r_masked_vect___iop2___bit 4 +#define reg_intr_vect_r_masked_vect___iop3___lsb 5 +#define reg_intr_vect_r_masked_vect___iop3___width 1 +#define reg_intr_vect_r_masked_vect___iop3___bit 5 +#define reg_intr_vect_r_masked_vect___dma0___lsb 6 +#define reg_intr_vect_r_masked_vect___dma0___width 1 +#define reg_intr_vect_r_masked_vect___dma0___bit 6 +#define reg_intr_vect_r_masked_vect___dma1___lsb 7 +#define reg_intr_vect_r_masked_vect___dma1___width 1 +#define reg_intr_vect_r_masked_vect___dma1___bit 7 +#define reg_intr_vect_r_masked_vect___dma2___lsb 8 +#define reg_intr_vect_r_masked_vect___dma2___width 1 +#define reg_intr_vect_r_masked_vect___dma2___bit 8 +#define reg_intr_vect_r_masked_vect___dma3___lsb 9 +#define reg_intr_vect_r_masked_vect___dma3___width 1 +#define reg_intr_vect_r_masked_vect___dma3___bit 9 +#define reg_intr_vect_r_masked_vect___dma4___lsb 10 +#define reg_intr_vect_r_masked_vect___dma4___width 1 +#define reg_intr_vect_r_masked_vect___dma4___bit 10 +#define reg_intr_vect_r_masked_vect___dma5___lsb 11 +#define reg_intr_vect_r_masked_vect___dma5___width 1 +#define reg_intr_vect_r_masked_vect___dma5___bit 11 +#define reg_intr_vect_r_masked_vect___dma6___lsb 12 +#define reg_intr_vect_r_masked_vect___dma6___width 1 +#define reg_intr_vect_r_masked_vect___dma6___bit 12 +#define reg_intr_vect_r_masked_vect___dma7___lsb 13 +#define reg_intr_vect_r_masked_vect___dma7___width 1 +#define reg_intr_vect_r_masked_vect___dma7___bit 13 +#define reg_intr_vect_r_masked_vect___dma8___lsb 14 +#define reg_intr_vect_r_masked_vect___dma8___width 1 +#define reg_intr_vect_r_masked_vect___dma8___bit 14 +#define reg_intr_vect_r_masked_vect___dma9___lsb 15 +#define reg_intr_vect_r_masked_vect___dma9___width 1 +#define reg_intr_vect_r_masked_vect___dma9___bit 15 +#define reg_intr_vect_r_masked_vect___ata___lsb 16 +#define reg_intr_vect_r_masked_vect___ata___width 1 +#define reg_intr_vect_r_masked_vect___ata___bit 16 +#define reg_intr_vect_r_masked_vect___sser0___lsb 17 +#define reg_intr_vect_r_masked_vect___sser0___width 1 +#define reg_intr_vect_r_masked_vect___sser0___bit 17 +#define reg_intr_vect_r_masked_vect___sser1___lsb 18 +#define reg_intr_vect_r_masked_vect___sser1___width 1 +#define reg_intr_vect_r_masked_vect___sser1___bit 18 +#define reg_intr_vect_r_masked_vect___ser0___lsb 19 +#define reg_intr_vect_r_masked_vect___ser0___width 1 +#define reg_intr_vect_r_masked_vect___ser0___bit 19 +#define reg_intr_vect_r_masked_vect___ser1___lsb 20 +#define reg_intr_vect_r_masked_vect___ser1___width 1 +#define reg_intr_vect_r_masked_vect___ser1___bit 20 +#define reg_intr_vect_r_masked_vect___ser2___lsb 21 +#define reg_intr_vect_r_masked_vect___ser2___width 1 +#define reg_intr_vect_r_masked_vect___ser2___bit 21 +#define reg_intr_vect_r_masked_vect___ser3___lsb 22 +#define reg_intr_vect_r_masked_vect___ser3___width 1 +#define reg_intr_vect_r_masked_vect___ser3___bit 22 +#define reg_intr_vect_r_masked_vect___p21___lsb 23 +#define reg_intr_vect_r_masked_vect___p21___width 1 +#define reg_intr_vect_r_masked_vect___p21___bit 23 +#define reg_intr_vect_r_masked_vect___eth0___lsb 24 +#define reg_intr_vect_r_masked_vect___eth0___width 1 +#define reg_intr_vect_r_masked_vect___eth0___bit 24 +#define reg_intr_vect_r_masked_vect___eth1___lsb 25 +#define reg_intr_vect_r_masked_vect___eth1___width 1 +#define reg_intr_vect_r_masked_vect___eth1___bit 25 +#define reg_intr_vect_r_masked_vect___timer___lsb 26 +#define reg_intr_vect_r_masked_vect___timer___width 1 +#define reg_intr_vect_r_masked_vect___timer___bit 26 +#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 +#define reg_intr_vect_r_masked_vect___bif_arb___width 1 +#define reg_intr_vect_r_masked_vect___bif_arb___bit 27 +#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 +#define reg_intr_vect_r_masked_vect___bif_dma___width 1 +#define reg_intr_vect_r_masked_vect___bif_dma___bit 28 +#define reg_intr_vect_r_masked_vect___ext___lsb 29 +#define reg_intr_vect_r_masked_vect___ext___width 1 +#define reg_intr_vect_r_masked_vect___ext___bit 29 +#define reg_intr_vect_r_masked_vect_offset 8 + +/* Register r_nmi, scope intr_vect, type r */ +#define reg_intr_vect_r_nmi___ext___lsb 0 +#define reg_intr_vect_r_nmi___ext___width 1 +#define reg_intr_vect_r_nmi___ext___bit 0 +#define reg_intr_vect_r_nmi___watchdog___lsb 1 +#define reg_intr_vect_r_nmi___watchdog___width 1 +#define reg_intr_vect_r_nmi___watchdog___bit 1 +#define reg_intr_vect_r_nmi_offset 12 + +/* Register r_guru, scope intr_vect, type r */ +#define reg_intr_vect_r_guru___jtag___lsb 0 +#define reg_intr_vect_r_guru___jtag___width 1 +#define reg_intr_vect_r_guru___jtag___bit 0 +#define reg_intr_vect_r_guru_offset 16 + + +/* Constants */ +#define regk_intr_vect_off 0x00000000 +#define regk_intr_vect_on 0x00000001 +#define regk_intr_vect_rw_mask_default 0x00000000 +#endif /* __intr_vect_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h new file mode 100644 index 000000000..0c8084054 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h @@ -0,0 +1,69 @@ +#ifndef __irq_nmi_defs_asm_h +#define __irq_nmi_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../mod/irq_nmi.r + * id: + * last modfied: Thu Jan 22 09:22:43 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r + * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cmd, scope irq_nmi, type rw */ +#define reg_irq_nmi_rw_cmd___delay___lsb 0 +#define reg_irq_nmi_rw_cmd___delay___width 16 +#define reg_irq_nmi_rw_cmd___op___lsb 16 +#define reg_irq_nmi_rw_cmd___op___width 2 +#define reg_irq_nmi_rw_cmd_offset 0 + + +/* Constants */ +#define regk_irq_nmi_ack_irq 0x00000002 +#define regk_irq_nmi_ack_nmi 0x00000003 +#define regk_irq_nmi_irq 0x00000000 +#define regk_irq_nmi_nmi 0x00000001 +#endif /* __irq_nmi_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h new file mode 100644 index 000000000..45400eb8d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h @@ -0,0 +1,579 @@ +#ifndef __marb_defs_asm_h +#define __marb_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +#define reg_marb_rw_int_slots___owner___lsb 0 +#define reg_marb_rw_int_slots___owner___width 4 +#define reg_marb_rw_int_slots_offset 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +#define reg_marb_rw_ext_slots___owner___lsb 0 +#define reg_marb_rw_ext_slots___owner___width 4 +#define reg_marb_rw_ext_slots_offset 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +#define reg_marb_rw_regs_slots___owner___lsb 0 +#define reg_marb_rw_regs_slots___owner___width 4 +#define reg_marb_rw_regs_slots_offset 512 + +/* Register rw_intr_mask, scope marb, type rw */ +#define reg_marb_rw_intr_mask___bp0___lsb 0 +#define reg_marb_rw_intr_mask___bp0___width 1 +#define reg_marb_rw_intr_mask___bp0___bit 0 +#define reg_marb_rw_intr_mask___bp1___lsb 1 +#define reg_marb_rw_intr_mask___bp1___width 1 +#define reg_marb_rw_intr_mask___bp1___bit 1 +#define reg_marb_rw_intr_mask___bp2___lsb 2 +#define reg_marb_rw_intr_mask___bp2___width 1 +#define reg_marb_rw_intr_mask___bp2___bit 2 +#define reg_marb_rw_intr_mask___bp3___lsb 3 +#define reg_marb_rw_intr_mask___bp3___width 1 +#define reg_marb_rw_intr_mask___bp3___bit 3 +#define reg_marb_rw_intr_mask_offset 528 + +/* Register rw_ack_intr, scope marb, type rw */ +#define reg_marb_rw_ack_intr___bp0___lsb 0 +#define reg_marb_rw_ack_intr___bp0___width 1 +#define reg_marb_rw_ack_intr___bp0___bit 0 +#define reg_marb_rw_ack_intr___bp1___lsb 1 +#define reg_marb_rw_ack_intr___bp1___width 1 +#define reg_marb_rw_ack_intr___bp1___bit 1 +#define reg_marb_rw_ack_intr___bp2___lsb 2 +#define reg_marb_rw_ack_intr___bp2___width 1 +#define reg_marb_rw_ack_intr___bp2___bit 2 +#define reg_marb_rw_ack_intr___bp3___lsb 3 +#define reg_marb_rw_ack_intr___bp3___width 1 +#define reg_marb_rw_ack_intr___bp3___bit 3 +#define reg_marb_rw_ack_intr_offset 532 + +/* Register r_intr, scope marb, type r */ +#define reg_marb_r_intr___bp0___lsb 0 +#define reg_marb_r_intr___bp0___width 1 +#define reg_marb_r_intr___bp0___bit 0 +#define reg_marb_r_intr___bp1___lsb 1 +#define reg_marb_r_intr___bp1___width 1 +#define reg_marb_r_intr___bp1___bit 1 +#define reg_marb_r_intr___bp2___lsb 2 +#define reg_marb_r_intr___bp2___width 1 +#define reg_marb_r_intr___bp2___bit 2 +#define reg_marb_r_intr___bp3___lsb 3 +#define reg_marb_r_intr___bp3___width 1 +#define reg_marb_r_intr___bp3___bit 3 +#define reg_marb_r_intr_offset 536 + +/* Register r_masked_intr, scope marb, type r */ +#define reg_marb_r_masked_intr___bp0___lsb 0 +#define reg_marb_r_masked_intr___bp0___width 1 +#define reg_marb_r_masked_intr___bp0___bit 0 +#define reg_marb_r_masked_intr___bp1___lsb 1 +#define reg_marb_r_masked_intr___bp1___width 1 +#define reg_marb_r_masked_intr___bp1___bit 1 +#define reg_marb_r_masked_intr___bp2___lsb 2 +#define reg_marb_r_masked_intr___bp2___width 1 +#define reg_marb_r_masked_intr___bp2___bit 2 +#define reg_marb_r_masked_intr___bp3___lsb 3 +#define reg_marb_r_masked_intr___bp3___width 1 +#define reg_marb_r_masked_intr___bp3___bit 3 +#define reg_marb_r_masked_intr_offset 540 + +/* Register rw_stop_mask, scope marb, type rw */ +#define reg_marb_rw_stop_mask___dma0___lsb 0 +#define reg_marb_rw_stop_mask___dma0___width 1 +#define reg_marb_rw_stop_mask___dma0___bit 0 +#define reg_marb_rw_stop_mask___dma1___lsb 1 +#define reg_marb_rw_stop_mask___dma1___width 1 +#define reg_marb_rw_stop_mask___dma1___bit 1 +#define reg_marb_rw_stop_mask___dma2___lsb 2 +#define reg_marb_rw_stop_mask___dma2___width 1 +#define reg_marb_rw_stop_mask___dma2___bit 2 +#define reg_marb_rw_stop_mask___dma3___lsb 3 +#define reg_marb_rw_stop_mask___dma3___width 1 +#define reg_marb_rw_stop_mask___dma3___bit 3 +#define reg_marb_rw_stop_mask___dma4___lsb 4 +#define reg_marb_rw_stop_mask___dma4___width 1 +#define reg_marb_rw_stop_mask___dma4___bit 4 +#define reg_marb_rw_stop_mask___dma5___lsb 5 +#define reg_marb_rw_stop_mask___dma5___width 1 +#define reg_marb_rw_stop_mask___dma5___bit 5 +#define reg_marb_rw_stop_mask___dma6___lsb 6 +#define reg_marb_rw_stop_mask___dma6___width 1 +#define reg_marb_rw_stop_mask___dma6___bit 6 +#define reg_marb_rw_stop_mask___dma7___lsb 7 +#define reg_marb_rw_stop_mask___dma7___width 1 +#define reg_marb_rw_stop_mask___dma7___bit 7 +#define reg_marb_rw_stop_mask___dma8___lsb 8 +#define reg_marb_rw_stop_mask___dma8___width 1 +#define reg_marb_rw_stop_mask___dma8___bit 8 +#define reg_marb_rw_stop_mask___dma9___lsb 9 +#define reg_marb_rw_stop_mask___dma9___width 1 +#define reg_marb_rw_stop_mask___dma9___bit 9 +#define reg_marb_rw_stop_mask___cpui___lsb 10 +#define reg_marb_rw_stop_mask___cpui___width 1 +#define reg_marb_rw_stop_mask___cpui___bit 10 +#define reg_marb_rw_stop_mask___cpud___lsb 11 +#define reg_marb_rw_stop_mask___cpud___width 1 +#define reg_marb_rw_stop_mask___cpud___bit 11 +#define reg_marb_rw_stop_mask___iop___lsb 12 +#define reg_marb_rw_stop_mask___iop___width 1 +#define reg_marb_rw_stop_mask___iop___bit 12 +#define reg_marb_rw_stop_mask___slave___lsb 13 +#define reg_marb_rw_stop_mask___slave___width 1 +#define reg_marb_rw_stop_mask___slave___bit 13 +#define reg_marb_rw_stop_mask_offset 544 + +/* Register r_stopped, scope marb, type r */ +#define reg_marb_r_stopped___dma0___lsb 0 +#define reg_marb_r_stopped___dma0___width 1 +#define reg_marb_r_stopped___dma0___bit 0 +#define reg_marb_r_stopped___dma1___lsb 1 +#define reg_marb_r_stopped___dma1___width 1 +#define reg_marb_r_stopped___dma1___bit 1 +#define reg_marb_r_stopped___dma2___lsb 2 +#define reg_marb_r_stopped___dma2___width 1 +#define reg_marb_r_stopped___dma2___bit 2 +#define reg_marb_r_stopped___dma3___lsb 3 +#define reg_marb_r_stopped___dma3___width 1 +#define reg_marb_r_stopped___dma3___bit 3 +#define reg_marb_r_stopped___dma4___lsb 4 +#define reg_marb_r_stopped___dma4___width 1 +#define reg_marb_r_stopped___dma4___bit 4 +#define reg_marb_r_stopped___dma5___lsb 5 +#define reg_marb_r_stopped___dma5___width 1 +#define reg_marb_r_stopped___dma5___bit 5 +#define reg_marb_r_stopped___dma6___lsb 6 +#define reg_marb_r_stopped___dma6___width 1 +#define reg_marb_r_stopped___dma6___bit 6 +#define reg_marb_r_stopped___dma7___lsb 7 +#define reg_marb_r_stopped___dma7___width 1 +#define reg_marb_r_stopped___dma7___bit 7 +#define reg_marb_r_stopped___dma8___lsb 8 +#define reg_marb_r_stopped___dma8___width 1 +#define reg_marb_r_stopped___dma8___bit 8 +#define reg_marb_r_stopped___dma9___lsb 9 +#define reg_marb_r_stopped___dma9___width 1 +#define reg_marb_r_stopped___dma9___bit 9 +#define reg_marb_r_stopped___cpui___lsb 10 +#define reg_marb_r_stopped___cpui___width 1 +#define reg_marb_r_stopped___cpui___bit 10 +#define reg_marb_r_stopped___cpud___lsb 11 +#define reg_marb_r_stopped___cpud___width 1 +#define reg_marb_r_stopped___cpud___bit 11 +#define reg_marb_r_stopped___iop___lsb 12 +#define reg_marb_r_stopped___iop___width 1 +#define reg_marb_r_stopped___iop___bit 12 +#define reg_marb_r_stopped___slave___lsb 13 +#define reg_marb_r_stopped___slave___width 1 +#define reg_marb_r_stopped___slave___bit 13 +#define reg_marb_r_stopped_offset 548 + +/* Register rw_no_snoop, scope marb, type rw */ +#define reg_marb_rw_no_snoop___dma0___lsb 0 +#define reg_marb_rw_no_snoop___dma0___width 1 +#define reg_marb_rw_no_snoop___dma0___bit 0 +#define reg_marb_rw_no_snoop___dma1___lsb 1 +#define reg_marb_rw_no_snoop___dma1___width 1 +#define reg_marb_rw_no_snoop___dma1___bit 1 +#define reg_marb_rw_no_snoop___dma2___lsb 2 +#define reg_marb_rw_no_snoop___dma2___width 1 +#define reg_marb_rw_no_snoop___dma2___bit 2 +#define reg_marb_rw_no_snoop___dma3___lsb 3 +#define reg_marb_rw_no_snoop___dma3___width 1 +#define reg_marb_rw_no_snoop___dma3___bit 3 +#define reg_marb_rw_no_snoop___dma4___lsb 4 +#define reg_marb_rw_no_snoop___dma4___width 1 +#define reg_marb_rw_no_snoop___dma4___bit 4 +#define reg_marb_rw_no_snoop___dma5___lsb 5 +#define reg_marb_rw_no_snoop___dma5___width 1 +#define reg_marb_rw_no_snoop___dma5___bit 5 +#define reg_marb_rw_no_snoop___dma6___lsb 6 +#define reg_marb_rw_no_snoop___dma6___width 1 +#define reg_marb_rw_no_snoop___dma6___bit 6 +#define reg_marb_rw_no_snoop___dma7___lsb 7 +#define reg_marb_rw_no_snoop___dma7___width 1 +#define reg_marb_rw_no_snoop___dma7___bit 7 +#define reg_marb_rw_no_snoop___dma8___lsb 8 +#define reg_marb_rw_no_snoop___dma8___width 1 +#define reg_marb_rw_no_snoop___dma8___bit 8 +#define reg_marb_rw_no_snoop___dma9___lsb 9 +#define reg_marb_rw_no_snoop___dma9___width 1 +#define reg_marb_rw_no_snoop___dma9___bit 9 +#define reg_marb_rw_no_snoop___cpui___lsb 10 +#define reg_marb_rw_no_snoop___cpui___width 1 +#define reg_marb_rw_no_snoop___cpui___bit 10 +#define reg_marb_rw_no_snoop___cpud___lsb 11 +#define reg_marb_rw_no_snoop___cpud___width 1 +#define reg_marb_rw_no_snoop___cpud___bit 11 +#define reg_marb_rw_no_snoop___iop___lsb 12 +#define reg_marb_rw_no_snoop___iop___width 1 +#define reg_marb_rw_no_snoop___iop___bit 12 +#define reg_marb_rw_no_snoop___slave___lsb 13 +#define reg_marb_rw_no_snoop___slave___width 1 +#define reg_marb_rw_no_snoop___slave___bit 13 +#define reg_marb_rw_no_snoop_offset 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +#define reg_marb_rw_no_snoop_rq___cpui___lsb 10 +#define reg_marb_rw_no_snoop_rq___cpui___width 1 +#define reg_marb_rw_no_snoop_rq___cpui___bit 10 +#define reg_marb_rw_no_snoop_rq___cpud___lsb 11 +#define reg_marb_rw_no_snoop_rq___cpud___width 1 +#define reg_marb_rw_no_snoop_rq___cpud___bit 11 +#define reg_marb_rw_no_snoop_rq_offset 836 + + +/* Constants */ +#define regk_marb_cpud 0x0000000b +#define regk_marb_cpui 0x0000000a +#define regk_marb_dma0 0x00000000 +#define regk_marb_dma1 0x00000001 +#define regk_marb_dma2 0x00000002 +#define regk_marb_dma3 0x00000003 +#define regk_marb_dma4 0x00000004 +#define regk_marb_dma5 0x00000005 +#define regk_marb_dma6 0x00000006 +#define regk_marb_dma7 0x00000007 +#define regk_marb_dma8 0x00000008 +#define regk_marb_dma9 0x00000009 +#define regk_marb_iop 0x0000000c +#define regk_marb_no 0x00000000 +#define regk_marb_r_stopped_default 0x00000000 +#define regk_marb_rw_ext_slots_default 0x00000000 +#define regk_marb_rw_ext_slots_size 0x00000040 +#define regk_marb_rw_int_slots_default 0x00000000 +#define regk_marb_rw_int_slots_size 0x00000040 +#define regk_marb_rw_intr_mask_default 0x00000000 +#define regk_marb_rw_no_snoop_default 0x00000000 +#define regk_marb_rw_no_snoop_rq_default 0x00000000 +#define regk_marb_rw_regs_slots_default 0x00000000 +#define regk_marb_rw_regs_slots_size 0x00000004 +#define regk_marb_rw_stop_mask_default 0x00000000 +#define regk_marb_slave 0x0000000d +#define regk_marb_yes 0x00000001 +#endif /* __marb_defs_asm_h */ +#ifndef __marb_bp_defs_asm_h +#define __marb_bp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_first_addr, scope marb_bp, type rw */ +#define reg_marb_bp_rw_first_addr_offset 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +#define reg_marb_bp_rw_last_addr_offset 4 + +/* Register rw_op, scope marb_bp, type rw */ +#define reg_marb_bp_rw_op___rd___lsb 0 +#define reg_marb_bp_rw_op___rd___width 1 +#define reg_marb_bp_rw_op___rd___bit 0 +#define reg_marb_bp_rw_op___wr___lsb 1 +#define reg_marb_bp_rw_op___wr___width 1 +#define reg_marb_bp_rw_op___wr___bit 1 +#define reg_marb_bp_rw_op___rd_excl___lsb 2 +#define reg_marb_bp_rw_op___rd_excl___width 1 +#define reg_marb_bp_rw_op___rd_excl___bit 2 +#define reg_marb_bp_rw_op___pri_wr___lsb 3 +#define reg_marb_bp_rw_op___pri_wr___width 1 +#define reg_marb_bp_rw_op___pri_wr___bit 3 +#define reg_marb_bp_rw_op___us_rd___lsb 4 +#define reg_marb_bp_rw_op___us_rd___width 1 +#define reg_marb_bp_rw_op___us_rd___bit 4 +#define reg_marb_bp_rw_op___us_wr___lsb 5 +#define reg_marb_bp_rw_op___us_wr___width 1 +#define reg_marb_bp_rw_op___us_wr___bit 5 +#define reg_marb_bp_rw_op___us_rd_excl___lsb 6 +#define reg_marb_bp_rw_op___us_rd_excl___width 1 +#define reg_marb_bp_rw_op___us_rd_excl___bit 6 +#define reg_marb_bp_rw_op___us_pri_wr___lsb 7 +#define reg_marb_bp_rw_op___us_pri_wr___width 1 +#define reg_marb_bp_rw_op___us_pri_wr___bit 7 +#define reg_marb_bp_rw_op_offset 8 + +/* Register rw_clients, scope marb_bp, type rw */ +#define reg_marb_bp_rw_clients___dma0___lsb 0 +#define reg_marb_bp_rw_clients___dma0___width 1 +#define reg_marb_bp_rw_clients___dma0___bit 0 +#define reg_marb_bp_rw_clients___dma1___lsb 1 +#define reg_marb_bp_rw_clients___dma1___width 1 +#define reg_marb_bp_rw_clients___dma1___bit 1 +#define reg_marb_bp_rw_clients___dma2___lsb 2 +#define reg_marb_bp_rw_clients___dma2___width 1 +#define reg_marb_bp_rw_clients___dma2___bit 2 +#define reg_marb_bp_rw_clients___dma3___lsb 3 +#define reg_marb_bp_rw_clients___dma3___width 1 +#define reg_marb_bp_rw_clients___dma3___bit 3 +#define reg_marb_bp_rw_clients___dma4___lsb 4 +#define reg_marb_bp_rw_clients___dma4___width 1 +#define reg_marb_bp_rw_clients___dma4___bit 4 +#define reg_marb_bp_rw_clients___dma5___lsb 5 +#define reg_marb_bp_rw_clients___dma5___width 1 +#define reg_marb_bp_rw_clients___dma5___bit 5 +#define reg_marb_bp_rw_clients___dma6___lsb 6 +#define reg_marb_bp_rw_clients___dma6___width 1 +#define reg_marb_bp_rw_clients___dma6___bit 6 +#define reg_marb_bp_rw_clients___dma7___lsb 7 +#define reg_marb_bp_rw_clients___dma7___width 1 +#define reg_marb_bp_rw_clients___dma7___bit 7 +#define reg_marb_bp_rw_clients___dma8___lsb 8 +#define reg_marb_bp_rw_clients___dma8___width 1 +#define reg_marb_bp_rw_clients___dma8___bit 8 +#define reg_marb_bp_rw_clients___dma9___lsb 9 +#define reg_marb_bp_rw_clients___dma9___width 1 +#define reg_marb_bp_rw_clients___dma9___bit 9 +#define reg_marb_bp_rw_clients___cpui___lsb 10 +#define reg_marb_bp_rw_clients___cpui___width 1 +#define reg_marb_bp_rw_clients___cpui___bit 10 +#define reg_marb_bp_rw_clients___cpud___lsb 11 +#define reg_marb_bp_rw_clients___cpud___width 1 +#define reg_marb_bp_rw_clients___cpud___bit 11 +#define reg_marb_bp_rw_clients___iop___lsb 12 +#define reg_marb_bp_rw_clients___iop___width 1 +#define reg_marb_bp_rw_clients___iop___bit 12 +#define reg_marb_bp_rw_clients___slave___lsb 13 +#define reg_marb_bp_rw_clients___slave___width 1 +#define reg_marb_bp_rw_clients___slave___bit 13 +#define reg_marb_bp_rw_clients_offset 12 + +/* Register rw_options, scope marb_bp, type rw */ +#define reg_marb_bp_rw_options___wrap___lsb 0 +#define reg_marb_bp_rw_options___wrap___width 1 +#define reg_marb_bp_rw_options___wrap___bit 0 +#define reg_marb_bp_rw_options_offset 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_addr_offset 20 + +/* Register r_brk_op, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_op___rd___lsb 0 +#define reg_marb_bp_r_brk_op___rd___width 1 +#define reg_marb_bp_r_brk_op___rd___bit 0 +#define reg_marb_bp_r_brk_op___wr___lsb 1 +#define reg_marb_bp_r_brk_op___wr___width 1 +#define reg_marb_bp_r_brk_op___wr___bit 1 +#define reg_marb_bp_r_brk_op___rd_excl___lsb 2 +#define reg_marb_bp_r_brk_op___rd_excl___width 1 +#define reg_marb_bp_r_brk_op___rd_excl___bit 2 +#define reg_marb_bp_r_brk_op___pri_wr___lsb 3 +#define reg_marb_bp_r_brk_op___pri_wr___width 1 +#define reg_marb_bp_r_brk_op___pri_wr___bit 3 +#define reg_marb_bp_r_brk_op___us_rd___lsb 4 +#define reg_marb_bp_r_brk_op___us_rd___width 1 +#define reg_marb_bp_r_brk_op___us_rd___bit 4 +#define reg_marb_bp_r_brk_op___us_wr___lsb 5 +#define reg_marb_bp_r_brk_op___us_wr___width 1 +#define reg_marb_bp_r_brk_op___us_wr___bit 5 +#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6 +#define reg_marb_bp_r_brk_op___us_rd_excl___width 1 +#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6 +#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7 +#define reg_marb_bp_r_brk_op___us_pri_wr___width 1 +#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7 +#define reg_marb_bp_r_brk_op_offset 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_clients___dma0___lsb 0 +#define reg_marb_bp_r_brk_clients___dma0___width 1 +#define reg_marb_bp_r_brk_clients___dma0___bit 0 +#define reg_marb_bp_r_brk_clients___dma1___lsb 1 +#define reg_marb_bp_r_brk_clients___dma1___width 1 +#define reg_marb_bp_r_brk_clients___dma1___bit 1 +#define reg_marb_bp_r_brk_clients___dma2___lsb 2 +#define reg_marb_bp_r_brk_clients___dma2___width 1 +#define reg_marb_bp_r_brk_clients___dma2___bit 2 +#define reg_marb_bp_r_brk_clients___dma3___lsb 3 +#define reg_marb_bp_r_brk_clients___dma3___width 1 +#define reg_marb_bp_r_brk_clients___dma3___bit 3 +#define reg_marb_bp_r_brk_clients___dma4___lsb 4 +#define reg_marb_bp_r_brk_clients___dma4___width 1 +#define reg_marb_bp_r_brk_clients___dma4___bit 4 +#define reg_marb_bp_r_brk_clients___dma5___lsb 5 +#define reg_marb_bp_r_brk_clients___dma5___width 1 +#define reg_marb_bp_r_brk_clients___dma5___bit 5 +#define reg_marb_bp_r_brk_clients___dma6___lsb 6 +#define reg_marb_bp_r_brk_clients___dma6___width 1 +#define reg_marb_bp_r_brk_clients___dma6___bit 6 +#define reg_marb_bp_r_brk_clients___dma7___lsb 7 +#define reg_marb_bp_r_brk_clients___dma7___width 1 +#define reg_marb_bp_r_brk_clients___dma7___bit 7 +#define reg_marb_bp_r_brk_clients___dma8___lsb 8 +#define reg_marb_bp_r_brk_clients___dma8___width 1 +#define reg_marb_bp_r_brk_clients___dma8___bit 8 +#define reg_marb_bp_r_brk_clients___dma9___lsb 9 +#define reg_marb_bp_r_brk_clients___dma9___width 1 +#define reg_marb_bp_r_brk_clients___dma9___bit 9 +#define reg_marb_bp_r_brk_clients___cpui___lsb 10 +#define reg_marb_bp_r_brk_clients___cpui___width 1 +#define reg_marb_bp_r_brk_clients___cpui___bit 10 +#define reg_marb_bp_r_brk_clients___cpud___lsb 11 +#define reg_marb_bp_r_brk_clients___cpud___width 1 +#define reg_marb_bp_r_brk_clients___cpud___bit 11 +#define reg_marb_bp_r_brk_clients___iop___lsb 12 +#define reg_marb_bp_r_brk_clients___iop___width 1 +#define reg_marb_bp_r_brk_clients___iop___bit 12 +#define reg_marb_bp_r_brk_clients___slave___lsb 13 +#define reg_marb_bp_r_brk_clients___slave___width 1 +#define reg_marb_bp_r_brk_clients___slave___bit 13 +#define reg_marb_bp_r_brk_clients_offset 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_first_client___dma0___lsb 0 +#define reg_marb_bp_r_brk_first_client___dma0___width 1 +#define reg_marb_bp_r_brk_first_client___dma0___bit 0 +#define reg_marb_bp_r_brk_first_client___dma1___lsb 1 +#define reg_marb_bp_r_brk_first_client___dma1___width 1 +#define reg_marb_bp_r_brk_first_client___dma1___bit 1 +#define reg_marb_bp_r_brk_first_client___dma2___lsb 2 +#define reg_marb_bp_r_brk_first_client___dma2___width 1 +#define reg_marb_bp_r_brk_first_client___dma2___bit 2 +#define reg_marb_bp_r_brk_first_client___dma3___lsb 3 +#define reg_marb_bp_r_brk_first_client___dma3___width 1 +#define reg_marb_bp_r_brk_first_client___dma3___bit 3 +#define reg_marb_bp_r_brk_first_client___dma4___lsb 4 +#define reg_marb_bp_r_brk_first_client___dma4___width 1 +#define reg_marb_bp_r_brk_first_client___dma4___bit 4 +#define reg_marb_bp_r_brk_first_client___dma5___lsb 5 +#define reg_marb_bp_r_brk_first_client___dma5___width 1 +#define reg_marb_bp_r_brk_first_client___dma5___bit 5 +#define reg_marb_bp_r_brk_first_client___dma6___lsb 6 +#define reg_marb_bp_r_brk_first_client___dma6___width 1 +#define reg_marb_bp_r_brk_first_client___dma6___bit 6 +#define reg_marb_bp_r_brk_first_client___dma7___lsb 7 +#define reg_marb_bp_r_brk_first_client___dma7___width 1 +#define reg_marb_bp_r_brk_first_client___dma7___bit 7 +#define reg_marb_bp_r_brk_first_client___dma8___lsb 8 +#define reg_marb_bp_r_brk_first_client___dma8___width 1 +#define reg_marb_bp_r_brk_first_client___dma8___bit 8 +#define reg_marb_bp_r_brk_first_client___dma9___lsb 9 +#define reg_marb_bp_r_brk_first_client___dma9___width 1 +#define reg_marb_bp_r_brk_first_client___dma9___bit 9 +#define reg_marb_bp_r_brk_first_client___cpui___lsb 10 +#define reg_marb_bp_r_brk_first_client___cpui___width 1 +#define reg_marb_bp_r_brk_first_client___cpui___bit 10 +#define reg_marb_bp_r_brk_first_client___cpud___lsb 11 +#define reg_marb_bp_r_brk_first_client___cpud___width 1 +#define reg_marb_bp_r_brk_first_client___cpud___bit 11 +#define reg_marb_bp_r_brk_first_client___iop___lsb 12 +#define reg_marb_bp_r_brk_first_client___iop___width 1 +#define reg_marb_bp_r_brk_first_client___iop___bit 12 +#define reg_marb_bp_r_brk_first_client___slave___lsb 13 +#define reg_marb_bp_r_brk_first_client___slave___width 1 +#define reg_marb_bp_r_brk_first_client___slave___bit 13 +#define reg_marb_bp_r_brk_first_client_offset 32 + +/* Register r_brk_size, scope marb_bp, type r */ +#define reg_marb_bp_r_brk_size_offset 36 + +/* Register rw_ack, scope marb_bp, type rw */ +#define reg_marb_bp_rw_ack_offset 40 + + +/* Constants */ +#define regk_marb_bp_no 0x00000000 +#define regk_marb_bp_rw_op_default 0x00000000 +#define regk_marb_bp_rw_options_default 0x00000000 +#define regk_marb_bp_yes 0x00000001 +#endif /* __marb_bp_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h new file mode 100644 index 000000000..505b7a16d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h @@ -0,0 +1,212 @@ +#ifndef __mmu_defs_asm_h +#define __mmu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/mmu/doc/mmu_regs.r + * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp + * last modfied: Mon Apr 11 17:03:20 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r + * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mm_cfg, scope mmu, type rw */ +#define reg_mmu_rw_mm_cfg___seg_0___lsb 0 +#define reg_mmu_rw_mm_cfg___seg_0___width 1 +#define reg_mmu_rw_mm_cfg___seg_0___bit 0 +#define reg_mmu_rw_mm_cfg___seg_1___lsb 1 +#define reg_mmu_rw_mm_cfg___seg_1___width 1 +#define reg_mmu_rw_mm_cfg___seg_1___bit 1 +#define reg_mmu_rw_mm_cfg___seg_2___lsb 2 +#define reg_mmu_rw_mm_cfg___seg_2___width 1 +#define reg_mmu_rw_mm_cfg___seg_2___bit 2 +#define reg_mmu_rw_mm_cfg___seg_3___lsb 3 +#define reg_mmu_rw_mm_cfg___seg_3___width 1 +#define reg_mmu_rw_mm_cfg___seg_3___bit 3 +#define reg_mmu_rw_mm_cfg___seg_4___lsb 4 +#define reg_mmu_rw_mm_cfg___seg_4___width 1 +#define reg_mmu_rw_mm_cfg___seg_4___bit 4 +#define reg_mmu_rw_mm_cfg___seg_5___lsb 5 +#define reg_mmu_rw_mm_cfg___seg_5___width 1 +#define reg_mmu_rw_mm_cfg___seg_5___bit 5 +#define reg_mmu_rw_mm_cfg___seg_6___lsb 6 +#define reg_mmu_rw_mm_cfg___seg_6___width 1 +#define reg_mmu_rw_mm_cfg___seg_6___bit 6 +#define reg_mmu_rw_mm_cfg___seg_7___lsb 7 +#define reg_mmu_rw_mm_cfg___seg_7___width 1 +#define reg_mmu_rw_mm_cfg___seg_7___bit 7 +#define reg_mmu_rw_mm_cfg___seg_8___lsb 8 +#define reg_mmu_rw_mm_cfg___seg_8___width 1 +#define reg_mmu_rw_mm_cfg___seg_8___bit 8 +#define reg_mmu_rw_mm_cfg___seg_9___lsb 9 +#define reg_mmu_rw_mm_cfg___seg_9___width 1 +#define reg_mmu_rw_mm_cfg___seg_9___bit 9 +#define reg_mmu_rw_mm_cfg___seg_a___lsb 10 +#define reg_mmu_rw_mm_cfg___seg_a___width 1 +#define reg_mmu_rw_mm_cfg___seg_a___bit 10 +#define reg_mmu_rw_mm_cfg___seg_b___lsb 11 +#define reg_mmu_rw_mm_cfg___seg_b___width 1 +#define reg_mmu_rw_mm_cfg___seg_b___bit 11 +#define reg_mmu_rw_mm_cfg___seg_c___lsb 12 +#define reg_mmu_rw_mm_cfg___seg_c___width 1 +#define reg_mmu_rw_mm_cfg___seg_c___bit 12 +#define reg_mmu_rw_mm_cfg___seg_d___lsb 13 +#define reg_mmu_rw_mm_cfg___seg_d___width 1 +#define reg_mmu_rw_mm_cfg___seg_d___bit 13 +#define reg_mmu_rw_mm_cfg___seg_e___lsb 14 +#define reg_mmu_rw_mm_cfg___seg_e___width 1 +#define reg_mmu_rw_mm_cfg___seg_e___bit 14 +#define reg_mmu_rw_mm_cfg___seg_f___lsb 15 +#define reg_mmu_rw_mm_cfg___seg_f___width 1 +#define reg_mmu_rw_mm_cfg___seg_f___bit 15 +#define reg_mmu_rw_mm_cfg___inv___lsb 16 +#define reg_mmu_rw_mm_cfg___inv___width 1 +#define reg_mmu_rw_mm_cfg___inv___bit 16 +#define reg_mmu_rw_mm_cfg___ex___lsb 17 +#define reg_mmu_rw_mm_cfg___ex___width 1 +#define reg_mmu_rw_mm_cfg___ex___bit 17 +#define reg_mmu_rw_mm_cfg___acc___lsb 18 +#define reg_mmu_rw_mm_cfg___acc___width 1 +#define reg_mmu_rw_mm_cfg___acc___bit 18 +#define reg_mmu_rw_mm_cfg___we___lsb 19 +#define reg_mmu_rw_mm_cfg___we___width 1 +#define reg_mmu_rw_mm_cfg___we___bit 19 +#define reg_mmu_rw_mm_cfg_offset 0 + +/* Register rw_mm_kbase_lo, scope mmu, type rw */ +#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 +#define reg_mmu_rw_mm_kbase_lo___base_0___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 +#define reg_mmu_rw_mm_kbase_lo___base_1___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 +#define reg_mmu_rw_mm_kbase_lo___base_2___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 +#define reg_mmu_rw_mm_kbase_lo___base_3___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 +#define reg_mmu_rw_mm_kbase_lo___base_4___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 +#define reg_mmu_rw_mm_kbase_lo___base_5___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 +#define reg_mmu_rw_mm_kbase_lo___base_6___width 4 +#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 +#define reg_mmu_rw_mm_kbase_lo___base_7___width 4 +#define reg_mmu_rw_mm_kbase_lo_offset 4 + +/* Register rw_mm_kbase_hi, scope mmu, type rw */ +#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 +#define reg_mmu_rw_mm_kbase_hi___base_8___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 +#define reg_mmu_rw_mm_kbase_hi___base_9___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 +#define reg_mmu_rw_mm_kbase_hi___base_a___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 +#define reg_mmu_rw_mm_kbase_hi___base_b___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 +#define reg_mmu_rw_mm_kbase_hi___base_c___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 +#define reg_mmu_rw_mm_kbase_hi___base_d___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 +#define reg_mmu_rw_mm_kbase_hi___base_e___width 4 +#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 +#define reg_mmu_rw_mm_kbase_hi___base_f___width 4 +#define reg_mmu_rw_mm_kbase_hi_offset 8 + +/* Register r_mm_cause, scope mmu, type r */ +#define reg_mmu_r_mm_cause___pid___lsb 0 +#define reg_mmu_r_mm_cause___pid___width 8 +#define reg_mmu_r_mm_cause___op___lsb 8 +#define reg_mmu_r_mm_cause___op___width 2 +#define reg_mmu_r_mm_cause___vpn___lsb 13 +#define reg_mmu_r_mm_cause___vpn___width 19 +#define reg_mmu_r_mm_cause_offset 12 + +/* Register rw_mm_tlb_sel, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 +#define reg_mmu_rw_mm_tlb_sel___idx___width 4 +#define reg_mmu_rw_mm_tlb_sel___set___lsb 4 +#define reg_mmu_rw_mm_tlb_sel___set___width 2 +#define reg_mmu_rw_mm_tlb_sel_offset 16 + +/* Register rw_mm_tlb_lo, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_lo___x___lsb 0 +#define reg_mmu_rw_mm_tlb_lo___x___width 1 +#define reg_mmu_rw_mm_tlb_lo___x___bit 0 +#define reg_mmu_rw_mm_tlb_lo___w___lsb 1 +#define reg_mmu_rw_mm_tlb_lo___w___width 1 +#define reg_mmu_rw_mm_tlb_lo___w___bit 1 +#define reg_mmu_rw_mm_tlb_lo___k___lsb 2 +#define reg_mmu_rw_mm_tlb_lo___k___width 1 +#define reg_mmu_rw_mm_tlb_lo___k___bit 2 +#define reg_mmu_rw_mm_tlb_lo___v___lsb 3 +#define reg_mmu_rw_mm_tlb_lo___v___width 1 +#define reg_mmu_rw_mm_tlb_lo___v___bit 3 +#define reg_mmu_rw_mm_tlb_lo___g___lsb 4 +#define reg_mmu_rw_mm_tlb_lo___g___width 1 +#define reg_mmu_rw_mm_tlb_lo___g___bit 4 +#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 +#define reg_mmu_rw_mm_tlb_lo___pfn___width 19 +#define reg_mmu_rw_mm_tlb_lo_offset 20 + +/* Register rw_mm_tlb_hi, scope mmu, type rw */ +#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 +#define reg_mmu_rw_mm_tlb_hi___pid___width 8 +#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 +#define reg_mmu_rw_mm_tlb_hi___vpn___width 19 +#define reg_mmu_rw_mm_tlb_hi_offset 24 + + +/* Constants */ +#define regk_mmu_execute 0x00000000 +#define regk_mmu_flush 0x00000003 +#define regk_mmu_linear 0x00000001 +#define regk_mmu_no 0x00000000 +#define regk_mmu_off 0x00000000 +#define regk_mmu_on 0x00000001 +#define regk_mmu_page 0x00000000 +#define regk_mmu_read 0x00000001 +#define regk_mmu_write 0x00000002 +#define regk_mmu_yes 0x00000001 +#endif /* __mmu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h new file mode 100644 index 000000000..339500bf3 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h @@ -0,0 +1,7 @@ +#define RW_MM_CFG 0 +#define RW_MM_KBASE_LO 1 +#define RW_MM_KBASE_HI 2 +#define R_MM_CAUSE 3 +#define RW_MM_TLB_SEL 4 +#define RW_MM_TLB_LO 5 +#define RW_MM_TLB_HI 6 diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h new file mode 100644 index 000000000..10246f49f --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h @@ -0,0 +1,142 @@ +#ifndef __rt_trace_defs_asm_h +#define __rt_trace_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/rt_trace/rtl/rt_regs.r + * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp + * last modfied: Mon Apr 11 16:09:14 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r + * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope rt_trace, type rw */ +#define reg_rt_trace_rw_cfg___en___lsb 0 +#define reg_rt_trace_rw_cfg___en___width 1 +#define reg_rt_trace_rw_cfg___en___bit 0 +#define reg_rt_trace_rw_cfg___mode___lsb 1 +#define reg_rt_trace_rw_cfg___mode___width 1 +#define reg_rt_trace_rw_cfg___mode___bit 1 +#define reg_rt_trace_rw_cfg___owner___lsb 2 +#define reg_rt_trace_rw_cfg___owner___width 1 +#define reg_rt_trace_rw_cfg___owner___bit 2 +#define reg_rt_trace_rw_cfg___wp___lsb 3 +#define reg_rt_trace_rw_cfg___wp___width 1 +#define reg_rt_trace_rw_cfg___wp___bit 3 +#define reg_rt_trace_rw_cfg___stall___lsb 4 +#define reg_rt_trace_rw_cfg___stall___width 1 +#define reg_rt_trace_rw_cfg___stall___bit 4 +#define reg_rt_trace_rw_cfg___wp_start___lsb 8 +#define reg_rt_trace_rw_cfg___wp_start___width 7 +#define reg_rt_trace_rw_cfg___wp_stop___lsb 16 +#define reg_rt_trace_rw_cfg___wp_stop___width 7 +#define reg_rt_trace_rw_cfg_offset 0 + +/* Register rw_tap_ctrl, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0 +#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1 +#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1 +#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1 +#define reg_rt_trace_rw_tap_ctrl_offset 4 + +/* Register r_tap_stat, scope rt_trace, type r */ +#define reg_rt_trace_r_tap_stat___dav___lsb 0 +#define reg_rt_trace_r_tap_stat___dav___width 1 +#define reg_rt_trace_r_tap_stat___dav___bit 0 +#define reg_rt_trace_r_tap_stat___empty___lsb 1 +#define reg_rt_trace_r_tap_stat___empty___width 1 +#define reg_rt_trace_r_tap_stat___empty___bit 1 +#define reg_rt_trace_r_tap_stat_offset 8 + +/* Register rw_tap_data, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_data_offset 12 + +/* Register rw_tap_hdata, scope rt_trace, type rw */ +#define reg_rt_trace_rw_tap_hdata___op___lsb 0 +#define reg_rt_trace_rw_tap_hdata___op___width 4 +#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4 +#define reg_rt_trace_rw_tap_hdata___sub_op___width 4 +#define reg_rt_trace_rw_tap_hdata_offset 16 + +/* Register r_redir, scope rt_trace, type r */ +#define reg_rt_trace_r_redir_offset 20 + + +/* Constants */ +#define regk_rt_trace_brk 0x0000000c +#define regk_rt_trace_dbg 0x00000003 +#define regk_rt_trace_dbgdi 0x00000004 +#define regk_rt_trace_dbgdo 0x00000005 +#define regk_rt_trace_gmode 0x00000000 +#define regk_rt_trace_no 0x00000000 +#define regk_rt_trace_nop 0x00000000 +#define regk_rt_trace_normal 0x00000000 +#define regk_rt_trace_rdmem 0x00000007 +#define regk_rt_trace_rdmemb 0x00000009 +#define regk_rt_trace_rdpreg 0x00000002 +#define regk_rt_trace_rdreg 0x00000001 +#define regk_rt_trace_rdsreg 0x00000003 +#define regk_rt_trace_redir 0x00000006 +#define regk_rt_trace_ret 0x0000000b +#define regk_rt_trace_rw_cfg_default 0x00000000 +#define regk_rt_trace_trcfg 0x00000001 +#define regk_rt_trace_wp 0x00000001 +#define regk_rt_trace_wp0 0x00000001 +#define regk_rt_trace_wp1 0x00000002 +#define regk_rt_trace_wp2 0x00000004 +#define regk_rt_trace_wp3 0x00000008 +#define regk_rt_trace_wp4 0x00000010 +#define regk_rt_trace_wp5 0x00000020 +#define regk_rt_trace_wp6 0x00000040 +#define regk_rt_trace_wrmem 0x00000008 +#define regk_rt_trace_wrmemb 0x0000000a +#define regk_rt_trace_wrpreg 0x00000005 +#define regk_rt_trace_wrreg 0x00000004 +#define regk_rt_trace_wrsreg 0x00000006 +#define regk_rt_trace_yes 0x00000001 +#endif /* __rt_trace_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h new file mode 100644 index 000000000..4a2808bdf --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h @@ -0,0 +1,359 @@ +#ifndef __ser_defs_asm_h +#define __ser_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/ser/rtl/ser_regs.r + * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp + * last modfied: Mon Apr 11 16:09:21 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r + * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tr_ctrl, scope ser, type rw */ +#define reg_ser_rw_tr_ctrl___base_freq___lsb 0 +#define reg_ser_rw_tr_ctrl___base_freq___width 3 +#define reg_ser_rw_tr_ctrl___en___lsb 3 +#define reg_ser_rw_tr_ctrl___en___width 1 +#define reg_ser_rw_tr_ctrl___en___bit 3 +#define reg_ser_rw_tr_ctrl___par___lsb 4 +#define reg_ser_rw_tr_ctrl___par___width 2 +#define reg_ser_rw_tr_ctrl___par_en___lsb 6 +#define reg_ser_rw_tr_ctrl___par_en___width 1 +#define reg_ser_rw_tr_ctrl___par_en___bit 6 +#define reg_ser_rw_tr_ctrl___data_bits___lsb 7 +#define reg_ser_rw_tr_ctrl___data_bits___width 1 +#define reg_ser_rw_tr_ctrl___data_bits___bit 7 +#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 +#define reg_ser_rw_tr_ctrl___stop_bits___width 1 +#define reg_ser_rw_tr_ctrl___stop_bits___bit 8 +#define reg_ser_rw_tr_ctrl___stop___lsb 9 +#define reg_ser_rw_tr_ctrl___stop___width 1 +#define reg_ser_rw_tr_ctrl___stop___bit 9 +#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 +#define reg_ser_rw_tr_ctrl___rts_delay___width 3 +#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 +#define reg_ser_rw_tr_ctrl___rts_setup___width 1 +#define reg_ser_rw_tr_ctrl___rts_setup___bit 13 +#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 +#define reg_ser_rw_tr_ctrl___auto_rts___width 1 +#define reg_ser_rw_tr_ctrl___auto_rts___bit 14 +#define reg_ser_rw_tr_ctrl___txd___lsb 15 +#define reg_ser_rw_tr_ctrl___txd___width 1 +#define reg_ser_rw_tr_ctrl___txd___bit 15 +#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 +#define reg_ser_rw_tr_ctrl___auto_cts___width 1 +#define reg_ser_rw_tr_ctrl___auto_cts___bit 16 +#define reg_ser_rw_tr_ctrl_offset 0 + +/* Register rw_tr_dma_en, scope ser, type rw */ +#define reg_ser_rw_tr_dma_en___en___lsb 0 +#define reg_ser_rw_tr_dma_en___en___width 1 +#define reg_ser_rw_tr_dma_en___en___bit 0 +#define reg_ser_rw_tr_dma_en_offset 4 + +/* Register rw_rec_ctrl, scope ser, type rw */ +#define reg_ser_rw_rec_ctrl___base_freq___lsb 0 +#define reg_ser_rw_rec_ctrl___base_freq___width 3 +#define reg_ser_rw_rec_ctrl___en___lsb 3 +#define reg_ser_rw_rec_ctrl___en___width 1 +#define reg_ser_rw_rec_ctrl___en___bit 3 +#define reg_ser_rw_rec_ctrl___par___lsb 4 +#define reg_ser_rw_rec_ctrl___par___width 2 +#define reg_ser_rw_rec_ctrl___par_en___lsb 6 +#define reg_ser_rw_rec_ctrl___par_en___width 1 +#define reg_ser_rw_rec_ctrl___par_en___bit 6 +#define reg_ser_rw_rec_ctrl___data_bits___lsb 7 +#define reg_ser_rw_rec_ctrl___data_bits___width 1 +#define reg_ser_rw_rec_ctrl___data_bits___bit 7 +#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 +#define reg_ser_rw_rec_ctrl___dma_mode___width 1 +#define reg_ser_rw_rec_ctrl___dma_mode___bit 8 +#define reg_ser_rw_rec_ctrl___dma_err___lsb 9 +#define reg_ser_rw_rec_ctrl___dma_err___width 1 +#define reg_ser_rw_rec_ctrl___dma_err___bit 9 +#define reg_ser_rw_rec_ctrl___sampling___lsb 10 +#define reg_ser_rw_rec_ctrl___sampling___width 1 +#define reg_ser_rw_rec_ctrl___sampling___bit 10 +#define reg_ser_rw_rec_ctrl___timeout___lsb 11 +#define reg_ser_rw_rec_ctrl___timeout___width 3 +#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 +#define reg_ser_rw_rec_ctrl___auto_eop___width 1 +#define reg_ser_rw_rec_ctrl___auto_eop___bit 14 +#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 +#define reg_ser_rw_rec_ctrl___half_duplex___width 1 +#define reg_ser_rw_rec_ctrl___half_duplex___bit 15 +#define reg_ser_rw_rec_ctrl___rts_n___lsb 16 +#define reg_ser_rw_rec_ctrl___rts_n___width 1 +#define reg_ser_rw_rec_ctrl___rts_n___bit 16 +#define reg_ser_rw_rec_ctrl___loopback___lsb 17 +#define reg_ser_rw_rec_ctrl___loopback___width 1 +#define reg_ser_rw_rec_ctrl___loopback___bit 17 +#define reg_ser_rw_rec_ctrl_offset 8 + +/* Register rw_tr_baud_div, scope ser, type rw */ +#define reg_ser_rw_tr_baud_div___div___lsb 0 +#define reg_ser_rw_tr_baud_div___div___width 16 +#define reg_ser_rw_tr_baud_div_offset 12 + +/* Register rw_rec_baud_div, scope ser, type rw */ +#define reg_ser_rw_rec_baud_div___div___lsb 0 +#define reg_ser_rw_rec_baud_div___div___width 16 +#define reg_ser_rw_rec_baud_div_offset 16 + +/* Register rw_xoff, scope ser, type rw */ +#define reg_ser_rw_xoff___chr___lsb 0 +#define reg_ser_rw_xoff___chr___width 8 +#define reg_ser_rw_xoff___automatic___lsb 8 +#define reg_ser_rw_xoff___automatic___width 1 +#define reg_ser_rw_xoff___automatic___bit 8 +#define reg_ser_rw_xoff_offset 20 + +/* Register rw_xoff_clr, scope ser, type rw */ +#define reg_ser_rw_xoff_clr___clr___lsb 0 +#define reg_ser_rw_xoff_clr___clr___width 1 +#define reg_ser_rw_xoff_clr___clr___bit 0 +#define reg_ser_rw_xoff_clr_offset 24 + +/* Register rw_dout, scope ser, type rw */ +#define reg_ser_rw_dout___data___lsb 0 +#define reg_ser_rw_dout___data___width 8 +#define reg_ser_rw_dout_offset 28 + +/* Register rs_stat_din, scope ser, type rs */ +#define reg_ser_rs_stat_din___data___lsb 0 +#define reg_ser_rs_stat_din___data___width 8 +#define reg_ser_rs_stat_din___dav___lsb 16 +#define reg_ser_rs_stat_din___dav___width 1 +#define reg_ser_rs_stat_din___dav___bit 16 +#define reg_ser_rs_stat_din___framing_err___lsb 17 +#define reg_ser_rs_stat_din___framing_err___width 1 +#define reg_ser_rs_stat_din___framing_err___bit 17 +#define reg_ser_rs_stat_din___par_err___lsb 18 +#define reg_ser_rs_stat_din___par_err___width 1 +#define reg_ser_rs_stat_din___par_err___bit 18 +#define reg_ser_rs_stat_din___orun___lsb 19 +#define reg_ser_rs_stat_din___orun___width 1 +#define reg_ser_rs_stat_din___orun___bit 19 +#define reg_ser_rs_stat_din___rec_err___lsb 20 +#define reg_ser_rs_stat_din___rec_err___width 1 +#define reg_ser_rs_stat_din___rec_err___bit 20 +#define reg_ser_rs_stat_din___rxd___lsb 21 +#define reg_ser_rs_stat_din___rxd___width 1 +#define reg_ser_rs_stat_din___rxd___bit 21 +#define reg_ser_rs_stat_din___tr_idle___lsb 22 +#define reg_ser_rs_stat_din___tr_idle___width 1 +#define reg_ser_rs_stat_din___tr_idle___bit 22 +#define reg_ser_rs_stat_din___tr_empty___lsb 23 +#define reg_ser_rs_stat_din___tr_empty___width 1 +#define reg_ser_rs_stat_din___tr_empty___bit 23 +#define reg_ser_rs_stat_din___tr_rdy___lsb 24 +#define reg_ser_rs_stat_din___tr_rdy___width 1 +#define reg_ser_rs_stat_din___tr_rdy___bit 24 +#define reg_ser_rs_stat_din___cts_n___lsb 25 +#define reg_ser_rs_stat_din___cts_n___width 1 +#define reg_ser_rs_stat_din___cts_n___bit 25 +#define reg_ser_rs_stat_din___xoff_detect___lsb 26 +#define reg_ser_rs_stat_din___xoff_detect___width 1 +#define reg_ser_rs_stat_din___xoff_detect___bit 26 +#define reg_ser_rs_stat_din___rts_n___lsb 27 +#define reg_ser_rs_stat_din___rts_n___width 1 +#define reg_ser_rs_stat_din___rts_n___bit 27 +#define reg_ser_rs_stat_din___txd___lsb 28 +#define reg_ser_rs_stat_din___txd___width 1 +#define reg_ser_rs_stat_din___txd___bit 28 +#define reg_ser_rs_stat_din_offset 32 + +/* Register r_stat_din, scope ser, type r */ +#define reg_ser_r_stat_din___data___lsb 0 +#define reg_ser_r_stat_din___data___width 8 +#define reg_ser_r_stat_din___dav___lsb 16 +#define reg_ser_r_stat_din___dav___width 1 +#define reg_ser_r_stat_din___dav___bit 16 +#define reg_ser_r_stat_din___framing_err___lsb 17 +#define reg_ser_r_stat_din___framing_err___width 1 +#define reg_ser_r_stat_din___framing_err___bit 17 +#define reg_ser_r_stat_din___par_err___lsb 18 +#define reg_ser_r_stat_din___par_err___width 1 +#define reg_ser_r_stat_din___par_err___bit 18 +#define reg_ser_r_stat_din___orun___lsb 19 +#define reg_ser_r_stat_din___orun___width 1 +#define reg_ser_r_stat_din___orun___bit 19 +#define reg_ser_r_stat_din___rec_err___lsb 20 +#define reg_ser_r_stat_din___rec_err___width 1 +#define reg_ser_r_stat_din___rec_err___bit 20 +#define reg_ser_r_stat_din___rxd___lsb 21 +#define reg_ser_r_stat_din___rxd___width 1 +#define reg_ser_r_stat_din___rxd___bit 21 +#define reg_ser_r_stat_din___tr_idle___lsb 22 +#define reg_ser_r_stat_din___tr_idle___width 1 +#define reg_ser_r_stat_din___tr_idle___bit 22 +#define reg_ser_r_stat_din___tr_empty___lsb 23 +#define reg_ser_r_stat_din___tr_empty___width 1 +#define reg_ser_r_stat_din___tr_empty___bit 23 +#define reg_ser_r_stat_din___tr_rdy___lsb 24 +#define reg_ser_r_stat_din___tr_rdy___width 1 +#define reg_ser_r_stat_din___tr_rdy___bit 24 +#define reg_ser_r_stat_din___cts_n___lsb 25 +#define reg_ser_r_stat_din___cts_n___width 1 +#define reg_ser_r_stat_din___cts_n___bit 25 +#define reg_ser_r_stat_din___xoff_detect___lsb 26 +#define reg_ser_r_stat_din___xoff_detect___width 1 +#define reg_ser_r_stat_din___xoff_detect___bit 26 +#define reg_ser_r_stat_din___rts_n___lsb 27 +#define reg_ser_r_stat_din___rts_n___width 1 +#define reg_ser_r_stat_din___rts_n___bit 27 +#define reg_ser_r_stat_din___txd___lsb 28 +#define reg_ser_r_stat_din___txd___width 1 +#define reg_ser_r_stat_din___txd___bit 28 +#define reg_ser_r_stat_din_offset 36 + +/* Register rw_rec_eop, scope ser, type rw */ +#define reg_ser_rw_rec_eop___set___lsb 0 +#define reg_ser_rw_rec_eop___set___width 1 +#define reg_ser_rw_rec_eop___set___bit 0 +#define reg_ser_rw_rec_eop_offset 40 + +/* Register rw_intr_mask, scope ser, type rw */ +#define reg_ser_rw_intr_mask___tr_rdy___lsb 0 +#define reg_ser_rw_intr_mask___tr_rdy___width 1 +#define reg_ser_rw_intr_mask___tr_rdy___bit 0 +#define reg_ser_rw_intr_mask___tr_empty___lsb 1 +#define reg_ser_rw_intr_mask___tr_empty___width 1 +#define reg_ser_rw_intr_mask___tr_empty___bit 1 +#define reg_ser_rw_intr_mask___tr_idle___lsb 2 +#define reg_ser_rw_intr_mask___tr_idle___width 1 +#define reg_ser_rw_intr_mask___tr_idle___bit 2 +#define reg_ser_rw_intr_mask___dav___lsb 3 +#define reg_ser_rw_intr_mask___dav___width 1 +#define reg_ser_rw_intr_mask___dav___bit 3 +#define reg_ser_rw_intr_mask_offset 44 + +/* Register rw_ack_intr, scope ser, type rw */ +#define reg_ser_rw_ack_intr___tr_rdy___lsb 0 +#define reg_ser_rw_ack_intr___tr_rdy___width 1 +#define reg_ser_rw_ack_intr___tr_rdy___bit 0 +#define reg_ser_rw_ack_intr___tr_empty___lsb 1 +#define reg_ser_rw_ack_intr___tr_empty___width 1 +#define reg_ser_rw_ack_intr___tr_empty___bit 1 +#define reg_ser_rw_ack_intr___tr_idle___lsb 2 +#define reg_ser_rw_ack_intr___tr_idle___width 1 +#define reg_ser_rw_ack_intr___tr_idle___bit 2 +#define reg_ser_rw_ack_intr___dav___lsb 3 +#define reg_ser_rw_ack_intr___dav___width 1 +#define reg_ser_rw_ack_intr___dav___bit 3 +#define reg_ser_rw_ack_intr_offset 48 + +/* Register r_intr, scope ser, type r */ +#define reg_ser_r_intr___tr_rdy___lsb 0 +#define reg_ser_r_intr___tr_rdy___width 1 +#define reg_ser_r_intr___tr_rdy___bit 0 +#define reg_ser_r_intr___tr_empty___lsb 1 +#define reg_ser_r_intr___tr_empty___width 1 +#define reg_ser_r_intr___tr_empty___bit 1 +#define reg_ser_r_intr___tr_idle___lsb 2 +#define reg_ser_r_intr___tr_idle___width 1 +#define reg_ser_r_intr___tr_idle___bit 2 +#define reg_ser_r_intr___dav___lsb 3 +#define reg_ser_r_intr___dav___width 1 +#define reg_ser_r_intr___dav___bit 3 +#define reg_ser_r_intr_offset 52 + +/* Register r_masked_intr, scope ser, type r */ +#define reg_ser_r_masked_intr___tr_rdy___lsb 0 +#define reg_ser_r_masked_intr___tr_rdy___width 1 +#define reg_ser_r_masked_intr___tr_rdy___bit 0 +#define reg_ser_r_masked_intr___tr_empty___lsb 1 +#define reg_ser_r_masked_intr___tr_empty___width 1 +#define reg_ser_r_masked_intr___tr_empty___bit 1 +#define reg_ser_r_masked_intr___tr_idle___lsb 2 +#define reg_ser_r_masked_intr___tr_idle___width 1 +#define reg_ser_r_masked_intr___tr_idle___bit 2 +#define reg_ser_r_masked_intr___dav___lsb 3 +#define reg_ser_r_masked_intr___dav___width 1 +#define reg_ser_r_masked_intr___dav___bit 3 +#define reg_ser_r_masked_intr_offset 56 + + +/* Constants */ +#define regk_ser_active 0x00000000 +#define regk_ser_bits1 0x00000000 +#define regk_ser_bits2 0x00000001 +#define regk_ser_bits7 0x00000001 +#define regk_ser_bits8 0x00000000 +#define regk_ser_del0_5 0x00000000 +#define regk_ser_del1 0x00000001 +#define regk_ser_del1_5 0x00000002 +#define regk_ser_del2 0x00000003 +#define regk_ser_del2_5 0x00000004 +#define regk_ser_del3 0x00000005 +#define regk_ser_del3_5 0x00000006 +#define regk_ser_del4 0x00000007 +#define regk_ser_even 0x00000000 +#define regk_ser_ext 0x00000001 +#define regk_ser_f100 0x00000007 +#define regk_ser_f29_493 0x00000004 +#define regk_ser_f32 0x00000005 +#define regk_ser_f32_768 0x00000006 +#define regk_ser_ignore 0x00000001 +#define regk_ser_inactive 0x00000001 +#define regk_ser_majority 0x00000001 +#define regk_ser_mark 0x00000002 +#define regk_ser_middle 0x00000000 +#define regk_ser_no 0x00000000 +#define regk_ser_odd 0x00000001 +#define regk_ser_off 0x00000000 +#define regk_ser_rw_intr_mask_default 0x00000000 +#define regk_ser_rw_rec_baud_div_default 0x00000000 +#define regk_ser_rw_rec_ctrl_default 0x00010000 +#define regk_ser_rw_tr_baud_div_default 0x00000000 +#define regk_ser_rw_tr_ctrl_default 0x00008000 +#define regk_ser_rw_tr_dma_en_default 0x00000000 +#define regk_ser_rw_xoff_default 0x00000000 +#define regk_ser_space 0x00000003 +#define regk_ser_stop 0x00000000 +#define regk_ser_yes 0x00000001 +#endif /* __ser_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h new file mode 100644 index 000000000..27d4d91b3 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h @@ -0,0 +1,462 @@ +#ifndef __sser_defs_asm_h +#define __sser_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/syncser/rtl/sser_regs.r + * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp + * last modfied: Mon Apr 11 16:09:48 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r + * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope sser, type rw */ +#define reg_sser_rw_cfg___clk_div___lsb 0 +#define reg_sser_rw_cfg___clk_div___width 16 +#define reg_sser_rw_cfg___base_freq___lsb 16 +#define reg_sser_rw_cfg___base_freq___width 3 +#define reg_sser_rw_cfg___gate_clk___lsb 19 +#define reg_sser_rw_cfg___gate_clk___width 1 +#define reg_sser_rw_cfg___gate_clk___bit 19 +#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 +#define reg_sser_rw_cfg___clkgate_ctrl___width 1 +#define reg_sser_rw_cfg___clkgate_ctrl___bit 20 +#define reg_sser_rw_cfg___clkgate_in___lsb 21 +#define reg_sser_rw_cfg___clkgate_in___width 1 +#define reg_sser_rw_cfg___clkgate_in___bit 21 +#define reg_sser_rw_cfg___clk_dir___lsb 22 +#define reg_sser_rw_cfg___clk_dir___width 1 +#define reg_sser_rw_cfg___clk_dir___bit 22 +#define reg_sser_rw_cfg___clk_od_mode___lsb 23 +#define reg_sser_rw_cfg___clk_od_mode___width 1 +#define reg_sser_rw_cfg___clk_od_mode___bit 23 +#define reg_sser_rw_cfg___out_clk_pol___lsb 24 +#define reg_sser_rw_cfg___out_clk_pol___width 1 +#define reg_sser_rw_cfg___out_clk_pol___bit 24 +#define reg_sser_rw_cfg___out_clk_src___lsb 25 +#define reg_sser_rw_cfg___out_clk_src___width 2 +#define reg_sser_rw_cfg___clk_in_sel___lsb 27 +#define reg_sser_rw_cfg___clk_in_sel___width 1 +#define reg_sser_rw_cfg___clk_in_sel___bit 27 +#define reg_sser_rw_cfg___hold_pol___lsb 28 +#define reg_sser_rw_cfg___hold_pol___width 1 +#define reg_sser_rw_cfg___hold_pol___bit 28 +#define reg_sser_rw_cfg___prepare___lsb 29 +#define reg_sser_rw_cfg___prepare___width 1 +#define reg_sser_rw_cfg___prepare___bit 29 +#define reg_sser_rw_cfg___en___lsb 30 +#define reg_sser_rw_cfg___en___width 1 +#define reg_sser_rw_cfg___en___bit 30 +#define reg_sser_rw_cfg_offset 0 + +/* Register rw_frm_cfg, scope sser, type rw */ +#define reg_sser_rw_frm_cfg___wordrate___lsb 0 +#define reg_sser_rw_frm_cfg___wordrate___width 10 +#define reg_sser_rw_frm_cfg___rec_delay___lsb 10 +#define reg_sser_rw_frm_cfg___rec_delay___width 3 +#define reg_sser_rw_frm_cfg___tr_delay___lsb 13 +#define reg_sser_rw_frm_cfg___tr_delay___width 3 +#define reg_sser_rw_frm_cfg___early_wend___lsb 16 +#define reg_sser_rw_frm_cfg___early_wend___width 1 +#define reg_sser_rw_frm_cfg___early_wend___bit 16 +#define reg_sser_rw_frm_cfg___level___lsb 17 +#define reg_sser_rw_frm_cfg___level___width 2 +#define reg_sser_rw_frm_cfg___type___lsb 19 +#define reg_sser_rw_frm_cfg___type___width 1 +#define reg_sser_rw_frm_cfg___type___bit 19 +#define reg_sser_rw_frm_cfg___clk_pol___lsb 20 +#define reg_sser_rw_frm_cfg___clk_pol___width 1 +#define reg_sser_rw_frm_cfg___clk_pol___bit 20 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 +#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 +#define reg_sser_rw_frm_cfg___clk_src___lsb 22 +#define reg_sser_rw_frm_cfg___clk_src___width 1 +#define reg_sser_rw_frm_cfg___clk_src___bit 22 +#define reg_sser_rw_frm_cfg___out_off___lsb 23 +#define reg_sser_rw_frm_cfg___out_off___width 1 +#define reg_sser_rw_frm_cfg___out_off___bit 23 +#define reg_sser_rw_frm_cfg___out_on___lsb 24 +#define reg_sser_rw_frm_cfg___out_on___width 1 +#define reg_sser_rw_frm_cfg___out_on___bit 24 +#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 +#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 +#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 +#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 +#define reg_sser_rw_frm_cfg___frame_pin_use___width 2 +#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 +#define reg_sser_rw_frm_cfg___status_pin_dir___width 1 +#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 +#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 +#define reg_sser_rw_frm_cfg___status_pin_use___width 2 +#define reg_sser_rw_frm_cfg_offset 4 + +/* Register rw_tr_cfg, scope sser, type rw */ +#define reg_sser_rw_tr_cfg___tr_en___lsb 0 +#define reg_sser_rw_tr_cfg___tr_en___width 1 +#define reg_sser_rw_tr_cfg___tr_en___bit 0 +#define reg_sser_rw_tr_cfg___stop___lsb 1 +#define reg_sser_rw_tr_cfg___stop___width 1 +#define reg_sser_rw_tr_cfg___stop___bit 1 +#define reg_sser_rw_tr_cfg___urun_stop___lsb 2 +#define reg_sser_rw_tr_cfg___urun_stop___width 1 +#define reg_sser_rw_tr_cfg___urun_stop___bit 2 +#define reg_sser_rw_tr_cfg___eop_stop___lsb 3 +#define reg_sser_rw_tr_cfg___eop_stop___width 1 +#define reg_sser_rw_tr_cfg___eop_stop___bit 3 +#define reg_sser_rw_tr_cfg___sample_size___lsb 4 +#define reg_sser_rw_tr_cfg___sample_size___width 6 +#define reg_sser_rw_tr_cfg___sh_dir___lsb 10 +#define reg_sser_rw_tr_cfg___sh_dir___width 1 +#define reg_sser_rw_tr_cfg___sh_dir___bit 10 +#define reg_sser_rw_tr_cfg___clk_pol___lsb 11 +#define reg_sser_rw_tr_cfg___clk_pol___width 1 +#define reg_sser_rw_tr_cfg___clk_pol___bit 11 +#define reg_sser_rw_tr_cfg___clk_src___lsb 12 +#define reg_sser_rw_tr_cfg___clk_src___width 1 +#define reg_sser_rw_tr_cfg___clk_src___bit 12 +#define reg_sser_rw_tr_cfg___use_dma___lsb 13 +#define reg_sser_rw_tr_cfg___use_dma___width 1 +#define reg_sser_rw_tr_cfg___use_dma___bit 13 +#define reg_sser_rw_tr_cfg___mode___lsb 14 +#define reg_sser_rw_tr_cfg___mode___width 2 +#define reg_sser_rw_tr_cfg___frm_src___lsb 16 +#define reg_sser_rw_tr_cfg___frm_src___width 1 +#define reg_sser_rw_tr_cfg___frm_src___bit 16 +#define reg_sser_rw_tr_cfg___use60958___lsb 17 +#define reg_sser_rw_tr_cfg___use60958___width 1 +#define reg_sser_rw_tr_cfg___use60958___bit 17 +#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 +#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 +#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 +#define reg_sser_rw_tr_cfg___rate_ctrl___width 1 +#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 +#define reg_sser_rw_tr_cfg___use_md___lsb 21 +#define reg_sser_rw_tr_cfg___use_md___width 1 +#define reg_sser_rw_tr_cfg___use_md___bit 21 +#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 +#define reg_sser_rw_tr_cfg___dual_i2s___width 1 +#define reg_sser_rw_tr_cfg___dual_i2s___bit 22 +#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 +#define reg_sser_rw_tr_cfg___data_pin_use___width 2 +#define reg_sser_rw_tr_cfg___od_mode___lsb 25 +#define reg_sser_rw_tr_cfg___od_mode___width 1 +#define reg_sser_rw_tr_cfg___od_mode___bit 25 +#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 +#define reg_sser_rw_tr_cfg___bulk_wspace___width 2 +#define reg_sser_rw_tr_cfg_offset 8 + +/* Register rw_rec_cfg, scope sser, type rw */ +#define reg_sser_rw_rec_cfg___rec_en___lsb 0 +#define reg_sser_rw_rec_cfg___rec_en___width 1 +#define reg_sser_rw_rec_cfg___rec_en___bit 0 +#define reg_sser_rw_rec_cfg___force_eop___lsb 1 +#define reg_sser_rw_rec_cfg___force_eop___width 1 +#define reg_sser_rw_rec_cfg___force_eop___bit 1 +#define reg_sser_rw_rec_cfg___stop___lsb 2 +#define reg_sser_rw_rec_cfg___stop___width 1 +#define reg_sser_rw_rec_cfg___stop___bit 2 +#define reg_sser_rw_rec_cfg___orun_stop___lsb 3 +#define reg_sser_rw_rec_cfg___orun_stop___width 1 +#define reg_sser_rw_rec_cfg___orun_stop___bit 3 +#define reg_sser_rw_rec_cfg___eop_stop___lsb 4 +#define reg_sser_rw_rec_cfg___eop_stop___width 1 +#define reg_sser_rw_rec_cfg___eop_stop___bit 4 +#define reg_sser_rw_rec_cfg___sample_size___lsb 5 +#define reg_sser_rw_rec_cfg___sample_size___width 6 +#define reg_sser_rw_rec_cfg___sh_dir___lsb 11 +#define reg_sser_rw_rec_cfg___sh_dir___width 1 +#define reg_sser_rw_rec_cfg___sh_dir___bit 11 +#define reg_sser_rw_rec_cfg___clk_pol___lsb 12 +#define reg_sser_rw_rec_cfg___clk_pol___width 1 +#define reg_sser_rw_rec_cfg___clk_pol___bit 12 +#define reg_sser_rw_rec_cfg___clk_src___lsb 13 +#define reg_sser_rw_rec_cfg___clk_src___width 1 +#define reg_sser_rw_rec_cfg___clk_src___bit 13 +#define reg_sser_rw_rec_cfg___use_dma___lsb 14 +#define reg_sser_rw_rec_cfg___use_dma___width 1 +#define reg_sser_rw_rec_cfg___use_dma___bit 14 +#define reg_sser_rw_rec_cfg___mode___lsb 15 +#define reg_sser_rw_rec_cfg___mode___width 2 +#define reg_sser_rw_rec_cfg___frm_src___lsb 17 +#define reg_sser_rw_rec_cfg___frm_src___width 2 +#define reg_sser_rw_rec_cfg___use60958___lsb 19 +#define reg_sser_rw_rec_cfg___use60958___width 1 +#define reg_sser_rw_rec_cfg___use60958___bit 19 +#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 +#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 +#define reg_sser_rw_rec_cfg___slave2_en___lsb 25 +#define reg_sser_rw_rec_cfg___slave2_en___width 1 +#define reg_sser_rw_rec_cfg___slave2_en___bit 25 +#define reg_sser_rw_rec_cfg___slave3_en___lsb 26 +#define reg_sser_rw_rec_cfg___slave3_en___width 1 +#define reg_sser_rw_rec_cfg___slave3_en___bit 26 +#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 +#define reg_sser_rw_rec_cfg___fifo_thr___width 2 +#define reg_sser_rw_rec_cfg_offset 12 + +/* Register rw_tr_data, scope sser, type rw */ +#define reg_sser_rw_tr_data___data___lsb 0 +#define reg_sser_rw_tr_data___data___width 16 +#define reg_sser_rw_tr_data___md___lsb 16 +#define reg_sser_rw_tr_data___md___width 1 +#define reg_sser_rw_tr_data___md___bit 16 +#define reg_sser_rw_tr_data_offset 16 + +/* Register r_rec_data, scope sser, type r */ +#define reg_sser_r_rec_data___data___lsb 0 +#define reg_sser_r_rec_data___data___width 16 +#define reg_sser_r_rec_data___md___lsb 16 +#define reg_sser_r_rec_data___md___width 1 +#define reg_sser_r_rec_data___md___bit 16 +#define reg_sser_r_rec_data___ext_clk___lsb 17 +#define reg_sser_r_rec_data___ext_clk___width 1 +#define reg_sser_r_rec_data___ext_clk___bit 17 +#define reg_sser_r_rec_data___status_in___lsb 18 +#define reg_sser_r_rec_data___status_in___width 1 +#define reg_sser_r_rec_data___status_in___bit 18 +#define reg_sser_r_rec_data___frame_in___lsb 19 +#define reg_sser_r_rec_data___frame_in___width 1 +#define reg_sser_r_rec_data___frame_in___bit 19 +#define reg_sser_r_rec_data___din___lsb 20 +#define reg_sser_r_rec_data___din___width 1 +#define reg_sser_r_rec_data___din___bit 20 +#define reg_sser_r_rec_data___data_in___lsb 21 +#define reg_sser_r_rec_data___data_in___width 1 +#define reg_sser_r_rec_data___data_in___bit 21 +#define reg_sser_r_rec_data___clk_in___lsb 22 +#define reg_sser_r_rec_data___clk_in___width 1 +#define reg_sser_r_rec_data___clk_in___bit 22 +#define reg_sser_r_rec_data_offset 20 + +/* Register rw_extra, scope sser, type rw */ +#define reg_sser_rw_extra___clkoff_cycles___lsb 0 +#define reg_sser_rw_extra___clkoff_cycles___width 20 +#define reg_sser_rw_extra___clkoff_en___lsb 20 +#define reg_sser_rw_extra___clkoff_en___width 1 +#define reg_sser_rw_extra___clkoff_en___bit 20 +#define reg_sser_rw_extra___clkon_en___lsb 21 +#define reg_sser_rw_extra___clkon_en___width 1 +#define reg_sser_rw_extra___clkon_en___bit 21 +#define reg_sser_rw_extra___dout_delay___lsb 22 +#define reg_sser_rw_extra___dout_delay___width 5 +#define reg_sser_rw_extra_offset 24 + +/* Register rw_intr_mask, scope sser, type rw */ +#define reg_sser_rw_intr_mask___trdy___lsb 0 +#define reg_sser_rw_intr_mask___trdy___width 1 +#define reg_sser_rw_intr_mask___trdy___bit 0 +#define reg_sser_rw_intr_mask___rdav___lsb 1 +#define reg_sser_rw_intr_mask___rdav___width 1 +#define reg_sser_rw_intr_mask___rdav___bit 1 +#define reg_sser_rw_intr_mask___tidle___lsb 2 +#define reg_sser_rw_intr_mask___tidle___width 1 +#define reg_sser_rw_intr_mask___tidle___bit 2 +#define reg_sser_rw_intr_mask___rstop___lsb 3 +#define reg_sser_rw_intr_mask___rstop___width 1 +#define reg_sser_rw_intr_mask___rstop___bit 3 +#define reg_sser_rw_intr_mask___urun___lsb 4 +#define reg_sser_rw_intr_mask___urun___width 1 +#define reg_sser_rw_intr_mask___urun___bit 4 +#define reg_sser_rw_intr_mask___orun___lsb 5 +#define reg_sser_rw_intr_mask___orun___width 1 +#define reg_sser_rw_intr_mask___orun___bit 5 +#define reg_sser_rw_intr_mask___md_rec___lsb 6 +#define reg_sser_rw_intr_mask___md_rec___width 1 +#define reg_sser_rw_intr_mask___md_rec___bit 6 +#define reg_sser_rw_intr_mask___md_sent___lsb 7 +#define reg_sser_rw_intr_mask___md_sent___width 1 +#define reg_sser_rw_intr_mask___md_sent___bit 7 +#define reg_sser_rw_intr_mask___r958err___lsb 8 +#define reg_sser_rw_intr_mask___r958err___width 1 +#define reg_sser_rw_intr_mask___r958err___bit 8 +#define reg_sser_rw_intr_mask_offset 28 + +/* Register rw_ack_intr, scope sser, type rw */ +#define reg_sser_rw_ack_intr___trdy___lsb 0 +#define reg_sser_rw_ack_intr___trdy___width 1 +#define reg_sser_rw_ack_intr___trdy___bit 0 +#define reg_sser_rw_ack_intr___rdav___lsb 1 +#define reg_sser_rw_ack_intr___rdav___width 1 +#define reg_sser_rw_ack_intr___rdav___bit 1 +#define reg_sser_rw_ack_intr___tidle___lsb 2 +#define reg_sser_rw_ack_intr___tidle___width 1 +#define reg_sser_rw_ack_intr___tidle___bit 2 +#define reg_sser_rw_ack_intr___rstop___lsb 3 +#define reg_sser_rw_ack_intr___rstop___width 1 +#define reg_sser_rw_ack_intr___rstop___bit 3 +#define reg_sser_rw_ack_intr___urun___lsb 4 +#define reg_sser_rw_ack_intr___urun___width 1 +#define reg_sser_rw_ack_intr___urun___bit 4 +#define reg_sser_rw_ack_intr___orun___lsb 5 +#define reg_sser_rw_ack_intr___orun___width 1 +#define reg_sser_rw_ack_intr___orun___bit 5 +#define reg_sser_rw_ack_intr___md_rec___lsb 6 +#define reg_sser_rw_ack_intr___md_rec___width 1 +#define reg_sser_rw_ack_intr___md_rec___bit 6 +#define reg_sser_rw_ack_intr___md_sent___lsb 7 +#define reg_sser_rw_ack_intr___md_sent___width 1 +#define reg_sser_rw_ack_intr___md_sent___bit 7 +#define reg_sser_rw_ack_intr___r958err___lsb 8 +#define reg_sser_rw_ack_intr___r958err___width 1 +#define reg_sser_rw_ack_intr___r958err___bit 8 +#define reg_sser_rw_ack_intr_offset 32 + +/* Register r_intr, scope sser, type r */ +#define reg_sser_r_intr___trdy___lsb 0 +#define reg_sser_r_intr___trdy___width 1 +#define reg_sser_r_intr___trdy___bit 0 +#define reg_sser_r_intr___rdav___lsb 1 +#define reg_sser_r_intr___rdav___width 1 +#define reg_sser_r_intr___rdav___bit 1 +#define reg_sser_r_intr___tidle___lsb 2 +#define reg_sser_r_intr___tidle___width 1 +#define reg_sser_r_intr___tidle___bit 2 +#define reg_sser_r_intr___rstop___lsb 3 +#define reg_sser_r_intr___rstop___width 1 +#define reg_sser_r_intr___rstop___bit 3 +#define reg_sser_r_intr___urun___lsb 4 +#define reg_sser_r_intr___urun___width 1 +#define reg_sser_r_intr___urun___bit 4 +#define reg_sser_r_intr___orun___lsb 5 +#define reg_sser_r_intr___orun___width 1 +#define reg_sser_r_intr___orun___bit 5 +#define reg_sser_r_intr___md_rec___lsb 6 +#define reg_sser_r_intr___md_rec___width 1 +#define reg_sser_r_intr___md_rec___bit 6 +#define reg_sser_r_intr___md_sent___lsb 7 +#define reg_sser_r_intr___md_sent___width 1 +#define reg_sser_r_intr___md_sent___bit 7 +#define reg_sser_r_intr___r958err___lsb 8 +#define reg_sser_r_intr___r958err___width 1 +#define reg_sser_r_intr___r958err___bit 8 +#define reg_sser_r_intr_offset 36 + +/* Register r_masked_intr, scope sser, type r */ +#define reg_sser_r_masked_intr___trdy___lsb 0 +#define reg_sser_r_masked_intr___trdy___width 1 +#define reg_sser_r_masked_intr___trdy___bit 0 +#define reg_sser_r_masked_intr___rdav___lsb 1 +#define reg_sser_r_masked_intr___rdav___width 1 +#define reg_sser_r_masked_intr___rdav___bit 1 +#define reg_sser_r_masked_intr___tidle___lsb 2 +#define reg_sser_r_masked_intr___tidle___width 1 +#define reg_sser_r_masked_intr___tidle___bit 2 +#define reg_sser_r_masked_intr___rstop___lsb 3 +#define reg_sser_r_masked_intr___rstop___width 1 +#define reg_sser_r_masked_intr___rstop___bit 3 +#define reg_sser_r_masked_intr___urun___lsb 4 +#define reg_sser_r_masked_intr___urun___width 1 +#define reg_sser_r_masked_intr___urun___bit 4 +#define reg_sser_r_masked_intr___orun___lsb 5 +#define reg_sser_r_masked_intr___orun___width 1 +#define reg_sser_r_masked_intr___orun___bit 5 +#define reg_sser_r_masked_intr___md_rec___lsb 6 +#define reg_sser_r_masked_intr___md_rec___width 1 +#define reg_sser_r_masked_intr___md_rec___bit 6 +#define reg_sser_r_masked_intr___md_sent___lsb 7 +#define reg_sser_r_masked_intr___md_sent___width 1 +#define reg_sser_r_masked_intr___md_sent___bit 7 +#define reg_sser_r_masked_intr___r958err___lsb 8 +#define reg_sser_r_masked_intr___r958err___width 1 +#define reg_sser_r_masked_intr___r958err___bit 8 +#define reg_sser_r_masked_intr_offset 40 + + +/* Constants */ +#define regk_sser_both 0x00000002 +#define regk_sser_bulk 0x00000001 +#define regk_sser_clk100 0x00000000 +#define regk_sser_clk_in 0x00000000 +#define regk_sser_const0 0x00000003 +#define regk_sser_dout 0x00000002 +#define regk_sser_edge 0x00000000 +#define regk_sser_ext 0x00000001 +#define regk_sser_ext_clk 0x00000001 +#define regk_sser_f100 0x00000000 +#define regk_sser_f29_493 0x00000004 +#define regk_sser_f32 0x00000005 +#define regk_sser_f32_768 0x00000006 +#define regk_sser_frm 0x00000003 +#define regk_sser_gio0 0x00000000 +#define regk_sser_gio1 0x00000001 +#define regk_sser_hispeed 0x00000001 +#define regk_sser_hold 0x00000002 +#define regk_sser_in 0x00000000 +#define regk_sser_inf 0x00000003 +#define regk_sser_intern 0x00000000 +#define regk_sser_intern_clk 0x00000001 +#define regk_sser_intern_tb 0x00000000 +#define regk_sser_iso 0x00000000 +#define regk_sser_level 0x00000001 +#define regk_sser_lospeed 0x00000000 +#define regk_sser_lsbfirst 0x00000000 +#define regk_sser_msbfirst 0x00000001 +#define regk_sser_neg 0x00000001 +#define regk_sser_neg_lo 0x00000000 +#define regk_sser_no 0x00000000 +#define regk_sser_no_clk 0x00000007 +#define regk_sser_nojitter 0x00000002 +#define regk_sser_out 0x00000001 +#define regk_sser_pos 0x00000000 +#define regk_sser_pos_hi 0x00000001 +#define regk_sser_rec 0x00000000 +#define regk_sser_rw_cfg_default 0x00000000 +#define regk_sser_rw_extra_default 0x00000000 +#define regk_sser_rw_frm_cfg_default 0x00000000 +#define regk_sser_rw_intr_mask_default 0x00000000 +#define regk_sser_rw_rec_cfg_default 0x00000000 +#define regk_sser_rw_tr_cfg_default 0x01800000 +#define regk_sser_rw_tr_data_default 0x00000000 +#define regk_sser_thr16 0x00000001 +#define regk_sser_thr32 0x00000002 +#define regk_sser_thr8 0x00000000 +#define regk_sser_tr 0x00000001 +#define regk_sser_ts_out 0x00000003 +#define regk_sser_tx_bulk 0x00000002 +#define regk_sser_wiresave 0x00000002 +#define regk_sser_yes 0x00000001 +#endif /* __sser_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h new file mode 100644 index 000000000..55083e6ae --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h @@ -0,0 +1,84 @@ +#ifndef __strcop_defs_asm_h +#define __strcop_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/strcop/rtl/strcop_regs.r + * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp + * last modfied: Mon Apr 11 16:09:38 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r + * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope strcop, type rw */ +#define reg_strcop_rw_cfg___td3___lsb 0 +#define reg_strcop_rw_cfg___td3___width 1 +#define reg_strcop_rw_cfg___td3___bit 0 +#define reg_strcop_rw_cfg___td2___lsb 1 +#define reg_strcop_rw_cfg___td2___width 1 +#define reg_strcop_rw_cfg___td2___bit 1 +#define reg_strcop_rw_cfg___td1___lsb 2 +#define reg_strcop_rw_cfg___td1___width 1 +#define reg_strcop_rw_cfg___td1___bit 2 +#define reg_strcop_rw_cfg___ipend___lsb 3 +#define reg_strcop_rw_cfg___ipend___width 1 +#define reg_strcop_rw_cfg___ipend___bit 3 +#define reg_strcop_rw_cfg___ignore_sync___lsb 4 +#define reg_strcop_rw_cfg___ignore_sync___width 1 +#define reg_strcop_rw_cfg___ignore_sync___bit 4 +#define reg_strcop_rw_cfg___en___lsb 5 +#define reg_strcop_rw_cfg___en___width 1 +#define reg_strcop_rw_cfg___en___bit 5 +#define reg_strcop_rw_cfg_offset 0 + + +/* Constants */ +#define regk_strcop_big 0x00000001 +#define regk_strcop_d 0x00000001 +#define regk_strcop_e 0x00000000 +#define regk_strcop_little 0x00000000 +#define regk_strcop_rw_cfg_default 0x00000002 +#endif /* __strcop_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h new file mode 100644 index 000000000..69b299920 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h @@ -0,0 +1,100 @@ +#ifndef __strmux_defs_asm_h +#define __strmux_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp + * last modfied: Mon Apr 11 16:09:43 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope strmux, type rw */ +#define reg_strmux_rw_cfg___dma0___lsb 0 +#define reg_strmux_rw_cfg___dma0___width 3 +#define reg_strmux_rw_cfg___dma1___lsb 3 +#define reg_strmux_rw_cfg___dma1___width 3 +#define reg_strmux_rw_cfg___dma2___lsb 6 +#define reg_strmux_rw_cfg___dma2___width 3 +#define reg_strmux_rw_cfg___dma3___lsb 9 +#define reg_strmux_rw_cfg___dma3___width 3 +#define reg_strmux_rw_cfg___dma4___lsb 12 +#define reg_strmux_rw_cfg___dma4___width 3 +#define reg_strmux_rw_cfg___dma5___lsb 15 +#define reg_strmux_rw_cfg___dma5___width 3 +#define reg_strmux_rw_cfg___dma6___lsb 18 +#define reg_strmux_rw_cfg___dma6___width 3 +#define reg_strmux_rw_cfg___dma7___lsb 21 +#define reg_strmux_rw_cfg___dma7___width 3 +#define reg_strmux_rw_cfg___dma8___lsb 24 +#define reg_strmux_rw_cfg___dma8___width 3 +#define reg_strmux_rw_cfg___dma9___lsb 27 +#define reg_strmux_rw_cfg___dma9___width 3 +#define reg_strmux_rw_cfg_offset 0 + + +/* Constants */ +#define regk_strmux_ata 0x00000003 +#define regk_strmux_eth0 0x00000001 +#define regk_strmux_eth1 0x00000004 +#define regk_strmux_ext0 0x00000001 +#define regk_strmux_ext1 0x00000001 +#define regk_strmux_ext2 0x00000001 +#define regk_strmux_ext3 0x00000001 +#define regk_strmux_iop0 0x00000002 +#define regk_strmux_iop1 0x00000001 +#define regk_strmux_off 0x00000000 +#define regk_strmux_p21 0x00000004 +#define regk_strmux_rw_cfg_default 0x00000000 +#define regk_strmux_ser0 0x00000002 +#define regk_strmux_ser1 0x00000002 +#define regk_strmux_ser2 0x00000004 +#define regk_strmux_ser3 0x00000003 +#define regk_strmux_sser0 0x00000003 +#define regk_strmux_sser1 0x00000003 +#define regk_strmux_strcop 0x00000002 +#endif /* __strmux_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000..43146021f --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,229 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h new file mode 100644 index 000000000..43b6643ff --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h @@ -0,0 +1,222 @@ +#ifndef __ata_defs_h +#define __ata_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ata/rtl/ata_regs.r + * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp + * last modfied: Mon Apr 11 16:06:25 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r + * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ata */ + +/* Register rw_ctrl0, scope ata, type rw */ +typedef struct { + unsigned int pio_hold : 6; + unsigned int pio_strb : 6; + unsigned int pio_setup : 6; + unsigned int dma_hold : 6; + unsigned int dma_strb : 6; + unsigned int rst : 1; + unsigned int en : 1; +} reg_ata_rw_ctrl0; +#define REG_RD_ADDR_ata_rw_ctrl0 12 +#define REG_WR_ADDR_ata_rw_ctrl0 12 + +/* Register rw_ctrl1, scope ata, type rw */ +typedef struct { + unsigned int udma_tcyc : 4; + unsigned int udma_tdvs : 4; + unsigned int dummy1 : 24; +} reg_ata_rw_ctrl1; +#define REG_RD_ADDR_ata_rw_ctrl1 16 +#define REG_WR_ADDR_ata_rw_ctrl1 16 + +/* Register rw_ctrl2, scope ata, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 3; + unsigned int dma_size : 1; + unsigned int multi : 1; + unsigned int hsh : 2; + unsigned int trf_mode : 1; + unsigned int rw : 1; + unsigned int addr : 3; + unsigned int cs0 : 1; + unsigned int cs1 : 1; + unsigned int sel : 2; +} reg_ata_rw_ctrl2; +#define REG_RD_ADDR_ata_rw_ctrl2 0 +#define REG_WR_ADDR_ata_rw_ctrl2 0 + +/* Register rs_stat_data, scope ata, type rs */ +typedef struct { + unsigned int data : 16; + unsigned int dav : 1; + unsigned int busy : 1; + unsigned int dummy1 : 14; +} reg_ata_rs_stat_data; +#define REG_RD_ADDR_ata_rs_stat_data 4 + +/* Register r_stat_data, scope ata, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dav : 1; + unsigned int busy : 1; + unsigned int dummy1 : 14; +} reg_ata_r_stat_data; +#define REG_RD_ADDR_ata_r_stat_data 8 + +/* Register rw_trf_cnt, scope ata, type rw */ +typedef struct { + unsigned int cnt : 17; + unsigned int dummy1 : 15; +} reg_ata_rw_trf_cnt; +#define REG_RD_ADDR_ata_rw_trf_cnt 20 +#define REG_WR_ADDR_ata_rw_trf_cnt 20 + +/* Register r_stat_misc, scope ata, type r */ +typedef struct { + unsigned int crc : 16; + unsigned int dummy1 : 16; +} reg_ata_r_stat_misc; +#define REG_RD_ADDR_ata_r_stat_misc 24 + +/* Register rw_intr_mask, scope ata, type rw */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_rw_intr_mask; +#define REG_RD_ADDR_ata_rw_intr_mask 28 +#define REG_WR_ADDR_ata_rw_intr_mask 28 + +/* Register rw_ack_intr, scope ata, type rw */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_rw_ack_intr; +#define REG_RD_ADDR_ata_rw_ack_intr 32 +#define REG_WR_ADDR_ata_rw_ack_intr 32 + +/* Register r_intr, scope ata, type r */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_r_intr; +#define REG_RD_ADDR_ata_r_intr 36 + +/* Register r_masked_intr, scope ata, type r */ +typedef struct { + unsigned int bus0 : 1; + unsigned int bus1 : 1; + unsigned int bus2 : 1; + unsigned int bus3 : 1; + unsigned int dummy1 : 28; +} reg_ata_r_masked_intr; +#define REG_RD_ADDR_ata_r_masked_intr 40 + + +/* Constants */ +enum { + regk_ata_active = 0x00000001, + regk_ata_byte = 0x00000001, + regk_ata_data = 0x00000001, + regk_ata_dma = 0x00000001, + regk_ata_inactive = 0x00000000, + regk_ata_no = 0x00000000, + regk_ata_nodata = 0x00000000, + regk_ata_pio = 0x00000000, + regk_ata_rd = 0x00000001, + regk_ata_reg = 0x00000000, + regk_ata_rw_ctrl0_default = 0x00000000, + regk_ata_rw_ctrl2_default = 0x00000000, + regk_ata_rw_intr_mask_default = 0x00000000, + regk_ata_udma = 0x00000002, + regk_ata_word = 0x00000000, + regk_ata_wr = 0x00000000, + regk_ata_yes = 0x00000001 +}; +#endif /* __ata_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h new file mode 100644 index 000000000..a56608b50 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h @@ -0,0 +1,284 @@ +#ifndef __bif_core_defs_h +#define __bif_core_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_core */ + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp1_cfg; +#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 +#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp2_cfg; +#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 +#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 2; + unsigned int gated_csp0 : 2; + unsigned int gated_csp1 : 2; + unsigned int gated_csp2 : 2; + unsigned int gated_csp3 : 2; +} reg_bif_core_rw_grp3_cfg; +#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 +#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 4; + unsigned int gated_csp4 : 2; + unsigned int gated_csp5 : 2; + unsigned int gated_csp6 : 2; +} reg_bif_core_rw_grp4_cfg; +#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 +#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int grp_sel : 5; + unsigned int dummy1 : 12; +} reg_bif_core_rw_sdram_cfg_grp0; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int dummy1 : 17; +} reg_bif_core_rw_sdram_cfg_grp1; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +typedef struct { + unsigned int cl : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int rc : 2; + unsigned int dpl : 2; + unsigned int pde : 1; + unsigned int ref : 2; + unsigned int cpd : 1; + unsigned int sdcke : 1; + unsigned int sdclk : 1; + unsigned int dummy1 : 13; +} reg_bif_core_rw_sdram_timing; +#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 +#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +typedef struct { + unsigned int cmd : 3; + unsigned int mrs_data : 15; + unsigned int dummy1 : 14; +} reg_bif_core_rw_sdram_cmd; +#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 +#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_rs_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_r_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 + + +/* Constants */ +enum { + regk_bif_core_bank2 = 0x00000000, + regk_bif_core_bank4 = 0x00000001, + regk_bif_core_bit10 = 0x0000000a, + regk_bif_core_bit11 = 0x0000000b, + regk_bif_core_bit12 = 0x0000000c, + regk_bif_core_bit13 = 0x0000000d, + regk_bif_core_bit14 = 0x0000000e, + regk_bif_core_bit15 = 0x0000000f, + regk_bif_core_bit16 = 0x00000010, + regk_bif_core_bit17 = 0x00000011, + regk_bif_core_bit18 = 0x00000012, + regk_bif_core_bit19 = 0x00000013, + regk_bif_core_bit20 = 0x00000014, + regk_bif_core_bit21 = 0x00000015, + regk_bif_core_bit22 = 0x00000016, + regk_bif_core_bit23 = 0x00000017, + regk_bif_core_bit24 = 0x00000018, + regk_bif_core_bit25 = 0x00000019, + regk_bif_core_bit26 = 0x0000001a, + regk_bif_core_bit27 = 0x0000001b, + regk_bif_core_bit28 = 0x0000001c, + regk_bif_core_bit29 = 0x0000001d, + regk_bif_core_bit9 = 0x00000009, + regk_bif_core_bw16 = 0x00000001, + regk_bif_core_bw32 = 0x00000000, + regk_bif_core_bwe = 0x00000000, + regk_bif_core_cwe = 0x00000001, + regk_bif_core_e15us = 0x00000001, + regk_bif_core_e7800ns = 0x00000002, + regk_bif_core_grp0 = 0x00000000, + regk_bif_core_grp1 = 0x00000001, + regk_bif_core_mrs = 0x00000003, + regk_bif_core_no = 0x00000000, + regk_bif_core_none = 0x00000000, + regk_bif_core_nop = 0x00000000, + regk_bif_core_off = 0x00000000, + regk_bif_core_pre = 0x00000002, + regk_bif_core_r_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rd = 0x00000002, + regk_bif_core_ref = 0x00000001, + regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rw_grp1_cfg_default = 0x000006cf, + regk_bif_core_rw_grp2_cfg_default = 0x000006cf, + regk_bif_core_rw_grp3_cfg_default = 0x000006cf, + regk_bif_core_rw_grp4_cfg_default = 0x000006cf, + regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, + regk_bif_core_slf = 0x00000004, + regk_bif_core_wr = 0x00000001, + regk_bif_core_yes = 0x00000001 +}; +#endif /* __bif_core_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h new file mode 100644 index 000000000..b931c1aab --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h @@ -0,0 +1,473 @@ +#ifndef __bif_dma_defs_h +#define __bif_dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_dma */ + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch0_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 +#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch0_addr; +#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 +#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch0_start; +#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 +#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch0_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 +#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch0_stat; +#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch1_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 +#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch1_addr; +#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 +#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch1_start; +#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 +#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch1_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 +#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch1_stat; +#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch2_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 +#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch2_addr; +#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 +#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch2_start; +#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 +#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch2_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 +#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch2_stat; +#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch3_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 +#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch3_addr; +#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 +#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch3_start; +#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 +#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch3_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 +#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch3_stat; +#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_intr_mask; +#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 +#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_ack_intr; +#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 +#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 + +/* Register r_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_intr; +#define REG_RD_ADDR_bif_dma_r_intr 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_masked_intr; +#define REG_RD_ADDR_bif_dma_r_masked_intr 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin0_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 +#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin1_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 +#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin2_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 +#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin3_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 +#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin4_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 +#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin5_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 +#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin6_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 +#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin7_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 +#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +typedef struct { + unsigned int pin0 : 1; + unsigned int pin1 : 1; + unsigned int pin2 : 1; + unsigned int pin3 : 1; + unsigned int pin4 : 1; + unsigned int pin5 : 1; + unsigned int pin6 : 1; + unsigned int pin7 : 1; + unsigned int dummy1 : 24; +} reg_bif_dma_r_pin_stat; +#define REG_RD_ADDR_bif_dma_r_pin_stat 192 + + +/* Constants */ +enum { + regk_bif_dma_as_master = 0x00000001, + regk_bif_dma_as_slave = 0x00000001, + regk_bif_dma_burst1 = 0x00000000, + regk_bif_dma_burst8 = 0x00000001, + regk_bif_dma_bw16 = 0x00000001, + regk_bif_dma_bw32 = 0x00000002, + regk_bif_dma_bw8 = 0x00000000, + regk_bif_dma_dack = 0x00000006, + regk_bif_dma_dack_inv = 0x00000007, + regk_bif_dma_force = 0x00000001, + regk_bif_dma_hi = 0x00000003, + regk_bif_dma_inv = 0x00000003, + regk_bif_dma_lo = 0x00000002, + regk_bif_dma_master = 0x00000001, + regk_bif_dma_no = 0x00000000, + regk_bif_dma_norm = 0x00000002, + regk_bif_dma_off = 0x00000000, + regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch0_start_default = 0x00000000, + regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch1_start_default = 0x00000000, + regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch2_start_default = 0x00000000, + regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch3_start_default = 0x00000000, + regk_bif_dma_rw_intr_mask_default = 0x00000000, + regk_bif_dma_rw_pin0_cfg_default = 0x00000000, + regk_bif_dma_rw_pin1_cfg_default = 0x00000000, + regk_bif_dma_rw_pin2_cfg_default = 0x00000000, + regk_bif_dma_rw_pin3_cfg_default = 0x00000000, + regk_bif_dma_rw_pin4_cfg_default = 0x00000000, + regk_bif_dma_rw_pin5_cfg_default = 0x00000000, + regk_bif_dma_rw_pin6_cfg_default = 0x00000000, + regk_bif_dma_rw_pin7_cfg_default = 0x00000000, + regk_bif_dma_slave = 0x00000002, + regk_bif_dma_sreq = 0x00000006, + regk_bif_dma_sreq_inv = 0x00000007, + regk_bif_dma_tc = 0x00000004, + regk_bif_dma_tc_inv = 0x00000005, + regk_bif_dma_yes = 0x00000001 +}; +#endif /* __bif_dma_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h new file mode 100644 index 000000000..d18fc3c9f --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_h +#define __bif_slave_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_slave */ + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int slave_id : 3; + unsigned int use_slave_id : 1; + unsigned int boot_rdy : 1; + unsigned int loopback : 1; + unsigned int dis : 1; + unsigned int dummy1 : 25; +} reg_bif_slave_rw_slave_cfg; +#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 +#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +typedef struct { + unsigned int ch0_mode : 1; + unsigned int ch1_mode : 1; + unsigned int ch2_mode : 1; + unsigned int ch3_mode : 1; + unsigned int dummy1 : 28; +} reg_bif_slave_r_slave_mode; +#define REG_RD_ADDR_bif_slave_r_slave_mode 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch0_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 +#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch1_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 +#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch2_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 +#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch3_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 +#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int brin_mode : 1; + unsigned int brout_mode : 3; + unsigned int bg_mode : 3; + unsigned int release : 2; + unsigned int acquire : 1; + unsigned int settle_time : 2; + unsigned int dram_ctrl : 1; + unsigned int dummy1 : 19; +} reg_bif_slave_rw_arb_cfg; +#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 +#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +typedef struct { + unsigned int init_mode : 1; + unsigned int mode : 1; + unsigned int brin : 1; + unsigned int brout : 1; + unsigned int bg : 1; + unsigned int dummy1 : 27; +} reg_bif_slave_r_arb_stat; +#define REG_RD_ADDR_bif_slave_r_arb_stat 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_intr_mask; +#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 +#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_ack_intr; +#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 +#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 + +/* Register r_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_intr; +#define REG_RD_ADDR_bif_slave_r_intr 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_masked_intr; +#define REG_RD_ADDR_bif_slave_r_masked_intr 76 + + +/* Constants */ +enum { + regk_bif_slave_active_hi = 0x00000003, + regk_bif_slave_active_lo = 0x00000002, + regk_bif_slave_addr = 0x00000000, + regk_bif_slave_always = 0x00000001, + regk_bif_slave_at_idle = 0x00000002, + regk_bif_slave_burst_end = 0x00000003, + regk_bif_slave_dma = 0x00000001, + regk_bif_slave_hi = 0x00000003, + regk_bif_slave_inv = 0x00000001, + regk_bif_slave_lo = 0x00000002, + regk_bif_slave_local = 0x00000001, + regk_bif_slave_master = 0x00000000, + regk_bif_slave_mode_reg = 0x00000001, + regk_bif_slave_no = 0x00000000, + regk_bif_slave_norm = 0x00000000, + regk_bif_slave_on_access = 0x00000000, + regk_bif_slave_rw_arb_cfg_default = 0x00000000, + regk_bif_slave_rw_ch0_cfg_default = 0x00000000, + regk_bif_slave_rw_ch1_cfg_default = 0x00000000, + regk_bif_slave_rw_ch2_cfg_default = 0x00000000, + regk_bif_slave_rw_ch3_cfg_default = 0x00000000, + regk_bif_slave_rw_intr_mask_default = 0x00000000, + regk_bif_slave_rw_slave_cfg_default = 0x00000000, + regk_bif_slave_shared = 0x00000000, + regk_bif_slave_slave = 0x00000001, + regk_bif_slave_t0ns = 0x00000003, + regk_bif_slave_t10ns = 0x00000002, + regk_bif_slave_t20ns = 0x00000003, + regk_bif_slave_t30ns = 0x00000002, + regk_bif_slave_t40ns = 0x00000001, + regk_bif_slave_t50ns = 0x00000000, + regk_bif_slave_yes = 0x00000001, + regk_bif_slave_z = 0x00000004 +}; +#endif /* __bif_slave_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/config_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/config_defs.h new file mode 100644 index 000000000..45457a4e3 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/config_defs.h @@ -0,0 +1,142 @@ +#ifndef __config_defs_h +#define __config_defs_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r + * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope config */ + +/* Register r_bootsel, scope config, type r */ +typedef struct { + unsigned int boot_mode : 3; + unsigned int full_duplex : 1; + unsigned int user : 1; + unsigned int pll : 1; + unsigned int flash_bw : 1; + unsigned int dummy1 : 25; +} reg_config_r_bootsel; +#define REG_RD_ADDR_config_r_bootsel 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop : 1; + unsigned int dma01_eth0 : 1; + unsigned int dma23 : 1; + unsigned int dma45 : 1; + unsigned int dma67 : 1; + unsigned int dma89_strcop : 1; + unsigned int bif : 1; + unsigned int fix_io : 1; + unsigned int dummy1 : 22; +} reg_config_rw_clk_ctrl; +#define REG_RD_ADDR_config_rw_clk_ctrl 4 +#define REG_WR_ADDR_config_rw_clk_ctrl 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +typedef struct { + unsigned int usb_susp : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 30; +} reg_config_rw_pad_ctrl; +#define REG_RD_ADDR_config_rw_pad_ctrl 8 +#define REG_WR_ADDR_config_rw_pad_ctrl 8 + + +/* Constants */ +enum { + regk_config_bw16 = 0x00000000, + regk_config_bw32 = 0x00000001, + regk_config_master = 0x00000005, + regk_config_nand = 0x00000003, + regk_config_net_rx = 0x00000001, + regk_config_net_tx_rx = 0x00000002, + regk_config_no = 0x00000000, + regk_config_none = 0x00000007, + regk_config_nor = 0x00000000, + regk_config_rw_clk_ctrl_default = 0x00000002, + regk_config_rw_pad_ctrl_default = 0x00000000, + regk_config_ser = 0x00000004, + regk_config_slave = 0x00000006, + regk_config_yes = 0x00000001 +}; +#endif /* __config_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h new file mode 100644 index 000000000..8370aee8a --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/crisp/doc/cpu_vect.r +version . */ + +#ifndef _______INST_CRISP_DOC_CPU_VECT_R +#define _______INST_CRISP_DOC_CPU_VECT_R +#define NMI_INTR_VECT 0x00 +#define RESERVED_1_INTR_VECT 0x01 +#define RESERVED_2_INTR_VECT 0x02 +#define SINGLE_STEP_INTR_VECT 0x03 +#define INSTR_TLB_REFILL_INTR_VECT 0x04 +#define INSTR_TLB_INV_INTR_VECT 0x05 +#define INSTR_TLB_ACC_INTR_VECT 0x06 +#define TLB_EX_INTR_VECT 0x07 +#define DATA_TLB_REFILL_INTR_VECT 0x08 +#define DATA_TLB_INV_INTR_VECT 0x09 +#define DATA_TLB_ACC_INTR_VECT 0x0a +#define DATA_TLB_WE_INTR_VECT 0x0b +#define HW_BP_INTR_VECT 0x0c +#define RESERVED_D_INTR_VECT 0x0d +#define RESERVED_E_INTR_VECT 0x0e +#define RESERVED_F_INTR_VECT 0x0f +#define BREAK_0_INTR_VECT 0x10 +#define BREAK_1_INTR_VECT 0x11 +#define BREAK_2_INTR_VECT 0x12 +#define BREAK_3_INTR_VECT 0x13 +#define BREAK_4_INTR_VECT 0x14 +#define BREAK_5_INTR_VECT 0x15 +#define BREAK_6_INTR_VECT 0x16 +#define BREAK_7_INTR_VECT 0x17 +#define BREAK_8_INTR_VECT 0x18 +#define BREAK_9_INTR_VECT 0x19 +#define BREAK_10_INTR_VECT 0x1a +#define BREAK_11_INTR_VECT 0x1b +#define BREAK_12_INTR_VECT 0x1c +#define BREAK_13_INTR_VECT 0x1d +#define BREAK_14_INTR_VECT 0x1e +#define BREAK_15_INTR_VECT 0x1f +#define MULTIPLE_INTR_VECT 0x30 + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/dma.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/dma.h new file mode 100644 index 000000000..52bf67907 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/dma.h @@ -0,0 +1,127 @@ +/* + * DMA C definitions and help macros + * + */ + +#ifndef dma_h +#define dma_h + +/* registers */ /* Really needed, since both are listed in sw.list? */ +#include + + +/* descriptors */ + +// ------------------------------------------------------------ dma_descr_group +typedef struct dma_descr_group { + struct dma_descr_group *next; + unsigned eol : 1; + unsigned tol : 1; + unsigned bol : 1; + unsigned : 1; + unsigned intr : 1; + unsigned : 2; + unsigned en : 1; + unsigned : 7; + unsigned dis : 1; + unsigned md : 16; + struct dma_descr_group *up; + union { + struct dma_descr_context *context; + struct dma_descr_group *group; + } down; +} dma_descr_group; + +// ---------------------------------------------------------- dma_descr_context +typedef struct dma_descr_context { + struct dma_descr_context *next; + unsigned eol : 1; + unsigned : 3; + unsigned intr : 1; + unsigned : 1; + unsigned store_mode : 1; + unsigned en : 1; + unsigned : 7; + unsigned dis : 1; + unsigned md0 : 16; + unsigned md1; + unsigned md2; + unsigned md3; + unsigned md4; + struct dma_descr_data *saved_data; + char *saved_data_buf; +} dma_descr_context; + +// ------------------------------------------------------------- dma_descr_data +typedef struct dma_descr_data { + struct dma_descr_data *next; + char *buf; + unsigned eol : 1; + unsigned : 2; + unsigned out_eop : 1; + unsigned intr : 1; + unsigned wait : 1; + unsigned : 2; + unsigned : 3; + unsigned in_eop : 1; + unsigned : 4; + unsigned md : 16; + char *after; +} dma_descr_data; + +// --------------------------------------------------------------------- macros + +// enable DMA channel +#define DMA_ENABLE( inst ) \ + do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ + e.en = regk_dma_yes; \ + REG_WR( dma, inst, rw_cfg, e); } while( 0 ) + +// reset DMA channel +#define DMA_RESET( inst ) \ + do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ + r.en = regk_dma_no; \ + REG_WR( dma, inst, rw_cfg, r); } while( 0 ) + +// stop DMA channel +#define DMA_STOP( inst ) \ + do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ + s.stop = regk_dma_yes; \ + REG_WR( dma, inst, rw_cfg, s); } while( 0 ) + +// continue DMA channel operation +#define DMA_CONTINUE( inst ) \ + do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ + c.stop = regk_dma_no; \ + REG_WR( dma, inst, rw_cfg, c); } while( 0 ) + +// give stream command +#define DMA_WR_CMD( inst, cmd_par ) \ + do { reg_dma_rw_stream_cmd __x = {0}; \ + do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \ + __x.cmd = (cmd_par); \ + REG_WR(dma, inst, rw_stream_cmd, __x); \ + } while (0) + +// load: g,c,d:burst +#define DMA_START_GROUP( inst, group_descr ) \ + do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ + DMA_WR_CMD( inst, regk_dma_load_g ); \ + DMA_WR_CMD( inst, regk_dma_load_c ); \ + DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ + } while( 0 ) + +// load: c,d:burst +#define DMA_START_CONTEXT( inst, ctx_descr ) \ + do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ + DMA_WR_CMD( inst, regk_dma_load_c ); \ + DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ + } while( 0 ) + +// if the DMA is at the end of the data list, the last data descr is reloaded +#define DMA_CONTINUE_DATA( inst ) \ +do { reg_dma_rw_cmd c = {0}; \ + c.cont_data = regk_dma_yes;\ + REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h new file mode 100644 index 000000000..48ac8cef7 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h @@ -0,0 +1,436 @@ +#ifndef __dma_defs_h +#define __dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp + * last modfied: Mon Apr 11 16:06:51 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r + * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope dma */ + +/* Register rw_data, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data; +#define REG_RD_ADDR_dma_rw_data 0 +#define REG_WR_ADDR_dma_rw_data 0 + +/* Register rw_data_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_next; +#define REG_RD_ADDR_dma_rw_data_next 4 +#define REG_WR_ADDR_dma_rw_data_next 4 + +/* Register rw_data_buf, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_buf; +#define REG_RD_ADDR_dma_rw_data_buf 8 +#define REG_WR_ADDR_dma_rw_data_buf 8 + +/* Register rw_data_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int dummy1 : 2; + unsigned int out_eop : 1; + unsigned int intr : 1; + unsigned int wait : 1; + unsigned int dummy2 : 26; +} reg_dma_rw_data_ctrl; +#define REG_RD_ADDR_dma_rw_data_ctrl 12 +#define REG_WR_ADDR_dma_rw_data_ctrl 12 + +/* Register rw_data_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 3; + unsigned int in_eop : 1; + unsigned int dummy2 : 28; +} reg_dma_rw_data_stat; +#define REG_RD_ADDR_dma_rw_data_stat 16 +#define REG_WR_ADDR_dma_rw_data_stat 16 + +/* Register rw_data_md, scope dma, type rw */ +typedef struct { + unsigned int md : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_data_md; +#define REG_RD_ADDR_dma_rw_data_md 20 +#define REG_WR_ADDR_dma_rw_data_md 20 + +/* Register rw_data_md_s, scope dma, type rw */ +typedef struct { + unsigned int md_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_data_md_s; +#define REG_RD_ADDR_dma_rw_data_md_s 24 +#define REG_WR_ADDR_dma_rw_data_md_s 24 + +/* Register rw_data_after, scope dma, type rw */ +typedef unsigned int reg_dma_rw_data_after; +#define REG_RD_ADDR_dma_rw_data_after 28 +#define REG_WR_ADDR_dma_rw_data_after 28 + +/* Register rw_ctxt, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt; +#define REG_RD_ADDR_dma_rw_ctxt 32 +#define REG_WR_ADDR_dma_rw_ctxt 32 + +/* Register rw_ctxt_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_next; +#define REG_RD_ADDR_dma_rw_ctxt_next 36 +#define REG_WR_ADDR_dma_rw_ctxt_next 36 + +/* Register rw_ctxt_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int dummy1 : 3; + unsigned int intr : 1; + unsigned int dummy2 : 1; + unsigned int store_mode : 1; + unsigned int en : 1; + unsigned int dummy3 : 24; +} reg_dma_rw_ctxt_ctrl; +#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 +#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 + +/* Register rw_ctxt_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int dis : 1; + unsigned int dummy2 : 24; +} reg_dma_rw_ctxt_stat; +#define REG_RD_ADDR_dma_rw_ctxt_stat 44 +#define REG_WR_ADDR_dma_rw_ctxt_stat 44 + +/* Register rw_ctxt_md0, scope dma, type rw */ +typedef struct { + unsigned int md0 : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_ctxt_md0; +#define REG_RD_ADDR_dma_rw_ctxt_md0 48 +#define REG_WR_ADDR_dma_rw_ctxt_md0 48 + +/* Register rw_ctxt_md0_s, scope dma, type rw */ +typedef struct { + unsigned int md0_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_ctxt_md0_s; +#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 +#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 + +/* Register rw_ctxt_md1, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md1; +#define REG_RD_ADDR_dma_rw_ctxt_md1 56 +#define REG_WR_ADDR_dma_rw_ctxt_md1 56 + +/* Register rw_ctxt_md1_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md1_s; +#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 +#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 + +/* Register rw_ctxt_md2, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md2; +#define REG_RD_ADDR_dma_rw_ctxt_md2 64 +#define REG_WR_ADDR_dma_rw_ctxt_md2 64 + +/* Register rw_ctxt_md2_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md2_s; +#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 +#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 + +/* Register rw_ctxt_md3, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md3; +#define REG_RD_ADDR_dma_rw_ctxt_md3 72 +#define REG_WR_ADDR_dma_rw_ctxt_md3 72 + +/* Register rw_ctxt_md3_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md3_s; +#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 +#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 + +/* Register rw_ctxt_md4, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md4; +#define REG_RD_ADDR_dma_rw_ctxt_md4 80 +#define REG_WR_ADDR_dma_rw_ctxt_md4 80 + +/* Register rw_ctxt_md4_s, scope dma, type rw */ +typedef unsigned int reg_dma_rw_ctxt_md4_s; +#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 +#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 + +/* Register rw_saved_data, scope dma, type rw */ +typedef unsigned int reg_dma_rw_saved_data; +#define REG_RD_ADDR_dma_rw_saved_data 88 +#define REG_WR_ADDR_dma_rw_saved_data 88 + +/* Register rw_saved_data_buf, scope dma, type rw */ +typedef unsigned int reg_dma_rw_saved_data_buf; +#define REG_RD_ADDR_dma_rw_saved_data_buf 92 +#define REG_WR_ADDR_dma_rw_saved_data_buf 92 + +/* Register rw_group, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group; +#define REG_RD_ADDR_dma_rw_group 96 +#define REG_WR_ADDR_dma_rw_group 96 + +/* Register rw_group_next, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_next; +#define REG_RD_ADDR_dma_rw_group_next 100 +#define REG_WR_ADDR_dma_rw_group_next 100 + +/* Register rw_group_ctrl, scope dma, type rw */ +typedef struct { + unsigned int eol : 1; + unsigned int tol : 1; + unsigned int bol : 1; + unsigned int dummy1 : 1; + unsigned int intr : 1; + unsigned int dummy2 : 2; + unsigned int en : 1; + unsigned int dummy3 : 24; +} reg_dma_rw_group_ctrl; +#define REG_RD_ADDR_dma_rw_group_ctrl 104 +#define REG_WR_ADDR_dma_rw_group_ctrl 104 + +/* Register rw_group_stat, scope dma, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int dis : 1; + unsigned int dummy2 : 24; +} reg_dma_rw_group_stat; +#define REG_RD_ADDR_dma_rw_group_stat 108 +#define REG_WR_ADDR_dma_rw_group_stat 108 + +/* Register rw_group_md, scope dma, type rw */ +typedef struct { + unsigned int md : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_group_md; +#define REG_RD_ADDR_dma_rw_group_md 112 +#define REG_WR_ADDR_dma_rw_group_md 112 + +/* Register rw_group_md_s, scope dma, type rw */ +typedef struct { + unsigned int md_s : 16; + unsigned int dummy1 : 16; +} reg_dma_rw_group_md_s; +#define REG_RD_ADDR_dma_rw_group_md_s 116 +#define REG_WR_ADDR_dma_rw_group_md_s 116 + +/* Register rw_group_up, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_up; +#define REG_RD_ADDR_dma_rw_group_up 120 +#define REG_WR_ADDR_dma_rw_group_up 120 + +/* Register rw_group_down, scope dma, type rw */ +typedef unsigned int reg_dma_rw_group_down; +#define REG_RD_ADDR_dma_rw_group_down 124 +#define REG_WR_ADDR_dma_rw_group_down 124 + +/* Register rw_cmd, scope dma, type rw */ +typedef struct { + unsigned int cont_data : 1; + unsigned int dummy1 : 31; +} reg_dma_rw_cmd; +#define REG_RD_ADDR_dma_rw_cmd 128 +#define REG_WR_ADDR_dma_rw_cmd 128 + +/* Register rw_cfg, scope dma, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int stop : 1; + unsigned int dummy1 : 30; +} reg_dma_rw_cfg; +#define REG_RD_ADDR_dma_rw_cfg 132 +#define REG_WR_ADDR_dma_rw_cfg 132 + +/* Register rw_stat, scope dma, type rw */ +typedef struct { + unsigned int mode : 5; + unsigned int list_state : 3; + unsigned int stream_cmd_src : 8; + unsigned int dummy1 : 8; + unsigned int buf : 8; +} reg_dma_rw_stat; +#define REG_RD_ADDR_dma_rw_stat 136 +#define REG_WR_ADDR_dma_rw_stat 136 + +/* Register rw_intr_mask, scope dma, type rw */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_rw_intr_mask; +#define REG_RD_ADDR_dma_rw_intr_mask 140 +#define REG_WR_ADDR_dma_rw_intr_mask 140 + +/* Register rw_ack_intr, scope dma, type rw */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_rw_ack_intr; +#define REG_RD_ADDR_dma_rw_ack_intr 144 +#define REG_WR_ADDR_dma_rw_ack_intr 144 + +/* Register r_intr, scope dma, type r */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_r_intr; +#define REG_RD_ADDR_dma_r_intr 148 + +/* Register r_masked_intr, scope dma, type r */ +typedef struct { + unsigned int group : 1; + unsigned int ctxt : 1; + unsigned int data : 1; + unsigned int in_eop : 1; + unsigned int stream_cmd : 1; + unsigned int dummy1 : 27; +} reg_dma_r_masked_intr; +#define REG_RD_ADDR_dma_r_masked_intr 152 + +/* Register rw_stream_cmd, scope dma, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 7; + unsigned int busy : 1; +} reg_dma_rw_stream_cmd; +#define REG_RD_ADDR_dma_rw_stream_cmd 156 +#define REG_WR_ADDR_dma_rw_stream_cmd 156 + + +/* Constants */ +enum { + regk_dma_ack_pkt = 0x00000100, + regk_dma_anytime = 0x00000001, + regk_dma_array = 0x00000008, + regk_dma_burst = 0x00000020, + regk_dma_client = 0x00000002, + regk_dma_copy_next = 0x00000010, + regk_dma_copy_up = 0x00000020, + regk_dma_data_at_eol = 0x00000001, + regk_dma_dis_c = 0x00000010, + regk_dma_dis_g = 0x00000020, + regk_dma_idle = 0x00000001, + regk_dma_intern = 0x00000004, + regk_dma_load_c = 0x00000200, + regk_dma_load_c_n = 0x00000280, + regk_dma_load_c_next = 0x00000240, + regk_dma_load_d = 0x00000140, + regk_dma_load_g = 0x00000300, + regk_dma_load_g_down = 0x000003c0, + regk_dma_load_g_next = 0x00000340, + regk_dma_load_g_up = 0x00000380, + regk_dma_next_en = 0x00000010, + regk_dma_next_pkt = 0x00000010, + regk_dma_no = 0x00000000, + regk_dma_only_at_wait = 0x00000000, + regk_dma_restore = 0x00000020, + regk_dma_rst = 0x00000001, + regk_dma_running = 0x00000004, + regk_dma_rw_cfg_default = 0x00000000, + regk_dma_rw_cmd_default = 0x00000000, + regk_dma_rw_intr_mask_default = 0x00000000, + regk_dma_rw_stat_default = 0x00000101, + regk_dma_rw_stream_cmd_default = 0x00000000, + regk_dma_save_down = 0x00000020, + regk_dma_save_up = 0x00000020, + regk_dma_set_reg = 0x00000050, + regk_dma_set_w_size1 = 0x00000190, + regk_dma_set_w_size2 = 0x000001a0, + regk_dma_set_w_size4 = 0x000001c0, + regk_dma_stopped = 0x00000002, + regk_dma_store_c = 0x00000002, + regk_dma_store_descr = 0x00000000, + regk_dma_store_g = 0x00000004, + regk_dma_store_md = 0x00000001, + regk_dma_sw = 0x00000008, + regk_dma_update_down = 0x00000020, + regk_dma_yes = 0x00000001 +}; +#endif /* __dma_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h new file mode 100644 index 000000000..90fe8a288 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h @@ -0,0 +1,378 @@ +#ifndef __eth_defs_h +#define __eth_defs_h + +/* + * This file is autogenerated from + * file: eth.r + * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp + * last modfied: Mon Jan 9 06:06:41 2006 + * + * by /n/asic/design/tools/rdesc/rdes2c eth.r + * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope eth */ + +/* Register rw_ma0_lo, scope eth, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_eth_rw_ma0_lo; +#define REG_RD_ADDR_eth_rw_ma0_lo 0 +#define REG_WR_ADDR_eth_rw_ma0_lo 0 + +/* Register rw_ma0_hi, scope eth, type rw */ +typedef struct { + unsigned int addr : 16; + unsigned int dummy1 : 16; +} reg_eth_rw_ma0_hi; +#define REG_RD_ADDR_eth_rw_ma0_hi 4 +#define REG_WR_ADDR_eth_rw_ma0_hi 4 + +/* Register rw_ma1_lo, scope eth, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_eth_rw_ma1_lo; +#define REG_RD_ADDR_eth_rw_ma1_lo 8 +#define REG_WR_ADDR_eth_rw_ma1_lo 8 + +/* Register rw_ma1_hi, scope eth, type rw */ +typedef struct { + unsigned int addr : 16; + unsigned int dummy1 : 16; +} reg_eth_rw_ma1_hi; +#define REG_RD_ADDR_eth_rw_ma1_hi 12 +#define REG_WR_ADDR_eth_rw_ma1_hi 12 + +/* Register rw_ga_lo, scope eth, type rw */ +typedef struct { + unsigned int tbl : 32; +} reg_eth_rw_ga_lo; +#define REG_RD_ADDR_eth_rw_ga_lo 16 +#define REG_WR_ADDR_eth_rw_ga_lo 16 + +/* Register rw_ga_hi, scope eth, type rw */ +typedef struct { + unsigned int tbl : 32; +} reg_eth_rw_ga_hi; +#define REG_RD_ADDR_eth_rw_ga_hi 20 +#define REG_WR_ADDR_eth_rw_ga_hi 20 + +/* Register rw_gen_ctrl, scope eth, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int phy : 2; + unsigned int protocol : 1; + unsigned int loopback : 1; + unsigned int flow_ctrl : 1; + unsigned int gtxclk_out : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 24; +} reg_eth_rw_gen_ctrl; +#define REG_RD_ADDR_eth_rw_gen_ctrl 24 +#define REG_WR_ADDR_eth_rw_gen_ctrl 24 + +/* Register rw_rec_ctrl, scope eth, type rw */ +typedef struct { + unsigned int ma0 : 1; + unsigned int ma1 : 1; + unsigned int individual : 1; + unsigned int broadcast : 1; + unsigned int undersize : 1; + unsigned int oversize : 1; + unsigned int bad_crc : 1; + unsigned int duplex : 1; + unsigned int max_size : 16; + unsigned int dummy1 : 8; +} reg_eth_rw_rec_ctrl; +#define REG_RD_ADDR_eth_rw_rec_ctrl 28 +#define REG_WR_ADDR_eth_rw_rec_ctrl 28 + +/* Register rw_tr_ctrl, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int pad : 1; + unsigned int retry : 1; + unsigned int ignore_col : 1; + unsigned int cancel : 1; + unsigned int hsh_delay : 1; + unsigned int ignore_crs : 1; + unsigned int carrier_ext : 1; + unsigned int dummy1 : 24; +} reg_eth_rw_tr_ctrl; +#define REG_RD_ADDR_eth_rw_tr_ctrl 32 +#define REG_WR_ADDR_eth_rw_tr_ctrl 32 + +/* Register rw_clr_err, scope eth, type rw */ +typedef struct { + unsigned int clr : 1; + unsigned int dummy1 : 31; +} reg_eth_rw_clr_err; +#define REG_RD_ADDR_eth_rw_clr_err 36 +#define REG_WR_ADDR_eth_rw_clr_err 36 + +/* Register rw_mgm_ctrl, scope eth, type rw */ +typedef struct { + unsigned int mdio : 1; + unsigned int mdoe : 1; + unsigned int mdc : 1; + unsigned int dummy1 : 29; +} reg_eth_rw_mgm_ctrl; +#define REG_RD_ADDR_eth_rw_mgm_ctrl 40 +#define REG_WR_ADDR_eth_rw_mgm_ctrl 40 + +/* Register r_stat, scope eth, type r */ +typedef struct { + unsigned int mdio : 1; + unsigned int exc_col : 1; + unsigned int urun : 1; + unsigned int clk_125 : 1; + unsigned int dummy1 : 28; +} reg_eth_r_stat; +#define REG_RD_ADDR_eth_r_stat 44 + +/* Register rs_rec_cnt, scope eth, type rs */ +typedef struct { + unsigned int crc_err : 8; + unsigned int align_err : 8; + unsigned int oversize : 8; + unsigned int congestion : 8; +} reg_eth_rs_rec_cnt; +#define REG_RD_ADDR_eth_rs_rec_cnt 48 + +/* Register r_rec_cnt, scope eth, type r */ +typedef struct { + unsigned int crc_err : 8; + unsigned int align_err : 8; + unsigned int oversize : 8; + unsigned int congestion : 8; +} reg_eth_r_rec_cnt; +#define REG_RD_ADDR_eth_r_rec_cnt 52 + +/* Register rs_tr_cnt, scope eth, type rs */ +typedef struct { + unsigned int single_col : 8; + unsigned int mult_col : 8; + unsigned int late_col : 8; + unsigned int deferred : 8; +} reg_eth_rs_tr_cnt; +#define REG_RD_ADDR_eth_rs_tr_cnt 56 + +/* Register r_tr_cnt, scope eth, type r */ +typedef struct { + unsigned int single_col : 8; + unsigned int mult_col : 8; + unsigned int late_col : 8; + unsigned int deferred : 8; +} reg_eth_r_tr_cnt; +#define REG_RD_ADDR_eth_r_tr_cnt 60 + +/* Register rs_phy_cnt, scope eth, type rs */ +typedef struct { + unsigned int carrier_loss : 8; + unsigned int sqe_err : 8; + unsigned int dummy1 : 16; +} reg_eth_rs_phy_cnt; +#define REG_RD_ADDR_eth_rs_phy_cnt 64 + +/* Register r_phy_cnt, scope eth, type r */ +typedef struct { + unsigned int carrier_loss : 8; + unsigned int sqe_err : 8; + unsigned int dummy1 : 16; +} reg_eth_r_phy_cnt; +#define REG_RD_ADDR_eth_r_phy_cnt 68 + +/* Register rw_test_ctrl, scope eth, type rw */ +typedef struct { + unsigned int snmp_inc : 1; + unsigned int snmp : 1; + unsigned int backoff : 1; + unsigned int dummy1 : 29; +} reg_eth_rw_test_ctrl; +#define REG_RD_ADDR_eth_rw_test_ctrl 72 +#define REG_WR_ADDR_eth_rw_test_ctrl 72 + +/* Register rw_intr_mask, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_rw_intr_mask; +#define REG_RD_ADDR_eth_rw_intr_mask 76 +#define REG_WR_ADDR_eth_rw_intr_mask 76 + +/* Register rw_ack_intr, scope eth, type rw */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_rw_ack_intr; +#define REG_RD_ADDR_eth_rw_ack_intr 80 +#define REG_WR_ADDR_eth_rw_ack_intr 80 + +/* Register r_intr, scope eth, type r */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_r_intr; +#define REG_RD_ADDR_eth_r_intr 84 + +/* Register r_masked_intr, scope eth, type r */ +typedef struct { + unsigned int crc : 1; + unsigned int align : 1; + unsigned int oversize : 1; + unsigned int congestion : 1; + unsigned int single_col : 1; + unsigned int mult_col : 1; + unsigned int late_col : 1; + unsigned int deferred : 1; + unsigned int carrier_loss : 1; + unsigned int sqe_test_err : 1; + unsigned int orun : 1; + unsigned int urun : 1; + unsigned int exc_col : 1; + unsigned int mdio : 1; + unsigned int dummy1 : 18; +} reg_eth_r_masked_intr; +#define REG_RD_ADDR_eth_r_masked_intr 88 + + +/* Constants */ +enum { + regk_eth_discard = 0x00000000, + regk_eth_ether = 0x00000000, + regk_eth_full = 0x00000001, + regk_eth_gmii = 0x00000003, + regk_eth_gtxclk = 0x00000001, + regk_eth_half = 0x00000000, + regk_eth_hsh = 0x00000001, + regk_eth_mii = 0x00000001, + regk_eth_mii_arec = 0x00000002, + regk_eth_mii_clk = 0x00000000, + regk_eth_no = 0x00000000, + regk_eth_phyrst = 0x00000000, + regk_eth_rec = 0x00000001, + regk_eth_rw_ga_hi_default = 0x00000000, + regk_eth_rw_ga_lo_default = 0x00000000, + regk_eth_rw_gen_ctrl_default = 0x00000000, + regk_eth_rw_intr_mask_default = 0x00000000, + regk_eth_rw_ma0_hi_default = 0x00000000, + regk_eth_rw_ma0_lo_default = 0x00000000, + regk_eth_rw_ma1_hi_default = 0x00000000, + regk_eth_rw_ma1_lo_default = 0x00000000, + regk_eth_rw_mgm_ctrl_default = 0x00000000, + regk_eth_rw_test_ctrl_default = 0x00000000, + regk_eth_size1518 = 0x000005ee, + regk_eth_size1522 = 0x000005f2, + regk_eth_yes = 0x00000001 +}; +#endif /* __eth_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h new file mode 100644 index 000000000..c47b5ca48 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h @@ -0,0 +1,369 @@ +#ifndef __extmem_defs_h +#define __extmem_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ext_mem/mod/extmem_regs.r + * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp + * last modfied: Tue Mar 30 22:26:21 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r + * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope extmem */ + +/* Register rw_cse0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_cse0_cfg; +#define REG_RD_ADDR_extmem_rw_cse0_cfg 0 +#define REG_WR_ADDR_extmem_rw_cse0_cfg 0 + +/* Register rw_cse1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_cse1_cfg; +#define REG_RD_ADDR_extmem_rw_cse1_cfg 4 +#define REG_WR_ADDR_extmem_rw_cse1_cfg 4 + +/* Register rw_csr0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csr0_cfg; +#define REG_RD_ADDR_extmem_rw_csr0_cfg 8 +#define REG_WR_ADDR_extmem_rw_csr0_cfg 8 + +/* Register rw_csr1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csr1_cfg; +#define REG_RD_ADDR_extmem_rw_csr1_cfg 12 +#define REG_WR_ADDR_extmem_rw_csr1_cfg 12 + +/* Register rw_csp0_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp0_cfg; +#define REG_RD_ADDR_extmem_rw_csp0_cfg 16 +#define REG_WR_ADDR_extmem_rw_csp0_cfg 16 + +/* Register rw_csp1_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp1_cfg; +#define REG_RD_ADDR_extmem_rw_csp1_cfg 20 +#define REG_WR_ADDR_extmem_rw_csp1_cfg 20 + +/* Register rw_csp2_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp2_cfg; +#define REG_RD_ADDR_extmem_rw_csp2_cfg 24 +#define REG_WR_ADDR_extmem_rw_csp2_cfg 24 + +/* Register rw_csp3_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp3_cfg; +#define REG_RD_ADDR_extmem_rw_csp3_cfg 28 +#define REG_WR_ADDR_extmem_rw_csp3_cfg 28 + +/* Register rw_csp4_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp4_cfg; +#define REG_RD_ADDR_extmem_rw_csp4_cfg 32 +#define REG_WR_ADDR_extmem_rw_csp4_cfg 32 + +/* Register rw_csp5_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp5_cfg; +#define REG_RD_ADDR_extmem_rw_csp5_cfg 36 +#define REG_WR_ADDR_extmem_rw_csp5_cfg 36 + +/* Register rw_csp6_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_csp6_cfg; +#define REG_RD_ADDR_extmem_rw_csp6_cfg 40 +#define REG_WR_ADDR_extmem_rw_csp6_cfg 40 + +/* Register rw_css_cfg, scope extmem, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int mode : 1; + unsigned int erc_en : 1; + unsigned int dummy1 : 6; + unsigned int size : 3; + unsigned int log : 1; + unsigned int en : 1; +} reg_extmem_rw_css_cfg; +#define REG_RD_ADDR_extmem_rw_css_cfg 44 +#define REG_WR_ADDR_extmem_rw_css_cfg 44 + +/* Register rw_status_handle, scope extmem, type rw */ +typedef struct { + unsigned int h : 32; +} reg_extmem_rw_status_handle; +#define REG_RD_ADDR_extmem_rw_status_handle 48 +#define REG_WR_ADDR_extmem_rw_status_handle 48 + +/* Register rw_wait_pin, scope extmem, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 15; + unsigned int start : 1; +} reg_extmem_rw_wait_pin; +#define REG_RD_ADDR_extmem_rw_wait_pin 52 +#define REG_WR_ADDR_extmem_rw_wait_pin 52 + +/* Register rw_gated_csp, scope extmem, type rw */ +typedef struct { + unsigned int dummy1 : 31; + unsigned int en : 1; +} reg_extmem_rw_gated_csp; +#define REG_RD_ADDR_extmem_rw_gated_csp 56 +#define REG_WR_ADDR_extmem_rw_gated_csp 56 + + +/* Constants */ +enum { + regk_extmem_b16 = 0x00000001, + regk_extmem_b32 = 0x00000000, + regk_extmem_bwe = 0x00000000, + regk_extmem_cwe = 0x00000001, + regk_extmem_no = 0x00000000, + regk_extmem_rw_cse0_cfg_default = 0x000006cf, + regk_extmem_rw_cse1_cfg_default = 0x000006cf, + regk_extmem_rw_csp0_cfg_default = 0x000006cf, + regk_extmem_rw_csp1_cfg_default = 0x000006cf, + regk_extmem_rw_csp2_cfg_default = 0x000006cf, + regk_extmem_rw_csp3_cfg_default = 0x000006cf, + regk_extmem_rw_csp4_cfg_default = 0x000006cf, + regk_extmem_rw_csp5_cfg_default = 0x000006cf, + regk_extmem_rw_csp6_cfg_default = 0x000006cf, + regk_extmem_rw_csr0_cfg_default = 0x000006cf, + regk_extmem_rw_csr1_cfg_default = 0x000006cf, + regk_extmem_rw_css_cfg_default = 0x000006cf, + regk_extmem_s128KB = 0x00000000, + regk_extmem_s16MB = 0x00000005, + regk_extmem_s1MB = 0x00000001, + regk_extmem_s2MB = 0x00000002, + regk_extmem_s32MB = 0x00000006, + regk_extmem_s4MB = 0x00000003, + regk_extmem_s64MB = 0x00000007, + regk_extmem_s8MB = 0x00000004, + regk_extmem_yes = 0x00000001 +}; +#endif /* __extmem_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile new file mode 100644 index 000000000..0747a22e3 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile @@ -0,0 +1,146 @@ +# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ +# Makefile to generate or copy the latest register definitions +# and related datastructures and helpermacros. +# The official place for these files is probably at: +RELEASE ?= r1_alfa5 +IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ + +IOPROCDIR = /n/asic/design/io/io_proc/rtl + +IOPROCINCL_FILES = +IOPROCINCL_FILES2= +IOPROCINCL_FILES += iop_crc_par_defs.h +IOPROCINCL_FILES += iop_dmc_in_defs.h +IOPROCINCL_FILES += iop_dmc_out_defs.h +IOPROCINCL_FILES += iop_fifo_in_defs.h +IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h +IOPROCINCL_FILES += iop_fifo_out_defs.h +IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h +IOPROCINCL_FILES += iop_mpu_defs.h +IOPROCINCL_FILES2+= iop_mpu_macros.h +IOPROCINCL_FILES2+= iop_reg_space.h +IOPROCINCL_FILES += iop_sap_in_defs.h +IOPROCINCL_FILES += iop_sap_out_defs.h +IOPROCINCL_FILES += iop_scrc_in_defs.h +IOPROCINCL_FILES += iop_scrc_out_defs.h +IOPROCINCL_FILES += iop_spu_defs.h +# in guiness/ +IOPROCINCL_FILES += iop_sw_cfg_defs.h +IOPROCINCL_FILES += iop_sw_cpu_defs.h +IOPROCINCL_FILES += iop_sw_mpu_defs.h +IOPROCINCL_FILES += iop_sw_spu_defs.h +# +IOPROCINCL_FILES += iop_timer_grp_defs.h +IOPROCINCL_FILES += iop_trigger_grp_defs.h +# in guiness/ +IOPROCINCL_FILES += iop_version_defs.h + +IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES)) +IOPROCASMINCL_FILES+= iop_reg_space_asm.h + + +IOPROCREGDESC = +IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r +#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r +IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r +IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r +IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r +IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r +IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r +IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r +IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r +IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r + + +RDES2C = /n/asic/bin/rdes2c +RDES2C = /n/asic/design/tools/rdesc/rdes2c +RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr +RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt + +## all - Just print help - you probably want to do 'make gen' +all: help + +## help - This help +help: + @grep '^## ' Makefile + +## gen - Generate include files +gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) + echo "INCL: $(IOPROCINCL_FILES)" + echo "INCL2: $(IOPROCINCL_FILES2)" + echo "ASMINCL: $(IOPROCASMINCL_FILES)" + +# From the official location... +iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ +iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h + cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ + +## copy - Copy files from official location +copy: + @echo "## Copying and fixing iop files ##" + @for HFILE in $(IOPROCINCL_FILES); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @for HFILE in $(IOPROCINCL_FILES2); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ + done + @echo "## Copying and fixing iop asm files ##" + @for HFILE in $(IOPROCASMINCL_FILES); do \ + echo " $$HFILE"; \ + cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \ + done + +# I/O processor files: +## iop - Generate I/O processor include files +iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) +iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r + $(RDES2C) $< +iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r + $(RDES2C) $< +%_defs.h: $(IOPROCDIR)/%.r + $(RDES2C) $< +%_defs_asm.h: $(IOPROCDIR)/%.r + $(RDES2C) -asm $< +iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r + $(RDES2C) -asm $< + +## doc - Generate .axw files from register description. +doc: $(IOPROCREGDESC) + for RDES in $^; do \ + $(RDES2TXT) $$RDES; \ + done + +.PHONY: axw +## %.axw - Generate the specified .axw file (doesn't work for all files +## due to inconsistent naming of .r files. +%.axw: axw + @for RDES in $(IOPROCREGDESC); do \ + if echo "$$RDES" | grep $* ; then \ + $(RDES2TXT) $$RDES; \ + fi \ + done + +.PHONY: clean +## clean - Remove .h files and .axw files. +clean: + rm -rf $(IOPROCINCL_FILES) *.axw + +.PHONY: cleandoc +## cleandoc - Remove .axw files. +cleandoc: + rm -rf *.axw + diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h new file mode 100644 index 000000000..a4b58000c --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h @@ -0,0 +1,171 @@ +#ifndef __iop_crc_par_defs_asm_h +#define __iop_crc_par_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_crc_par.r + * id: + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r + * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_cfg___mode___lsb 0 +#define reg_iop_crc_par_rw_cfg___mode___width 1 +#define reg_iop_crc_par_rw_cfg___mode___bit 0 +#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1 +#define reg_iop_crc_par_rw_cfg___crc_out___width 1 +#define reg_iop_crc_par_rw_cfg___crc_out___bit 1 +#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2 +#define reg_iop_crc_par_rw_cfg___rev_out___width 1 +#define reg_iop_crc_par_rw_cfg___rev_out___bit 2 +#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3 +#define reg_iop_crc_par_rw_cfg___inv_out___width 1 +#define reg_iop_crc_par_rw_cfg___inv_out___bit 3 +#define reg_iop_crc_par_rw_cfg___trig___lsb 4 +#define reg_iop_crc_par_rw_cfg___trig___width 2 +#define reg_iop_crc_par_rw_cfg___poly___lsb 6 +#define reg_iop_crc_par_rw_cfg___poly___width 3 +#define reg_iop_crc_par_rw_cfg_offset 0 + +/* Register rw_init_crc, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_init_crc_offset 4 + +/* Register rw_correct_crc, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_correct_crc_offset 8 + +/* Register rw_ctrl, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_ctrl___en___lsb 0 +#define reg_iop_crc_par_rw_ctrl___en___width 1 +#define reg_iop_crc_par_rw_ctrl___en___bit 0 +#define reg_iop_crc_par_rw_ctrl_offset 12 + +/* Register rw_set_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0 +#define reg_iop_crc_par_rw_set_last___tr_dif___width 1 +#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0 +#define reg_iop_crc_par_rw_set_last_offset 16 + +/* Register rw_wr1byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr1byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr1byte___data___width 8 +#define reg_iop_crc_par_rw_wr1byte_offset 20 + +/* Register rw_wr2byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr2byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr2byte___data___width 16 +#define reg_iop_crc_par_rw_wr2byte_offset 24 + +/* Register rw_wr3byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr3byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr3byte___data___width 24 +#define reg_iop_crc_par_rw_wr3byte_offset 28 + +/* Register rw_wr4byte, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr4byte___data___lsb 0 +#define reg_iop_crc_par_rw_wr4byte___data___width 32 +#define reg_iop_crc_par_rw_wr4byte_offset 32 + +/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr1byte_last___data___width 8 +#define reg_iop_crc_par_rw_wr1byte_last_offset 36 + +/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr2byte_last___data___width 16 +#define reg_iop_crc_par_rw_wr2byte_last_offset 40 + +/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr3byte_last___data___width 24 +#define reg_iop_crc_par_rw_wr3byte_last_offset 44 + +/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0 +#define reg_iop_crc_par_rw_wr4byte_last___data___width 32 +#define reg_iop_crc_par_rw_wr4byte_last_offset 48 + +/* Register r_stat, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_stat___err___lsb 0 +#define reg_iop_crc_par_r_stat___err___width 1 +#define reg_iop_crc_par_r_stat___err___bit 0 +#define reg_iop_crc_par_r_stat___busy___lsb 1 +#define reg_iop_crc_par_r_stat___busy___width 1 +#define reg_iop_crc_par_r_stat___busy___bit 1 +#define reg_iop_crc_par_r_stat_offset 52 + +/* Register r_sh_reg, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_sh_reg_offset 56 + +/* Register r_crc, scope iop_crc_par, type r */ +#define reg_iop_crc_par_r_crc_offset 60 + +/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ +#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0 +#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2 +#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64 + + +/* Constants */ +#define regk_iop_crc_par_calc 0x00000001 +#define regk_iop_crc_par_ccitt 0x00000002 +#define regk_iop_crc_par_check 0x00000000 +#define regk_iop_crc_par_crc16 0x00000001 +#define regk_iop_crc_par_crc32 0x00000000 +#define regk_iop_crc_par_crc5 0x00000003 +#define regk_iop_crc_par_crc5_11 0x00000004 +#define regk_iop_crc_par_dif_in 0x00000002 +#define regk_iop_crc_par_hi 0x00000000 +#define regk_iop_crc_par_neg 0x00000002 +#define regk_iop_crc_par_no 0x00000000 +#define regk_iop_crc_par_pos 0x00000001 +#define regk_iop_crc_par_pos_neg 0x00000003 +#define regk_iop_crc_par_rw_cfg_default 0x00000000 +#define regk_iop_crc_par_rw_ctrl_default 0x00000000 +#define regk_iop_crc_par_yes 0x00000001 +#endif /* __iop_crc_par_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h new file mode 100644 index 000000000..e7d539fec --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h @@ -0,0 +1,321 @@ +#ifndef __iop_dmc_in_defs_asm_h +#define __iop_dmc_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_in.r + * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r + * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0 +#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1 +#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3 +#define reg_iop_dmc_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0 +#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1 +#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1 +#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1 +#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2 +#define reg_iop_dmc_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_stat___dif_en___lsb 0 +#define reg_iop_dmc_in_r_stat___dif_en___width 1 +#define reg_iop_dmc_in_r_stat___dif_en___bit 0 +#define reg_iop_dmc_in_r_stat_offset 8 + +/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0 +#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10 +#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16 +#define reg_iop_dmc_in_rw_stream_cmd___n___width 8 +#define reg_iop_dmc_in_rw_stream_cmd_offset 12 + +/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_wr_data_offset 16 + +/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20 + +/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0 +#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1 +#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2 +#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3 +#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3 +#define reg_iop_dmc_in_rw_stream_ctrl_offset 24 + +/* Register r_stream_stat, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0 +#define reg_iop_dmc_in_r_stream_stat___sth___width 7 +#define reg_iop_dmc_in_r_stream_stat___full___lsb 16 +#define reg_iop_dmc_in_r_stream_stat___full___width 1 +#define reg_iop_dmc_in_r_stream_stat___full___bit 16 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1 +#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1 +#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1 +#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22 +#define reg_iop_dmc_in_r_stream_stat_offset 28 + +/* Register r_data_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_data_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_data_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_data_descr___stat___width 8 +#define reg_iop_dmc_in_r_data_descr___md___lsb 16 +#define reg_iop_dmc_in_r_data_descr___md___width 16 +#define reg_iop_dmc_in_r_data_descr_offset 32 + +/* Register r_ctxt_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8 +#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16 +#define reg_iop_dmc_in_r_ctxt_descr_offset 36 + +/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40 + +/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44 + +/* Register r_group_descr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0 +#define reg_iop_dmc_in_r_group_descr___ctrl___width 8 +#define reg_iop_dmc_in_r_group_descr___stat___lsb 8 +#define reg_iop_dmc_in_r_group_descr___stat___width 8 +#define reg_iop_dmc_in_r_group_descr___md___lsb 16 +#define reg_iop_dmc_in_r_group_descr___md___width 16 +#define reg_iop_dmc_in_r_group_descr_offset 56 + +/* Register rw_data_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_data_descr___md___lsb 16 +#define reg_iop_dmc_in_rw_data_descr___md___width 16 +#define reg_iop_dmc_in_rw_data_descr_offset 60 + +/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16 +#define reg_iop_dmc_in_rw_ctxt_descr_offset 64 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72 + +/* Register rw_group_descr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_group_descr___md___lsb 16 +#define reg_iop_dmc_in_rw_group_descr___md___width 16 +#define reg_iop_dmc_in_rw_group_descr_offset 84 + +/* Register rw_intr_mask, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0 +#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1 +#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2 +#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1 +#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1 +#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3 +#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4 +#define reg_iop_dmc_in_rw_intr_mask___sth___width 1 +#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4 +#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5 +#define reg_iop_dmc_in_rw_intr_mask___full___width 1 +#define reg_iop_dmc_in_rw_intr_mask___full___bit 5 +#define reg_iop_dmc_in_rw_intr_mask_offset 88 + +/* Register rw_ack_intr, scope iop_dmc_in, type rw */ +#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0 +#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2 +#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1 +#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4 +#define reg_iop_dmc_in_rw_ack_intr___sth___width 1 +#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4 +#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5 +#define reg_iop_dmc_in_rw_ack_intr___full___width 1 +#define reg_iop_dmc_in_rw_ack_intr___full___bit 5 +#define reg_iop_dmc_in_rw_ack_intr_offset 92 + +/* Register r_intr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_intr___data_md___lsb 0 +#define reg_iop_dmc_in_r_intr___data_md___width 1 +#define reg_iop_dmc_in_r_intr___data_md___bit 0 +#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_r_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_r_intr___group_md___lsb 2 +#define reg_iop_dmc_in_r_intr___group_md___width 1 +#define reg_iop_dmc_in_r_intr___group_md___bit 2 +#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_r_intr___sth___lsb 4 +#define reg_iop_dmc_in_r_intr___sth___width 1 +#define reg_iop_dmc_in_r_intr___sth___bit 4 +#define reg_iop_dmc_in_r_intr___full___lsb 5 +#define reg_iop_dmc_in_r_intr___full___width 1 +#define reg_iop_dmc_in_r_intr___full___bit 5 +#define reg_iop_dmc_in_r_intr_offset 96 + +/* Register r_masked_intr, scope iop_dmc_in, type r */ +#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0 +#define reg_iop_dmc_in_r_masked_intr___data_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1 +#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2 +#define reg_iop_dmc_in_r_masked_intr___group_md___width 1 +#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1 +#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4 +#define reg_iop_dmc_in_r_masked_intr___sth___width 1 +#define reg_iop_dmc_in_r_masked_intr___sth___bit 4 +#define reg_iop_dmc_in_r_masked_intr___full___lsb 5 +#define reg_iop_dmc_in_r_masked_intr___full___width 1 +#define reg_iop_dmc_in_r_masked_intr___full___bit 5 +#define reg_iop_dmc_in_r_masked_intr_offset 100 + + +/* Constants */ +#define regk_iop_dmc_in_ack_pkt 0x00000100 +#define regk_iop_dmc_in_array 0x00000008 +#define regk_iop_dmc_in_burst 0x00000020 +#define regk_iop_dmc_in_copy_next 0x00000010 +#define regk_iop_dmc_in_copy_up 0x00000020 +#define regk_iop_dmc_in_dis_c 0x00000010 +#define regk_iop_dmc_in_dis_g 0x00000020 +#define regk_iop_dmc_in_lim1 0x00000000 +#define regk_iop_dmc_in_lim16 0x00000004 +#define regk_iop_dmc_in_lim2 0x00000001 +#define regk_iop_dmc_in_lim32 0x00000005 +#define regk_iop_dmc_in_lim4 0x00000002 +#define regk_iop_dmc_in_lim64 0x00000006 +#define regk_iop_dmc_in_lim8 0x00000003 +#define regk_iop_dmc_in_load_c 0x00000200 +#define regk_iop_dmc_in_load_c_n 0x00000280 +#define regk_iop_dmc_in_load_c_next 0x00000240 +#define regk_iop_dmc_in_load_d 0x00000140 +#define regk_iop_dmc_in_load_g 0x00000300 +#define regk_iop_dmc_in_load_g_down 0x000003c0 +#define regk_iop_dmc_in_load_g_next 0x00000340 +#define regk_iop_dmc_in_load_g_up 0x00000380 +#define regk_iop_dmc_in_next_en 0x00000010 +#define regk_iop_dmc_in_next_pkt 0x00000010 +#define regk_iop_dmc_in_no 0x00000000 +#define regk_iop_dmc_in_restore 0x00000020 +#define regk_iop_dmc_in_rw_cfg_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000 +#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000 +#define regk_iop_dmc_in_rw_data_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_group_descr_default 0x00000000 +#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000 +#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000 +#define regk_iop_dmc_in_save_down 0x00000020 +#define regk_iop_dmc_in_save_up 0x00000020 +#define regk_iop_dmc_in_set_reg 0x00000050 +#define regk_iop_dmc_in_set_w_size1 0x00000190 +#define regk_iop_dmc_in_set_w_size2 0x000001a0 +#define regk_iop_dmc_in_set_w_size4 0x000001c0 +#define regk_iop_dmc_in_store_c 0x00000002 +#define regk_iop_dmc_in_store_descr 0x00000000 +#define regk_iop_dmc_in_store_g 0x00000004 +#define regk_iop_dmc_in_store_md 0x00000001 +#define regk_iop_dmc_in_update_down 0x00000020 +#define regk_iop_dmc_in_yes 0x00000001 +#endif /* __iop_dmc_in_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h new file mode 100644 index 000000000..9fe1a8054 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h @@ -0,0 +1,349 @@ +#ifndef __iop_dmc_out_defs_asm_h +#define __iop_dmc_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_out.r + * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r + * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 +#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 +#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 +#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 +#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 +#define reg_iop_dmc_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 +#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 +#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 +#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 +#define reg_iop_dmc_out_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stat___dif_en___lsb 0 +#define reg_iop_dmc_out_r_stat___dif_en___width 1 +#define reg_iop_dmc_out_r_stat___dif_en___bit 0 +#define reg_iop_dmc_out_r_stat_offset 8 + +/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 +#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 +#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 +#define reg_iop_dmc_out_rw_stream_cmd___n___width 8 +#define reg_iop_dmc_out_rw_stream_cmd_offset 12 + +/* Register rs_stream_data, scope iop_dmc_out, type rs */ +#define reg_iop_dmc_out_rs_stream_data_offset 16 + +/* Register r_stream_data, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stream_data_offset 20 + +/* Register r_stream_stat, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 +#define reg_iop_dmc_out_r_stream_stat___dth___width 7 +#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 +#define reg_iop_dmc_out_r_stream_stat___dv___width 1 +#define reg_iop_dmc_out_r_stream_stat___dv___bit 16 +#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 +#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 +#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 +#define reg_iop_dmc_out_r_stream_stat___last___lsb 18 +#define reg_iop_dmc_out_r_stream_stat___last___width 1 +#define reg_iop_dmc_out_r_stream_stat___last___bit 18 +#define reg_iop_dmc_out_r_stream_stat___size___lsb 19 +#define reg_iop_dmc_out_r_stream_stat___size___width 3 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 +#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 +#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 +#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 +#define reg_iop_dmc_out_r_stream_stat_offset 24 + +/* Register r_data_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_data_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_data_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_data_descr___stat___width 8 +#define reg_iop_dmc_out_r_data_descr___md___lsb 16 +#define reg_iop_dmc_out_r_data_descr___md___width 16 +#define reg_iop_dmc_out_r_data_descr_offset 28 + +/* Register r_ctxt_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 +#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 +#define reg_iop_dmc_out_r_ctxt_descr_offset 32 + +/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 + +/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 + +/* Register r_group_descr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 +#define reg_iop_dmc_out_r_group_descr___ctrl___width 8 +#define reg_iop_dmc_out_r_group_descr___stat___lsb 8 +#define reg_iop_dmc_out_r_group_descr___stat___width 8 +#define reg_iop_dmc_out_r_group_descr___md___lsb 16 +#define reg_iop_dmc_out_r_group_descr___md___width 16 +#define reg_iop_dmc_out_r_group_descr_offset 52 + +/* Register rw_data_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_data_descr___md___lsb 16 +#define reg_iop_dmc_out_rw_data_descr___md___width 16 +#define reg_iop_dmc_out_rw_data_descr_offset 56 + +/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 +#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 +#define reg_iop_dmc_out_rw_ctxt_descr_offset 60 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 + +/* Register rw_group_descr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_group_descr___md___lsb 16 +#define reg_iop_dmc_out_rw_group_descr___md___width 16 +#define reg_iop_dmc_out_rw_group_descr_offset 80 + +/* Register rw_intr_mask, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 +#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 +#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 +#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 +#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 +#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 +#define reg_iop_dmc_out_rw_intr_mask___dth___width 1 +#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 +#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 +#define reg_iop_dmc_out_rw_intr_mask___dv___width 1 +#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 +#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 +#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 +#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 +#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 +#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 +#define reg_iop_dmc_out_rw_intr_mask_offset 84 + +/* Register rw_ack_intr, scope iop_dmc_out, type rw */ +#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 +#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 +#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 +#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 +#define reg_iop_dmc_out_rw_ack_intr___dth___width 1 +#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 +#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 +#define reg_iop_dmc_out_rw_ack_intr___dv___width 1 +#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 +#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 +#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 +#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 +#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_rw_ack_intr_offset 88 + +/* Register r_intr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_intr___data_md___lsb 0 +#define reg_iop_dmc_out_r_intr___data_md___width 1 +#define reg_iop_dmc_out_r_intr___data_md___bit 0 +#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_r_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_r_intr___group_md___lsb 2 +#define reg_iop_dmc_out_r_intr___group_md___width 1 +#define reg_iop_dmc_out_r_intr___group_md___bit 2 +#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_r_intr___dth___lsb 4 +#define reg_iop_dmc_out_r_intr___dth___width 1 +#define reg_iop_dmc_out_r_intr___dth___bit 4 +#define reg_iop_dmc_out_r_intr___dv___lsb 5 +#define reg_iop_dmc_out_r_intr___dv___width 1 +#define reg_iop_dmc_out_r_intr___dv___bit 5 +#define reg_iop_dmc_out_r_intr___last_data___lsb 6 +#define reg_iop_dmc_out_r_intr___last_data___width 1 +#define reg_iop_dmc_out_r_intr___last_data___bit 6 +#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_r_intr___trf_lim___width 1 +#define reg_iop_dmc_out_r_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_r_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_r_intr_offset 92 + +/* Register r_masked_intr, scope iop_dmc_out, type r */ +#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 +#define reg_iop_dmc_out_r_masked_intr___data_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 +#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 +#define reg_iop_dmc_out_r_masked_intr___group_md___width 1 +#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 +#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 +#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 +#define reg_iop_dmc_out_r_masked_intr___dth___width 1 +#define reg_iop_dmc_out_r_masked_intr___dth___bit 4 +#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 +#define reg_iop_dmc_out_r_masked_intr___dv___width 1 +#define reg_iop_dmc_out_r_masked_intr___dv___bit 5 +#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 +#define reg_iop_dmc_out_r_masked_intr___last_data___width 1 +#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 +#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 +#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 +#define reg_iop_dmc_out_r_masked_intr_offset 96 + + +/* Constants */ +#define regk_iop_dmc_out_ack_pkt 0x00000100 +#define regk_iop_dmc_out_array 0x00000008 +#define regk_iop_dmc_out_burst 0x00000020 +#define regk_iop_dmc_out_copy_next 0x00000010 +#define regk_iop_dmc_out_copy_up 0x00000020 +#define regk_iop_dmc_out_dis_c 0x00000010 +#define regk_iop_dmc_out_dis_g 0x00000020 +#define regk_iop_dmc_out_lim1 0x00000000 +#define regk_iop_dmc_out_lim16 0x00000004 +#define regk_iop_dmc_out_lim2 0x00000001 +#define regk_iop_dmc_out_lim32 0x00000005 +#define regk_iop_dmc_out_lim4 0x00000002 +#define regk_iop_dmc_out_lim64 0x00000006 +#define regk_iop_dmc_out_lim8 0x00000003 +#define regk_iop_dmc_out_load_c 0x00000200 +#define regk_iop_dmc_out_load_c_n 0x00000280 +#define regk_iop_dmc_out_load_c_next 0x00000240 +#define regk_iop_dmc_out_load_d 0x00000140 +#define regk_iop_dmc_out_load_g 0x00000300 +#define regk_iop_dmc_out_load_g_down 0x000003c0 +#define regk_iop_dmc_out_load_g_next 0x00000340 +#define regk_iop_dmc_out_load_g_up 0x00000380 +#define regk_iop_dmc_out_next_en 0x00000010 +#define regk_iop_dmc_out_next_pkt 0x00000010 +#define regk_iop_dmc_out_no 0x00000000 +#define regk_iop_dmc_out_restore 0x00000020 +#define regk_iop_dmc_out_rw_cfg_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 +#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 +#define regk_iop_dmc_out_rw_data_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_group_descr_default 0x00000000 +#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 +#define regk_iop_dmc_out_save_down 0x00000020 +#define regk_iop_dmc_out_save_up 0x00000020 +#define regk_iop_dmc_out_set_reg 0x00000050 +#define regk_iop_dmc_out_set_w_size1 0x00000190 +#define regk_iop_dmc_out_set_w_size2 0x000001a0 +#define regk_iop_dmc_out_set_w_size4 0x000001c0 +#define regk_iop_dmc_out_store_c 0x00000002 +#define regk_iop_dmc_out_store_descr 0x00000000 +#define regk_iop_dmc_out_store_g 0x00000004 +#define regk_iop_dmc_out_store_md 0x00000001 +#define regk_iop_dmc_out_update_down 0x00000020 +#define regk_iop_dmc_out_yes 0x00000001 +#endif /* __iop_dmc_out_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h new file mode 100644 index 000000000..974dee082 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h @@ -0,0 +1,234 @@ +#ifndef __iop_fifo_in_defs_asm_h +#define __iop_fifo_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in.r + * id: + * last modfied: Mon Apr 11 16:10:07 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r + * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0 +#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3 +#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3 +#define reg_iop_fifo_in_rw_cfg___byte_order___width 2 +#define reg_iop_fifo_in_rw_cfg___trig___lsb 5 +#define reg_iop_fifo_in_rw_cfg___trig___width 2 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1 +#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7 +#define reg_iop_fifo_in_rw_cfg___mode___lsb 8 +#define reg_iop_fifo_in_rw_cfg___mode___width 2 +#define reg_iop_fifo_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1 +#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1 +#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1 +#define reg_iop_fifo_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_in_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_in_r_stat___last___lsb 4 +#define reg_iop_fifo_in_r_stat___last___width 8 +#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_in_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_in_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_in_r_stat_offset 8 + +/* Register rs_rd1byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd1byte___data___width 8 +#define reg_iop_fifo_in_rs_rd1byte_offset 12 + +/* Register r_rd1byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd1byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd1byte___data___width 8 +#define reg_iop_fifo_in_r_rd1byte_offset 16 + +/* Register rs_rd2byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd2byte___data___width 16 +#define reg_iop_fifo_in_rs_rd2byte_offset 20 + +/* Register r_rd2byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd2byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd2byte___data___width 16 +#define reg_iop_fifo_in_r_rd2byte_offset 24 + +/* Register rs_rd3byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd3byte___data___width 24 +#define reg_iop_fifo_in_rs_rd3byte_offset 28 + +/* Register r_rd3byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd3byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd3byte___data___width 24 +#define reg_iop_fifo_in_r_rd3byte_offset 32 + +/* Register rs_rd4byte, scope iop_fifo_in, type rs */ +#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0 +#define reg_iop_fifo_in_rs_rd4byte___data___width 32 +#define reg_iop_fifo_in_rs_rd4byte_offset 36 + +/* Register r_rd4byte, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_rd4byte___data___lsb 0 +#define reg_iop_fifo_in_r_rd4byte___data___width 32 +#define reg_iop_fifo_in_r_rd4byte_offset 40 + +/* Register rw_set_last, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_set_last_offset 44 + +/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0 +#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2 +#define reg_iop_fifo_in_rw_strb_dif_in_offset 48 + +/* Register rw_intr_mask, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_in_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_in_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3 +#define reg_iop_fifo_in_rw_intr_mask___avail___width 1 +#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3 +#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_in_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_in_rw_intr_mask_offset 52 + +/* Register rw_ack_intr, scope iop_fifo_in, type rw */ +#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_in_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_in_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3 +#define reg_iop_fifo_in_rw_ack_intr___avail___width 1 +#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3 +#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_in_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_in_rw_ack_intr_offset 56 + +/* Register r_intr, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_intr___urun___lsb 0 +#define reg_iop_fifo_in_r_intr___urun___width 1 +#define reg_iop_fifo_in_r_intr___urun___bit 0 +#define reg_iop_fifo_in_r_intr___last_data___lsb 1 +#define reg_iop_fifo_in_r_intr___last_data___width 1 +#define reg_iop_fifo_in_r_intr___last_data___bit 1 +#define reg_iop_fifo_in_r_intr___dav___lsb 2 +#define reg_iop_fifo_in_r_intr___dav___width 1 +#define reg_iop_fifo_in_r_intr___dav___bit 2 +#define reg_iop_fifo_in_r_intr___avail___lsb 3 +#define reg_iop_fifo_in_r_intr___avail___width 1 +#define reg_iop_fifo_in_r_intr___avail___bit 3 +#define reg_iop_fifo_in_r_intr___orun___lsb 4 +#define reg_iop_fifo_in_r_intr___orun___width 1 +#define reg_iop_fifo_in_r_intr___orun___bit 4 +#define reg_iop_fifo_in_r_intr_offset 60 + +/* Register r_masked_intr, scope iop_fifo_in, type r */ +#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_in_r_masked_intr___urun___width 1 +#define reg_iop_fifo_in_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_in_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_in_r_masked_intr___dav___width 1 +#define reg_iop_fifo_in_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3 +#define reg_iop_fifo_in_r_masked_intr___avail___width 1 +#define reg_iop_fifo_in_r_masked_intr___avail___bit 3 +#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_in_r_masked_intr___orun___width 1 +#define reg_iop_fifo_in_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_in_r_masked_intr_offset 64 + + +/* Constants */ +#define regk_iop_fifo_in_dif_in 0x00000002 +#define regk_iop_fifo_in_hi 0x00000000 +#define regk_iop_fifo_in_neg 0x00000002 +#define regk_iop_fifo_in_no 0x00000000 +#define regk_iop_fifo_in_order16 0x00000001 +#define regk_iop_fifo_in_order24 0x00000002 +#define regk_iop_fifo_in_order32 0x00000003 +#define regk_iop_fifo_in_order8 0x00000000 +#define regk_iop_fifo_in_pos 0x00000001 +#define regk_iop_fifo_in_pos_neg 0x00000003 +#define regk_iop_fifo_in_rw_cfg_default 0x00000024 +#define regk_iop_fifo_in_rw_ctrl_default 0x00000000 +#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_in_rw_set_last_default 0x00000000 +#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000 +#define regk_iop_fifo_in_size16 0x00000002 +#define regk_iop_fifo_in_size24 0x00000001 +#define regk_iop_fifo_in_size32 0x00000000 +#define regk_iop_fifo_in_size8 0x00000003 +#define regk_iop_fifo_in_yes 0x00000001 +#endif /* __iop_fifo_in_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h new file mode 100644 index 000000000..e00fab0c9 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h @@ -0,0 +1,155 @@ +#ifndef __iop_fifo_in_extra_defs_asm_h +#define __iop_fifo_in_extra_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: + * last modfied: Mon Apr 11 16:10:08 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_wr_data_offset 0 + +/* Register r_stat, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_in_extra_r_stat___last___lsb 4 +#define reg_iop_fifo_in_extra_r_stat___last___width 8 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_in_extra_r_stat_offset 4 + +/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0 +#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2 +#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8 + +/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12 + +/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16 + +/* Register r_intr, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_r_intr___urun___width 1 +#define reg_iop_fifo_in_extra_r_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_r_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_r_intr___dav___width 1 +#define reg_iop_fifo_in_extra_r_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_r_intr___avail___width 1 +#define reg_iop_fifo_in_extra_r_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_r_intr___orun___width 1 +#define reg_iop_fifo_in_extra_r_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_r_intr_offset 20 + +/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ +#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1 +#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_in_extra_r_masked_intr_offset 24 + + +/* Constants */ +#define regk_iop_fifo_in_extra_fifo_in 0x00000002 +#define regk_iop_fifo_in_extra_no 0x00000000 +#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_in_extra_yes 0x00000001 +#endif /* __iop_fifo_in_extra_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h new file mode 100644 index 000000000..9ec5f4a82 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h @@ -0,0 +1,254 @@ +#ifndef __iop_fifo_out_defs_asm_h +#define __iop_fifo_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out.r + * id: + * last modfied: Mon Apr 11 16:10:09 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r + * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 +#define reg_iop_fifo_out_rw_cfg___free_lim___width 3 +#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 +#define reg_iop_fifo_out_rw_cfg___byte_order___width 2 +#define reg_iop_fifo_out_rw_cfg___trig___lsb 5 +#define reg_iop_fifo_out_rw_cfg___trig___width 2 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 +#define reg_iop_fifo_out_rw_cfg___mode___lsb 8 +#define reg_iop_fifo_out_rw_cfg___mode___width 2 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 +#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 +#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 +#define reg_iop_fifo_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 +#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 +#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 +#define reg_iop_fifo_out_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_out_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_out_r_stat___last___lsb 4 +#define reg_iop_fifo_out_r_stat___last___width 8 +#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_out_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_out_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 +#define reg_iop_fifo_out_r_stat___zero_data_last___width 1 +#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 +#define reg_iop_fifo_out_r_stat_offset 8 + +/* Register rw_wr1byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr1byte___data___width 8 +#define reg_iop_fifo_out_rw_wr1byte_offset 12 + +/* Register rw_wr2byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr2byte___data___width 16 +#define reg_iop_fifo_out_rw_wr2byte_offset 16 + +/* Register rw_wr3byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr3byte___data___width 24 +#define reg_iop_fifo_out_rw_wr3byte_offset 20 + +/* Register rw_wr4byte, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 +#define reg_iop_fifo_out_rw_wr4byte___data___width 32 +#define reg_iop_fifo_out_rw_wr4byte_offset 24 + +/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 +#define reg_iop_fifo_out_rw_wr1byte_last_offset 28 + +/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 +#define reg_iop_fifo_out_rw_wr2byte_last_offset 32 + +/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 +#define reg_iop_fifo_out_rw_wr3byte_last_offset 36 + +/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 +#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 +#define reg_iop_fifo_out_rw_wr4byte_last_offset 40 + +/* Register rw_set_last, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_set_last_offset 44 + +/* Register rs_rd_data, scope iop_fifo_out, type rs */ +#define reg_iop_fifo_out_rs_rd_data_offset 48 + +/* Register r_rd_data, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_rd_data_offset 52 + +/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_strb_dif_out_offset 56 + +/* Register rw_intr_mask, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_out_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_out_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 +#define reg_iop_fifo_out_rw_intr_mask___free___width 1 +#define reg_iop_fifo_out_rw_intr_mask___free___bit 3 +#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_out_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_out_rw_intr_mask_offset 60 + +/* Register rw_ack_intr, scope iop_fifo_out, type rw */ +#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_out_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_out_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 +#define reg_iop_fifo_out_rw_ack_intr___free___width 1 +#define reg_iop_fifo_out_rw_ack_intr___free___bit 3 +#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_out_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_out_rw_ack_intr_offset 64 + +/* Register r_intr, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_intr___urun___lsb 0 +#define reg_iop_fifo_out_r_intr___urun___width 1 +#define reg_iop_fifo_out_r_intr___urun___bit 0 +#define reg_iop_fifo_out_r_intr___last_data___lsb 1 +#define reg_iop_fifo_out_r_intr___last_data___width 1 +#define reg_iop_fifo_out_r_intr___last_data___bit 1 +#define reg_iop_fifo_out_r_intr___dav___lsb 2 +#define reg_iop_fifo_out_r_intr___dav___width 1 +#define reg_iop_fifo_out_r_intr___dav___bit 2 +#define reg_iop_fifo_out_r_intr___free___lsb 3 +#define reg_iop_fifo_out_r_intr___free___width 1 +#define reg_iop_fifo_out_r_intr___free___bit 3 +#define reg_iop_fifo_out_r_intr___orun___lsb 4 +#define reg_iop_fifo_out_r_intr___orun___width 1 +#define reg_iop_fifo_out_r_intr___orun___bit 4 +#define reg_iop_fifo_out_r_intr_offset 68 + +/* Register r_masked_intr, scope iop_fifo_out, type r */ +#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_out_r_masked_intr___urun___width 1 +#define reg_iop_fifo_out_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_out_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_out_r_masked_intr___dav___width 1 +#define reg_iop_fifo_out_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_out_r_masked_intr___free___lsb 3 +#define reg_iop_fifo_out_r_masked_intr___free___width 1 +#define reg_iop_fifo_out_r_masked_intr___free___bit 3 +#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_out_r_masked_intr___orun___width 1 +#define reg_iop_fifo_out_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_out_r_masked_intr_offset 72 + + +/* Constants */ +#define regk_iop_fifo_out_hi 0x00000000 +#define regk_iop_fifo_out_neg 0x00000002 +#define regk_iop_fifo_out_no 0x00000000 +#define regk_iop_fifo_out_order16 0x00000001 +#define regk_iop_fifo_out_order24 0x00000002 +#define regk_iop_fifo_out_order32 0x00000003 +#define regk_iop_fifo_out_order8 0x00000000 +#define regk_iop_fifo_out_pos 0x00000001 +#define regk_iop_fifo_out_pos_neg 0x00000003 +#define regk_iop_fifo_out_rw_cfg_default 0x00000024 +#define regk_iop_fifo_out_rw_ctrl_default 0x00000000 +#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_out_rw_set_last_default 0x00000000 +#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 +#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 +#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 +#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 +#define regk_iop_fifo_out_size16 0x00000002 +#define regk_iop_fifo_out_size24 0x00000001 +#define regk_iop_fifo_out_size32 0x00000000 +#define regk_iop_fifo_out_size8 0x00000003 +#define regk_iop_fifo_out_yes 0x00000001 +#endif /* __iop_fifo_out_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h new file mode 100644 index 000000000..0f84a50cf --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h @@ -0,0 +1,158 @@ +#ifndef __iop_fifo_out_extra_defs_asm_h +#define __iop_fifo_out_extra_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: + * last modfied: Mon Apr 11 16:10:10 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ +#define reg_iop_fifo_out_extra_rs_rd_data_offset 0 + +/* Register r_rd_data, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_rd_data_offset 4 + +/* Register r_stat, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0 +#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4 +#define reg_iop_fifo_out_extra_r_stat___last___lsb 4 +#define reg_iop_fifo_out_extra_r_stat___last___width 8 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1 +#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1 +#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1 +#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14 +#define reg_iop_fifo_out_extra_r_stat_offset 8 + +/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12 + +/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0 +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1 +#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4 +#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1 +#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20 + +/* Register r_intr, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_r_intr___urun___width 1 +#define reg_iop_fifo_out_extra_r_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_r_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_r_intr___dav___width 1 +#define reg_iop_fifo_out_extra_r_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_r_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_r_intr___free___width 1 +#define reg_iop_fifo_out_extra_r_intr___free___bit 3 +#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_r_intr___orun___width 1 +#define reg_iop_fifo_out_extra_r_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_r_intr_offset 24 + +/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ +#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0 +#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2 +#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3 +#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1 +#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4 +#define reg_iop_fifo_out_extra_r_masked_intr_offset 28 + + +/* Constants */ +#define regk_iop_fifo_out_extra_no 0x00000000 +#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000 +#define regk_iop_fifo_out_extra_yes 0x00000001 +#endif /* __iop_fifo_out_extra_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h new file mode 100644 index 000000000..80490c82c --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h @@ -0,0 +1,177 @@ +#ifndef __iop_mpu_defs_asm_h +#define __iop_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_mpu.r + * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r + * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_mpu_rw_r 4 +/* Register rw_r, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_r_offset 0 + +/* Register rw_ctrl, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_ctrl___en___lsb 0 +#define reg_iop_mpu_rw_ctrl___en___width 1 +#define reg_iop_mpu_rw_ctrl___en___bit 0 +#define reg_iop_mpu_rw_ctrl_offset 128 + +/* Register r_pc, scope iop_mpu, type r */ +#define reg_iop_mpu_r_pc___addr___lsb 0 +#define reg_iop_mpu_r_pc___addr___width 12 +#define reg_iop_mpu_r_pc_offset 132 + +/* Register r_stat, scope iop_mpu, type r */ +#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0 +#define reg_iop_mpu_r_stat___instr_reg_busy___width 1 +#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0 +#define reg_iop_mpu_r_stat___intr_busy___lsb 1 +#define reg_iop_mpu_r_stat___intr_busy___width 1 +#define reg_iop_mpu_r_stat___intr_busy___bit 1 +#define reg_iop_mpu_r_stat___intr_vect___lsb 2 +#define reg_iop_mpu_r_stat___intr_vect___width 16 +#define reg_iop_mpu_r_stat_offset 136 + +/* Register rw_instr, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_instr_offset 140 + +/* Register rw_immediate, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_immediate_offset 144 + +/* Register r_trace, scope iop_mpu, type r */ +#define reg_iop_mpu_r_trace___intr_vect___lsb 0 +#define reg_iop_mpu_r_trace___intr_vect___width 16 +#define reg_iop_mpu_r_trace___pc___lsb 16 +#define reg_iop_mpu_r_trace___pc___width 12 +#define reg_iop_mpu_r_trace___en___lsb 28 +#define reg_iop_mpu_r_trace___en___width 1 +#define reg_iop_mpu_r_trace___en___bit 28 +#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29 +#define reg_iop_mpu_r_trace___instr_reg_busy___width 1 +#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29 +#define reg_iop_mpu_r_trace___intr_busy___lsb 30 +#define reg_iop_mpu_r_trace___intr_busy___width 1 +#define reg_iop_mpu_r_trace___intr_busy___bit 30 +#define reg_iop_mpu_r_trace_offset 148 + +/* Register r_wr_stat, scope iop_mpu, type r */ +#define reg_iop_mpu_r_wr_stat___r0___lsb 0 +#define reg_iop_mpu_r_wr_stat___r0___width 1 +#define reg_iop_mpu_r_wr_stat___r0___bit 0 +#define reg_iop_mpu_r_wr_stat___r1___lsb 1 +#define reg_iop_mpu_r_wr_stat___r1___width 1 +#define reg_iop_mpu_r_wr_stat___r1___bit 1 +#define reg_iop_mpu_r_wr_stat___r2___lsb 2 +#define reg_iop_mpu_r_wr_stat___r2___width 1 +#define reg_iop_mpu_r_wr_stat___r2___bit 2 +#define reg_iop_mpu_r_wr_stat___r3___lsb 3 +#define reg_iop_mpu_r_wr_stat___r3___width 1 +#define reg_iop_mpu_r_wr_stat___r3___bit 3 +#define reg_iop_mpu_r_wr_stat___r4___lsb 4 +#define reg_iop_mpu_r_wr_stat___r4___width 1 +#define reg_iop_mpu_r_wr_stat___r4___bit 4 +#define reg_iop_mpu_r_wr_stat___r5___lsb 5 +#define reg_iop_mpu_r_wr_stat___r5___width 1 +#define reg_iop_mpu_r_wr_stat___r5___bit 5 +#define reg_iop_mpu_r_wr_stat___r6___lsb 6 +#define reg_iop_mpu_r_wr_stat___r6___width 1 +#define reg_iop_mpu_r_wr_stat___r6___bit 6 +#define reg_iop_mpu_r_wr_stat___r7___lsb 7 +#define reg_iop_mpu_r_wr_stat___r7___width 1 +#define reg_iop_mpu_r_wr_stat___r7___bit 7 +#define reg_iop_mpu_r_wr_stat___r8___lsb 8 +#define reg_iop_mpu_r_wr_stat___r8___width 1 +#define reg_iop_mpu_r_wr_stat___r8___bit 8 +#define reg_iop_mpu_r_wr_stat___r9___lsb 9 +#define reg_iop_mpu_r_wr_stat___r9___width 1 +#define reg_iop_mpu_r_wr_stat___r9___bit 9 +#define reg_iop_mpu_r_wr_stat___r10___lsb 10 +#define reg_iop_mpu_r_wr_stat___r10___width 1 +#define reg_iop_mpu_r_wr_stat___r10___bit 10 +#define reg_iop_mpu_r_wr_stat___r11___lsb 11 +#define reg_iop_mpu_r_wr_stat___r11___width 1 +#define reg_iop_mpu_r_wr_stat___r11___bit 11 +#define reg_iop_mpu_r_wr_stat___r12___lsb 12 +#define reg_iop_mpu_r_wr_stat___r12___width 1 +#define reg_iop_mpu_r_wr_stat___r12___bit 12 +#define reg_iop_mpu_r_wr_stat___r13___lsb 13 +#define reg_iop_mpu_r_wr_stat___r13___width 1 +#define reg_iop_mpu_r_wr_stat___r13___bit 13 +#define reg_iop_mpu_r_wr_stat___r14___lsb 14 +#define reg_iop_mpu_r_wr_stat___r14___width 1 +#define reg_iop_mpu_r_wr_stat___r14___bit 14 +#define reg_iop_mpu_r_wr_stat___r15___lsb 15 +#define reg_iop_mpu_r_wr_stat___r15___width 1 +#define reg_iop_mpu_r_wr_stat___r15___bit 15 +#define reg_iop_mpu_r_wr_stat_offset 152 + +#define STRIDE_iop_mpu_rw_thread 4 +/* Register rw_thread, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_thread___addr___lsb 0 +#define reg_iop_mpu_rw_thread___addr___width 12 +#define reg_iop_mpu_rw_thread_offset 156 + +#define STRIDE_iop_mpu_rw_intr 4 +/* Register rw_intr, scope iop_mpu, type rw */ +#define reg_iop_mpu_rw_intr___addr___lsb 0 +#define reg_iop_mpu_rw_intr___addr___width 12 +#define reg_iop_mpu_rw_intr_offset 196 + + +/* Constants */ +#define regk_iop_mpu_no 0x00000000 +#define regk_iop_mpu_r_pc_default 0x00000000 +#define regk_iop_mpu_rw_ctrl_default 0x00000000 +#define regk_iop_mpu_rw_intr_size 0x00000010 +#define regk_iop_mpu_rw_r_size 0x00000010 +#define regk_iop_mpu_rw_thread_default 0x00000000 +#define regk_iop_mpu_rw_thread_size 0x00000004 +#define regk_iop_mpu_yes 0x00000001 +#endif /* __iop_mpu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h new file mode 100644 index 000000000..a20b8857b --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h @@ -0,0 +1,44 @@ +/* Autogenerated Changes here will be lost! + * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg + */ +#define iop_version 0 +#define iop_fifo_in0_extra 64 +#define iop_fifo_in1_extra 128 +#define iop_fifo_out0_extra 192 +#define iop_fifo_out1_extra 256 +#define iop_trigger_grp0 320 +#define iop_trigger_grp1 384 +#define iop_trigger_grp2 448 +#define iop_trigger_grp3 512 +#define iop_trigger_grp4 576 +#define iop_trigger_grp5 640 +#define iop_trigger_grp6 704 +#define iop_trigger_grp7 768 +#define iop_crc_par0 896 +#define iop_crc_par1 1024 +#define iop_dmc_in0 1152 +#define iop_dmc_in1 1280 +#define iop_dmc_out0 1408 +#define iop_dmc_out1 1536 +#define iop_fifo_in0 1664 +#define iop_fifo_in1 1792 +#define iop_fifo_out0 1920 +#define iop_fifo_out1 2048 +#define iop_scrc_in0 2176 +#define iop_scrc_in1 2304 +#define iop_scrc_out0 2432 +#define iop_scrc_out1 2560 +#define iop_timer_grp0 2688 +#define iop_timer_grp1 2816 +#define iop_timer_grp2 2944 +#define iop_timer_grp3 3072 +#define iop_sap_in 3328 +#define iop_sap_out 3584 +#define iop_spu0 3840 +#define iop_spu1 4096 +#define iop_sw_cfg 4352 +#define iop_sw_cpu 4608 +#define iop_sw_mpu 4864 +#define iop_sw_spu0 5120 +#define iop_sw_spu1 5376 +#define iop_mpu 5632 diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h new file mode 100644 index 000000000..a4a10ff30 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h @@ -0,0 +1,182 @@ +#ifndef __iop_sap_in_defs_asm_h +#define __iop_sap_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_in.r + * id: + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r + * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_bus0_sync, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0 +#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5 +#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7 +#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8 +#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10 +#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13 +#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15 +#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16 +#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18 +#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21 +#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23 +#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24 +#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26 +#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3 +#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29 +#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1 +#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31 +#define reg_iop_sap_in_rw_bus0_sync_offset 0 + +/* Register rw_bus1_sync, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0 +#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5 +#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7 +#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8 +#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10 +#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13 +#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15 +#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16 +#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18 +#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21 +#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23 +#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24 +#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26 +#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3 +#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29 +#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1 +#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31 +#define reg_iop_sap_in_rw_bus1_sync_offset 4 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_gio___sync_sel___width 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_gio___sync_edge___width 2 +#define reg_iop_sap_in_rw_gio___delay___lsb 7 +#define reg_iop_sap_in_rw_gio___delay___width 1 +#define reg_iop_sap_in_rw_gio___delay___bit 7 +#define reg_iop_sap_in_rw_gio___logic___lsb 8 +#define reg_iop_sap_in_rw_gio___logic___width 2 +#define reg_iop_sap_in_rw_gio_offset 8 + + +/* Constants */ +#define regk_iop_sap_in_and 0x00000002 +#define regk_iop_sap_in_ext_clk200 0x00000003 +#define regk_iop_sap_in_gio1 0x00000000 +#define regk_iop_sap_in_gio13 0x00000005 +#define regk_iop_sap_in_gio18 0x00000003 +#define regk_iop_sap_in_gio19 0x00000004 +#define regk_iop_sap_in_gio21 0x00000006 +#define regk_iop_sap_in_gio23 0x00000005 +#define regk_iop_sap_in_gio29 0x00000007 +#define regk_iop_sap_in_gio5 0x00000004 +#define regk_iop_sap_in_gio6 0x00000001 +#define regk_iop_sap_in_gio7 0x00000002 +#define regk_iop_sap_in_inv 0x00000001 +#define regk_iop_sap_in_neg 0x00000002 +#define regk_iop_sap_in_no 0x00000000 +#define regk_iop_sap_in_no_del_ext_clk200 0x00000001 +#define regk_iop_sap_in_none 0x00000000 +#define regk_iop_sap_in_or 0x00000003 +#define regk_iop_sap_in_pos 0x00000001 +#define regk_iop_sap_in_pos_neg 0x00000003 +#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202 +#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202 +#define regk_iop_sap_in_rw_gio_default 0x00000002 +#define regk_iop_sap_in_rw_gio_size 0x00000020 +#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006 +#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004 +#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005 +#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007 +#define regk_iop_sap_in_tmr_clk200 0x00000000 +#define regk_iop_sap_in_two_clk200 0x00000002 +#define regk_iop_sap_in_yes 0x00000001 +#endif /* __iop_sap_in_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 000000000..0ec727f92 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h @@ -0,0 +1,346 @@ +#ifndef __iop_sap_out_defs_asm_h +#define __iop_sap_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_out.r + * id: + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r + * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 +#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 +#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 +#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 +#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 +#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 +#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 +#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated_offset 0 + +/* Register rw_bus0, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 +#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 +#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 +#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 +#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 +#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 +#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 +#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 +#define reg_iop_sap_out_rw_bus0_offset 4 + +/* Register rw_bus1, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 +#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 +#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 +#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 +#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 +#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 +#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 +#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 +#define reg_iop_sap_out_rw_bus1_offset 8 + +/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 +#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 + +/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 +#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 + +/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 +#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 + +/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 +#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 +#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 +#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 +#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 +#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 +#define reg_iop_sap_out_rw_gio___out_logic___lsb 10 +#define reg_iop_sap_out_rw_gio___out_logic___width 1 +#define reg_iop_sap_out_rw_gio___out_logic___bit 10 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 +#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 +#define reg_iop_sap_out_rw_gio___oe_logic___width 2 +#define reg_iop_sap_out_rw_gio_offset 28 + + +/* Constants */ +#define regk_iop_sap_out_and 0x00000002 +#define regk_iop_sap_out_clk0 0x00000000 +#define regk_iop_sap_out_clk1 0x00000001 +#define regk_iop_sap_out_clk12 0x00000002 +#define regk_iop_sap_out_clk2 0x00000002 +#define regk_iop_sap_out_clk200 0x00000001 +#define regk_iop_sap_out_clk3 0x00000003 +#define regk_iop_sap_out_ext 0x00000003 +#define regk_iop_sap_out_gated 0x00000004 +#define regk_iop_sap_out_gio1 0x00000000 +#define regk_iop_sap_out_gio13 0x00000002 +#define regk_iop_sap_out_gio13_clk 0x0000000c +#define regk_iop_sap_out_gio15 0x00000001 +#define regk_iop_sap_out_gio18 0x00000003 +#define regk_iop_sap_out_gio18_clk 0x0000000d +#define regk_iop_sap_out_gio1_clk 0x00000008 +#define regk_iop_sap_out_gio21_clk 0x0000000e +#define regk_iop_sap_out_gio23 0x00000002 +#define regk_iop_sap_out_gio29_clk 0x0000000f +#define regk_iop_sap_out_gio31 0x00000003 +#define regk_iop_sap_out_gio5 0x00000001 +#define regk_iop_sap_out_gio5_clk 0x00000009 +#define regk_iop_sap_out_gio6_clk 0x0000000a +#define regk_iop_sap_out_gio7 0x00000000 +#define regk_iop_sap_out_gio7_clk 0x0000000b +#define regk_iop_sap_out_gio_in13 0x00000001 +#define regk_iop_sap_out_gio_in21 0x00000002 +#define regk_iop_sap_out_gio_in29 0x00000003 +#define regk_iop_sap_out_gio_in5 0x00000000 +#define regk_iop_sap_out_inv 0x00000001 +#define regk_iop_sap_out_nand 0x00000003 +#define regk_iop_sap_out_no 0x00000000 +#define regk_iop_sap_out_none 0x00000000 +#define regk_iop_sap_out_rw_bus0_default 0x00000000 +#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 +#define regk_iop_sap_out_rw_gio_default 0x00000000 +#define regk_iop_sap_out_rw_gio_size 0x00000020 +#define regk_iop_sap_out_spu0_gio0 0x00000002 +#define regk_iop_sap_out_spu0_gio1 0x00000003 +#define regk_iop_sap_out_spu0_gio12 0x00000004 +#define regk_iop_sap_out_spu0_gio13 0x00000004 +#define regk_iop_sap_out_spu0_gio14 0x00000004 +#define regk_iop_sap_out_spu0_gio15 0x00000004 +#define regk_iop_sap_out_spu0_gio2 0x00000002 +#define regk_iop_sap_out_spu0_gio3 0x00000003 +#define regk_iop_sap_out_spu0_gio4 0x00000002 +#define regk_iop_sap_out_spu0_gio5 0x00000003 +#define regk_iop_sap_out_spu0_gio6 0x00000002 +#define regk_iop_sap_out_spu0_gio7 0x00000003 +#define regk_iop_sap_out_spu1_gio0 0x00000005 +#define regk_iop_sap_out_spu1_gio1 0x00000006 +#define regk_iop_sap_out_spu1_gio12 0x00000007 +#define regk_iop_sap_out_spu1_gio13 0x00000007 +#define regk_iop_sap_out_spu1_gio14 0x00000007 +#define regk_iop_sap_out_spu1_gio15 0x00000007 +#define regk_iop_sap_out_spu1_gio2 0x00000005 +#define regk_iop_sap_out_spu1_gio3 0x00000006 +#define regk_iop_sap_out_spu1_gio4 0x00000005 +#define regk_iop_sap_out_spu1_gio5 0x00000006 +#define regk_iop_sap_out_spu1_gio6 0x00000005 +#define regk_iop_sap_out_spu1_gio7 0x00000006 +#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 +#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 +#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 +#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 +#define regk_iop_sap_out_tmr 0x00000005 +#define regk_iop_sap_out_yes 0x00000001 +#endif /* __iop_sap_out_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h new file mode 100644 index 000000000..2cf572159 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h @@ -0,0 +1,111 @@ +#ifndef __iop_scrc_in_defs_asm_h +#define __iop_scrc_in_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_in.r + * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r + * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_cfg___trig___lsb 0 +#define reg_iop_scrc_in_rw_cfg___trig___width 2 +#define reg_iop_scrc_in_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 +#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 +#define reg_iop_scrc_in_rw_ctrl_offset 4 + +/* Register r_stat, scope iop_scrc_in, type r */ +#define reg_iop_scrc_in_r_stat___err___lsb 0 +#define reg_iop_scrc_in_r_stat___err___width 1 +#define reg_iop_scrc_in_r_stat___err___bit 0 +#define reg_iop_scrc_in_r_stat_offset 8 + +/* Register rw_init_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_init_crc_offset 12 + +/* Register rs_computed_crc, scope iop_scrc_in, type rs */ +#define reg_iop_scrc_in_rs_computed_crc_offset 16 + +/* Register r_computed_crc, scope iop_scrc_in, type r */ +#define reg_iop_scrc_in_r_computed_crc_offset 20 + +/* Register rw_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_crc_offset 24 + +/* Register rw_correct_crc, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_correct_crc_offset 28 + +/* Register rw_wr1bit, scope iop_scrc_in, type rw */ +#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 +#define reg_iop_scrc_in_rw_wr1bit___data___width 2 +#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 +#define reg_iop_scrc_in_rw_wr1bit___last___width 2 +#define reg_iop_scrc_in_rw_wr1bit_offset 32 + + +/* Constants */ +#define regk_iop_scrc_in_dif_in 0x00000002 +#define regk_iop_scrc_in_hi 0x00000000 +#define regk_iop_scrc_in_neg 0x00000002 +#define regk_iop_scrc_in_no 0x00000000 +#define regk_iop_scrc_in_pos 0x00000001 +#define regk_iop_scrc_in_pos_neg 0x00000003 +#define regk_iop_scrc_in_r_computed_crc_default 0x00000000 +#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 +#define regk_iop_scrc_in_rw_cfg_default 0x00000000 +#define regk_iop_scrc_in_rw_ctrl_default 0x00000000 +#define regk_iop_scrc_in_rw_init_crc_default 0x00000000 +#define regk_iop_scrc_in_set0 0x00000000 +#define regk_iop_scrc_in_set1 0x00000001 +#define regk_iop_scrc_in_yes 0x00000001 +#endif /* __iop_scrc_in_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h new file mode 100644 index 000000000..640a25725 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h @@ -0,0 +1,105 @@ +#ifndef __iop_scrc_out_defs_asm_h +#define __iop_scrc_out_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_out.r + * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r + * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_cfg___trig___lsb 0 +#define reg_iop_scrc_out_rw_cfg___trig___width 2 +#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2 +#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1 +#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2 +#define reg_iop_scrc_out_rw_cfg_offset 0 + +/* Register rw_ctrl, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0 +#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1 +#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0 +#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1 +#define reg_iop_scrc_out_rw_ctrl___out_src___width 1 +#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1 +#define reg_iop_scrc_out_rw_ctrl_offset 4 + +/* Register rw_init_crc, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_init_crc_offset 8 + +/* Register rw_crc, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_crc_offset 12 + +/* Register rw_data, scope iop_scrc_out, type rw */ +#define reg_iop_scrc_out_rw_data___val___lsb 0 +#define reg_iop_scrc_out_rw_data___val___width 1 +#define reg_iop_scrc_out_rw_data___val___bit 0 +#define reg_iop_scrc_out_rw_data_offset 16 + +/* Register r_computed_crc, scope iop_scrc_out, type r */ +#define reg_iop_scrc_out_r_computed_crc_offset 20 + + +/* Constants */ +#define regk_iop_scrc_out_crc 0x00000001 +#define regk_iop_scrc_out_data 0x00000000 +#define regk_iop_scrc_out_dif 0x00000001 +#define regk_iop_scrc_out_hi 0x00000000 +#define regk_iop_scrc_out_neg 0x00000002 +#define regk_iop_scrc_out_no 0x00000000 +#define regk_iop_scrc_out_pos 0x00000001 +#define regk_iop_scrc_out_pos_neg 0x00000003 +#define regk_iop_scrc_out_reg 0x00000000 +#define regk_iop_scrc_out_rw_cfg_default 0x00000000 +#define regk_iop_scrc_out_rw_crc_default 0x00000000 +#define regk_iop_scrc_out_rw_ctrl_default 0x00000000 +#define regk_iop_scrc_out_rw_data_default 0x00000000 +#define regk_iop_scrc_out_rw_init_crc_default 0x00000000 +#define regk_iop_scrc_out_yes 0x00000001 +#endif /* __iop_scrc_out_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h new file mode 100644 index 000000000..bb402c1aa --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h @@ -0,0 +1,573 @@ +#ifndef __iop_spu_defs_asm_h +#define __iop_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_spu.r + * id: + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r + * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_spu_rw_r 4 +/* Register rw_r, scope iop_spu, type rw */ +#define reg_iop_spu_rw_r_offset 0 + +/* Register rw_seq_pc, scope iop_spu, type rw */ +#define reg_iop_spu_rw_seq_pc___addr___lsb 0 +#define reg_iop_spu_rw_seq_pc___addr___width 12 +#define reg_iop_spu_rw_seq_pc_offset 64 + +/* Register rw_fsm_pc, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_pc___addr___lsb 0 +#define reg_iop_spu_rw_fsm_pc___addr___width 12 +#define reg_iop_spu_rw_fsm_pc_offset 68 + +/* Register rw_ctrl, scope iop_spu, type rw */ +#define reg_iop_spu_rw_ctrl___fsm___lsb 0 +#define reg_iop_spu_rw_ctrl___fsm___width 1 +#define reg_iop_spu_rw_ctrl___fsm___bit 0 +#define reg_iop_spu_rw_ctrl___en___lsb 1 +#define reg_iop_spu_rw_ctrl___en___width 1 +#define reg_iop_spu_rw_ctrl___en___bit 1 +#define reg_iop_spu_rw_ctrl_offset 72 + +/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 +#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 +#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 +#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 +#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 +#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 +#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 +#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 +#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 +#define reg_iop_spu_rw_fsm_inputs3_0_offset 76 + +/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ +#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 +#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 +#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 +#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 +#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 +#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 +#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 +#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 +#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 +#define reg_iop_spu_rw_fsm_inputs7_4_offset 80 + +/* Register rw_gio_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_offset 84 + +/* Register rw_bus0_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_bus0_out_offset 88 + +/* Register rw_bus1_out, scope iop_spu, type rw */ +#define reg_iop_spu_rw_bus1_out_offset 92 + +/* Register r_gio_in, scope iop_spu, type r */ +#define reg_iop_spu_r_gio_in_offset 96 + +/* Register r_bus0_in, scope iop_spu, type r */ +#define reg_iop_spu_r_bus0_in_offset 100 + +/* Register r_bus1_in, scope iop_spu, type r */ +#define reg_iop_spu_r_bus1_in_offset 104 + +/* Register rw_gio_out_set, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_set_offset 108 + +/* Register rw_gio_out_clr, scope iop_spu, type rw */ +#define reg_iop_spu_rw_gio_out_clr_offset 112 + +/* Register rs_wr_stat, scope iop_spu, type rs */ +#define reg_iop_spu_rs_wr_stat___r0___lsb 0 +#define reg_iop_spu_rs_wr_stat___r0___width 1 +#define reg_iop_spu_rs_wr_stat___r0___bit 0 +#define reg_iop_spu_rs_wr_stat___r1___lsb 1 +#define reg_iop_spu_rs_wr_stat___r1___width 1 +#define reg_iop_spu_rs_wr_stat___r1___bit 1 +#define reg_iop_spu_rs_wr_stat___r2___lsb 2 +#define reg_iop_spu_rs_wr_stat___r2___width 1 +#define reg_iop_spu_rs_wr_stat___r2___bit 2 +#define reg_iop_spu_rs_wr_stat___r3___lsb 3 +#define reg_iop_spu_rs_wr_stat___r3___width 1 +#define reg_iop_spu_rs_wr_stat___r3___bit 3 +#define reg_iop_spu_rs_wr_stat___r4___lsb 4 +#define reg_iop_spu_rs_wr_stat___r4___width 1 +#define reg_iop_spu_rs_wr_stat___r4___bit 4 +#define reg_iop_spu_rs_wr_stat___r5___lsb 5 +#define reg_iop_spu_rs_wr_stat___r5___width 1 +#define reg_iop_spu_rs_wr_stat___r5___bit 5 +#define reg_iop_spu_rs_wr_stat___r6___lsb 6 +#define reg_iop_spu_rs_wr_stat___r6___width 1 +#define reg_iop_spu_rs_wr_stat___r6___bit 6 +#define reg_iop_spu_rs_wr_stat___r7___lsb 7 +#define reg_iop_spu_rs_wr_stat___r7___width 1 +#define reg_iop_spu_rs_wr_stat___r7___bit 7 +#define reg_iop_spu_rs_wr_stat___r8___lsb 8 +#define reg_iop_spu_rs_wr_stat___r8___width 1 +#define reg_iop_spu_rs_wr_stat___r8___bit 8 +#define reg_iop_spu_rs_wr_stat___r9___lsb 9 +#define reg_iop_spu_rs_wr_stat___r9___width 1 +#define reg_iop_spu_rs_wr_stat___r9___bit 9 +#define reg_iop_spu_rs_wr_stat___r10___lsb 10 +#define reg_iop_spu_rs_wr_stat___r10___width 1 +#define reg_iop_spu_rs_wr_stat___r10___bit 10 +#define reg_iop_spu_rs_wr_stat___r11___lsb 11 +#define reg_iop_spu_rs_wr_stat___r11___width 1 +#define reg_iop_spu_rs_wr_stat___r11___bit 11 +#define reg_iop_spu_rs_wr_stat___r12___lsb 12 +#define reg_iop_spu_rs_wr_stat___r12___width 1 +#define reg_iop_spu_rs_wr_stat___r12___bit 12 +#define reg_iop_spu_rs_wr_stat___r13___lsb 13 +#define reg_iop_spu_rs_wr_stat___r13___width 1 +#define reg_iop_spu_rs_wr_stat___r13___bit 13 +#define reg_iop_spu_rs_wr_stat___r14___lsb 14 +#define reg_iop_spu_rs_wr_stat___r14___width 1 +#define reg_iop_spu_rs_wr_stat___r14___bit 14 +#define reg_iop_spu_rs_wr_stat___r15___lsb 15 +#define reg_iop_spu_rs_wr_stat___r15___width 1 +#define reg_iop_spu_rs_wr_stat___r15___bit 15 +#define reg_iop_spu_rs_wr_stat_offset 116 + +/* Register r_wr_stat, scope iop_spu, type r */ +#define reg_iop_spu_r_wr_stat___r0___lsb 0 +#define reg_iop_spu_r_wr_stat___r0___width 1 +#define reg_iop_spu_r_wr_stat___r0___bit 0 +#define reg_iop_spu_r_wr_stat___r1___lsb 1 +#define reg_iop_spu_r_wr_stat___r1___width 1 +#define reg_iop_spu_r_wr_stat___r1___bit 1 +#define reg_iop_spu_r_wr_stat___r2___lsb 2 +#define reg_iop_spu_r_wr_stat___r2___width 1 +#define reg_iop_spu_r_wr_stat___r2___bit 2 +#define reg_iop_spu_r_wr_stat___r3___lsb 3 +#define reg_iop_spu_r_wr_stat___r3___width 1 +#define reg_iop_spu_r_wr_stat___r3___bit 3 +#define reg_iop_spu_r_wr_stat___r4___lsb 4 +#define reg_iop_spu_r_wr_stat___r4___width 1 +#define reg_iop_spu_r_wr_stat___r4___bit 4 +#define reg_iop_spu_r_wr_stat___r5___lsb 5 +#define reg_iop_spu_r_wr_stat___r5___width 1 +#define reg_iop_spu_r_wr_stat___r5___bit 5 +#define reg_iop_spu_r_wr_stat___r6___lsb 6 +#define reg_iop_spu_r_wr_stat___r6___width 1 +#define reg_iop_spu_r_wr_stat___r6___bit 6 +#define reg_iop_spu_r_wr_stat___r7___lsb 7 +#define reg_iop_spu_r_wr_stat___r7___width 1 +#define reg_iop_spu_r_wr_stat___r7___bit 7 +#define reg_iop_spu_r_wr_stat___r8___lsb 8 +#define reg_iop_spu_r_wr_stat___r8___width 1 +#define reg_iop_spu_r_wr_stat___r8___bit 8 +#define reg_iop_spu_r_wr_stat___r9___lsb 9 +#define reg_iop_spu_r_wr_stat___r9___width 1 +#define reg_iop_spu_r_wr_stat___r9___bit 9 +#define reg_iop_spu_r_wr_stat___r10___lsb 10 +#define reg_iop_spu_r_wr_stat___r10___width 1 +#define reg_iop_spu_r_wr_stat___r10___bit 10 +#define reg_iop_spu_r_wr_stat___r11___lsb 11 +#define reg_iop_spu_r_wr_stat___r11___width 1 +#define reg_iop_spu_r_wr_stat___r11___bit 11 +#define reg_iop_spu_r_wr_stat___r12___lsb 12 +#define reg_iop_spu_r_wr_stat___r12___width 1 +#define reg_iop_spu_r_wr_stat___r12___bit 12 +#define reg_iop_spu_r_wr_stat___r13___lsb 13 +#define reg_iop_spu_r_wr_stat___r13___width 1 +#define reg_iop_spu_r_wr_stat___r13___bit 13 +#define reg_iop_spu_r_wr_stat___r14___lsb 14 +#define reg_iop_spu_r_wr_stat___r14___width 1 +#define reg_iop_spu_r_wr_stat___r14___bit 14 +#define reg_iop_spu_r_wr_stat___r15___lsb 15 +#define reg_iop_spu_r_wr_stat___r15___width 1 +#define reg_iop_spu_r_wr_stat___r15___bit 15 +#define reg_iop_spu_r_wr_stat_offset 120 + +/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ +#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 + +/* Register r_stat_in, scope iop_spu, type r */ +#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 +#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 +#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 +#define reg_iop_spu_r_stat_in___fifo_out_last___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 +#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 +#define reg_iop_spu_r_stat_in___fifo_out_all___width 1 +#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 +#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 +#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 +#define reg_iop_spu_r_stat_in___dmc_out_all___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 +#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 +#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 +#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 +#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 +#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 +#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 +#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 +#define reg_iop_spu_r_stat_in___dmc_out_last___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 +#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 +#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 +#define reg_iop_spu_r_stat_in___pcrc_correct___width 1 +#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 +#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 +#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 +#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 +#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 +#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 +#define reg_iop_spu_r_stat_in___dmc_in_full___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 +#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 +#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 +#define reg_iop_spu_r_stat_in___spu_gio_out___width 4 +#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 +#define reg_iop_spu_r_stat_in___sync_clk12___width 1 +#define reg_iop_spu_r_stat_in___sync_clk12___bit 27 +#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 +#define reg_iop_spu_r_stat_in___scrc_out_data___width 1 +#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 +#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 +#define reg_iop_spu_r_stat_in___scrc_in_err___width 1 +#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 +#define reg_iop_spu_r_stat_in___mc_busy___lsb 30 +#define reg_iop_spu_r_stat_in___mc_busy___width 1 +#define reg_iop_spu_r_stat_in___mc_busy___bit 30 +#define reg_iop_spu_r_stat_in___mc_owned___lsb 31 +#define reg_iop_spu_r_stat_in___mc_owned___width 1 +#define reg_iop_spu_r_stat_in___mc_owned___bit 31 +#define reg_iop_spu_r_stat_in_offset 128 + +/* Register r_trigger_in, scope iop_spu, type r */ +#define reg_iop_spu_r_trigger_in_offset 132 + +/* Register r_special_stat, scope iop_spu, type r */ +#define reg_iop_spu_r_special_stat___c_flag___lsb 0 +#define reg_iop_spu_r_special_stat___c_flag___width 1 +#define reg_iop_spu_r_special_stat___c_flag___bit 0 +#define reg_iop_spu_r_special_stat___v_flag___lsb 1 +#define reg_iop_spu_r_special_stat___v_flag___width 1 +#define reg_iop_spu_r_special_stat___v_flag___bit 1 +#define reg_iop_spu_r_special_stat___z_flag___lsb 2 +#define reg_iop_spu_r_special_stat___z_flag___width 1 +#define reg_iop_spu_r_special_stat___z_flag___bit 2 +#define reg_iop_spu_r_special_stat___n_flag___lsb 3 +#define reg_iop_spu_r_special_stat___n_flag___width 1 +#define reg_iop_spu_r_special_stat___n_flag___bit 3 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 +#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 +#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 +#define reg_iop_spu_r_special_stat___fsm_in0___width 1 +#define reg_iop_spu_r_special_stat___fsm_in0___bit 8 +#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 +#define reg_iop_spu_r_special_stat___fsm_in1___width 1 +#define reg_iop_spu_r_special_stat___fsm_in1___bit 9 +#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 +#define reg_iop_spu_r_special_stat___fsm_in2___width 1 +#define reg_iop_spu_r_special_stat___fsm_in2___bit 10 +#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 +#define reg_iop_spu_r_special_stat___fsm_in3___width 1 +#define reg_iop_spu_r_special_stat___fsm_in3___bit 11 +#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 +#define reg_iop_spu_r_special_stat___fsm_in4___width 1 +#define reg_iop_spu_r_special_stat___fsm_in4___bit 12 +#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 +#define reg_iop_spu_r_special_stat___fsm_in5___width 1 +#define reg_iop_spu_r_special_stat___fsm_in5___bit 13 +#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 +#define reg_iop_spu_r_special_stat___fsm_in6___width 1 +#define reg_iop_spu_r_special_stat___fsm_in6___bit 14 +#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 +#define reg_iop_spu_r_special_stat___fsm_in7___width 1 +#define reg_iop_spu_r_special_stat___fsm_in7___bit 15 +#define reg_iop_spu_r_special_stat___event0___lsb 16 +#define reg_iop_spu_r_special_stat___event0___width 1 +#define reg_iop_spu_r_special_stat___event0___bit 16 +#define reg_iop_spu_r_special_stat___event1___lsb 17 +#define reg_iop_spu_r_special_stat___event1___width 1 +#define reg_iop_spu_r_special_stat___event1___bit 17 +#define reg_iop_spu_r_special_stat___event2___lsb 18 +#define reg_iop_spu_r_special_stat___event2___width 1 +#define reg_iop_spu_r_special_stat___event2___bit 18 +#define reg_iop_spu_r_special_stat___event3___lsb 19 +#define reg_iop_spu_r_special_stat___event3___width 1 +#define reg_iop_spu_r_special_stat___event3___bit 19 +#define reg_iop_spu_r_special_stat_offset 136 + +/* Register rw_reg_access, scope iop_spu, type rw */ +#define reg_iop_spu_rw_reg_access___addr___lsb 0 +#define reg_iop_spu_rw_reg_access___addr___width 13 +#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 +#define reg_iop_spu_rw_reg_access___imm_hi___width 16 +#define reg_iop_spu_rw_reg_access_offset 140 + +#define STRIDE_iop_spu_rw_event_cfg 4 +/* Register rw_event_cfg, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_cfg___addr___lsb 0 +#define reg_iop_spu_rw_event_cfg___addr___width 12 +#define reg_iop_spu_rw_event_cfg___src___lsb 12 +#define reg_iop_spu_rw_event_cfg___src___width 2 +#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 +#define reg_iop_spu_rw_event_cfg___eq_en___width 1 +#define reg_iop_spu_rw_event_cfg___eq_en___bit 14 +#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 +#define reg_iop_spu_rw_event_cfg___eq_inv___width 1 +#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 +#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 +#define reg_iop_spu_rw_event_cfg___gt_en___width 1 +#define reg_iop_spu_rw_event_cfg___gt_en___bit 16 +#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 +#define reg_iop_spu_rw_event_cfg___gt_inv___width 1 +#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 +#define reg_iop_spu_rw_event_cfg_offset 144 + +#define STRIDE_iop_spu_rw_event_mask 4 +/* Register rw_event_mask, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_mask_offset 160 + +#define STRIDE_iop_spu_rw_event_val 4 +/* Register rw_event_val, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_val_offset 176 + +/* Register rw_event_ret, scope iop_spu, type rw */ +#define reg_iop_spu_rw_event_ret___addr___lsb 0 +#define reg_iop_spu_rw_event_ret___addr___width 12 +#define reg_iop_spu_rw_event_ret_offset 192 + +/* Register r_trace, scope iop_spu, type r */ +#define reg_iop_spu_r_trace___fsm___lsb 0 +#define reg_iop_spu_r_trace___fsm___width 1 +#define reg_iop_spu_r_trace___fsm___bit 0 +#define reg_iop_spu_r_trace___en___lsb 1 +#define reg_iop_spu_r_trace___en___width 1 +#define reg_iop_spu_r_trace___en___bit 1 +#define reg_iop_spu_r_trace___c_flag___lsb 2 +#define reg_iop_spu_r_trace___c_flag___width 1 +#define reg_iop_spu_r_trace___c_flag___bit 2 +#define reg_iop_spu_r_trace___v_flag___lsb 3 +#define reg_iop_spu_r_trace___v_flag___width 1 +#define reg_iop_spu_r_trace___v_flag___bit 3 +#define reg_iop_spu_r_trace___z_flag___lsb 4 +#define reg_iop_spu_r_trace___z_flag___width 1 +#define reg_iop_spu_r_trace___z_flag___bit 4 +#define reg_iop_spu_r_trace___n_flag___lsb 5 +#define reg_iop_spu_r_trace___n_flag___width 1 +#define reg_iop_spu_r_trace___n_flag___bit 5 +#define reg_iop_spu_r_trace___seq_addr___lsb 6 +#define reg_iop_spu_r_trace___seq_addr___width 12 +#define reg_iop_spu_r_trace___fsm_addr___lsb 20 +#define reg_iop_spu_r_trace___fsm_addr___width 12 +#define reg_iop_spu_r_trace_offset 196 + +/* Register r_fsm_trace, scope iop_spu, type r */ +#define reg_iop_spu_r_fsm_trace___fsm___lsb 0 +#define reg_iop_spu_r_fsm_trace___fsm___width 1 +#define reg_iop_spu_r_fsm_trace___fsm___bit 0 +#define reg_iop_spu_r_fsm_trace___en___lsb 1 +#define reg_iop_spu_r_fsm_trace___en___width 1 +#define reg_iop_spu_r_fsm_trace___en___bit 1 +#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 +#define reg_iop_spu_r_fsm_trace___tmr_done___width 1 +#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 +#define reg_iop_spu_r_fsm_trace___inp0___lsb 3 +#define reg_iop_spu_r_fsm_trace___inp0___width 1 +#define reg_iop_spu_r_fsm_trace___inp0___bit 3 +#define reg_iop_spu_r_fsm_trace___inp1___lsb 4 +#define reg_iop_spu_r_fsm_trace___inp1___width 1 +#define reg_iop_spu_r_fsm_trace___inp1___bit 4 +#define reg_iop_spu_r_fsm_trace___inp2___lsb 5 +#define reg_iop_spu_r_fsm_trace___inp2___width 1 +#define reg_iop_spu_r_fsm_trace___inp2___bit 5 +#define reg_iop_spu_r_fsm_trace___inp3___lsb 6 +#define reg_iop_spu_r_fsm_trace___inp3___width 1 +#define reg_iop_spu_r_fsm_trace___inp3___bit 6 +#define reg_iop_spu_r_fsm_trace___event0___lsb 7 +#define reg_iop_spu_r_fsm_trace___event0___width 1 +#define reg_iop_spu_r_fsm_trace___event0___bit 7 +#define reg_iop_spu_r_fsm_trace___event1___lsb 8 +#define reg_iop_spu_r_fsm_trace___event1___width 1 +#define reg_iop_spu_r_fsm_trace___event1___bit 8 +#define reg_iop_spu_r_fsm_trace___event2___lsb 9 +#define reg_iop_spu_r_fsm_trace___event2___width 1 +#define reg_iop_spu_r_fsm_trace___event2___bit 9 +#define reg_iop_spu_r_fsm_trace___event3___lsb 10 +#define reg_iop_spu_r_fsm_trace___event3___width 1 +#define reg_iop_spu_r_fsm_trace___event3___bit 10 +#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 +#define reg_iop_spu_r_fsm_trace___gio_out___width 8 +#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 +#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 +#define reg_iop_spu_r_fsm_trace_offset 200 + +#define STRIDE_iop_spu_rw_brp 4 +/* Register rw_brp, scope iop_spu, type rw */ +#define reg_iop_spu_rw_brp___addr___lsb 0 +#define reg_iop_spu_rw_brp___addr___width 12 +#define reg_iop_spu_rw_brp___fsm___lsb 12 +#define reg_iop_spu_rw_brp___fsm___width 1 +#define reg_iop_spu_rw_brp___fsm___bit 12 +#define reg_iop_spu_rw_brp___en___lsb 13 +#define reg_iop_spu_rw_brp___en___width 1 +#define reg_iop_spu_rw_brp___en___bit 13 +#define reg_iop_spu_rw_brp_offset 204 + + +/* Constants */ +#define regk_iop_spu_attn_hi 0x00000005 +#define regk_iop_spu_attn_lo 0x00000005 +#define regk_iop_spu_attn_r0 0x00000000 +#define regk_iop_spu_attn_r1 0x00000001 +#define regk_iop_spu_attn_r10 0x00000002 +#define regk_iop_spu_attn_r11 0x00000003 +#define regk_iop_spu_attn_r12 0x00000004 +#define regk_iop_spu_attn_r13 0x00000005 +#define regk_iop_spu_attn_r14 0x00000006 +#define regk_iop_spu_attn_r15 0x00000007 +#define regk_iop_spu_attn_r2 0x00000002 +#define regk_iop_spu_attn_r3 0x00000003 +#define regk_iop_spu_attn_r4 0x00000004 +#define regk_iop_spu_attn_r5 0x00000005 +#define regk_iop_spu_attn_r6 0x00000006 +#define regk_iop_spu_attn_r7 0x00000007 +#define regk_iop_spu_attn_r8 0x00000000 +#define regk_iop_spu_attn_r9 0x00000001 +#define regk_iop_spu_c 0x00000000 +#define regk_iop_spu_flag 0x00000002 +#define regk_iop_spu_gio_in 0x00000000 +#define regk_iop_spu_gio_out 0x00000005 +#define regk_iop_spu_gio_out0 0x00000008 +#define regk_iop_spu_gio_out1 0x00000009 +#define regk_iop_spu_gio_out2 0x0000000a +#define regk_iop_spu_gio_out3 0x0000000b +#define regk_iop_spu_gio_out4 0x0000000c +#define regk_iop_spu_gio_out5 0x0000000d +#define regk_iop_spu_gio_out6 0x0000000e +#define regk_iop_spu_gio_out7 0x0000000f +#define regk_iop_spu_n 0x00000003 +#define regk_iop_spu_no 0x00000000 +#define regk_iop_spu_r0 0x00000008 +#define regk_iop_spu_r1 0x00000009 +#define regk_iop_spu_r10 0x0000000a +#define regk_iop_spu_r11 0x0000000b +#define regk_iop_spu_r12 0x0000000c +#define regk_iop_spu_r13 0x0000000d +#define regk_iop_spu_r14 0x0000000e +#define regk_iop_spu_r15 0x0000000f +#define regk_iop_spu_r2 0x0000000a +#define regk_iop_spu_r3 0x0000000b +#define regk_iop_spu_r4 0x0000000c +#define regk_iop_spu_r5 0x0000000d +#define regk_iop_spu_r6 0x0000000e +#define regk_iop_spu_r7 0x0000000f +#define regk_iop_spu_r8 0x00000008 +#define regk_iop_spu_r9 0x00000009 +#define regk_iop_spu_reg_hi 0x00000002 +#define regk_iop_spu_reg_lo 0x00000002 +#define regk_iop_spu_rw_brp_default 0x00000000 +#define regk_iop_spu_rw_brp_size 0x00000004 +#define regk_iop_spu_rw_ctrl_default 0x00000000 +#define regk_iop_spu_rw_event_cfg_size 0x00000004 +#define regk_iop_spu_rw_event_mask_size 0x00000004 +#define regk_iop_spu_rw_event_val_size 0x00000004 +#define regk_iop_spu_rw_gio_out_default 0x00000000 +#define regk_iop_spu_rw_r_size 0x00000010 +#define regk_iop_spu_rw_reg_access_default 0x00000000 +#define regk_iop_spu_stat_in 0x00000002 +#define regk_iop_spu_statin_hi 0x00000004 +#define regk_iop_spu_statin_lo 0x00000004 +#define regk_iop_spu_trig 0x00000003 +#define regk_iop_spu_trigger 0x00000006 +#define regk_iop_spu_v 0x00000001 +#define regk_iop_spu_wsts_gioout_spec 0x00000001 +#define regk_iop_spu_xor 0x00000003 +#define regk_iop_spu_xor_bus0_r2_0 0x00000000 +#define regk_iop_spu_xor_bus0m_r2_0 0x00000002 +#define regk_iop_spu_xor_bus1_r3_0 0x00000001 +#define regk_iop_spu_xor_bus1m_r3_0 0x00000003 +#define regk_iop_spu_yes 0x00000001 +#define regk_iop_spu_z 0x00000002 +#endif /* __iop_spu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h new file mode 100644 index 000000000..3be60f9b0 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h @@ -0,0 +1,1052 @@ +#ifndef __iop_sw_cfg_defs_asm_h +#define __iop_sw_cfg_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 + +/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 + +/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 + +/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 + +/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 + +/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 + +/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 + +/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 + +/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 + +/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 + +/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 + +/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 + +/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 + +/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 + +/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 + +/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 + +/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 + +/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 + +/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_spu0_owner_offset 80 + +/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_spu1_owner_offset 84 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 + +/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 + +/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 + +/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus0_mask_offset 136 + +/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 + +/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus1_mask_offset 144 + +/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_mask_offset 152 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 +#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 +#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 +#define reg_iop_sw_cfg_rw_pinmapping_offset 160 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 +#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 + +/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 +#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 +#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 + +/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 +#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 +#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 + +/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 + +/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 +#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 + +/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 +#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 +#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 +#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 + +/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 +#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 +#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 +#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 + + +/* Constants */ +#define regk_iop_sw_cfg_a 0x00000001 +#define regk_iop_sw_cfg_b 0x00000002 +#define regk_iop_sw_cfg_bus0 0x00000000 +#define regk_iop_sw_cfg_bus0_rot16 0x00000004 +#define regk_iop_sw_cfg_bus0_rot24 0x00000006 +#define regk_iop_sw_cfg_bus0_rot8 0x00000002 +#define regk_iop_sw_cfg_bus1 0x00000001 +#define regk_iop_sw_cfg_bus1_rot16 0x00000005 +#define regk_iop_sw_cfg_bus1_rot24 0x00000007 +#define regk_iop_sw_cfg_bus1_rot8 0x00000003 +#define regk_iop_sw_cfg_clk12 0x00000000 +#define regk_iop_sw_cfg_cpu 0x00000000 +#define regk_iop_sw_cfg_dmc0 0x00000000 +#define regk_iop_sw_cfg_dmc1 0x00000001 +#define regk_iop_sw_cfg_gated_clk0 0x00000010 +#define regk_iop_sw_cfg_gated_clk1 0x00000011 +#define regk_iop_sw_cfg_gated_clk2 0x00000012 +#define regk_iop_sw_cfg_gated_clk3 0x00000013 +#define regk_iop_sw_cfg_gio0 0x00000004 +#define regk_iop_sw_cfg_gio1 0x00000001 +#define regk_iop_sw_cfg_gio2 0x00000005 +#define regk_iop_sw_cfg_gio3 0x00000002 +#define regk_iop_sw_cfg_gio4 0x00000006 +#define regk_iop_sw_cfg_gio5 0x00000003 +#define regk_iop_sw_cfg_gio6 0x00000007 +#define regk_iop_sw_cfg_gio7 0x00000004 +#define regk_iop_sw_cfg_gio_in0 0x00000000 +#define regk_iop_sw_cfg_gio_in1 0x00000001 +#define regk_iop_sw_cfg_gio_in10 0x00000002 +#define regk_iop_sw_cfg_gio_in11 0x00000003 +#define regk_iop_sw_cfg_gio_in14 0x00000004 +#define regk_iop_sw_cfg_gio_in15 0x00000005 +#define regk_iop_sw_cfg_gio_in18 0x00000002 +#define regk_iop_sw_cfg_gio_in19 0x00000003 +#define regk_iop_sw_cfg_gio_in20 0x00000004 +#define regk_iop_sw_cfg_gio_in21 0x00000005 +#define regk_iop_sw_cfg_gio_in26 0x00000006 +#define regk_iop_sw_cfg_gio_in27 0x00000007 +#define regk_iop_sw_cfg_gio_in28 0x00000006 +#define regk_iop_sw_cfg_gio_in29 0x00000007 +#define regk_iop_sw_cfg_gio_in4 0x00000000 +#define regk_iop_sw_cfg_gio_in5 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 +#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 +#define regk_iop_sw_cfg_mpu 0x00000001 +#define regk_iop_sw_cfg_none 0x00000000 +#define regk_iop_sw_cfg_par0 0x00000000 +#define regk_iop_sw_cfg_par1 0x00000001 +#define regk_iop_sw_cfg_pdp_out0 0x00000002 +#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 +#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 +#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 +#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 +#define regk_iop_sw_cfg_pdp_out1 0x00000003 +#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 +#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 +#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 +#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 +#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 +#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 +#define regk_iop_sw_cfg_sdp_out0 0x00000008 +#define regk_iop_sw_cfg_sdp_out1 0x00000009 +#define regk_iop_sw_cfg_size16 0x00000002 +#define regk_iop_sw_cfg_size24 0x00000003 +#define regk_iop_sw_cfg_size32 0x00000004 +#define regk_iop_sw_cfg_size8 0x00000001 +#define regk_iop_sw_cfg_spu0 0x00000002 +#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 +#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 +#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 +#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 +#define regk_iop_sw_cfg_spu0_g0 0x0000000e +#define regk_iop_sw_cfg_spu0_g1 0x0000000e +#define regk_iop_sw_cfg_spu0_g2 0x0000000e +#define regk_iop_sw_cfg_spu0_g3 0x0000000e +#define regk_iop_sw_cfg_spu0_g4 0x0000000e +#define regk_iop_sw_cfg_spu0_g5 0x0000000e +#define regk_iop_sw_cfg_spu0_g6 0x0000000e +#define regk_iop_sw_cfg_spu0_g7 0x0000000e +#define regk_iop_sw_cfg_spu0_gio0 0x00000000 +#define regk_iop_sw_cfg_spu0_gio1 0x00000001 +#define regk_iop_sw_cfg_spu0_gio2 0x00000000 +#define regk_iop_sw_cfg_spu0_gio5 0x00000005 +#define regk_iop_sw_cfg_spu0_gio6 0x00000006 +#define regk_iop_sw_cfg_spu0_gio7 0x00000007 +#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu0_gioout0 0x00000000 +#define regk_iop_sw_cfg_spu0_gioout1 0x00000000 +#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout2 0x00000002 +#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout3 0x00000002 +#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout4 0x00000004 +#define regk_iop_sw_cfg_spu0_gioout5 0x00000004 +#define regk_iop_sw_cfg_spu0_gioout6 0x00000006 +#define regk_iop_sw_cfg_spu0_gioout7 0x00000006 +#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e +#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e +#define regk_iop_sw_cfg_spu1 0x00000003 +#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 +#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 +#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 +#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 +#define regk_iop_sw_cfg_spu1_g0 0x0000000f +#define regk_iop_sw_cfg_spu1_g1 0x0000000f +#define regk_iop_sw_cfg_spu1_g2 0x0000000f +#define regk_iop_sw_cfg_spu1_g3 0x0000000f +#define regk_iop_sw_cfg_spu1_g4 0x0000000f +#define regk_iop_sw_cfg_spu1_g5 0x0000000f +#define regk_iop_sw_cfg_spu1_g6 0x0000000f +#define regk_iop_sw_cfg_spu1_g7 0x0000000f +#define regk_iop_sw_cfg_spu1_gio0 0x00000002 +#define regk_iop_sw_cfg_spu1_gio1 0x00000003 +#define regk_iop_sw_cfg_spu1_gio2 0x00000002 +#define regk_iop_sw_cfg_spu1_gio5 0x00000005 +#define regk_iop_sw_cfg_spu1_gio6 0x00000006 +#define regk_iop_sw_cfg_spu1_gio7 0x00000007 +#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout0 0x00000001 +#define regk_iop_sw_cfg_spu1_gioout1 0x00000001 +#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout2 0x00000003 +#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout3 0x00000003 +#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout4 0x00000005 +#define regk_iop_sw_cfg_spu1_gioout5 0x00000005 +#define regk_iop_sw_cfg_spu1_gioout6 0x00000007 +#define regk_iop_sw_cfg_spu1_gioout7 0x00000007 +#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f +#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f +#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 +#define regk_iop_sw_cfg_timer_grp0 0x00000000 +#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a +#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 +#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 +#define regk_iop_sw_cfg_timer_grp1 0x00000000 +#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b +#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 +#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 +#define regk_iop_sw_cfg_timer_grp2 0x00000000 +#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c +#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 +#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 +#define regk_iop_sw_cfg_timer_grp3 0x00000000 +#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d +#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 +#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 +#define regk_iop_sw_cfg_trig0_0 0x00000000 +#define regk_iop_sw_cfg_trig0_1 0x00000000 +#define regk_iop_sw_cfg_trig0_2 0x00000000 +#define regk_iop_sw_cfg_trig0_3 0x00000000 +#define regk_iop_sw_cfg_trig1_0 0x00000000 +#define regk_iop_sw_cfg_trig1_1 0x00000000 +#define regk_iop_sw_cfg_trig1_2 0x00000000 +#define regk_iop_sw_cfg_trig1_3 0x00000000 +#define regk_iop_sw_cfg_trig2_0 0x00000000 +#define regk_iop_sw_cfg_trig2_1 0x00000000 +#define regk_iop_sw_cfg_trig2_2 0x00000000 +#define regk_iop_sw_cfg_trig2_3 0x00000000 +#define regk_iop_sw_cfg_trig3_0 0x00000000 +#define regk_iop_sw_cfg_trig3_1 0x00000000 +#define regk_iop_sw_cfg_trig3_2 0x00000000 +#define regk_iop_sw_cfg_trig3_3 0x00000000 +#define regk_iop_sw_cfg_trig4_0 0x00000001 +#define regk_iop_sw_cfg_trig4_1 0x00000001 +#define regk_iop_sw_cfg_trig4_2 0x00000001 +#define regk_iop_sw_cfg_trig4_3 0x00000001 +#define regk_iop_sw_cfg_trig5_0 0x00000001 +#define regk_iop_sw_cfg_trig5_1 0x00000001 +#define regk_iop_sw_cfg_trig5_2 0x00000001 +#define regk_iop_sw_cfg_trig5_3 0x00000001 +#define regk_iop_sw_cfg_trig6_0 0x00000001 +#define regk_iop_sw_cfg_trig6_1 0x00000001 +#define regk_iop_sw_cfg_trig6_2 0x00000001 +#define regk_iop_sw_cfg_trig6_3 0x00000001 +#define regk_iop_sw_cfg_trig7_0 0x00000001 +#define regk_iop_sw_cfg_trig7_1 0x00000001 +#define regk_iop_sw_cfg_trig7_2 0x00000001 +#define regk_iop_sw_cfg_trig7_3 0x00000001 +#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h new file mode 100644 index 000000000..db347bcba --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h @@ -0,0 +1,1758 @@ +#ifndef __iop_sw_cpu_defs_asm_h +#define __iop_sw_cpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_cpu_rw_mc_data___val___width 32 +#define reg_iop_sw_cpu_rw_mc_data_offset 4 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_addr_offset 8 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +#define reg_iop_sw_cpu_rs_mc_data_offset 12 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_data_offset 16 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_cpu_r_mc_stat_offset 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 + +/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 + +/* Register r_bus0_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus0_in_offset 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 + +/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 + +/* Register r_bus1_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus1_in_offset 60 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_gio_in_offset 80 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 +#define reg_iop_sw_cpu_rw_intr0_mask_offset 84 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr0_offset 88 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_r_intr0_offset 92 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 +#define reg_iop_sw_cpu_r_masked_intr0_offset 96 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 +#define reg_iop_sw_cpu_rw_intr1_mask_offset 100 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr1_offset 104 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_r_intr1_offset 108 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 +#define reg_iop_sw_cpu_r_masked_intr1_offset 112 + +/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 +#define reg_iop_sw_cpu_rw_intr2_mask_offset 116 + +/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr2_offset 120 + +/* Register r_intr2, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 +#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 +#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_intr2_offset 124 + +/* Register r_masked_intr2, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_masked_intr2_offset 128 + +/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 +#define reg_iop_sw_cpu_rw_intr3_mask_offset 132 + +/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr3_offset 136 + +/* Register r_intr3, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 +#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 +#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 +#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 +#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 +#define reg_iop_sw_cpu_r_intr3_offset 140 + +/* Register r_masked_intr3, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 +#define reg_iop_sw_cpu_r_masked_intr3_offset 144 + + +/* Constants */ +#define regk_iop_sw_cpu_copy 0x00000000 +#define regk_iop_sw_cpu_no 0x00000000 +#define regk_iop_sw_cpu_rd 0x00000002 +#define regk_iop_sw_cpu_reg_copy 0x00000001 +#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 +#define regk_iop_sw_cpu_wr 0x00000003 +#define regk_iop_sw_cpu_yes 0x00000001 +#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h new file mode 100644 index 000000000..ee7dc0435 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h @@ -0,0 +1,1776 @@ +#ifndef __iop_sw_mpu_defs_asm_h +#define __iop_sw_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 +#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_mpu_rw_mc_data___val___width 32 +#define reg_iop_sw_mpu_rw_mc_data_offset 8 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_addr_offset 12 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +#define reg_iop_sw_mpu_rs_mc_data_offset 16 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_data_offset 20 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_mpu_r_mc_stat_offset 24 + +/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 + +/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 + +/* Register r_bus0_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus0_in_offset 44 + +/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 + +/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 + +/* Register r_bus1_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus1_in_offset 64 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_gio_in_offset 84 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_rw_cpu_intr_offset 88 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_r_cpu_intr_offset 92 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp0_offset 104 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp1_offset 120 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp2_offset 136 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 +#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_intr_grp3_offset 152 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 +#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 + + +/* Constants */ +#define regk_iop_sw_mpu_copy 0x00000000 +#define regk_iop_sw_mpu_cpu 0x00000000 +#define regk_iop_sw_mpu_mpu 0x00000001 +#define regk_iop_sw_mpu_no 0x00000000 +#define regk_iop_sw_mpu_nop 0x00000000 +#define regk_iop_sw_mpu_rd 0x00000002 +#define regk_iop_sw_mpu_reg_copy 0x00000001 +#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 +#define regk_iop_sw_mpu_set 0x00000001 +#define regk_iop_sw_mpu_spu0 0x00000002 +#define regk_iop_sw_mpu_spu1 0x00000003 +#define regk_iop_sw_mpu_wr 0x00000003 +#define regk_iop_sw_mpu_yes 0x00000001 +#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h new file mode 100644 index 000000000..0929f144c --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h @@ -0,0 +1,691 @@ +#ifndef __iop_sw_spu_defs_asm_h +#define __iop_sw_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 +#define reg_iop_sw_spu_rw_mc_ctrl_offset 0 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_spu_rw_mc_data___val___width 32 +#define reg_iop_sw_spu_rw_mc_data_offset 4 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_addr_offset 8 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +#define reg_iop_sw_spu_rs_mc_data_offset 12 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_data_offset 16 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 +#define reg_iop_sw_spu_r_mc_stat_offset 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 + +/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 + +/* Register r_bus0_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus0_in_offset 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 + +/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 + +/* Register r_bus1_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus1_in_offset 60 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_set_mask_offset 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_gio_in_offset 80 + +/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 + +/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 + +/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 + +/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 + +/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 + +/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 + +/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 + +/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_cpu_intr_offset 148 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_cpu_intr_offset 152 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 +#define reg_iop_sw_spu_r_hw_intr_offset 156 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_mpu_intr_offset 160 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 +#define reg_iop_sw_spu_r_mpu_intr_offset 164 + + +/* Constants */ +#define regk_iop_sw_spu_copy 0x00000000 +#define regk_iop_sw_spu_no 0x00000000 +#define regk_iop_sw_spu_nop 0x00000000 +#define regk_iop_sw_spu_rd 0x00000002 +#define regk_iop_sw_spu_reg_copy 0x00000001 +#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_spu_set 0x00000001 +#define regk_iop_sw_spu_wr 0x00000003 +#define regk_iop_sw_spu_yes 0x00000001 +#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h new file mode 100644 index 000000000..7129a9a4b --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h @@ -0,0 +1,237 @@ +#ifndef __iop_timer_grp_defs_asm_h +#define __iop_timer_grp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_timer_grp.r + * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r + * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0 +#define reg_iop_timer_grp_rw_cfg___clk_src___width 1 +#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0 +#define reg_iop_timer_grp_rw_cfg___trig___lsb 1 +#define reg_iop_timer_grp_rw_cfg___trig___width 2 +#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3 +#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8 +#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11 +#define reg_iop_timer_grp_rw_cfg___clk_div___width 8 +#define reg_iop_timer_grp_rw_cfg_offset 0 + +/* Register rw_half_period, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0 +#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1 +#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30 +#define reg_iop_timer_grp_rw_half_period_offset 4 + +/* Register rw_half_period_len, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_half_period_len_offset 8 + +#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 +/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0 +#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3 +#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3 +#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5 +#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7 +#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8 +#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10 +#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11 +#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1 +#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17 +#define reg_iop_timer_grp_rw_tmr_cfg_offset 12 + +#define STRIDE_iop_timer_grp_rw_tmr_len 4 +/* Register rw_tmr_len, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0 +#define reg_iop_timer_grp_rw_tmr_len___val___width 16 +#define reg_iop_timer_grp_rw_tmr_len_offset 44 + +/* Register rw_cmd, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_cmd___rst___lsb 0 +#define reg_iop_timer_grp_rw_cmd___rst___width 4 +#define reg_iop_timer_grp_rw_cmd___en___lsb 4 +#define reg_iop_timer_grp_rw_cmd___en___width 4 +#define reg_iop_timer_grp_rw_cmd___dis___lsb 8 +#define reg_iop_timer_grp_rw_cmd___dis___width 4 +#define reg_iop_timer_grp_rw_cmd___strb___lsb 12 +#define reg_iop_timer_grp_rw_cmd___strb___width 4 +#define reg_iop_timer_grp_rw_cmd_offset 60 + +/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64 + +#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 +/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ +#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0 +#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16 +#define reg_iop_timer_grp_rs_tmr_cnt_offset 68 + +#define STRIDE_iop_timer_grp_r_tmr_cnt 8 +/* Register r_tmr_cnt, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0 +#define reg_iop_timer_grp_r_tmr_cnt___val___width 16 +#define reg_iop_timer_grp_r_tmr_cnt_offset 72 + +/* Register rw_intr_mask, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0 +#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1 +#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3 +#define reg_iop_timer_grp_rw_intr_mask_offset 100 + +/* Register rw_ack_intr, scope iop_timer_grp, type rw */ +#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1 +#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3 +#define reg_iop_timer_grp_rw_ack_intr_offset 104 + +/* Register r_intr, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_r_intr___tmr0___width 1 +#define reg_iop_timer_grp_r_intr___tmr0___bit 0 +#define reg_iop_timer_grp_r_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_r_intr___tmr1___width 1 +#define reg_iop_timer_grp_r_intr___tmr1___bit 1 +#define reg_iop_timer_grp_r_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_r_intr___tmr2___width 1 +#define reg_iop_timer_grp_r_intr___tmr2___bit 2 +#define reg_iop_timer_grp_r_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_r_intr___tmr3___width 1 +#define reg_iop_timer_grp_r_intr___tmr3___bit 3 +#define reg_iop_timer_grp_r_intr_offset 108 + +/* Register r_masked_intr, scope iop_timer_grp, type r */ +#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0 +#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0 +#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1 +#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1 +#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2 +#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2 +#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3 +#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1 +#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3 +#define reg_iop_timer_grp_r_masked_intr_offset 112 + + +/* Constants */ +#define regk_iop_timer_grp_clk200 0x00000000 +#define regk_iop_timer_grp_clk_gen 0x00000002 +#define regk_iop_timer_grp_complete 0x00000002 +#define regk_iop_timer_grp_div_clk200 0x00000001 +#define regk_iop_timer_grp_div_clk_gen 0x00000003 +#define regk_iop_timer_grp_ext 0x00000001 +#define regk_iop_timer_grp_hi 0x00000000 +#define regk_iop_timer_grp_long_period 0x00000001 +#define regk_iop_timer_grp_neg 0x00000002 +#define regk_iop_timer_grp_no 0x00000000 +#define regk_iop_timer_grp_once 0x00000003 +#define regk_iop_timer_grp_pause 0x00000001 +#define regk_iop_timer_grp_pos 0x00000001 +#define regk_iop_timer_grp_pos_neg 0x00000003 +#define regk_iop_timer_grp_pulse 0x00000000 +#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004 +#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004 +#define regk_iop_timer_grp_rw_cfg_default 0x00000002 +#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000 +#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000 +#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900 +#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200 +#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00 +#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004 +#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000 +#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004 +#define regk_iop_timer_grp_short_period 0x00000000 +#define regk_iop_timer_grp_stop 0x00000000 +#define regk_iop_timer_grp_tmr 0x00000004 +#define regk_iop_timer_grp_toggle 0x00000001 +#define regk_iop_timer_grp_yes 0x00000001 +#endif /* __iop_timer_grp_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h new file mode 100644 index 000000000..1005d9db8 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h @@ -0,0 +1,157 @@ +#ifndef __iop_trigger_grp_defs_asm_h +#define __iop_trigger_grp_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_trigger_grp_rw_cfg 4 +/* Register rw_cfg, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_cfg___action___lsb 0 +#define reg_iop_trigger_grp_rw_cfg___action___width 2 +#define reg_iop_trigger_grp_rw_cfg___once___lsb 2 +#define reg_iop_trigger_grp_rw_cfg___once___width 1 +#define reg_iop_trigger_grp_rw_cfg___once___bit 2 +#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 +#define reg_iop_trigger_grp_rw_cfg___trig___width 3 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 +#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 +#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 +#define reg_iop_trigger_grp_rw_cfg_offset 0 + +/* Register rw_cmd, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 +#define reg_iop_trigger_grp_rw_cmd___dis___width 4 +#define reg_iop_trigger_grp_rw_cmd___en___lsb 4 +#define reg_iop_trigger_grp_rw_cmd___en___width 4 +#define reg_iop_trigger_grp_rw_cmd_offset 16 + +/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 +#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 +#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 +#define reg_iop_trigger_grp_rw_intr_mask_offset 20 + +/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ +#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 +#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 +#define reg_iop_trigger_grp_rw_ack_intr_offset 24 + +/* Register r_intr, scope iop_trigger_grp, type r */ +#define reg_iop_trigger_grp_r_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_r_intr___trig0___width 1 +#define reg_iop_trigger_grp_r_intr___trig0___bit 0 +#define reg_iop_trigger_grp_r_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_r_intr___trig1___width 1 +#define reg_iop_trigger_grp_r_intr___trig1___bit 1 +#define reg_iop_trigger_grp_r_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_r_intr___trig2___width 1 +#define reg_iop_trigger_grp_r_intr___trig2___bit 2 +#define reg_iop_trigger_grp_r_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_r_intr___trig3___width 1 +#define reg_iop_trigger_grp_r_intr___trig3___bit 3 +#define reg_iop_trigger_grp_r_intr_offset 28 + +/* Register r_masked_intr, scope iop_trigger_grp, type r */ +#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 +#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 +#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 +#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 +#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 +#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 +#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 +#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 +#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 +#define reg_iop_trigger_grp_r_masked_intr_offset 32 + + +/* Constants */ +#define regk_iop_trigger_grp_fall 0x00000002 +#define regk_iop_trigger_grp_fall_lo 0x00000006 +#define regk_iop_trigger_grp_no 0x00000000 +#define regk_iop_trigger_grp_off 0x00000000 +#define regk_iop_trigger_grp_pulse 0x00000000 +#define regk_iop_trigger_grp_rise 0x00000001 +#define regk_iop_trigger_grp_rise_fall 0x00000003 +#define regk_iop_trigger_grp_rise_fall_hi 0x00000007 +#define regk_iop_trigger_grp_rise_fall_lo 0x00000004 +#define regk_iop_trigger_grp_rise_hi 0x00000005 +#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 +#define regk_iop_trigger_grp_rw_cfg_size 0x00000004 +#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 +#define regk_iop_trigger_grp_toggle 0x00000003 +#define regk_iop_trigger_grp_yes 0x00000001 +#endif /* __iop_trigger_grp_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h new file mode 100644 index 000000000..e13feb20a --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h @@ -0,0 +1,64 @@ +#ifndef __iop_version_defs_asm_h +#define __iop_version_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_version.r + * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp + * last modfied: Mon Apr 11 16:08:44 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r + * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_version, scope iop_version, type r */ +#define reg_iop_version_r_version___nr___lsb 0 +#define reg_iop_version_r_version___nr___width 8 +#define reg_iop_version_r_version_offset 0 + + +/* Constants */ +#define regk_iop_version_v1_0 0x00000001 +#endif /* __iop_version_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h new file mode 100644 index 000000000..90e4785b6 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h @@ -0,0 +1,232 @@ +#ifndef __iop_crc_par_defs_h +#define __iop_crc_par_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_crc_par.r + * id: + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r + * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_crc_par */ + +/* Register rw_cfg, scope iop_crc_par, type rw */ +typedef struct { + unsigned int mode : 1; + unsigned int crc_out : 1; + unsigned int rev_out : 1; + unsigned int inv_out : 1; + unsigned int trig : 2; + unsigned int poly : 3; + unsigned int dummy1 : 23; +} reg_iop_crc_par_rw_cfg; +#define REG_RD_ADDR_iop_crc_par_rw_cfg 0 +#define REG_WR_ADDR_iop_crc_par_rw_cfg 0 + +/* Register rw_init_crc, scope iop_crc_par, type rw */ +typedef unsigned int reg_iop_crc_par_rw_init_crc; +#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 +#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 + +/* Register rw_correct_crc, scope iop_crc_par, type rw */ +typedef unsigned int reg_iop_crc_par_rw_correct_crc; +#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 +#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 + +/* Register rw_ctrl, scope iop_crc_par, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_iop_crc_par_rw_ctrl; +#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 +#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 + +/* Register rw_set_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int tr_dif : 1; + unsigned int dummy1 : 31; +} reg_iop_crc_par_rw_set_last; +#define REG_RD_ADDR_iop_crc_par_rw_set_last 16 +#define REG_WR_ADDR_iop_crc_par_rw_set_last 16 + +/* Register rw_wr1byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_crc_par_rw_wr1byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 +#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 + +/* Register rw_wr2byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_crc_par_rw_wr2byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 +#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 + +/* Register rw_wr3byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_crc_par_rw_wr3byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 +#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 + +/* Register rw_wr4byte, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_crc_par_rw_wr4byte; +#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 +#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 + +/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_crc_par_rw_wr1byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 +#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 + +/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_crc_par_rw_wr2byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 +#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 + +/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_crc_par_rw_wr3byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 +#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 + +/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_crc_par_rw_wr4byte_last; +#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 +#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 + +/* Register r_stat, scope iop_crc_par, type r */ +typedef struct { + unsigned int err : 1; + unsigned int busy : 1; + unsigned int dummy1 : 30; +} reg_iop_crc_par_r_stat; +#define REG_RD_ADDR_iop_crc_par_r_stat 52 + +/* Register r_sh_reg, scope iop_crc_par, type r */ +typedef unsigned int reg_iop_crc_par_r_sh_reg; +#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 + +/* Register r_crc, scope iop_crc_par, type r */ +typedef unsigned int reg_iop_crc_par_r_crc; +#define REG_RD_ADDR_iop_crc_par_r_crc 60 + +/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_crc_par_rw_strb_rec_dif_in; +#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 +#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 + + +/* Constants */ +enum { + regk_iop_crc_par_calc = 0x00000001, + regk_iop_crc_par_ccitt = 0x00000002, + regk_iop_crc_par_check = 0x00000000, + regk_iop_crc_par_crc16 = 0x00000001, + regk_iop_crc_par_crc32 = 0x00000000, + regk_iop_crc_par_crc5 = 0x00000003, + regk_iop_crc_par_crc5_11 = 0x00000004, + regk_iop_crc_par_dif_in = 0x00000002, + regk_iop_crc_par_hi = 0x00000000, + regk_iop_crc_par_neg = 0x00000002, + regk_iop_crc_par_no = 0x00000000, + regk_iop_crc_par_pos = 0x00000001, + regk_iop_crc_par_pos_neg = 0x00000003, + regk_iop_crc_par_rw_cfg_default = 0x00000000, + regk_iop_crc_par_rw_ctrl_default = 0x00000000, + regk_iop_crc_par_yes = 0x00000001 +}; +#endif /* __iop_crc_par_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h new file mode 100644 index 000000000..76aec6e37 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h @@ -0,0 +1,325 @@ +#ifndef __iop_dmc_in_defs_h +#define __iop_dmc_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_in.r + * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r + * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_dmc_in */ + +/* Register rw_cfg, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int sth_intr : 3; + unsigned int last_dis_dif : 1; + unsigned int dummy1 : 28; +} reg_iop_dmc_in_rw_cfg; +#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 +#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dif_dis : 1; + unsigned int stream_clr : 1; + unsigned int dummy1 : 29; +} reg_iop_dmc_in_rw_ctrl; +#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 + +/* Register r_stat, scope iop_dmc_in, type r */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dummy1 : 31; +} reg_iop_dmc_in_r_stat; +#define REG_RD_ADDR_iop_dmc_in_r_stat 8 + +/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 8; +} reg_iop_dmc_in_rw_stream_cmd; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 + +/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 + +/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 + +/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int eop : 1; + unsigned int wait : 1; + unsigned int keep_md : 1; + unsigned int size : 3; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_stream_ctrl; +#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 +#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 + +/* Register r_stream_stat, scope iop_dmc_in, type r */ +typedef struct { + unsigned int sth : 7; + unsigned int dummy1 : 9; + unsigned int full : 1; + unsigned int last_pkt : 1; + unsigned int data_md_valid : 1; + unsigned int ctxt_md_valid : 1; + unsigned int group_md_valid : 1; + unsigned int stream_busy : 1; + unsigned int cmd_rdy : 1; + unsigned int dummy2 : 9; +} reg_iop_dmc_in_r_stream_stat; +#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 + +/* Register r_data_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_in_r_data_descr; +#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 + +/* Register r_ctxt_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md0 : 16; +} reg_iop_dmc_in_r_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 + +/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ +typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 + +/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ +typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 + +/* Register r_group_descr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_in_r_group_descr; +#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 + +/* Register rw_data_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_in_rw_data_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 +#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 + +/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md0 : 16; +} reg_iop_dmc_in_rw_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ +typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 +#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 + +/* Register rw_group_descr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_in_rw_group_descr; +#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 +#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 + +/* Register rw_intr_mask, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_intr_mask; +#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 +#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 + +/* Register rw_ack_intr, scope iop_dmc_in, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_rw_ack_intr; +#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 +#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 + +/* Register r_intr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_r_intr; +#define REG_RD_ADDR_iop_dmc_in_r_intr 96 + +/* Register r_masked_intr, scope iop_dmc_in, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int sth : 1; + unsigned int full : 1; + unsigned int dummy1 : 26; +} reg_iop_dmc_in_r_masked_intr; +#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 + + +/* Constants */ +enum { + regk_iop_dmc_in_ack_pkt = 0x00000100, + regk_iop_dmc_in_array = 0x00000008, + regk_iop_dmc_in_burst = 0x00000020, + regk_iop_dmc_in_copy_next = 0x00000010, + regk_iop_dmc_in_copy_up = 0x00000020, + regk_iop_dmc_in_dis_c = 0x00000010, + regk_iop_dmc_in_dis_g = 0x00000020, + regk_iop_dmc_in_lim1 = 0x00000000, + regk_iop_dmc_in_lim16 = 0x00000004, + regk_iop_dmc_in_lim2 = 0x00000001, + regk_iop_dmc_in_lim32 = 0x00000005, + regk_iop_dmc_in_lim4 = 0x00000002, + regk_iop_dmc_in_lim64 = 0x00000006, + regk_iop_dmc_in_lim8 = 0x00000003, + regk_iop_dmc_in_load_c = 0x00000200, + regk_iop_dmc_in_load_c_n = 0x00000280, + regk_iop_dmc_in_load_c_next = 0x00000240, + regk_iop_dmc_in_load_d = 0x00000140, + regk_iop_dmc_in_load_g = 0x00000300, + regk_iop_dmc_in_load_g_down = 0x000003c0, + regk_iop_dmc_in_load_g_next = 0x00000340, + regk_iop_dmc_in_load_g_up = 0x00000380, + regk_iop_dmc_in_next_en = 0x00000010, + regk_iop_dmc_in_next_pkt = 0x00000010, + regk_iop_dmc_in_no = 0x00000000, + regk_iop_dmc_in_restore = 0x00000020, + regk_iop_dmc_in_rw_cfg_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, + regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, + regk_iop_dmc_in_rw_data_descr_default = 0x00000000, + regk_iop_dmc_in_rw_group_descr_default = 0x00000000, + regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, + regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, + regk_iop_dmc_in_save_down = 0x00000020, + regk_iop_dmc_in_save_up = 0x00000020, + regk_iop_dmc_in_set_reg = 0x00000050, + regk_iop_dmc_in_set_w_size1 = 0x00000190, + regk_iop_dmc_in_set_w_size2 = 0x000001a0, + regk_iop_dmc_in_set_w_size4 = 0x000001c0, + regk_iop_dmc_in_store_c = 0x00000002, + regk_iop_dmc_in_store_descr = 0x00000000, + regk_iop_dmc_in_store_g = 0x00000004, + regk_iop_dmc_in_store_md = 0x00000001, + regk_iop_dmc_in_update_down = 0x00000020, + regk_iop_dmc_in_yes = 0x00000001 +}; +#endif /* __iop_dmc_in_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h new file mode 100644 index 000000000..938a0d4c4 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h @@ -0,0 +1,326 @@ +#ifndef __iop_dmc_out_defs_h +#define __iop_dmc_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_dmc_out.r + * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r + * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_dmc_out */ + +/* Register rw_cfg, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int trf_lim : 16; + unsigned int last_at_trf_lim : 1; + unsigned int dth_intr : 3; + unsigned int dummy1 : 12; +} reg_iop_dmc_out_rw_cfg; +#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0 +#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dif_dis : 1; + unsigned int dummy1 : 30; +} reg_iop_dmc_out_rw_ctrl; +#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4 + +/* Register r_stat, scope iop_dmc_out, type r */ +typedef struct { + unsigned int dif_en : 1; + unsigned int dummy1 : 31; +} reg_iop_dmc_out_r_stat; +#define REG_RD_ADDR_iop_dmc_out_r_stat 8 + +/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int cmd : 10; + unsigned int dummy1 : 6; + unsigned int n : 8; + unsigned int dummy2 : 8; +} reg_iop_dmc_out_rw_stream_cmd; +#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12 +#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12 + +/* Register rs_stream_data, scope iop_dmc_out, type rs */ +typedef unsigned int reg_iop_dmc_out_rs_stream_data; +#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16 + +/* Register r_stream_data, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_stream_data; +#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20 + +/* Register r_stream_stat, scope iop_dmc_out, type r */ +typedef struct { + unsigned int dth : 7; + unsigned int dummy1 : 9; + unsigned int dv : 1; + unsigned int all_avail : 1; + unsigned int last : 1; + unsigned int size : 3; + unsigned int data_md_valid : 1; + unsigned int ctxt_md_valid : 1; + unsigned int group_md_valid : 1; + unsigned int stream_busy : 1; + unsigned int cmd_rdy : 1; + unsigned int cmd_rq : 1; + unsigned int dummy2 : 4; +} reg_iop_dmc_out_r_stream_stat; +#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24 + +/* Register r_data_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_out_r_data_descr; +#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28 + +/* Register r_ctxt_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md0 : 16; +} reg_iop_dmc_out_r_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32 + +/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36 + +/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ +typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40 + +/* Register r_group_descr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int ctrl : 8; + unsigned int stat : 8; + unsigned int md : 16; +} reg_iop_dmc_out_r_group_descr; +#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52 + +/* Register rw_data_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_out_rw_data_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56 +#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56 + +/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md0 : 16; +} reg_iop_dmc_out_rw_ctxt_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60 + +/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ +typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 + +/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ +typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2; +#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 +#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 + +/* Register rw_group_descr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int dummy1 : 16; + unsigned int md : 16; +} reg_iop_dmc_out_rw_group_descr; +#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80 +#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80 + +/* Register rw_intr_mask, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_rw_intr_mask; +#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84 +#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84 + +/* Register rw_ack_intr, scope iop_dmc_out, type rw */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_rw_ack_intr; +#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88 +#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88 + +/* Register r_intr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_r_intr; +#define REG_RD_ADDR_iop_dmc_out_r_intr 92 + +/* Register r_masked_intr, scope iop_dmc_out, type r */ +typedef struct { + unsigned int data_md : 1; + unsigned int ctxt_md : 1; + unsigned int group_md : 1; + unsigned int cmd_rdy : 1; + unsigned int dth : 1; + unsigned int dv : 1; + unsigned int last_data : 1; + unsigned int trf_lim : 1; + unsigned int cmd_rq : 1; + unsigned int dummy1 : 23; +} reg_iop_dmc_out_r_masked_intr; +#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96 + + +/* Constants */ +enum { + regk_iop_dmc_out_ack_pkt = 0x00000100, + regk_iop_dmc_out_array = 0x00000008, + regk_iop_dmc_out_burst = 0x00000020, + regk_iop_dmc_out_copy_next = 0x00000010, + regk_iop_dmc_out_copy_up = 0x00000020, + regk_iop_dmc_out_dis_c = 0x00000010, + regk_iop_dmc_out_dis_g = 0x00000020, + regk_iop_dmc_out_lim1 = 0x00000000, + regk_iop_dmc_out_lim16 = 0x00000004, + regk_iop_dmc_out_lim2 = 0x00000001, + regk_iop_dmc_out_lim32 = 0x00000005, + regk_iop_dmc_out_lim4 = 0x00000002, + regk_iop_dmc_out_lim64 = 0x00000006, + regk_iop_dmc_out_lim8 = 0x00000003, + regk_iop_dmc_out_load_c = 0x00000200, + regk_iop_dmc_out_load_c_n = 0x00000280, + regk_iop_dmc_out_load_c_next = 0x00000240, + regk_iop_dmc_out_load_d = 0x00000140, + regk_iop_dmc_out_load_g = 0x00000300, + regk_iop_dmc_out_load_g_down = 0x000003c0, + regk_iop_dmc_out_load_g_next = 0x00000340, + regk_iop_dmc_out_load_g_up = 0x00000380, + regk_iop_dmc_out_next_en = 0x00000010, + regk_iop_dmc_out_next_pkt = 0x00000010, + regk_iop_dmc_out_no = 0x00000000, + regk_iop_dmc_out_restore = 0x00000020, + regk_iop_dmc_out_rw_cfg_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000, + regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000, + regk_iop_dmc_out_rw_data_descr_default = 0x00000000, + regk_iop_dmc_out_rw_group_descr_default = 0x00000000, + regk_iop_dmc_out_rw_intr_mask_default = 0x00000000, + regk_iop_dmc_out_save_down = 0x00000020, + regk_iop_dmc_out_save_up = 0x00000020, + regk_iop_dmc_out_set_reg = 0x00000050, + regk_iop_dmc_out_set_w_size1 = 0x00000190, + regk_iop_dmc_out_set_w_size2 = 0x000001a0, + regk_iop_dmc_out_set_w_size4 = 0x000001c0, + regk_iop_dmc_out_store_c = 0x00000002, + regk_iop_dmc_out_store_descr = 0x00000000, + regk_iop_dmc_out_store_g = 0x00000004, + regk_iop_dmc_out_store_md = 0x00000001, + regk_iop_dmc_out_update_down = 0x00000020, + regk_iop_dmc_out_yes = 0x00000001 +}; +#endif /* __iop_dmc_out_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h new file mode 100644 index 000000000..e0c982b26 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h @@ -0,0 +1,255 @@ +#ifndef __iop_fifo_in_defs_h +#define __iop_fifo_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in.r + * id: + * last modfied: Mon Apr 11 16:10:07 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r + * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_in */ + +/* Register rw_cfg, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int avail_lim : 3; + unsigned int byte_order : 2; + unsigned int trig : 2; + unsigned int last_dis_dif_in : 1; + unsigned int mode : 2; + unsigned int dummy1 : 22; +} reg_iop_fifo_in_rw_cfg; +#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 +#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_rw_ctrl; +#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 + +/* Register r_stat, scope iop_fifo_in, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 18; +} reg_iop_fifo_in_r_stat; +#define REG_RD_ADDR_iop_fifo_in_r_stat 8 + +/* Register rs_rd1byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_in_rs_rd1byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 + +/* Register r_rd1byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_in_r_rd1byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 + +/* Register rs_rd2byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_in_rs_rd2byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 + +/* Register r_rd2byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_in_r_rd2byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 + +/* Register rs_rd3byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_in_rs_rd3byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 + +/* Register r_rd3byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_in_r_rd3byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 + +/* Register rs_rd4byte, scope iop_fifo_in, type rs */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_in_rs_rd4byte; +#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 + +/* Register r_rd4byte, scope iop_fifo_in, type r */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_in_r_rd4byte; +#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 + +/* Register rw_set_last, scope iop_fifo_in, type rw */ +typedef unsigned int reg_iop_fifo_in_rw_set_last; +#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 +#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 + +/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_rw_strb_dif_in; +#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 +#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 + +/* Register rw_intr_mask, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 +#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 + +/* Register rw_ack_intr, scope iop_fifo_in, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 +#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 + +/* Register r_intr, scope iop_fifo_in, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_r_intr; +#define REG_RD_ADDR_iop_fifo_in_r_intr 60 + +/* Register r_masked_intr, scope iop_fifo_in, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 + + +/* Constants */ +enum { + regk_iop_fifo_in_dif_in = 0x00000002, + regk_iop_fifo_in_hi = 0x00000000, + regk_iop_fifo_in_neg = 0x00000002, + regk_iop_fifo_in_no = 0x00000000, + regk_iop_fifo_in_order16 = 0x00000001, + regk_iop_fifo_in_order24 = 0x00000002, + regk_iop_fifo_in_order32 = 0x00000003, + regk_iop_fifo_in_order8 = 0x00000000, + regk_iop_fifo_in_pos = 0x00000001, + regk_iop_fifo_in_pos_neg = 0x00000003, + regk_iop_fifo_in_rw_cfg_default = 0x00000024, + regk_iop_fifo_in_rw_ctrl_default = 0x00000000, + regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_in_rw_set_last_default = 0x00000000, + regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, + regk_iop_fifo_in_size16 = 0x00000002, + regk_iop_fifo_in_size24 = 0x00000001, + regk_iop_fifo_in_size32 = 0x00000000, + regk_iop_fifo_in_size8 = 0x00000003, + regk_iop_fifo_in_yes = 0x00000001 +}; +#endif /* __iop_fifo_in_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h new file mode 100644 index 000000000..798ac9587 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h @@ -0,0 +1,164 @@ +#ifndef __iop_fifo_in_extra_defs_h +#define __iop_fifo_in_extra_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: + * last modfied: Mon Apr 11 16:10:08 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r + * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_in_extra */ + +/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ +typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0 + +/* Register r_stat, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 18; +} reg_iop_fifo_in_extra_r_stat; +#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4 + +/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int last : 2; + unsigned int dummy1 : 30; +} reg_iop_fifo_in_extra_rw_strb_dif_in; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 + +/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12 + +/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16 +#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16 + +/* Register r_intr, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_r_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20 + +/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int avail : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_in_extra_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24 + + +/* Constants */ +enum { + regk_iop_fifo_in_extra_fifo_in = 0x00000002, + regk_iop_fifo_in_extra_no = 0x00000000, + regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_in_extra_yes = 0x00000001 +}; +#endif /* __iop_fifo_in_extra_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h new file mode 100644 index 000000000..833e10f02 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h @@ -0,0 +1,278 @@ +#ifndef __iop_fifo_out_defs_h +#define __iop_fifo_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out.r + * id: + * last modfied: Mon Apr 11 16:10:09 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r + * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_out */ + +/* Register rw_cfg, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int free_lim : 3; + unsigned int byte_order : 2; + unsigned int trig : 2; + unsigned int last_dis_dif_in : 1; + unsigned int mode : 2; + unsigned int delay_out_last : 1; + unsigned int last_dis_dif_out : 1; + unsigned int dummy1 : 20; +} reg_iop_fifo_out_rw_cfg; +#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 +#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int dummy1 : 30; +} reg_iop_fifo_out_rw_ctrl; +#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 + +/* Register r_stat, scope iop_fifo_out, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int zero_data_last : 1; + unsigned int dummy1 : 17; +} reg_iop_fifo_out_r_stat; +#define REG_RD_ADDR_iop_fifo_out_r_stat 8 + +/* Register rw_wr1byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_out_rw_wr1byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 +#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 + +/* Register rw_wr2byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_out_rw_wr2byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 +#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 + +/* Register rw_wr3byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_out_rw_wr3byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 +#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 + +/* Register rw_wr4byte, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_out_rw_wr4byte; +#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 +#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 + +/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_iop_fifo_out_rw_wr1byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 +#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 + +/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_iop_fifo_out_rw_wr2byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 +#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 + +/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 24; + unsigned int dummy1 : 8; +} reg_iop_fifo_out_rw_wr3byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 +#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 + +/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int data : 32; +} reg_iop_fifo_out_rw_wr4byte_last; +#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 +#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 + +/* Register rw_set_last, scope iop_fifo_out, type rw */ +typedef unsigned int reg_iop_fifo_out_rw_set_last; +#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 +#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 + +/* Register rs_rd_data, scope iop_fifo_out, type rs */ +typedef unsigned int reg_iop_fifo_out_rs_rd_data; +#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 + +/* Register r_rd_data, scope iop_fifo_out, type r */ +typedef unsigned int reg_iop_fifo_out_r_rd_data; +#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 + +/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ +typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; +#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 +#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 + +/* Register rw_intr_mask, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 +#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 + +/* Register rw_ack_intr, scope iop_fifo_out, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 +#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 + +/* Register r_intr, scope iop_fifo_out, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_r_intr; +#define REG_RD_ADDR_iop_fifo_out_r_intr 68 + +/* Register r_masked_intr, scope iop_fifo_out, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 + + +/* Constants */ +enum { + regk_iop_fifo_out_hi = 0x00000000, + regk_iop_fifo_out_neg = 0x00000002, + regk_iop_fifo_out_no = 0x00000000, + regk_iop_fifo_out_order16 = 0x00000001, + regk_iop_fifo_out_order24 = 0x00000002, + regk_iop_fifo_out_order32 = 0x00000003, + regk_iop_fifo_out_order8 = 0x00000000, + regk_iop_fifo_out_pos = 0x00000001, + regk_iop_fifo_out_pos_neg = 0x00000003, + regk_iop_fifo_out_rw_cfg_default = 0x00000024, + regk_iop_fifo_out_rw_ctrl_default = 0x00000000, + regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_out_rw_set_last_default = 0x00000000, + regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, + regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, + regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, + regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, + regk_iop_fifo_out_size16 = 0x00000002, + regk_iop_fifo_out_size24 = 0x00000001, + regk_iop_fifo_out_size32 = 0x00000000, + regk_iop_fifo_out_size8 = 0x00000003, + regk_iop_fifo_out_yes = 0x00000001 +}; +#endif /* __iop_fifo_out_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h new file mode 100644 index 000000000..4a840aae8 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h @@ -0,0 +1,164 @@ +#ifndef __iop_fifo_out_extra_defs_h +#define __iop_fifo_out_extra_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: + * last modfied: Mon Apr 11 16:10:10 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r + * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_fifo_out_extra */ + +/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ +typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data; +#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0 + +/* Register r_rd_data, scope iop_fifo_out_extra, type r */ +typedef unsigned int reg_iop_fifo_out_extra_r_rd_data; +#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4 + +/* Register r_stat, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int avail_bytes : 4; + unsigned int last : 8; + unsigned int dif_in_en : 1; + unsigned int dif_out_en : 1; + unsigned int zero_data_last : 1; + unsigned int dummy1 : 17; +} reg_iop_fifo_out_extra_r_stat; +#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8 + +/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ +typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 + +/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_rw_intr_mask; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16 + +/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_rw_ack_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20 +#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20 + +/* Register r_intr, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_r_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24 + +/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ +typedef struct { + unsigned int urun : 1; + unsigned int last_data : 1; + unsigned int dav : 1; + unsigned int free : 1; + unsigned int orun : 1; + unsigned int dummy1 : 27; +} reg_iop_fifo_out_extra_r_masked_intr; +#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28 + + +/* Constants */ +enum { + regk_iop_fifo_out_extra_no = 0x00000000, + regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000, + regk_iop_fifo_out_extra_yes = 0x00000001 +}; +#endif /* __iop_fifo_out_extra_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h new file mode 100644 index 000000000..c2b0ba1be --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h @@ -0,0 +1,190 @@ +#ifndef __iop_mpu_defs_h +#define __iop_mpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_mpu.r + * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r + * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_mpu */ + +#define STRIDE_iop_mpu_rw_r 4 +/* Register rw_r, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_r; +#define REG_RD_ADDR_iop_mpu_rw_r 0 +#define REG_WR_ADDR_iop_mpu_rw_r 0 + +/* Register rw_ctrl, scope iop_mpu, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_iop_mpu_rw_ctrl; +#define REG_RD_ADDR_iop_mpu_rw_ctrl 128 +#define REG_WR_ADDR_iop_mpu_rw_ctrl 128 + +/* Register r_pc, scope iop_mpu, type r */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_r_pc; +#define REG_RD_ADDR_iop_mpu_r_pc 132 + +/* Register r_stat, scope iop_mpu, type r */ +typedef struct { + unsigned int instr_reg_busy : 1; + unsigned int intr_busy : 1; + unsigned int intr_vect : 16; + unsigned int dummy1 : 14; +} reg_iop_mpu_r_stat; +#define REG_RD_ADDR_iop_mpu_r_stat 136 + +/* Register rw_instr, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_instr; +#define REG_RD_ADDR_iop_mpu_rw_instr 140 +#define REG_WR_ADDR_iop_mpu_rw_instr 140 + +/* Register rw_immediate, scope iop_mpu, type rw */ +typedef unsigned int reg_iop_mpu_rw_immediate; +#define REG_RD_ADDR_iop_mpu_rw_immediate 144 +#define REG_WR_ADDR_iop_mpu_rw_immediate 144 + +/* Register r_trace, scope iop_mpu, type r */ +typedef struct { + unsigned int intr_vect : 16; + unsigned int pc : 12; + unsigned int en : 1; + unsigned int instr_reg_busy : 1; + unsigned int intr_busy : 1; + unsigned int dummy1 : 1; +} reg_iop_mpu_r_trace; +#define REG_RD_ADDR_iop_mpu_r_trace 148 + +/* Register r_wr_stat, scope iop_mpu, type r */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_mpu_r_wr_stat; +#define REG_RD_ADDR_iop_mpu_r_wr_stat 152 + +#define STRIDE_iop_mpu_rw_thread 4 +/* Register rw_thread, scope iop_mpu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_rw_thread; +#define REG_RD_ADDR_iop_mpu_rw_thread 156 +#define REG_WR_ADDR_iop_mpu_rw_thread 156 + +#define STRIDE_iop_mpu_rw_intr 4 +/* Register rw_intr, scope iop_mpu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_mpu_rw_intr; +#define REG_RD_ADDR_iop_mpu_rw_intr 196 +#define REG_WR_ADDR_iop_mpu_rw_intr 196 + + +/* Constants */ +enum { + regk_iop_mpu_no = 0x00000000, + regk_iop_mpu_r_pc_default = 0x00000000, + regk_iop_mpu_rw_ctrl_default = 0x00000000, + regk_iop_mpu_rw_intr_size = 0x00000010, + regk_iop_mpu_rw_r_size = 0x00000010, + regk_iop_mpu_rw_thread_default = 0x00000000, + regk_iop_mpu_rw_thread_size = 0x00000004, + regk_iop_mpu_yes = 0x00000001 +}; +#endif /* __iop_mpu_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h new file mode 100644 index 000000000..2ec897ced --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h @@ -0,0 +1,764 @@ +/* ************************************************************************* */ +/* This file is autogenerated by IOPASM Version 1.2 */ +/* DO NOT EDIT THIS FILE - All changes will be lost! */ +/* ************************************************************************* */ + + + +#ifndef __IOP_MPU_MACROS_H__ +#define __IOP_MPU_MACROS_H__ + + +/* ************************************************************************* */ +/* REGISTER DEFINITIONS */ +/* ************************************************************************* */ +#define MPU_R0 (0x0) +#define MPU_R1 (0x1) +#define MPU_R2 (0x2) +#define MPU_R3 (0x3) +#define MPU_R4 (0x4) +#define MPU_R5 (0x5) +#define MPU_R6 (0x6) +#define MPU_R7 (0x7) +#define MPU_R8 (0x8) +#define MPU_R9 (0x9) +#define MPU_R10 (0xa) +#define MPU_R11 (0xb) +#define MPU_R12 (0xc) +#define MPU_R13 (0xd) +#define MPU_R14 (0xe) +#define MPU_R15 (0xf) +#define MPU_PC (0x2) +#define MPU_WSTS (0x3) +#define MPU_JADDR (0x4) +#define MPU_IRP (0x5) +#define MPU_SRP (0x6) +#define MPU_T0 (0x8) +#define MPU_T1 (0x9) +#define MPU_T2 (0xa) +#define MPU_T3 (0xb) +#define MPU_I0 (0x10) +#define MPU_I1 (0x11) +#define MPU_I2 (0x12) +#define MPU_I3 (0x13) +#define MPU_I4 (0x14) +#define MPU_I5 (0x15) +#define MPU_I6 (0x16) +#define MPU_I7 (0x17) +#define MPU_I8 (0x18) +#define MPU_I9 (0x19) +#define MPU_I10 (0x1a) +#define MPU_I11 (0x1b) +#define MPU_I12 (0x1c) +#define MPU_I13 (0x1d) +#define MPU_I14 (0x1e) +#define MPU_I15 (0x1f) +#define MPU_P2 (0x2) +#define MPU_P3 (0x3) +#define MPU_P5 (0x5) +#define MPU_P6 (0x6) +#define MPU_P8 (0x8) +#define MPU_P9 (0x9) +#define MPU_P10 (0xa) +#define MPU_P11 (0xb) +#define MPU_P16 (0x10) +#define MPU_P17 (0x12) +#define MPU_P18 (0x12) +#define MPU_P19 (0x13) +#define MPU_P20 (0x14) +#define MPU_P21 (0x15) +#define MPU_P22 (0x16) +#define MPU_P23 (0x17) +#define MPU_P24 (0x18) +#define MPU_P25 (0x19) +#define MPU_P26 (0x1a) +#define MPU_P27 (0x1b) +#define MPU_P28 (0x1c) +#define MPU_P29 (0x1d) +#define MPU_P30 (0x1e) +#define MPU_P31 (0x1f) +#define MPU_P1 (0x1) +#define MPU_REGA (0x1) + + + +/* ************************************************************************* */ +/* ADDRESS MACROS */ +/* ************************************************************************* */ +#define MK_DWORD_ADDR(ADDR) (ADDR >> 2) +#define MK_BYTE_ADDR(ADDR) (ADDR) + + + +/* ************************************************************************* */ +/* INSTRUCTION MACROS */ +/* ************************************************************************* */ +#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 21)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 21)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_DI() (0x40000001) + +#define MPU_EI() (0x40000003) + +#define MPU_HALT() (0x40000002) + +#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JNT() (0x61000000) + +#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0)) + +#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11)) + +#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_NOP() (0x40000000) + +#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_RET() (0x63003000) + +#define MPU_RETI() (0x63602800) + +#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\ + | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0)) + +#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16)) + +#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0)) + +#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 11)) + +#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\ + | ((N & ((1 << 16) - 1)) << 0)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\ + | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) + +#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) + +#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\ + | ((D & ((1 << 5) - 1)) << 21)) + +#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) + + +#endif /* end of __IOP_MPU_MACROS_H__ */ +/* End of iop_mpu_macros.h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h new file mode 100644 index 000000000..756550f5d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h @@ -0,0 +1,44 @@ +/* Autogenerated Changes here will be lost! + * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg + */ +#define regi_iop_version (regi_iop + 0) +#define regi_iop_fifo_in0_extra (regi_iop + 64) +#define regi_iop_fifo_in1_extra (regi_iop + 128) +#define regi_iop_fifo_out0_extra (regi_iop + 192) +#define regi_iop_fifo_out1_extra (regi_iop + 256) +#define regi_iop_trigger_grp0 (regi_iop + 320) +#define regi_iop_trigger_grp1 (regi_iop + 384) +#define regi_iop_trigger_grp2 (regi_iop + 448) +#define regi_iop_trigger_grp3 (regi_iop + 512) +#define regi_iop_trigger_grp4 (regi_iop + 576) +#define regi_iop_trigger_grp5 (regi_iop + 640) +#define regi_iop_trigger_grp6 (regi_iop + 704) +#define regi_iop_trigger_grp7 (regi_iop + 768) +#define regi_iop_crc_par0 (regi_iop + 896) +#define regi_iop_crc_par1 (regi_iop + 1024) +#define regi_iop_dmc_in0 (regi_iop + 1152) +#define regi_iop_dmc_in1 (regi_iop + 1280) +#define regi_iop_dmc_out0 (regi_iop + 1408) +#define regi_iop_dmc_out1 (regi_iop + 1536) +#define regi_iop_fifo_in0 (regi_iop + 1664) +#define regi_iop_fifo_in1 (regi_iop + 1792) +#define regi_iop_fifo_out0 (regi_iop + 1920) +#define regi_iop_fifo_out1 (regi_iop + 2048) +#define regi_iop_scrc_in0 (regi_iop + 2176) +#define regi_iop_scrc_in1 (regi_iop + 2304) +#define regi_iop_scrc_out0 (regi_iop + 2432) +#define regi_iop_scrc_out1 (regi_iop + 2560) +#define regi_iop_timer_grp0 (regi_iop + 2688) +#define regi_iop_timer_grp1 (regi_iop + 2816) +#define regi_iop_timer_grp2 (regi_iop + 2944) +#define regi_iop_timer_grp3 (regi_iop + 3072) +#define regi_iop_sap_in (regi_iop + 3328) +#define regi_iop_sap_out (regi_iop + 3584) +#define regi_iop_spu0 (regi_iop + 3840) +#define regi_iop_spu1 (regi_iop + 4096) +#define regi_iop_sw_cfg (regi_iop + 4352) +#define regi_iop_sw_cpu (regi_iop + 4608) +#define regi_iop_sw_mpu (regi_iop + 4864) +#define regi_iop_sw_spu0 (regi_iop + 5120) +#define regi_iop_sw_spu1 (regi_iop + 5376) +#define regi_iop_mpu (regi_iop + 5632) diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h new file mode 100644 index 000000000..5548ac100 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h @@ -0,0 +1,179 @@ +#ifndef __iop_sap_in_defs_h +#define __iop_sap_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_in.r + * id: + * last modfied: Mon Apr 11 16:08:45 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r + * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_in */ + +/* Register rw_bus0_sync, scope iop_sap_in, type rw */ +typedef struct { + unsigned int byte0_sel : 2; + unsigned int byte0_ext_src : 3; + unsigned int byte0_edge : 2; + unsigned int byte0_delay : 1; + unsigned int byte1_sel : 2; + unsigned int byte1_ext_src : 3; + unsigned int byte1_edge : 2; + unsigned int byte1_delay : 1; + unsigned int byte2_sel : 2; + unsigned int byte2_ext_src : 3; + unsigned int byte2_edge : 2; + unsigned int byte2_delay : 1; + unsigned int byte3_sel : 2; + unsigned int byte3_ext_src : 3; + unsigned int byte3_edge : 2; + unsigned int byte3_delay : 1; +} reg_iop_sap_in_rw_bus0_sync; +#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 +#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 + +/* Register rw_bus1_sync, scope iop_sap_in, type rw */ +typedef struct { + unsigned int byte0_sel : 2; + unsigned int byte0_ext_src : 3; + unsigned int byte0_edge : 2; + unsigned int byte0_delay : 1; + unsigned int byte1_sel : 2; + unsigned int byte1_ext_src : 3; + unsigned int byte1_edge : 2; + unsigned int byte1_delay : 1; + unsigned int byte2_sel : 2; + unsigned int byte2_ext_src : 3; + unsigned int byte2_edge : 2; + unsigned int byte2_delay : 1; + unsigned int byte3_sel : 2; + unsigned int byte3_ext_src : 3; + unsigned int byte3_edge : 2; + unsigned int byte3_delay : 1; +} reg_iop_sap_in_rw_bus1_sync; +#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 +#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 1; + unsigned int logic : 2; + unsigned int dummy1 : 22; +} reg_iop_sap_in_rw_gio; +#define REG_RD_ADDR_iop_sap_in_rw_gio 8 +#define REG_WR_ADDR_iop_sap_in_rw_gio 8 + + +/* Constants */ +enum { + regk_iop_sap_in_and = 0x00000002, + regk_iop_sap_in_ext_clk200 = 0x00000003, + regk_iop_sap_in_gio1 = 0x00000000, + regk_iop_sap_in_gio13 = 0x00000005, + regk_iop_sap_in_gio18 = 0x00000003, + regk_iop_sap_in_gio19 = 0x00000004, + regk_iop_sap_in_gio21 = 0x00000006, + regk_iop_sap_in_gio23 = 0x00000005, + regk_iop_sap_in_gio29 = 0x00000007, + regk_iop_sap_in_gio5 = 0x00000004, + regk_iop_sap_in_gio6 = 0x00000001, + regk_iop_sap_in_gio7 = 0x00000002, + regk_iop_sap_in_inv = 0x00000001, + regk_iop_sap_in_neg = 0x00000002, + regk_iop_sap_in_no = 0x00000000, + regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, + regk_iop_sap_in_none = 0x00000000, + regk_iop_sap_in_or = 0x00000003, + regk_iop_sap_in_pos = 0x00000001, + regk_iop_sap_in_pos_neg = 0x00000003, + regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, + regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, + regk_iop_sap_in_rw_gio_default = 0x00000002, + regk_iop_sap_in_rw_gio_size = 0x00000020, + regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, + regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, + regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, + regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, + regk_iop_sap_in_tmr_clk200 = 0x00000000, + regk_iop_sap_in_two_clk200 = 0x00000002, + regk_iop_sap_in_yes = 0x00000001 +}; +#endif /* __iop_sap_in_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h new file mode 100644 index 000000000..273936996 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h @@ -0,0 +1,306 @@ +#ifndef __iop_sap_out_defs_h +#define __iop_sap_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_sap_out.r + * id: + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r + * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_out */ + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +typedef struct { + unsigned int clk0_src : 2; + unsigned int clk0_gate_src : 2; + unsigned int clk0_force_src : 3; + unsigned int clk1_src : 2; + unsigned int clk1_gate_src : 2; + unsigned int clk1_force_src : 3; + unsigned int clk2_src : 2; + unsigned int clk2_gate_src : 2; + unsigned int clk2_force_src : 3; + unsigned int clk3_src : 2; + unsigned int clk3_gate_src : 2; + unsigned int clk3_force_src : 3; + unsigned int dummy1 : 4; +} reg_iop_sap_out_rw_gen_gated; +#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 +#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 + +/* Register rw_bus0, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte2_clk_sel : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_bus0; +#define REG_RD_ADDR_iop_sap_out_rw_bus0 4 +#define REG_WR_ADDR_iop_sap_out_rw_bus0 4 + +/* Register rw_bus1, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte2_clk_sel : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_bus1; +#define REG_RD_ADDR_iop_sap_out_rw_bus1 8 +#define REG_WR_ADDR_iop_sap_out_rw_bus1 8 + +/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_clk_ext : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_logic : 2; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_clk_ext : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus0_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12 +#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12 + +/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 3; + unsigned int byte2_clk_ext : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_logic : 2; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_clk_ext : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus0_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16 +#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16 + +/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 3; + unsigned int byte0_clk_ext : 3; + unsigned int byte0_gated_clk : 2; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_logic : 2; + unsigned int byte1_clk_sel : 3; + unsigned int byte1_clk_ext : 3; + unsigned int byte1_gated_clk : 2; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus1_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20 +#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20 + +/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 3; + unsigned int byte2_clk_ext : 3; + unsigned int byte2_gated_clk : 2; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_logic : 2; + unsigned int byte3_clk_sel : 3; + unsigned int byte3_clk_ext : 3; + unsigned int byte3_gated_clk : 2; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus1_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24 +#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +typedef struct { + unsigned int out_clk_sel : 3; + unsigned int out_clk_ext : 4; + unsigned int out_gated_clk : 2; + unsigned int out_clk_inv : 1; + unsigned int out_logic : 1; + unsigned int oe_clk_sel : 3; + unsigned int oe_clk_ext : 3; + unsigned int oe_gated_clk : 2; + unsigned int oe_clk_inv : 1; + unsigned int oe_logic : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_gio; +#define REG_RD_ADDR_iop_sap_out_rw_gio 28 +#define REG_WR_ADDR_iop_sap_out_rw_gio 28 + + +/* Constants */ +enum { + regk_iop_sap_out_and = 0x00000002, + regk_iop_sap_out_clk0 = 0x00000000, + regk_iop_sap_out_clk1 = 0x00000001, + regk_iop_sap_out_clk12 = 0x00000002, + regk_iop_sap_out_clk2 = 0x00000002, + regk_iop_sap_out_clk200 = 0x00000001, + regk_iop_sap_out_clk3 = 0x00000003, + regk_iop_sap_out_ext = 0x00000003, + regk_iop_sap_out_gated = 0x00000004, + regk_iop_sap_out_gio1 = 0x00000000, + regk_iop_sap_out_gio13 = 0x00000002, + regk_iop_sap_out_gio13_clk = 0x0000000c, + regk_iop_sap_out_gio15 = 0x00000001, + regk_iop_sap_out_gio18 = 0x00000003, + regk_iop_sap_out_gio18_clk = 0x0000000d, + regk_iop_sap_out_gio1_clk = 0x00000008, + regk_iop_sap_out_gio21_clk = 0x0000000e, + regk_iop_sap_out_gio23 = 0x00000002, + regk_iop_sap_out_gio29_clk = 0x0000000f, + regk_iop_sap_out_gio31 = 0x00000003, + regk_iop_sap_out_gio5 = 0x00000001, + regk_iop_sap_out_gio5_clk = 0x00000009, + regk_iop_sap_out_gio6_clk = 0x0000000a, + regk_iop_sap_out_gio7 = 0x00000000, + regk_iop_sap_out_gio7_clk = 0x0000000b, + regk_iop_sap_out_gio_in13 = 0x00000001, + regk_iop_sap_out_gio_in21 = 0x00000002, + regk_iop_sap_out_gio_in29 = 0x00000003, + regk_iop_sap_out_gio_in5 = 0x00000000, + regk_iop_sap_out_inv = 0x00000001, + regk_iop_sap_out_nand = 0x00000003, + regk_iop_sap_out_no = 0x00000000, + regk_iop_sap_out_none = 0x00000000, + regk_iop_sap_out_rw_bus0_default = 0x00000000, + regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus1_default = 0x00000000, + regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_gen_gated_default = 0x00000000, + regk_iop_sap_out_rw_gio_default = 0x00000000, + regk_iop_sap_out_rw_gio_size = 0x00000020, + regk_iop_sap_out_spu0_gio0 = 0x00000002, + regk_iop_sap_out_spu0_gio1 = 0x00000003, + regk_iop_sap_out_spu0_gio12 = 0x00000004, + regk_iop_sap_out_spu0_gio13 = 0x00000004, + regk_iop_sap_out_spu0_gio14 = 0x00000004, + regk_iop_sap_out_spu0_gio15 = 0x00000004, + regk_iop_sap_out_spu0_gio2 = 0x00000002, + regk_iop_sap_out_spu0_gio3 = 0x00000003, + regk_iop_sap_out_spu0_gio4 = 0x00000002, + regk_iop_sap_out_spu0_gio5 = 0x00000003, + regk_iop_sap_out_spu0_gio6 = 0x00000002, + regk_iop_sap_out_spu0_gio7 = 0x00000003, + regk_iop_sap_out_spu1_gio0 = 0x00000005, + regk_iop_sap_out_spu1_gio1 = 0x00000006, + regk_iop_sap_out_spu1_gio12 = 0x00000007, + regk_iop_sap_out_spu1_gio13 = 0x00000007, + regk_iop_sap_out_spu1_gio14 = 0x00000007, + regk_iop_sap_out_spu1_gio15 = 0x00000007, + regk_iop_sap_out_spu1_gio2 = 0x00000005, + regk_iop_sap_out_spu1_gio3 = 0x00000006, + regk_iop_sap_out_spu1_gio4 = 0x00000005, + regk_iop_sap_out_spu1_gio5 = 0x00000006, + regk_iop_sap_out_spu1_gio6 = 0x00000005, + regk_iop_sap_out_spu1_gio7 = 0x00000006, + regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004, + regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005, + regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006, + regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007, + regk_iop_sap_out_tmr = 0x00000005, + regk_iop_sap_out_yes = 0x00000001 +}; +#endif /* __iop_sap_out_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h new file mode 100644 index 000000000..4f0a9a81e --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h @@ -0,0 +1,160 @@ +#ifndef __iop_scrc_in_defs_h +#define __iop_scrc_in_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_in.r + * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r + * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_scrc_in */ + +/* Register rw_cfg, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int trig : 2; + unsigned int dummy1 : 30; +} reg_iop_scrc_in_rw_cfg; +#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0 +#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0 + +/* Register rw_ctrl, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int dif_in_en : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_in_rw_ctrl; +#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4 +#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4 + +/* Register r_stat, scope iop_scrc_in, type r */ +typedef struct { + unsigned int err : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_in_r_stat; +#define REG_RD_ADDR_iop_scrc_in_r_stat 8 + +/* Register rw_init_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_init_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12 +#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12 + +/* Register rs_computed_crc, scope iop_scrc_in, type rs */ +typedef unsigned int reg_iop_scrc_in_rs_computed_crc; +#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16 + +/* Register r_computed_crc, scope iop_scrc_in, type r */ +typedef unsigned int reg_iop_scrc_in_r_computed_crc; +#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20 + +/* Register rw_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_crc 24 +#define REG_WR_ADDR_iop_scrc_in_rw_crc 24 + +/* Register rw_correct_crc, scope iop_scrc_in, type rw */ +typedef unsigned int reg_iop_scrc_in_rw_correct_crc; +#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28 +#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28 + +/* Register rw_wr1bit, scope iop_scrc_in, type rw */ +typedef struct { + unsigned int data : 2; + unsigned int last : 2; + unsigned int dummy1 : 28; +} reg_iop_scrc_in_rw_wr1bit; +#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32 +#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32 + + +/* Constants */ +enum { + regk_iop_scrc_in_dif_in = 0x00000002, + regk_iop_scrc_in_hi = 0x00000000, + regk_iop_scrc_in_neg = 0x00000002, + regk_iop_scrc_in_no = 0x00000000, + regk_iop_scrc_in_pos = 0x00000001, + regk_iop_scrc_in_pos_neg = 0x00000003, + regk_iop_scrc_in_r_computed_crc_default = 0x00000000, + regk_iop_scrc_in_rs_computed_crc_default = 0x00000000, + regk_iop_scrc_in_rw_cfg_default = 0x00000000, + regk_iop_scrc_in_rw_ctrl_default = 0x00000000, + regk_iop_scrc_in_rw_init_crc_default = 0x00000000, + regk_iop_scrc_in_set0 = 0x00000000, + regk_iop_scrc_in_set1 = 0x00000001, + regk_iop_scrc_in_yes = 0x00000001 +}; +#endif /* __iop_scrc_in_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h new file mode 100644 index 000000000..fd1d6ea1d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h @@ -0,0 +1,146 @@ +#ifndef __iop_scrc_out_defs_h +#define __iop_scrc_out_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_scrc_out.r + * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r + * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_scrc_out */ + +/* Register rw_cfg, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int trig : 2; + unsigned int inv_crc : 1; + unsigned int dummy1 : 29; +} reg_iop_scrc_out_rw_cfg; +#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 +#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 + +/* Register rw_ctrl, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int strb_src : 1; + unsigned int out_src : 1; + unsigned int dummy1 : 30; +} reg_iop_scrc_out_rw_ctrl; +#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 +#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 + +/* Register rw_init_crc, scope iop_scrc_out, type rw */ +typedef unsigned int reg_iop_scrc_out_rw_init_crc; +#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 +#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 + +/* Register rw_crc, scope iop_scrc_out, type rw */ +typedef unsigned int reg_iop_scrc_out_rw_crc; +#define REG_RD_ADDR_iop_scrc_out_rw_crc 12 +#define REG_WR_ADDR_iop_scrc_out_rw_crc 12 + +/* Register rw_data, scope iop_scrc_out, type rw */ +typedef struct { + unsigned int val : 1; + unsigned int dummy1 : 31; +} reg_iop_scrc_out_rw_data; +#define REG_RD_ADDR_iop_scrc_out_rw_data 16 +#define REG_WR_ADDR_iop_scrc_out_rw_data 16 + +/* Register r_computed_crc, scope iop_scrc_out, type r */ +typedef unsigned int reg_iop_scrc_out_r_computed_crc; +#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 + + +/* Constants */ +enum { + regk_iop_scrc_out_crc = 0x00000001, + regk_iop_scrc_out_data = 0x00000000, + regk_iop_scrc_out_dif = 0x00000001, + regk_iop_scrc_out_hi = 0x00000000, + regk_iop_scrc_out_neg = 0x00000002, + regk_iop_scrc_out_no = 0x00000000, + regk_iop_scrc_out_pos = 0x00000001, + regk_iop_scrc_out_pos_neg = 0x00000003, + regk_iop_scrc_out_reg = 0x00000000, + regk_iop_scrc_out_rw_cfg_default = 0x00000000, + regk_iop_scrc_out_rw_crc_default = 0x00000000, + regk_iop_scrc_out_rw_ctrl_default = 0x00000000, + regk_iop_scrc_out_rw_data_default = 0x00000000, + regk_iop_scrc_out_rw_init_crc_default = 0x00000000, + regk_iop_scrc_out_yes = 0x00000001 +}; +#endif /* __iop_scrc_out_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h new file mode 100644 index 000000000..0fda26e2f --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h @@ -0,0 +1,453 @@ +#ifndef __iop_spu_defs_h +#define __iop_spu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_spu.r + * id: + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r + * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_spu */ + +#define STRIDE_iop_spu_rw_r 4 +/* Register rw_r, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_r; +#define REG_RD_ADDR_iop_spu_rw_r 0 +#define REG_WR_ADDR_iop_spu_rw_r 0 + +/* Register rw_seq_pc, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_seq_pc; +#define REG_RD_ADDR_iop_spu_rw_seq_pc 64 +#define REG_WR_ADDR_iop_spu_rw_seq_pc 64 + +/* Register rw_fsm_pc, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_fsm_pc; +#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 +#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 + +/* Register rw_ctrl, scope iop_spu, type rw */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_iop_spu_rw_ctrl; +#define REG_RD_ADDR_iop_spu_rw_ctrl 72 +#define REG_WR_ADDR_iop_spu_rw_ctrl 72 + +/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ +typedef struct { + unsigned int val0 : 5; + unsigned int src0 : 3; + unsigned int val1 : 5; + unsigned int src1 : 3; + unsigned int val2 : 5; + unsigned int src2 : 3; + unsigned int val3 : 5; + unsigned int src3 : 3; +} reg_iop_spu_rw_fsm_inputs3_0; +#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 +#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 + +/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ +typedef struct { + unsigned int val4 : 5; + unsigned int src4 : 3; + unsigned int val5 : 5; + unsigned int src5 : 3; + unsigned int val6 : 5; + unsigned int src6 : 3; + unsigned int val7 : 5; + unsigned int src7 : 3; +} reg_iop_spu_rw_fsm_inputs7_4; +#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 +#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 + +/* Register rw_gio_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out; +#define REG_RD_ADDR_iop_spu_rw_gio_out 84 +#define REG_WR_ADDR_iop_spu_rw_gio_out 84 + +/* Register rw_bus0_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_bus0_out; +#define REG_RD_ADDR_iop_spu_rw_bus0_out 88 +#define REG_WR_ADDR_iop_spu_rw_bus0_out 88 + +/* Register rw_bus1_out, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_bus1_out; +#define REG_RD_ADDR_iop_spu_rw_bus1_out 92 +#define REG_WR_ADDR_iop_spu_rw_bus1_out 92 + +/* Register r_gio_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_gio_in; +#define REG_RD_ADDR_iop_spu_r_gio_in 96 + +/* Register r_bus0_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_bus0_in; +#define REG_RD_ADDR_iop_spu_r_bus0_in 100 + +/* Register r_bus1_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_bus1_in; +#define REG_RD_ADDR_iop_spu_r_bus1_in 104 + +/* Register rw_gio_out_set, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out_set; +#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 +#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 + +/* Register rw_gio_out_clr, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_gio_out_clr; +#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 +#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 + +/* Register rs_wr_stat, scope iop_spu, type rs */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_spu_rs_wr_stat; +#define REG_RD_ADDR_iop_spu_rs_wr_stat 116 + +/* Register r_wr_stat, scope iop_spu, type r */ +typedef struct { + unsigned int r0 : 1; + unsigned int r1 : 1; + unsigned int r2 : 1; + unsigned int r3 : 1; + unsigned int r4 : 1; + unsigned int r5 : 1; + unsigned int r6 : 1; + unsigned int r7 : 1; + unsigned int r8 : 1; + unsigned int r9 : 1; + unsigned int r10 : 1; + unsigned int r11 : 1; + unsigned int r12 : 1; + unsigned int r13 : 1; + unsigned int r14 : 1; + unsigned int r15 : 1; + unsigned int dummy1 : 16; +} reg_iop_spu_r_wr_stat; +#define REG_RD_ADDR_iop_spu_r_wr_stat 120 + +/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; +#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 + +/* Register r_stat_in, scope iop_spu, type r */ +typedef struct { + unsigned int timer_grp_lo : 4; + unsigned int fifo_out_last : 1; + unsigned int fifo_out_rdy : 1; + unsigned int fifo_out_all : 1; + unsigned int fifo_in_rdy : 1; + unsigned int dmc_out_all : 1; + unsigned int dmc_out_dth : 1; + unsigned int dmc_out_eop : 1; + unsigned int dmc_out_dv : 1; + unsigned int dmc_out_last : 1; + unsigned int dmc_out_cmd_rq : 1; + unsigned int dmc_out_cmd_rdy : 1; + unsigned int pcrc_correct : 1; + unsigned int timer_grp_hi : 4; + unsigned int dmc_in_sth : 1; + unsigned int dmc_in_full : 1; + unsigned int dmc_in_cmd_rdy : 1; + unsigned int spu_gio_out : 4; + unsigned int sync_clk12 : 1; + unsigned int scrc_out_data : 1; + unsigned int scrc_in_err : 1; + unsigned int mc_busy : 1; + unsigned int mc_owned : 1; +} reg_iop_spu_r_stat_in; +#define REG_RD_ADDR_iop_spu_r_stat_in 128 + +/* Register r_trigger_in, scope iop_spu, type r */ +typedef unsigned int reg_iop_spu_r_trigger_in; +#define REG_RD_ADDR_iop_spu_r_trigger_in 132 + +/* Register r_special_stat, scope iop_spu, type r */ +typedef struct { + unsigned int c_flag : 1; + unsigned int v_flag : 1; + unsigned int z_flag : 1; + unsigned int n_flag : 1; + unsigned int xor_bus0_r2_0 : 1; + unsigned int xor_bus1_r3_0 : 1; + unsigned int xor_bus0m_r2_0 : 1; + unsigned int xor_bus1m_r3_0 : 1; + unsigned int fsm_in0 : 1; + unsigned int fsm_in1 : 1; + unsigned int fsm_in2 : 1; + unsigned int fsm_in3 : 1; + unsigned int fsm_in4 : 1; + unsigned int fsm_in5 : 1; + unsigned int fsm_in6 : 1; + unsigned int fsm_in7 : 1; + unsigned int event0 : 1; + unsigned int event1 : 1; + unsigned int event2 : 1; + unsigned int event3 : 1; + unsigned int dummy1 : 12; +} reg_iop_spu_r_special_stat; +#define REG_RD_ADDR_iop_spu_r_special_stat 136 + +/* Register rw_reg_access, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 13; + unsigned int dummy1 : 3; + unsigned int imm_hi : 16; +} reg_iop_spu_rw_reg_access; +#define REG_RD_ADDR_iop_spu_rw_reg_access 140 +#define REG_WR_ADDR_iop_spu_rw_reg_access 140 + +#define STRIDE_iop_spu_rw_event_cfg 4 +/* Register rw_event_cfg, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int src : 2; + unsigned int eq_en : 1; + unsigned int eq_inv : 1; + unsigned int gt_en : 1; + unsigned int gt_inv : 1; + unsigned int dummy1 : 14; +} reg_iop_spu_rw_event_cfg; +#define REG_RD_ADDR_iop_spu_rw_event_cfg 144 +#define REG_WR_ADDR_iop_spu_rw_event_cfg 144 + +#define STRIDE_iop_spu_rw_event_mask 4 +/* Register rw_event_mask, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_event_mask; +#define REG_RD_ADDR_iop_spu_rw_event_mask 160 +#define REG_WR_ADDR_iop_spu_rw_event_mask 160 + +#define STRIDE_iop_spu_rw_event_val 4 +/* Register rw_event_val, scope iop_spu, type rw */ +typedef unsigned int reg_iop_spu_rw_event_val; +#define REG_RD_ADDR_iop_spu_rw_event_val 176 +#define REG_WR_ADDR_iop_spu_rw_event_val 176 + +/* Register rw_event_ret, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int dummy1 : 20; +} reg_iop_spu_rw_event_ret; +#define REG_RD_ADDR_iop_spu_rw_event_ret 192 +#define REG_WR_ADDR_iop_spu_rw_event_ret 192 + +/* Register r_trace, scope iop_spu, type r */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int c_flag : 1; + unsigned int v_flag : 1; + unsigned int z_flag : 1; + unsigned int n_flag : 1; + unsigned int seq_addr : 12; + unsigned int dummy1 : 2; + unsigned int fsm_addr : 12; +} reg_iop_spu_r_trace; +#define REG_RD_ADDR_iop_spu_r_trace 196 + +/* Register r_fsm_trace, scope iop_spu, type r */ +typedef struct { + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int tmr_done : 1; + unsigned int inp0 : 1; + unsigned int inp1 : 1; + unsigned int inp2 : 1; + unsigned int inp3 : 1; + unsigned int event0 : 1; + unsigned int event1 : 1; + unsigned int event2 : 1; + unsigned int event3 : 1; + unsigned int gio_out : 8; + unsigned int dummy1 : 1; + unsigned int fsm_addr : 12; +} reg_iop_spu_r_fsm_trace; +#define REG_RD_ADDR_iop_spu_r_fsm_trace 200 + +#define STRIDE_iop_spu_rw_brp 4 +/* Register rw_brp, scope iop_spu, type rw */ +typedef struct { + unsigned int addr : 12; + unsigned int fsm : 1; + unsigned int en : 1; + unsigned int dummy1 : 18; +} reg_iop_spu_rw_brp; +#define REG_RD_ADDR_iop_spu_rw_brp 204 +#define REG_WR_ADDR_iop_spu_rw_brp 204 + + +/* Constants */ +enum { + regk_iop_spu_attn_hi = 0x00000005, + regk_iop_spu_attn_lo = 0x00000005, + regk_iop_spu_attn_r0 = 0x00000000, + regk_iop_spu_attn_r1 = 0x00000001, + regk_iop_spu_attn_r10 = 0x00000002, + regk_iop_spu_attn_r11 = 0x00000003, + regk_iop_spu_attn_r12 = 0x00000004, + regk_iop_spu_attn_r13 = 0x00000005, + regk_iop_spu_attn_r14 = 0x00000006, + regk_iop_spu_attn_r15 = 0x00000007, + regk_iop_spu_attn_r2 = 0x00000002, + regk_iop_spu_attn_r3 = 0x00000003, + regk_iop_spu_attn_r4 = 0x00000004, + regk_iop_spu_attn_r5 = 0x00000005, + regk_iop_spu_attn_r6 = 0x00000006, + regk_iop_spu_attn_r7 = 0x00000007, + regk_iop_spu_attn_r8 = 0x00000000, + regk_iop_spu_attn_r9 = 0x00000001, + regk_iop_spu_c = 0x00000000, + regk_iop_spu_flag = 0x00000002, + regk_iop_spu_gio_in = 0x00000000, + regk_iop_spu_gio_out = 0x00000005, + regk_iop_spu_gio_out0 = 0x00000008, + regk_iop_spu_gio_out1 = 0x00000009, + regk_iop_spu_gio_out2 = 0x0000000a, + regk_iop_spu_gio_out3 = 0x0000000b, + regk_iop_spu_gio_out4 = 0x0000000c, + regk_iop_spu_gio_out5 = 0x0000000d, + regk_iop_spu_gio_out6 = 0x0000000e, + regk_iop_spu_gio_out7 = 0x0000000f, + regk_iop_spu_n = 0x00000003, + regk_iop_spu_no = 0x00000000, + regk_iop_spu_r0 = 0x00000008, + regk_iop_spu_r1 = 0x00000009, + regk_iop_spu_r10 = 0x0000000a, + regk_iop_spu_r11 = 0x0000000b, + regk_iop_spu_r12 = 0x0000000c, + regk_iop_spu_r13 = 0x0000000d, + regk_iop_spu_r14 = 0x0000000e, + regk_iop_spu_r15 = 0x0000000f, + regk_iop_spu_r2 = 0x0000000a, + regk_iop_spu_r3 = 0x0000000b, + regk_iop_spu_r4 = 0x0000000c, + regk_iop_spu_r5 = 0x0000000d, + regk_iop_spu_r6 = 0x0000000e, + regk_iop_spu_r7 = 0x0000000f, + regk_iop_spu_r8 = 0x00000008, + regk_iop_spu_r9 = 0x00000009, + regk_iop_spu_reg_hi = 0x00000002, + regk_iop_spu_reg_lo = 0x00000002, + regk_iop_spu_rw_brp_default = 0x00000000, + regk_iop_spu_rw_brp_size = 0x00000004, + regk_iop_spu_rw_ctrl_default = 0x00000000, + regk_iop_spu_rw_event_cfg_size = 0x00000004, + regk_iop_spu_rw_event_mask_size = 0x00000004, + regk_iop_spu_rw_event_val_size = 0x00000004, + regk_iop_spu_rw_gio_out_default = 0x00000000, + regk_iop_spu_rw_r_size = 0x00000010, + regk_iop_spu_rw_reg_access_default = 0x00000000, + regk_iop_spu_stat_in = 0x00000002, + regk_iop_spu_statin_hi = 0x00000004, + regk_iop_spu_statin_lo = 0x00000004, + regk_iop_spu_trig = 0x00000003, + regk_iop_spu_trigger = 0x00000006, + regk_iop_spu_v = 0x00000001, + regk_iop_spu_wsts_gioout_spec = 0x00000001, + regk_iop_spu_xor = 0x00000003, + regk_iop_spu_xor_bus0_r2_0 = 0x00000000, + regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, + regk_iop_spu_xor_bus1_r3_0 = 0x00000001, + regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, + regk_iop_spu_yes = 0x00000001, + regk_iop_spu_z = 0x00000002 +}; +#endif /* __iop_spu_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h new file mode 100644 index 000000000..d7b6d7588 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h @@ -0,0 +1,1042 @@ +#ifndef __iop_sw_cfg_defs_h +#define __iop_sw_cfg_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r + * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cfg */ + +/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 + +/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 + +/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 + +/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 + +/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 + +/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 + +/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 + +/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in0_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 + +/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 + +/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in1_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 + +/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 + +/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out0_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 + +/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 + +/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out1_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 + +/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 + +/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 + +/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 + +/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 + +/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 + +/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 + +/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 + +/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp4_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp5_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp6_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp7_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 + +/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus0_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 + +/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus0_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 + +/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus1_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 + +/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus1_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_byte0 : 2; + unsigned int bus0_byte1 : 2; + unsigned int bus0_byte2 : 2; + unsigned int bus0_byte3 : 2; + unsigned int bus1_byte0 : 2; + unsigned int bus1_byte1 : 2; + unsigned int bus1_byte2 : 2; + unsigned int bus1_byte3 : 2; + unsigned int gio3_0 : 2; + unsigned int gio7_4 : 2; + unsigned int gio11_8 : 2; + unsigned int gio15_12 : 2; + unsigned int gio19_16 : 2; + unsigned int gio23_20 : 2; + unsigned int gio27_24 : 2; + unsigned int gio31_28 : 2; +} reg_iop_sw_cfg_rw_pinmapping; +#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 +#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_lo : 3; + unsigned int bus0_hi : 3; + unsigned int bus0_lo_oe : 3; + unsigned int bus0_hi_oe : 3; + unsigned int bus1_lo : 3; + unsigned int bus1_hi : 3; + unsigned int bus1_lo_oe : 3; + unsigned int bus1_hi_oe : 3; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_bus_out_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio0 : 4; + unsigned int gio0_oe : 2; + unsigned int gio1 : 4; + unsigned int gio1_oe : 2; + unsigned int gio2 : 4; + unsigned int gio2_oe : 2; + unsigned int gio3 : 4; + unsigned int gio3_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio4 : 4; + unsigned int gio4_oe : 2; + unsigned int gio5 : 4; + unsigned int gio5_oe : 2; + unsigned int gio6 : 4; + unsigned int gio6_oe : 2; + unsigned int gio7 : 4; + unsigned int gio7_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio8 : 4; + unsigned int gio8_oe : 2; + unsigned int gio9 : 4; + unsigned int gio9_oe : 2; + unsigned int gio10 : 4; + unsigned int gio10_oe : 2; + unsigned int gio11 : 4; + unsigned int gio11_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio12 : 4; + unsigned int gio12_oe : 2; + unsigned int gio13 : 4; + unsigned int gio13_oe : 2; + unsigned int gio14 : 4; + unsigned int gio14_oe : 2; + unsigned int gio15 : 4; + unsigned int gio15_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio16 : 4; + unsigned int gio16_oe : 2; + unsigned int gio17 : 4; + unsigned int gio17_oe : 2; + unsigned int gio18 : 4; + unsigned int gio18_oe : 2; + unsigned int gio19 : 4; + unsigned int gio19_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio20 : 4; + unsigned int gio20_oe : 2; + unsigned int gio21 : 4; + unsigned int gio21_oe : 2; + unsigned int gio22 : 4; + unsigned int gio22_oe : 2; + unsigned int gio23 : 4; + unsigned int gio23_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio24 : 4; + unsigned int gio24_oe : 2; + unsigned int gio25 : 4; + unsigned int gio25_oe : 2; + unsigned int gio26 : 4; + unsigned int gio26_oe : 2; + unsigned int gio27 : 4; + unsigned int gio27_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio28 : 4; + unsigned int gio28_oe : 2; + unsigned int gio29 : 4; + unsigned int gio29_oe : 2; + unsigned int gio30 : 4; + unsigned int gio30_oe : 2; + unsigned int gio31 : 4; + unsigned int gio31_oe : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 + +/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 2; + unsigned int bus1_in : 2; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_spu0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 + +/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 2; + unsigned int bus1_in : 2; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_spu1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 + +/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 + +/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 1; + unsigned int tmr1_en : 1; + unsigned int tmr2_en : 1; + unsigned int tmr3_en : 1; + unsigned int tmr0_dis : 1; + unsigned int tmr1_dis : 1; + unsigned int tmr2_dis : 1; + unsigned int tmr3_dis : 1; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_timer_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int grp0_dis : 1; + unsigned int grp0_en : 1; + unsigned int grp1_dis : 1; + unsigned int grp1_en : 1; + unsigned int grp2_dis : 1; + unsigned int grp2_en : 1; + unsigned int grp3_dis : 1; + unsigned int grp3_en : 1; + unsigned int grp4_dis : 1; + unsigned int grp4_en : 1; + unsigned int grp5_dis : 1; + unsigned int grp5_en : 1; + unsigned int grp6_dis : 1; + unsigned int grp6_en : 1; + unsigned int grp7_dis : 1; + unsigned int grp7_en : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_trigger_grps_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 + +/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int dmc0_usr : 1; + unsigned int out_strb : 5; + unsigned int in_src : 3; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int out_src : 1; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_pdp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 + +/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int dmc1_usr : 1; + unsigned int out_strb : 5; + unsigned int in_src : 3; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int out_src : 1; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_pdp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int sdp_out0_strb : 3; + unsigned int sdp_out1_strb : 3; + unsigned int sdp_in0_data : 3; + unsigned int sdp_in0_last : 2; + unsigned int sdp_in0_strb : 3; + unsigned int sdp_in1_data : 3; + unsigned int sdp_in1_last : 2; + unsigned int sdp_in1_strb : 3; + unsigned int dummy1 : 10; +} reg_iop_sw_cfg_rw_sdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 +#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 + + +/* Constants */ +enum { + regk_iop_sw_cfg_a = 0x00000001, + regk_iop_sw_cfg_b = 0x00000002, + regk_iop_sw_cfg_bus0 = 0x00000000, + regk_iop_sw_cfg_bus0_rot16 = 0x00000004, + regk_iop_sw_cfg_bus0_rot24 = 0x00000006, + regk_iop_sw_cfg_bus0_rot8 = 0x00000002, + regk_iop_sw_cfg_bus1 = 0x00000001, + regk_iop_sw_cfg_bus1_rot16 = 0x00000005, + regk_iop_sw_cfg_bus1_rot24 = 0x00000007, + regk_iop_sw_cfg_bus1_rot8 = 0x00000003, + regk_iop_sw_cfg_clk12 = 0x00000000, + regk_iop_sw_cfg_cpu = 0x00000000, + regk_iop_sw_cfg_dmc0 = 0x00000000, + regk_iop_sw_cfg_dmc1 = 0x00000001, + regk_iop_sw_cfg_gated_clk0 = 0x00000010, + regk_iop_sw_cfg_gated_clk1 = 0x00000011, + regk_iop_sw_cfg_gated_clk2 = 0x00000012, + regk_iop_sw_cfg_gated_clk3 = 0x00000013, + regk_iop_sw_cfg_gio0 = 0x00000004, + regk_iop_sw_cfg_gio1 = 0x00000001, + regk_iop_sw_cfg_gio2 = 0x00000005, + regk_iop_sw_cfg_gio3 = 0x00000002, + regk_iop_sw_cfg_gio4 = 0x00000006, + regk_iop_sw_cfg_gio5 = 0x00000003, + regk_iop_sw_cfg_gio6 = 0x00000007, + regk_iop_sw_cfg_gio7 = 0x00000004, + regk_iop_sw_cfg_gio_in0 = 0x00000000, + regk_iop_sw_cfg_gio_in1 = 0x00000001, + regk_iop_sw_cfg_gio_in10 = 0x00000002, + regk_iop_sw_cfg_gio_in11 = 0x00000003, + regk_iop_sw_cfg_gio_in14 = 0x00000004, + regk_iop_sw_cfg_gio_in15 = 0x00000005, + regk_iop_sw_cfg_gio_in18 = 0x00000002, + regk_iop_sw_cfg_gio_in19 = 0x00000003, + regk_iop_sw_cfg_gio_in20 = 0x00000004, + regk_iop_sw_cfg_gio_in21 = 0x00000005, + regk_iop_sw_cfg_gio_in26 = 0x00000006, + regk_iop_sw_cfg_gio_in27 = 0x00000007, + regk_iop_sw_cfg_gio_in28 = 0x00000006, + regk_iop_sw_cfg_gio_in29 = 0x00000007, + regk_iop_sw_cfg_gio_in4 = 0x00000000, + regk_iop_sw_cfg_gio_in5 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, + regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, + regk_iop_sw_cfg_mpu = 0x00000001, + regk_iop_sw_cfg_none = 0x00000000, + regk_iop_sw_cfg_par0 = 0x00000000, + regk_iop_sw_cfg_par1 = 0x00000001, + regk_iop_sw_cfg_pdp_out0 = 0x00000002, + regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, + regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, + regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, + regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, + regk_iop_sw_cfg_pdp_out1 = 0x00000003, + regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, + regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, + regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, + regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, + regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, + regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, + regk_iop_sw_cfg_sdp_out0 = 0x00000008, + regk_iop_sw_cfg_sdp_out1 = 0x00000009, + regk_iop_sw_cfg_size16 = 0x00000002, + regk_iop_sw_cfg_size24 = 0x00000003, + regk_iop_sw_cfg_size32 = 0x00000004, + regk_iop_sw_cfg_size8 = 0x00000001, + regk_iop_sw_cfg_spu0 = 0x00000002, + regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, + regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, + regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, + regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, + regk_iop_sw_cfg_spu0_g0 = 0x0000000e, + regk_iop_sw_cfg_spu0_g1 = 0x0000000e, + regk_iop_sw_cfg_spu0_g2 = 0x0000000e, + regk_iop_sw_cfg_spu0_g3 = 0x0000000e, + regk_iop_sw_cfg_spu0_g4 = 0x0000000e, + regk_iop_sw_cfg_spu0_g5 = 0x0000000e, + regk_iop_sw_cfg_spu0_g6 = 0x0000000e, + regk_iop_sw_cfg_spu0_g7 = 0x0000000e, + regk_iop_sw_cfg_spu0_gio0 = 0x00000000, + regk_iop_sw_cfg_spu0_gio1 = 0x00000001, + regk_iop_sw_cfg_spu0_gio2 = 0x00000000, + regk_iop_sw_cfg_spu0_gio5 = 0x00000005, + regk_iop_sw_cfg_spu0_gio6 = 0x00000006, + regk_iop_sw_cfg_spu0_gio7 = 0x00000007, + regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, + regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, + regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, + regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, + regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, + regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, + regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, + regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, + regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, + regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, + regk_iop_sw_cfg_spu1 = 0x00000003, + regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, + regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, + regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, + regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, + regk_iop_sw_cfg_spu1_g0 = 0x0000000f, + regk_iop_sw_cfg_spu1_g1 = 0x0000000f, + regk_iop_sw_cfg_spu1_g2 = 0x0000000f, + regk_iop_sw_cfg_spu1_g3 = 0x0000000f, + regk_iop_sw_cfg_spu1_g4 = 0x0000000f, + regk_iop_sw_cfg_spu1_g5 = 0x0000000f, + regk_iop_sw_cfg_spu1_g6 = 0x0000000f, + regk_iop_sw_cfg_spu1_g7 = 0x0000000f, + regk_iop_sw_cfg_spu1_gio0 = 0x00000002, + regk_iop_sw_cfg_spu1_gio1 = 0x00000003, + regk_iop_sw_cfg_spu1_gio2 = 0x00000002, + regk_iop_sw_cfg_spu1_gio5 = 0x00000005, + regk_iop_sw_cfg_spu1_gio6 = 0x00000006, + regk_iop_sw_cfg_spu1_gio7 = 0x00000007, + regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, + regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, + regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, + regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, + regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, + regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, + regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, + regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, + regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, + regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, + regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, + regk_iop_sw_cfg_timer_grp0 = 0x00000000, + regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, + regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, + regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, + regk_iop_sw_cfg_timer_grp1 = 0x00000000, + regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, + regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, + regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, + regk_iop_sw_cfg_timer_grp2 = 0x00000000, + regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, + regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, + regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, + regk_iop_sw_cfg_timer_grp3 = 0x00000000, + regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, + regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, + regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, + regk_iop_sw_cfg_trig0_0 = 0x00000000, + regk_iop_sw_cfg_trig0_1 = 0x00000000, + regk_iop_sw_cfg_trig0_2 = 0x00000000, + regk_iop_sw_cfg_trig0_3 = 0x00000000, + regk_iop_sw_cfg_trig1_0 = 0x00000000, + regk_iop_sw_cfg_trig1_1 = 0x00000000, + regk_iop_sw_cfg_trig1_2 = 0x00000000, + regk_iop_sw_cfg_trig1_3 = 0x00000000, + regk_iop_sw_cfg_trig2_0 = 0x00000000, + regk_iop_sw_cfg_trig2_1 = 0x00000000, + regk_iop_sw_cfg_trig2_2 = 0x00000000, + regk_iop_sw_cfg_trig2_3 = 0x00000000, + regk_iop_sw_cfg_trig3_0 = 0x00000000, + regk_iop_sw_cfg_trig3_1 = 0x00000000, + regk_iop_sw_cfg_trig3_2 = 0x00000000, + regk_iop_sw_cfg_trig3_3 = 0x00000000, + regk_iop_sw_cfg_trig4_0 = 0x00000001, + regk_iop_sw_cfg_trig4_1 = 0x00000001, + regk_iop_sw_cfg_trig4_2 = 0x00000001, + regk_iop_sw_cfg_trig4_3 = 0x00000001, + regk_iop_sw_cfg_trig5_0 = 0x00000001, + regk_iop_sw_cfg_trig5_1 = 0x00000001, + regk_iop_sw_cfg_trig5_2 = 0x00000001, + regk_iop_sw_cfg_trig5_3 = 0x00000001, + regk_iop_sw_cfg_trig6_0 = 0x00000001, + regk_iop_sw_cfg_trig6_1 = 0x00000001, + regk_iop_sw_cfg_trig6_2 = 0x00000001, + regk_iop_sw_cfg_trig6_3 = 0x00000001, + regk_iop_sw_cfg_trig7_0 = 0x00000001, + regk_iop_sw_cfg_trig7_1 = 0x00000001, + regk_iop_sw_cfg_trig7_2 = 0x00000001, + regk_iop_sw_cfg_trig7_3 = 0x00000001 +}; +#endif /* __iop_sw_cfg_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h new file mode 100644 index 000000000..5fed844b1 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h @@ -0,0 +1,853 @@ +#ifndef __iop_sw_cpu_defs_h +#define __iop_sw_cpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r + * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cpu */ + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_cpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +typedef unsigned int reg_iop_sw_cpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_cpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 + +/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 + +/* Register r_bus0_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 + +/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 + +/* Register r_bus1_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_rw_intr0_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_rw_ack_intr0; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_r_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int spu1_8 : 1; + unsigned int spu1_9 : 1; + unsigned int spu1_10 : 1; + unsigned int spu1_11 : 1; + unsigned int spu1_12 : 1; + unsigned int spu1_13 : 1; + unsigned int spu1_14 : 1; + unsigned int spu1_15 : 1; +} reg_iop_sw_cpu_r_masked_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_rw_intr1_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_rw_ack_intr1; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_r_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int spu0_8 : 1; + unsigned int spu0_9 : 1; + unsigned int spu0_10 : 1; + unsigned int spu0_11 : 1; + unsigned int spu0_12 : 1; + unsigned int spu0_13 : 1; + unsigned int spu0_14 : 1; + unsigned int spu0_15 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; +} reg_iop_sw_cpu_r_masked_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112 + +/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_rw_intr2_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116 + +/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr2; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120 + +/* Register r_intr2, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_intr2; +#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124 + +/* Register r_masked_intr2, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int spu0_0 : 1; + unsigned int spu0_1 : 1; + unsigned int spu0_2 : 1; + unsigned int spu0_3 : 1; + unsigned int spu0_4 : 1; + unsigned int spu0_5 : 1; + unsigned int spu0_6 : 1; + unsigned int spu0_7 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out0_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_masked_intr2; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128 + +/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_rw_intr3_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132 + +/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr3; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136 + +/* Register r_intr3, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_r_intr3; +#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140 + +/* Register r_masked_intr3, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int spu1_0 : 1; + unsigned int spu1_1 : 1; + unsigned int spu1_2 : 1; + unsigned int spu1_3 : 1; + unsigned int spu1_4 : 1; + unsigned int spu1_5 : 1; + unsigned int spu1_6 : 1; + unsigned int spu1_7 : 1; + unsigned int dmc_in1 : 1; + unsigned int dmc_out1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int fifo_out1_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; +} reg_iop_sw_cpu_r_masked_intr3; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144 + + +/* Constants */ +enum { + regk_iop_sw_cpu_copy = 0x00000000, + regk_iop_sw_cpu_no = 0x00000000, + regk_iop_sw_cpu_rd = 0x00000002, + regk_iop_sw_cpu_reg_copy = 0x00000001, + regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, + regk_iop_sw_cpu_wr = 0x00000003, + regk_iop_sw_cpu_yes = 0x00000001 +}; +#endif /* __iop_sw_cpu_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h new file mode 100644 index 000000000..da718f2a8 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h @@ -0,0 +1,893 @@ +#ifndef __iop_sw_mpu_defs_h +#define __iop_sw_mpu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r + * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_mpu */ + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_mpu_rw_sw_cfg_owner; +#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 +#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_mpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +typedef unsigned int reg_iop_sw_mpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_mpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24 + +/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 + +/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 + +/* Register r_bus0_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44 + +/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 + +/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 + +/* Register r_bus1_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88 +#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp0_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr0 : 1; + unsigned int spu1_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr1 : 1; + unsigned int spu1_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr2 : 1; + unsigned int spu1_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr3 : 1; + unsigned int spu1_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp1_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr4 : 1; + unsigned int spu1_intr4 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr5 : 1; + unsigned int spu1_intr5 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr6 : 1; + unsigned int spu1_intr6 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr7 : 1; + unsigned int spu1_intr7 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp2_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr8 : 1; + unsigned int spu1_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr9 : 1; + unsigned int spu1_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr10 : 1; + unsigned int spu1_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr11 : 1; + unsigned int spu1_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_rw_intr_grp3_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int dummy1 : 6; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int dummy2 : 6; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int dummy3 : 6; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int dummy4 : 6; +} reg_iop_sw_mpu_rw_ack_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu0_intr12 : 1; + unsigned int spu1_intr12 : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int spu0_intr13 : 1; + unsigned int spu1_intr13 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp4 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int dmc_in0 : 1; + unsigned int spu0_intr14 : 1; + unsigned int spu1_intr14 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp5 : 1; + unsigned int timer_grp2 : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int dmc_out1 : 1; + unsigned int spu0_intr15 : 1; + unsigned int spu1_intr15 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int dmc_in1 : 1; +} reg_iop_sw_mpu_r_masked_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156 + + +/* Constants */ +enum { + regk_iop_sw_mpu_copy = 0x00000000, + regk_iop_sw_mpu_cpu = 0x00000000, + regk_iop_sw_mpu_mpu = 0x00000001, + regk_iop_sw_mpu_no = 0x00000000, + regk_iop_sw_mpu_nop = 0x00000000, + regk_iop_sw_mpu_rd = 0x00000002, + regk_iop_sw_mpu_reg_copy = 0x00000001, + regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, + regk_iop_sw_mpu_set = 0x00000001, + regk_iop_sw_mpu_spu0 = 0x00000002, + regk_iop_sw_mpu_spu1 = 0x00000003, + regk_iop_sw_mpu_wr = 0x00000003, + regk_iop_sw_mpu_yes = 0x00000001 +}; +#endif /* __iop_sw_mpu_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h new file mode 100644 index 000000000..b59dde4bd --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h @@ -0,0 +1,552 @@ +#ifndef __iop_sw_spu_defs_h +#define __iop_sw_spu_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: + * last modfied: Mon Apr 11 16:10:19 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r + * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_spu */ + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu0_mem : 1; + unsigned int wr_spu1_mem : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_spu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +typedef unsigned int reg_iop_sw_spu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +typedef unsigned int reg_iop_sw_spu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mc_data; +#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu0 : 1; + unsigned int busy_spu1 : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu0 : 1; + unsigned int owned_by_spu1 : 1; + unsigned int dummy1 : 24; +} reg_iop_sw_spu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 + +/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus0_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 + +/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus0_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 + +/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus0_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 + +/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus0_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 + +/* Register r_bus0_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus0_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 + +/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus1_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 + +/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus1_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 + +/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus1_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 + +/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus1_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 + +/* Register r_bus1_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus1_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_gio_in; +#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 + +/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 + +/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 + +/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 + +/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus0_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 +#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 + +/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 + +/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 + +/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 + +/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus1_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 +#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 +#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; + unsigned int timer_grp2 : 1; + unsigned int timer_grp3 : 1; + unsigned int fifo_out0 : 1; + unsigned int fifo_out0_extra : 1; + unsigned int fifo_in0 : 1; + unsigned int fifo_in0_extra : 1; + unsigned int fifo_out1 : 1; + unsigned int fifo_out1_extra : 1; + unsigned int fifo_in1 : 1; + unsigned int fifo_in1_extra : 1; + unsigned int dmc_out0 : 1; + unsigned int dmc_in0 : 1; + unsigned int dmc_out1 : 1; + unsigned int dmc_in1 : 1; + unsigned int dummy1 : 8; +} reg_iop_sw_spu_r_hw_intr; +#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 +#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int other_spu_intr0 : 1; + unsigned int other_spu_intr1 : 1; + unsigned int other_spu_intr2 : 1; + unsigned int other_spu_intr3 : 1; + unsigned int other_spu_intr4 : 1; + unsigned int other_spu_intr5 : 1; + unsigned int other_spu_intr6 : 1; + unsigned int other_spu_intr7 : 1; + unsigned int other_spu_intr8 : 1; + unsigned int other_spu_intr9 : 1; + unsigned int other_spu_intr10 : 1; + unsigned int other_spu_intr11 : 1; + unsigned int other_spu_intr12 : 1; + unsigned int other_spu_intr13 : 1; + unsigned int other_spu_intr14 : 1; + unsigned int other_spu_intr15 : 1; +} reg_iop_sw_spu_r_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 + + +/* Constants */ +enum { + regk_iop_sw_spu_copy = 0x00000000, + regk_iop_sw_spu_no = 0x00000000, + regk_iop_sw_spu_nop = 0x00000000, + regk_iop_sw_spu_rd = 0x00000002, + regk_iop_sw_spu_reg_copy = 0x00000001, + regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_spu_set = 0x00000001, + regk_iop_sw_spu_wr = 0x00000003, + regk_iop_sw_spu_yes = 0x00000001 +}; +#endif /* __iop_sw_spu_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h new file mode 100644 index 000000000..c994114f3 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h @@ -0,0 +1,249 @@ +#ifndef __iop_timer_grp_defs_h +#define __iop_timer_grp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_timer_grp.r + * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r + * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_timer_grp */ + +/* Register rw_cfg, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int clk_src : 1; + unsigned int trig : 2; + unsigned int clk_gen_div : 8; + unsigned int clk_div : 8; + unsigned int dummy1 : 13; +} reg_iop_timer_grp_rw_cfg; +#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 +#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 + +/* Register rw_half_period, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int quota_lo : 15; + unsigned int quota_hi : 15; + unsigned int quota_hi_sel : 1; + unsigned int dummy1 : 1; +} reg_iop_timer_grp_rw_half_period; +#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 +#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 + +/* Register rw_half_period_len, scope iop_timer_grp, type rw */ +typedef unsigned int reg_iop_timer_grp_rw_half_period_len; +#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 +#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 + +#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 +/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int clk_src : 3; + unsigned int strb : 2; + unsigned int run_mode : 2; + unsigned int out_mode : 1; + unsigned int active_on_tmr : 2; + unsigned int inv : 1; + unsigned int en_by_tmr : 2; + unsigned int dis_by_tmr : 2; + unsigned int en_only_by_reg : 1; + unsigned int dis_only_by_reg : 1; + unsigned int rst_at_en_strb : 1; + unsigned int dummy1 : 14; +} reg_iop_timer_grp_rw_tmr_cfg; +#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 +#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 + +#define STRIDE_iop_timer_grp_rw_tmr_len 4 +/* Register rw_tmr_len, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rw_tmr_len; +#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 +#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 + +/* Register rw_cmd, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int rst : 4; + unsigned int en : 4; + unsigned int dis : 4; + unsigned int strb : 4; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rw_cmd; +#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 +#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 + +/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ +typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; +#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 + +#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 +/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_rs_tmr_cnt; +#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 + +#define STRIDE_iop_timer_grp_r_tmr_cnt 8 +/* Register r_tmr_cnt, scope iop_timer_grp, type r */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_timer_grp_r_tmr_cnt; +#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 + +/* Register rw_intr_mask, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_rw_intr_mask; +#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 +#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 + +/* Register rw_ack_intr, scope iop_timer_grp, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_rw_ack_intr; +#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 +#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 + +/* Register r_intr, scope iop_timer_grp, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_r_intr; +#define REG_RD_ADDR_iop_timer_grp_r_intr 108 + +/* Register r_masked_intr, scope iop_timer_grp, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int tmr2 : 1; + unsigned int tmr3 : 1; + unsigned int dummy1 : 28; +} reg_iop_timer_grp_r_masked_intr; +#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 + + +/* Constants */ +enum { + regk_iop_timer_grp_clk200 = 0x00000000, + regk_iop_timer_grp_clk_gen = 0x00000002, + regk_iop_timer_grp_complete = 0x00000002, + regk_iop_timer_grp_div_clk200 = 0x00000001, + regk_iop_timer_grp_div_clk_gen = 0x00000003, + regk_iop_timer_grp_ext = 0x00000001, + regk_iop_timer_grp_hi = 0x00000000, + regk_iop_timer_grp_long_period = 0x00000001, + regk_iop_timer_grp_neg = 0x00000002, + regk_iop_timer_grp_no = 0x00000000, + regk_iop_timer_grp_once = 0x00000003, + regk_iop_timer_grp_pause = 0x00000001, + regk_iop_timer_grp_pos = 0x00000001, + regk_iop_timer_grp_pos_neg = 0x00000003, + regk_iop_timer_grp_pulse = 0x00000000, + regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, + regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, + regk_iop_timer_grp_rw_cfg_default = 0x00000002, + regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, + regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, + regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, + regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, + regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, + regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, + regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, + regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, + regk_iop_timer_grp_short_period = 0x00000000, + regk_iop_timer_grp_stop = 0x00000000, + regk_iop_timer_grp_tmr = 0x00000004, + regk_iop_timer_grp_toggle = 0x00000001, + regk_iop_timer_grp_yes = 0x00000001 +}; +#endif /* __iop_timer_grp_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h new file mode 100644 index 000000000..36e442823 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h @@ -0,0 +1,170 @@ +#ifndef __iop_trigger_grp_defs_h +#define __iop_trigger_grp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp + * last modfied: Mon Apr 11 16:08:46 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r + * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_trigger_grp */ + +#define STRIDE_iop_trigger_grp_rw_cfg 4 +/* Register rw_cfg, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int action : 2; + unsigned int once : 1; + unsigned int trig : 3; + unsigned int en_only_by_reg : 1; + unsigned int dis_only_by_reg : 1; + unsigned int dummy1 : 24; +} reg_iop_trigger_grp_rw_cfg; +#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 +#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 + +/* Register rw_cmd, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int dis : 4; + unsigned int en : 4; + unsigned int dummy1 : 24; +} reg_iop_trigger_grp_rw_cmd; +#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 +#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 + +/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_rw_intr_mask; +#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 +#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 + +/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_rw_ack_intr; +#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 +#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 + +/* Register r_intr, scope iop_trigger_grp, type r */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_r_intr; +#define REG_RD_ADDR_iop_trigger_grp_r_intr 28 + +/* Register r_masked_intr, scope iop_trigger_grp, type r */ +typedef struct { + unsigned int trig0 : 1; + unsigned int trig1 : 1; + unsigned int trig2 : 1; + unsigned int trig3 : 1; + unsigned int dummy1 : 28; +} reg_iop_trigger_grp_r_masked_intr; +#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 + + +/* Constants */ +enum { + regk_iop_trigger_grp_fall = 0x00000002, + regk_iop_trigger_grp_fall_lo = 0x00000006, + regk_iop_trigger_grp_no = 0x00000000, + regk_iop_trigger_grp_off = 0x00000000, + regk_iop_trigger_grp_pulse = 0x00000000, + regk_iop_trigger_grp_rise = 0x00000001, + regk_iop_trigger_grp_rise_fall = 0x00000003, + regk_iop_trigger_grp_rise_fall_hi = 0x00000007, + regk_iop_trigger_grp_rise_fall_lo = 0x00000004, + regk_iop_trigger_grp_rise_hi = 0x00000005, + regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, + regk_iop_trigger_grp_rw_cfg_size = 0x00000004, + regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, + regk_iop_trigger_grp_toggle = 0x00000003, + regk_iop_trigger_grp_yes = 0x00000001 +}; +#endif /* __iop_trigger_grp_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h new file mode 100644 index 000000000..b8d6a910c --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h @@ -0,0 +1,99 @@ +#ifndef __iop_version_defs_h +#define __iop_version_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/io_proc/rtl/guinness/iop_version.r + * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp + * last modfied: Mon Apr 11 16:08:44 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r + * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_version */ + +/* Register r_version, scope iop_version, type r */ +typedef struct { + unsigned int nr : 8; + unsigned int dummy1 : 24; +} reg_iop_version_r_version; +#define REG_RD_ADDR_iop_version_r_version 0 + + +/* Constants */ +enum { + regk_iop_version_v1_0 = 0x00000001 +}; +#endif /* __iop_version_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h new file mode 100644 index 000000000..7b167e3c0 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h @@ -0,0 +1,104 @@ +#ifndef __irq_nmi_defs_h +#define __irq_nmi_defs_h + +/* + * This file is autogenerated from + * file: ../../mod/irq_nmi.r + * id: + * last modfied: Thu Jan 22 09:22:43 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r + * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope irq_nmi */ + +/* Register rw_cmd, scope irq_nmi, type rw */ +typedef struct { + unsigned int delay : 16; + unsigned int op : 2; + unsigned int dummy1 : 14; +} reg_irq_nmi_rw_cmd; +#define REG_RD_ADDR_irq_nmi_rw_cmd 0 +#define REG_WR_ADDR_irq_nmi_rw_cmd 0 + + +/* Constants */ +enum { + regk_irq_nmi_ack_irq = 0x00000002, + regk_irq_nmi_ack_nmi = 0x00000003, + regk_irq_nmi_irq = 0x00000000, + regk_irq_nmi_nmi = 0x00000001 +}; +#endif /* __irq_nmi_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h new file mode 100644 index 000000000..a11fdd3cd --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h @@ -0,0 +1,205 @@ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Fri Nov 7 15:36:04 2003 + * + * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_break_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_addr; +#define REG_RD_ADDR_marb_bp_r_break_addr 20 + +/* Register r_break_op, scope marb_bp, type r */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_break_op; +#define REG_RD_ADDR_marb_bp_r_break_op 24 + +/* Register r_break_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_clients; +#define REG_RD_ADDR_marb_bp_r_break_clients 28 + +/* Register r_break_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_first_client; +#define REG_RD_ADDR_marb_bp_r_break_first_client 32 + +/* Register r_break_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_size; +#define REG_RD_ADDR_marb_bp_r_break_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h new file mode 100644 index 000000000..71e8af0bb --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h @@ -0,0 +1,475 @@ +#ifndef __marb_defs_h +#define __marb_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb */ + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_int_slots; +#define REG_RD_ADDR_marb_rw_int_slots 0 +#define REG_WR_ADDR_marb_rw_int_slots 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_ext_slots; +#define REG_RD_ADDR_marb_rw_ext_slots 256 +#define REG_WR_ADDR_marb_rw_ext_slots 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_regs_slots; +#define REG_RD_ADDR_marb_rw_regs_slots 512 +#define REG_WR_ADDR_marb_rw_regs_slots 512 + +/* Register rw_intr_mask, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_intr_mask; +#define REG_RD_ADDR_marb_rw_intr_mask 528 +#define REG_WR_ADDR_marb_rw_intr_mask 528 + +/* Register rw_ack_intr, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_ack_intr; +#define REG_RD_ADDR_marb_rw_ack_intr 532 +#define REG_WR_ADDR_marb_rw_ack_intr 532 + +/* Register r_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_intr; +#define REG_RD_ADDR_marb_r_intr 536 + +/* Register r_masked_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_masked_intr; +#define REG_RD_ADDR_marb_r_masked_intr 540 + +/* Register rw_stop_mask, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_stop_mask; +#define REG_RD_ADDR_marb_rw_stop_mask 544 +#define REG_WR_ADDR_marb_rw_stop_mask 544 + +/* Register r_stopped, scope marb, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_r_stopped; +#define REG_RD_ADDR_marb_r_stopped 548 + +/* Register rw_no_snoop, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_no_snoop; +#define REG_RD_ADDR_marb_rw_no_snoop 832 +#define REG_WR_ADDR_marb_rw_no_snoop 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +typedef struct { + unsigned int dummy1 : 10; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 20; +} reg_marb_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 +#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 + + +/* Constants */ +enum { + regk_marb_cpud = 0x0000000b, + regk_marb_cpui = 0x0000000a, + regk_marb_dma0 = 0x00000000, + regk_marb_dma1 = 0x00000001, + regk_marb_dma2 = 0x00000002, + regk_marb_dma3 = 0x00000003, + regk_marb_dma4 = 0x00000004, + regk_marb_dma5 = 0x00000005, + regk_marb_dma6 = 0x00000006, + regk_marb_dma7 = 0x00000007, + regk_marb_dma8 = 0x00000008, + regk_marb_dma9 = 0x00000009, + regk_marb_iop = 0x0000000c, + regk_marb_no = 0x00000000, + regk_marb_r_stopped_default = 0x00000000, + regk_marb_rw_ext_slots_default = 0x00000000, + regk_marb_rw_ext_slots_size = 0x00000040, + regk_marb_rw_int_slots_default = 0x00000000, + regk_marb_rw_int_slots_size = 0x00000040, + regk_marb_rw_intr_mask_default = 0x00000000, + regk_marb_rw_no_snoop_default = 0x00000000, + regk_marb_rw_no_snoop_rq_default = 0x00000000, + regk_marb_rw_regs_slots_default = 0x00000000, + regk_marb_rw_regs_slots_size = 0x00000004, + regk_marb_rw_stop_mask_default = 0x00000000, + regk_marb_slave = 0x0000000d, + regk_marb_yes = 0x00000001 +}; +#endif /* __marb_defs_h */ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_brk_op; +#define REG_RD_ADDR_marb_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_size; +#define REG_RD_ADDR_marb_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h new file mode 100644 index 000000000..236f91efe --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h @@ -0,0 +1,17 @@ +/* + * Read/write register macros used by *_defs.h + */ + +#ifndef reg_rdwr_h +#define reg_rdwr_h + +#ifndef REG_READ +#define REG_READ(type, addr) (*((volatile type *) (addr))) +#endif + +#ifndef REG_WRITE +#define REG_WRITE(type, addr, val) \ + do { *((volatile type *) (addr)) = (val); } while(0) +#endif + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h new file mode 100644 index 000000000..d9f0e924f --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h @@ -0,0 +1,173 @@ +#ifndef __rt_trace_defs_h +#define __rt_trace_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/rt_trace/rtl/rt_regs.r + * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp + * last modfied: Mon Apr 11 16:09:14 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r + * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope rt_trace */ + +/* Register rw_cfg, scope rt_trace, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int mode : 1; + unsigned int owner : 1; + unsigned int wp : 1; + unsigned int stall : 1; + unsigned int dummy1 : 3; + unsigned int wp_start : 7; + unsigned int dummy2 : 1; + unsigned int wp_stop : 7; + unsigned int dummy3 : 9; +} reg_rt_trace_rw_cfg; +#define REG_RD_ADDR_rt_trace_rw_cfg 0 +#define REG_WR_ADDR_rt_trace_rw_cfg 0 + +/* Register rw_tap_ctrl, scope rt_trace, type rw */ +typedef struct { + unsigned int ack_data : 1; + unsigned int ack_guru : 1; + unsigned int dummy1 : 30; +} reg_rt_trace_rw_tap_ctrl; +#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4 +#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4 + +/* Register r_tap_stat, scope rt_trace, type r */ +typedef struct { + unsigned int dav : 1; + unsigned int empty : 1; + unsigned int dummy1 : 30; +} reg_rt_trace_r_tap_stat; +#define REG_RD_ADDR_rt_trace_r_tap_stat 8 + +/* Register rw_tap_data, scope rt_trace, type rw */ +typedef unsigned int reg_rt_trace_rw_tap_data; +#define REG_RD_ADDR_rt_trace_rw_tap_data 12 +#define REG_WR_ADDR_rt_trace_rw_tap_data 12 + +/* Register rw_tap_hdata, scope rt_trace, type rw */ +typedef struct { + unsigned int op : 4; + unsigned int sub_op : 4; + unsigned int dummy1 : 24; +} reg_rt_trace_rw_tap_hdata; +#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16 +#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16 + +/* Register r_redir, scope rt_trace, type r */ +typedef unsigned int reg_rt_trace_r_redir; +#define REG_RD_ADDR_rt_trace_r_redir 20 + + +/* Constants */ +enum { + regk_rt_trace_brk = 0x0000000c, + regk_rt_trace_dbg = 0x00000003, + regk_rt_trace_dbgdi = 0x00000004, + regk_rt_trace_dbgdo = 0x00000005, + regk_rt_trace_gmode = 0x00000000, + regk_rt_trace_no = 0x00000000, + regk_rt_trace_nop = 0x00000000, + regk_rt_trace_normal = 0x00000000, + regk_rt_trace_rdmem = 0x00000007, + regk_rt_trace_rdmemb = 0x00000009, + regk_rt_trace_rdpreg = 0x00000002, + regk_rt_trace_rdreg = 0x00000001, + regk_rt_trace_rdsreg = 0x00000003, + regk_rt_trace_redir = 0x00000006, + regk_rt_trace_ret = 0x0000000b, + regk_rt_trace_rw_cfg_default = 0x00000000, + regk_rt_trace_trcfg = 0x00000001, + regk_rt_trace_wp = 0x00000001, + regk_rt_trace_wp0 = 0x00000001, + regk_rt_trace_wp1 = 0x00000002, + regk_rt_trace_wp2 = 0x00000004, + regk_rt_trace_wp3 = 0x00000008, + regk_rt_trace_wp4 = 0x00000010, + regk_rt_trace_wp5 = 0x00000020, + regk_rt_trace_wp6 = 0x00000040, + regk_rt_trace_wrmem = 0x00000008, + regk_rt_trace_wrmemb = 0x0000000a, + regk_rt_trace_wrpreg = 0x00000005, + regk_rt_trace_wrreg = 0x00000004, + regk_rt_trace_wrsreg = 0x00000006, + regk_rt_trace_yes = 0x00000001 +}; +#endif /* __rt_trace_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h new file mode 100644 index 000000000..01c2fab97 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h @@ -0,0 +1,308 @@ +#ifndef __ser_defs_h +#define __ser_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/ser/rtl/ser_regs.r + * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp + * last modfied: Mon Apr 11 16:09:21 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r + * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ser */ + +/* Register rw_tr_ctrl, scope ser, type rw */ +typedef struct { + unsigned int base_freq : 3; + unsigned int en : 1; + unsigned int par : 2; + unsigned int par_en : 1; + unsigned int data_bits : 1; + unsigned int stop_bits : 1; + unsigned int stop : 1; + unsigned int rts_delay : 3; + unsigned int rts_setup : 1; + unsigned int auto_rts : 1; + unsigned int txd : 1; + unsigned int auto_cts : 1; + unsigned int dummy1 : 15; +} reg_ser_rw_tr_ctrl; +#define REG_RD_ADDR_ser_rw_tr_ctrl 0 +#define REG_WR_ADDR_ser_rw_tr_ctrl 0 + +/* Register rw_tr_dma_en, scope ser, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_tr_dma_en; +#define REG_RD_ADDR_ser_rw_tr_dma_en 4 +#define REG_WR_ADDR_ser_rw_tr_dma_en 4 + +/* Register rw_rec_ctrl, scope ser, type rw */ +typedef struct { + unsigned int base_freq : 3; + unsigned int en : 1; + unsigned int par : 2; + unsigned int par_en : 1; + unsigned int data_bits : 1; + unsigned int dma_mode : 1; + unsigned int dma_err : 1; + unsigned int sampling : 1; + unsigned int timeout : 3; + unsigned int auto_eop : 1; + unsigned int half_duplex : 1; + unsigned int rts_n : 1; + unsigned int loopback : 1; + unsigned int dummy1 : 14; +} reg_ser_rw_rec_ctrl; +#define REG_RD_ADDR_ser_rw_rec_ctrl 8 +#define REG_WR_ADDR_ser_rw_rec_ctrl 8 + +/* Register rw_tr_baud_div, scope ser, type rw */ +typedef struct { + unsigned int div : 16; + unsigned int dummy1 : 16; +} reg_ser_rw_tr_baud_div; +#define REG_RD_ADDR_ser_rw_tr_baud_div 12 +#define REG_WR_ADDR_ser_rw_tr_baud_div 12 + +/* Register rw_rec_baud_div, scope ser, type rw */ +typedef struct { + unsigned int div : 16; + unsigned int dummy1 : 16; +} reg_ser_rw_rec_baud_div; +#define REG_RD_ADDR_ser_rw_rec_baud_div 16 +#define REG_WR_ADDR_ser_rw_rec_baud_div 16 + +/* Register rw_xoff, scope ser, type rw */ +typedef struct { + unsigned int chr : 8; + unsigned int automatic : 1; + unsigned int dummy1 : 23; +} reg_ser_rw_xoff; +#define REG_RD_ADDR_ser_rw_xoff 20 +#define REG_WR_ADDR_ser_rw_xoff 20 + +/* Register rw_xoff_clr, scope ser, type rw */ +typedef struct { + unsigned int clr : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_xoff_clr; +#define REG_RD_ADDR_ser_rw_xoff_clr 24 +#define REG_WR_ADDR_ser_rw_xoff_clr 24 + +/* Register rw_dout, scope ser, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_ser_rw_dout; +#define REG_RD_ADDR_ser_rw_dout 28 +#define REG_WR_ADDR_ser_rw_dout 28 + +/* Register rs_stat_din, scope ser, type rs */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 8; + unsigned int dav : 1; + unsigned int framing_err : 1; + unsigned int par_err : 1; + unsigned int orun : 1; + unsigned int rec_err : 1; + unsigned int rxd : 1; + unsigned int tr_idle : 1; + unsigned int tr_empty : 1; + unsigned int tr_rdy : 1; + unsigned int cts_n : 1; + unsigned int xoff_detect : 1; + unsigned int rts_n : 1; + unsigned int txd : 1; + unsigned int dummy2 : 3; +} reg_ser_rs_stat_din; +#define REG_RD_ADDR_ser_rs_stat_din 32 + +/* Register r_stat_din, scope ser, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 8; + unsigned int dav : 1; + unsigned int framing_err : 1; + unsigned int par_err : 1; + unsigned int orun : 1; + unsigned int rec_err : 1; + unsigned int rxd : 1; + unsigned int tr_idle : 1; + unsigned int tr_empty : 1; + unsigned int tr_rdy : 1; + unsigned int cts_n : 1; + unsigned int xoff_detect : 1; + unsigned int rts_n : 1; + unsigned int txd : 1; + unsigned int dummy2 : 3; +} reg_ser_r_stat_din; +#define REG_RD_ADDR_ser_r_stat_din 36 + +/* Register rw_rec_eop, scope ser, type rw */ +typedef struct { + unsigned int set : 1; + unsigned int dummy1 : 31; +} reg_ser_rw_rec_eop; +#define REG_RD_ADDR_ser_rw_rec_eop 40 +#define REG_WR_ADDR_ser_rw_rec_eop 40 + +/* Register rw_intr_mask, scope ser, type rw */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_rw_intr_mask; +#define REG_RD_ADDR_ser_rw_intr_mask 44 +#define REG_WR_ADDR_ser_rw_intr_mask 44 + +/* Register rw_ack_intr, scope ser, type rw */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_rw_ack_intr; +#define REG_RD_ADDR_ser_rw_ack_intr 48 +#define REG_WR_ADDR_ser_rw_ack_intr 48 + +/* Register r_intr, scope ser, type r */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_r_intr; +#define REG_RD_ADDR_ser_r_intr 52 + +/* Register r_masked_intr, scope ser, type r */ +typedef struct { + unsigned int tr_rdy : 1; + unsigned int tr_empty : 1; + unsigned int tr_idle : 1; + unsigned int dav : 1; + unsigned int dummy1 : 28; +} reg_ser_r_masked_intr; +#define REG_RD_ADDR_ser_r_masked_intr 56 + + +/* Constants */ +enum { + regk_ser_active = 0x00000000, + regk_ser_bits1 = 0x00000000, + regk_ser_bits2 = 0x00000001, + regk_ser_bits7 = 0x00000001, + regk_ser_bits8 = 0x00000000, + regk_ser_del0_5 = 0x00000000, + regk_ser_del1 = 0x00000001, + regk_ser_del1_5 = 0x00000002, + regk_ser_del2 = 0x00000003, + regk_ser_del2_5 = 0x00000004, + regk_ser_del3 = 0x00000005, + regk_ser_del3_5 = 0x00000006, + regk_ser_del4 = 0x00000007, + regk_ser_even = 0x00000000, + regk_ser_ext = 0x00000001, + regk_ser_f100 = 0x00000007, + regk_ser_f29_493 = 0x00000004, + regk_ser_f32 = 0x00000005, + regk_ser_f32_768 = 0x00000006, + regk_ser_ignore = 0x00000001, + regk_ser_inactive = 0x00000001, + regk_ser_majority = 0x00000001, + regk_ser_mark = 0x00000002, + regk_ser_middle = 0x00000000, + regk_ser_no = 0x00000000, + regk_ser_odd = 0x00000001, + regk_ser_off = 0x00000000, + regk_ser_rw_intr_mask_default = 0x00000000, + regk_ser_rw_rec_baud_div_default = 0x00000000, + regk_ser_rw_rec_ctrl_default = 0x00010000, + regk_ser_rw_tr_baud_div_default = 0x00000000, + regk_ser_rw_tr_ctrl_default = 0x00008000, + regk_ser_rw_tr_dma_en_default = 0x00000000, + regk_ser_rw_xoff_default = 0x00000000, + regk_ser_space = 0x00000003, + regk_ser_stop = 0x00000000, + regk_ser_yes = 0x00000001 +}; +#endif /* __ser_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h new file mode 100644 index 000000000..8d1dab218 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h @@ -0,0 +1,331 @@ +#ifndef __sser_defs_h +#define __sser_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/syncser/rtl/sser_regs.r + * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp + * last modfied: Mon Apr 11 16:09:48 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r + * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope sser */ + +/* Register rw_cfg, scope sser, type rw */ +typedef struct { + unsigned int clk_div : 16; + unsigned int base_freq : 3; + unsigned int gate_clk : 1; + unsigned int clkgate_ctrl : 1; + unsigned int clkgate_in : 1; + unsigned int clk_dir : 1; + unsigned int clk_od_mode : 1; + unsigned int out_clk_pol : 1; + unsigned int out_clk_src : 2; + unsigned int clk_in_sel : 1; + unsigned int hold_pol : 1; + unsigned int prepare : 1; + unsigned int en : 1; + unsigned int dummy1 : 1; +} reg_sser_rw_cfg; +#define REG_RD_ADDR_sser_rw_cfg 0 +#define REG_WR_ADDR_sser_rw_cfg 0 + +/* Register rw_frm_cfg, scope sser, type rw */ +typedef struct { + unsigned int wordrate : 10; + unsigned int rec_delay : 3; + unsigned int tr_delay : 3; + unsigned int early_wend : 1; + unsigned int level : 2; + unsigned int type : 1; + unsigned int clk_pol : 1; + unsigned int fr_in_rxclk : 1; + unsigned int clk_src : 1; + unsigned int out_off : 1; + unsigned int out_on : 1; + unsigned int frame_pin_dir : 1; + unsigned int frame_pin_use : 2; + unsigned int status_pin_dir : 1; + unsigned int status_pin_use : 2; + unsigned int dummy1 : 1; +} reg_sser_rw_frm_cfg; +#define REG_RD_ADDR_sser_rw_frm_cfg 4 +#define REG_WR_ADDR_sser_rw_frm_cfg 4 + +/* Register rw_tr_cfg, scope sser, type rw */ +typedef struct { + unsigned int tr_en : 1; + unsigned int stop : 1; + unsigned int urun_stop : 1; + unsigned int eop_stop : 1; + unsigned int sample_size : 6; + unsigned int sh_dir : 1; + unsigned int clk_pol : 1; + unsigned int clk_src : 1; + unsigned int use_dma : 1; + unsigned int mode : 2; + unsigned int frm_src : 1; + unsigned int use60958 : 1; + unsigned int iec60958_ckdiv : 2; + unsigned int rate_ctrl : 1; + unsigned int use_md : 1; + unsigned int dual_i2s : 1; + unsigned int data_pin_use : 2; + unsigned int od_mode : 1; + unsigned int bulk_wspace : 2; + unsigned int dummy1 : 4; +} reg_sser_rw_tr_cfg; +#define REG_RD_ADDR_sser_rw_tr_cfg 8 +#define REG_WR_ADDR_sser_rw_tr_cfg 8 + +/* Register rw_rec_cfg, scope sser, type rw */ +typedef struct { + unsigned int rec_en : 1; + unsigned int force_eop : 1; + unsigned int stop : 1; + unsigned int orun_stop : 1; + unsigned int eop_stop : 1; + unsigned int sample_size : 6; + unsigned int sh_dir : 1; + unsigned int clk_pol : 1; + unsigned int clk_src : 1; + unsigned int use_dma : 1; + unsigned int mode : 2; + unsigned int frm_src : 2; + unsigned int use60958 : 1; + unsigned int iec60958_ui_len : 5; + unsigned int slave2_en : 1; + unsigned int slave3_en : 1; + unsigned int fifo_thr : 2; + unsigned int dummy1 : 3; +} reg_sser_rw_rec_cfg; +#define REG_RD_ADDR_sser_rw_rec_cfg 12 +#define REG_WR_ADDR_sser_rw_rec_cfg 12 + +/* Register rw_tr_data, scope sser, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int md : 1; + unsigned int dummy1 : 15; +} reg_sser_rw_tr_data; +#define REG_RD_ADDR_sser_rw_tr_data 16 +#define REG_WR_ADDR_sser_rw_tr_data 16 + +/* Register r_rec_data, scope sser, type r */ +typedef struct { + unsigned int data : 16; + unsigned int md : 1; + unsigned int ext_clk : 1; + unsigned int status_in : 1; + unsigned int frame_in : 1; + unsigned int din : 1; + unsigned int data_in : 1; + unsigned int clk_in : 1; + unsigned int dummy1 : 9; +} reg_sser_r_rec_data; +#define REG_RD_ADDR_sser_r_rec_data 20 + +/* Register rw_extra, scope sser, type rw */ +typedef struct { + unsigned int clkoff_cycles : 20; + unsigned int clkoff_en : 1; + unsigned int clkon_en : 1; + unsigned int dout_delay : 5; + unsigned int dummy1 : 5; +} reg_sser_rw_extra; +#define REG_RD_ADDR_sser_rw_extra 24 +#define REG_WR_ADDR_sser_rw_extra 24 + +/* Register rw_intr_mask, scope sser, type rw */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_rw_intr_mask; +#define REG_RD_ADDR_sser_rw_intr_mask 28 +#define REG_WR_ADDR_sser_rw_intr_mask 28 + +/* Register rw_ack_intr, scope sser, type rw */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_rw_ack_intr; +#define REG_RD_ADDR_sser_rw_ack_intr 32 +#define REG_WR_ADDR_sser_rw_ack_intr 32 + +/* Register r_intr, scope sser, type r */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_r_intr; +#define REG_RD_ADDR_sser_r_intr 36 + +/* Register r_masked_intr, scope sser, type r */ +typedef struct { + unsigned int trdy : 1; + unsigned int rdav : 1; + unsigned int tidle : 1; + unsigned int rstop : 1; + unsigned int urun : 1; + unsigned int orun : 1; + unsigned int md_rec : 1; + unsigned int md_sent : 1; + unsigned int r958err : 1; + unsigned int dummy1 : 23; +} reg_sser_r_masked_intr; +#define REG_RD_ADDR_sser_r_masked_intr 40 + + +/* Constants */ +enum { + regk_sser_both = 0x00000002, + regk_sser_bulk = 0x00000001, + regk_sser_clk100 = 0x00000000, + regk_sser_clk_in = 0x00000000, + regk_sser_const0 = 0x00000003, + regk_sser_dout = 0x00000002, + regk_sser_edge = 0x00000000, + regk_sser_ext = 0x00000001, + regk_sser_ext_clk = 0x00000001, + regk_sser_f100 = 0x00000000, + regk_sser_f29_493 = 0x00000004, + regk_sser_f32 = 0x00000005, + regk_sser_f32_768 = 0x00000006, + regk_sser_frm = 0x00000003, + regk_sser_gio0 = 0x00000000, + regk_sser_gio1 = 0x00000001, + regk_sser_hispeed = 0x00000001, + regk_sser_hold = 0x00000002, + regk_sser_in = 0x00000000, + regk_sser_inf = 0x00000003, + regk_sser_intern = 0x00000000, + regk_sser_intern_clk = 0x00000001, + regk_sser_intern_tb = 0x00000000, + regk_sser_iso = 0x00000000, + regk_sser_level = 0x00000001, + regk_sser_lospeed = 0x00000000, + regk_sser_lsbfirst = 0x00000000, + regk_sser_msbfirst = 0x00000001, + regk_sser_neg = 0x00000001, + regk_sser_neg_lo = 0x00000000, + regk_sser_no = 0x00000000, + regk_sser_no_clk = 0x00000007, + regk_sser_nojitter = 0x00000002, + regk_sser_out = 0x00000001, + regk_sser_pos = 0x00000000, + regk_sser_pos_hi = 0x00000001, + regk_sser_rec = 0x00000000, + regk_sser_rw_cfg_default = 0x00000000, + regk_sser_rw_extra_default = 0x00000000, + regk_sser_rw_frm_cfg_default = 0x00000000, + regk_sser_rw_intr_mask_default = 0x00000000, + regk_sser_rw_rec_cfg_default = 0x00000000, + regk_sser_rw_tr_cfg_default = 0x01800000, + regk_sser_rw_tr_data_default = 0x00000000, + regk_sser_thr16 = 0x00000001, + regk_sser_thr32 = 0x00000002, + regk_sser_thr8 = 0x00000000, + regk_sser_tr = 0x00000001, + regk_sser_ts_out = 0x00000003, + regk_sser_tx_bulk = 0x00000002, + regk_sser_wiresave = 0x00000002, + regk_sser_yes = 0x00000001 +}; +#endif /* __sser_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/strcop.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/strcop.h new file mode 100644 index 000000000..35131ba46 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/strcop.h @@ -0,0 +1,57 @@ +// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $ + +// Streamcop meta-data configuration structs + +struct strcop_meta_out { + unsigned char csumsel : 3; + unsigned char ciphsel : 3; + unsigned char ciphconf : 2; + unsigned char hashsel : 3; + unsigned char hashconf : 1; + unsigned char hashmode : 1; + unsigned char decrypt : 1; + unsigned char dlkey : 1; + unsigned char cbcmode : 1; +}; + +struct strcop_meta_in { + unsigned char dmasel : 3; + unsigned char sync : 1; + unsigned char res1 : 5; + unsigned char res2; +}; + +// Source definitions + +enum { + src_none = 0, + src_dma = 1, + src_des = 2, + src_sha1 = 3, + src_csum = 4, + src_aes = 5, + src_md5 = 6, + src_res = 7 +}; + +// Cipher definitions + +enum { + ciph_des = 0, + ciph_3des = 1, + ciph_aes = 2 +}; + +// Hash definitions + +enum { + hash_sha1 = 0, + hash_md5 = 1 +}; + +enum { + hash_noiv = 0, + hash_iv = 1 +}; + + diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h new file mode 100644 index 000000000..bd145a49b --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h @@ -0,0 +1,109 @@ +#ifndef __strcop_defs_h +#define __strcop_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/strcop/rtl/strcop_regs.r + * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp + * last modfied: Mon Apr 11 16:09:38 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r + * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strcop */ + +/* Register rw_cfg, scope strcop, type rw */ +typedef struct { + unsigned int td3 : 1; + unsigned int td2 : 1; + unsigned int td1 : 1; + unsigned int ipend : 1; + unsigned int ignore_sync : 1; + unsigned int en : 1; + unsigned int dummy1 : 26; +} reg_strcop_rw_cfg; +#define REG_RD_ADDR_strcop_rw_cfg 0 +#define REG_WR_ADDR_strcop_rw_cfg 0 + + +/* Constants */ +enum { + regk_strcop_big = 0x00000001, + regk_strcop_d = 0x00000001, + regk_strcop_e = 0x00000000, + regk_strcop_little = 0x00000000, + regk_strcop_rw_cfg_default = 0x00000002 +}; +#endif /* __strcop_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h b/kernel/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h new file mode 100644 index 000000000..ffe49625a --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h @@ -0,0 +1,78 @@ +#ifndef __SUPP_REG_H__ +#define __SUPP_REG_H__ + +/* Macros for reading and writing support/special registers. */ + +#ifndef STRINGIFYFY +#define STRINGIFYFY(i) #i +#endif + +#ifndef STRINGIFY +#define STRINGIFY(i) STRINGIFYFY(i) +#endif + +#define SPEC_REG_BZ "BZ" +#define SPEC_REG_VR "VR" +#define SPEC_REG_PID "PID" +#define SPEC_REG_SRS "SRS" +#define SPEC_REG_WZ "WZ" +#define SPEC_REG_EXS "EXS" +#define SPEC_REG_EDA "EDA" +#define SPEC_REG_MOF "MOF" +#define SPEC_REG_DZ "DZ" +#define SPEC_REG_EBP "EBP" +#define SPEC_REG_ERP "ERP" +#define SPEC_REG_SRP "SRP" +#define SPEC_REG_NRP "NRP" +#define SPEC_REG_CCS "CCS" +#define SPEC_REG_USP "USP" +#define SPEC_REG_SPC "SPC" + +#define RW_MM_CFG 0 +#define RW_MM_KBASE_LO 1 +#define RW_MM_KBASE_HI 2 +#define RW_MM_CAUSE 3 +#define RW_MM_TLB_SEL 4 +#define RW_MM_TLB_LO 5 +#define RW_MM_TLB_HI 6 +#define RW_MM_TLB_PGD 7 + +#define BANK_GC 0 +#define BANK_IM 1 +#define BANK_DM 2 +#define BANK_BP 3 + +#define RW_GC_CFG 0 +#define RW_GC_CCS 1 +#define RW_GC_SRS 2 +#define RW_GC_NRP 3 +#define RW_GC_EXS 4 +#define RW_GC_R0 8 +#define RW_GC_R1 9 + +#define SPEC_REG_WR(r,v) \ +__asm__ __volatile__ ("move %0, $" r : : "r" (v)); + +#define SPEC_REG_RD(r,v) \ +__asm__ __volatile__ ("move $" r ",%0" : "=r" (v)); + +#define NOP() \ + __asm__ __volatile__ ("nop"); + +#define SUPP_BANK_SEL(b) \ + SPEC_REG_WR(SPEC_REG_SRS,b); \ + NOP(); \ + NOP(); \ + NOP(); + +#define SUPP_REG_WR(r,v) \ +__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + : : "r" (v)); + +#define SUPP_REG_RD(r,v) \ +__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v)); + +#endif /* __SUPP_REG_H__ */ diff --git a/kernel/arch/cris/include/arch-v32/arch/intmem.h b/kernel/arch/cris/include/arch-v32/arch/intmem.h new file mode 100644 index 000000000..c0ada33bf --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/intmem.h @@ -0,0 +1,9 @@ +#ifndef _ASM_CRIS_INTMEM_H +#define _ASM_CRIS_INTMEM_H + +void* crisv32_intmem_alloc(unsigned size, unsigned align); +void crisv32_intmem_free(void* addr); +void* crisv32_intmem_phys_to_virt(unsigned long addr); +unsigned long crisv32_intmem_virt_to_phys(void *addr); + +#endif /* _ASM_CRIS_ARCH_INTMEM_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/io.h b/kernel/arch/cris/include/arch-v32/arch/io.h new file mode 100644 index 000000000..adc548435 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/io.h @@ -0,0 +1,140 @@ +#ifndef _ASM_ARCH_CRIS_IO_H +#define _ASM_ARCH_CRIS_IO_H + +#include +#include +#include +#include + +enum crisv32_io_dir +{ + crisv32_io_dir_in = 0, + crisv32_io_dir_out = 1 +}; + +struct crisv32_ioport +{ + volatile unsigned long *oe; + volatile unsigned long *data; + volatile unsigned long *data_in; + unsigned int pin_count; + spinlock_t lock; +}; + +struct crisv32_iopin +{ + struct crisv32_ioport* port; + int bit; +}; + +extern struct crisv32_ioport crisv32_ioports[]; + +extern struct crisv32_iopin crisv32_led1_green; +extern struct crisv32_iopin crisv32_led1_red; +extern struct crisv32_iopin crisv32_led2_green; +extern struct crisv32_iopin crisv32_led2_red; +extern struct crisv32_iopin crisv32_led3_green; +extern struct crisv32_iopin crisv32_led3_red; + +extern struct crisv32_iopin crisv32_led_net0_green; +extern struct crisv32_iopin crisv32_led_net0_red; +extern struct crisv32_iopin crisv32_led_net1_green; +extern struct crisv32_iopin crisv32_led_net1_red; + +static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val) +{ + unsigned long flags; + spin_lock_irqsave(&iopin->port->lock, flags); + + if (iopin->port->data) { + if (val) + *iopin->port->data |= iopin->bit; + else + *iopin->port->data &= ~iopin->bit; + } + + spin_unlock_irqrestore(&iopin->port->lock, flags); +} + +static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin, + enum crisv32_io_dir dir) +{ + unsigned long flags; + spin_lock_irqsave(&iopin->port->lock, flags); + + if (iopin->port->oe) { + if (dir == crisv32_io_dir_in) + *iopin->port->oe &= ~iopin->bit; + else + *iopin->port->oe |= iopin->bit; + } + + spin_unlock_irqrestore(&iopin->port->lock, flags); +} + +static inline int crisv32_io_rd(struct crisv32_iopin* iopin) +{ + return ((*iopin->port->data_in & iopin->bit) ? 1 : 0); +} + +int crisv32_io_get(struct crisv32_iopin* iopin, + unsigned int port, unsigned int pin); +int crisv32_io_get_name(struct crisv32_iopin* iopin, + const char *name); + +#define CRIS_LED_OFF 0x00 +#define CRIS_LED_GREEN 0x01 +#define CRIS_LED_RED 0x02 +#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) + +#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)) +#define CRIS_LED_NETWORK_GRP0_SET(x) \ + do { \ + CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#else +#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {} +#endif + +#define CRIS_LED_NETWORK_GRP0_SET_G(x) \ + crisv32_io_set(&crisv32_led_net0_green, !(x)); + +#define CRIS_LED_NETWORK_GRP0_SET_R(x) \ + crisv32_io_set(&crisv32_led_net0_red, !(x)); + +#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO) +#define CRIS_LED_NETWORK_GRP1_SET(x) \ + do { \ + CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \ + } while (0) +#else +#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {} +#endif + +#define CRIS_LED_NETWORK_GRP1_SET_G(x) \ + crisv32_io_set(&crisv32_led_net1_green, !(x)); + +#define CRIS_LED_NETWORK_GRP1_SET_R(x) \ + crisv32_io_set(&crisv32_led_net1_red, !(x)); + +#define CRIS_LED_ACTIVE_SET(x) \ + do { \ + CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ + CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ + } while (0) + +#define CRIS_LED_ACTIVE_SET_G(x) \ + crisv32_io_set(&crisv32_led2_green, !(x)); +#define CRIS_LED_ACTIVE_SET_R(x) \ + crisv32_io_set(&crisv32_led2_red, !(x)); +#define CRIS_LED_DISK_WRITE(x) \ + do{\ + crisv32_io_set(&crisv32_led3_green, !(x)); \ + crisv32_io_set(&crisv32_led3_red, !(x)); \ + }while(0) +#define CRIS_LED_DISK_READ(x) \ + crisv32_io_set(&crisv32_led3_green, !(x)); + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/irq.h b/kernel/arch/cris/include/arch-v32/arch/irq.h new file mode 100644 index 000000000..0c1b4d3a3 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/irq.h @@ -0,0 +1,124 @@ +#ifndef _ASM_ARCH_IRQ_H +#define _ASM_ARCH_IRQ_H + +#include + +/* Number of non-cpu interrupts. */ +#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */ +#define FIRST_IRQ 0x31 /* Exception number for first IRQ */ +#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */ +#if NR_REAL_IRQS > 32 +#define MACH_IRQS 64 +#else +#define MACH_IRQS 32 +#endif + +#ifndef __ASSEMBLY__ +/* Global IRQ vector. */ +typedef void (*irqvectptr)(void); + +struct etrax_interrupt_vector { + irqvectptr v[256]; +}; + +extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ + +void crisv32_mask_irq(int irq); +void crisv32_unmask_irq(int irq); + +void set_exception_vector(int n, irqvectptr addr); + +/* Save registers so that they match pt_regs. */ +#define SAVE_ALL \ + "subq 12,$sp\n\t" \ + "move $erp,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $srp,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $ccs,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $spc,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $mof,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move $srs,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move.d $acr,[$sp]\n\t" \ + "subq 14*4,$sp\n\t" \ + "movem $r13,[$sp]\n\t" \ + "subq 4,$sp\n\t" \ + "move.d $r10,[$sp]\n" + +#define STR2(x) #x +#define STR(x) STR2(x) + +#define IRQ_NAME2(nr) nr##_interrupt(void) +#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) + +/* + * The reason for setting the S-bit when debugging the kernel is that we want + * hardware breakpoints to remain active while we are in an exception handler. + * Note that we cannot simply copy S1, since we may come here from user-space, + * or any context where the S-bit wasn't set. + */ +#ifdef CONFIG_ETRAX_KGDB +#define KGDB_FIXUP \ + "move $ccs, $r10\n\t" \ + "or.d (1<<9), $r10\n\t" \ + "move $r10, $ccs\n\t" +#else +#define KGDB_FIXUP "" +#endif + +/* + * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock + * and jump to ret_from_intr which is found in entry.S. + * + * The reason for blocking the IRQ is to allow an sti() before the handler, + * which will acknowledge the interrupt, is run. The actual blocking is made + * by crisv32_do_IRQ. + */ +#define BUILD_IRQ(nr) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + KGDB_FIXUP \ + "move.d "#nr",$r10\n\t" \ + "move.d $sp, $r12\n\t" \ + "jsr crisv32_do_IRQ\n\t" \ + "moveq 1, $r11\n\t" \ + "jump ret_from_intr\n\t" \ + "nop\n\t"); +/* + * This is subtle. The timer interrupt is crucial and it should not be disabled + * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it + * would have been BLOCK'ed, and then softirq's are run before we return here to + * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run + * and the watchdog will kill us. + * + * Furthermore, if a lot of other irq's occur before we return here, the + * multiple_irq handler is run and it prioritizes the timer interrupt. However + * if we had BLOCK'edit here, we would not get the multiple_irq at all. + * + * The non-blocking here is based on the knowledge that the timer interrupt runs + * with interrupts disabled, and therefore there will not be an sti() before the + * timer irq handler is run to acknowledge the interrupt. + */ +#define BUILD_TIMER_IRQ(nr, mask) \ +void IRQ_NAME(nr); \ +__asm__ ( \ + ".text\n\t" \ + "IRQ" #nr "_interrupt:\n\t" \ + SAVE_ALL \ + KGDB_FIXUP \ + "move.d "#nr",$r10\n\t" \ + "move.d $sp,$r12\n\t" \ + "jsr crisv32_do_IRQ\n\t" \ + "moveq 0,$r11\n\t" \ + "jump ret_from_intr\n\t" \ + "nop\n\t"); + +#endif /* __ASSEMBLY__ */ +#endif /* _ASM_ARCH_IRQ_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/irqflags.h b/kernel/arch/cris/include/arch-v32/arch/irqflags.h new file mode 100644 index 000000000..041851f8e --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/irqflags.h @@ -0,0 +1,46 @@ +#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H +#define __ASM_CRIS_ARCH_IRQFLAGS_H + +#include +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("move $ccs,%0" : "=rm" (flags) : : "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + asm volatile("di" : : : "memory"); +} + +static inline void arch_local_irq_enable(void) +{ + asm volatile("ei" : : : "memory"); +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = arch_local_save_flags(); + arch_local_irq_disable(); + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile("move %0,$ccs" : : "rm" (flags) : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return !(flags & (1 << I_CCS_BITNR)); +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/memmap.h b/kernel/arch/cris/include/arch-v32/arch/memmap.h new file mode 100644 index 000000000..81985c0a6 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/memmap.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/arch-v32/arch/mmu.h b/kernel/arch/cris/include/arch-v32/arch/mmu.h new file mode 100644 index 000000000..e6db1616d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/mmu.h @@ -0,0 +1,110 @@ +#ifndef _ASM_CRIS_ARCH_MMU_H +#define _ASM_CRIS_ARCH_MMU_H + +/* MMU context type. */ +typedef struct +{ + unsigned int page_id; +} mm_context_t; + +/* Kernel memory segments. */ +#define KSEG_F 0xf0000000UL +#define KSEG_E 0xe0000000UL +#define KSEG_D 0xd0000000UL +#define KSEG_C 0xc0000000UL +#define KSEG_B 0xb0000000UL +#define KSEG_A 0xa0000000UL +#define KSEG_9 0x90000000UL +#define KSEG_8 0x80000000UL +#define KSEG_7 0x70000000UL +#define KSEG_6 0x60000000UL +#define KSEG_5 0x50000000UL +#define KSEG_4 0x40000000UL +#define KSEG_3 0x30000000UL +#define KSEG_2 0x20000000UL +#define KSEG_1 0x10000000UL +#define KSEG_0 0x00000000UL + +/* + * CRISv32 PTE bits: + * + * Bit: 31 30-13 12-5 4 3 2 1 0 + * +-------+-----+------+--------+-------+--------+-------+---------+ + * | cache | pfn | zero | global | valid | kernel | write | execute | + * +-------+-----+------+--------+-------+--------+-------+---------+ + */ + +/* + * Defines for accessing the bits. Also define some synonyms for use with + * the software-based defined bits below. + */ +#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */ +#define _PAGE_WE (1 << 1) /* Write bit. */ +#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */ +#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */ +#define _PAGE_VALID (1 << 3) /* Page is valid. */ +#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ +#define _PAGE_GLOBAL (1 << 4) /* Global page. */ +#define _PAGE_NO_CACHE (1 << 31) /* part of the uncached memory map */ + + +/* + * The hardware doesn't care about these bits, but the kernel uses them in + * software. + */ +#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */ +#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */ +#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */ +#define _PAGE_READ (1 << 8) /* Read enabled. */ +#define _PAGE_WRITE (1 << 9) /* Write enabled. */ + +/* Define some higher level generic page attributes. */ +#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) + +#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) + +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ + _PAGE_ACCESSED) +#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ + _PAGE_ACCESSED | _PAGE_EXECUTE) + +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) +#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED) + +#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) +#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE) +#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ + _PAGE_PRESENT | __READABLE | __WRITEABLE) +#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \ + _PAGE_PRESENT | __READABLE | __WRITEABLE) +#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \ + _PAGE_PRESENT | __READABLE) + +#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) + +/* CRISv32 can do page protection for execute. + * Write permissions imply read permissions. + * Note that the numbers are in Execute-Write-Read order! + */ +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY_EXEC +#define __P101 PAGE_READONLY_EXEC +#define __P110 PAGE_COPY_EXEC +#define __P111 PAGE_COPY_EXEC + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY_EXEC +#define __S101 PAGE_READONLY_EXEC +#define __S110 PAGE_SHARED_EXEC +#define __S111 PAGE_SHARED_EXEC + +#endif /* _ASM_CRIS_ARCH_MMU_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/offset.h b/kernel/arch/cris/include/arch-v32/arch/offset.h new file mode 100644 index 000000000..4442c4bd5 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/offset.h @@ -0,0 +1,35 @@ +#ifndef __ASM_OFFSETS_H__ +#define __ASM_OFFSETS_H__ +/* + * DO NOT MODIFY. + * + * This file was generated by arch/cris/Makefile + * + */ + +#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */ +#define PT_r13 56 /* offsetof(struct pt_regs, r13) */ +#define PT_r12 52 /* offsetof(struct pt_regs, r12) */ +#define PT_r11 48 /* offsetof(struct pt_regs, r11) */ +#define PT_r10 44 /* offsetof(struct pt_regs, r10) */ +#define PT_r9 40 /* offsetof(struct pt_regs, r9) */ +#define PT_acr 60 /* offsetof(struct pt_regs, acr) */ +#define PT_srs 64 /* offsetof(struct pt_regs, srs) */ +#define PT_mof 68 /* offsetof(struct pt_regs, mof) */ +#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */ +#define PT_srp 80 /* offsetof(struct pt_regs, srp) */ + +#define TI_task 0 /* offsetof(struct thread_info, task) */ +#define TI_flags 8 /* offsetof(struct thread_info, flags) */ +#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ + +#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ +#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ +#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ + +#define TASK_pid 151 /* offsetof(struct task_struct, pid) */ + +#define LCLONE_VM 256 /* CLONE_VM */ +#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/page.h b/kernel/arch/cris/include/arch-v32/arch/page.h new file mode 100644 index 000000000..e5b5aab52 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/page.h @@ -0,0 +1,22 @@ +#ifndef _ASM_CRIS_ARCH_PAGE_H +#define _ASM_CRIS_ARCH_PAGE_H + + +#ifdef __KERNEL__ + +#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ + +/* + * Macros to convert between physical and virtual addresses. By stripping a + * selected bit it's possible to convert between KSEG_x and 0x40000000 where the + * DRAM really resides. DRAM is virtually at 0xc. + */ +#define __pa(x) ((unsigned long)(x) & 0x7fffffff) +#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) + +#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ + VM_MAYREAD | VM_MAYWRITE) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_CRIS_ARCH_PAGE_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/pgtable.h b/kernel/arch/cris/include/arch-v32/arch/pgtable.h new file mode 100644 index 000000000..c1051a8da --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/pgtable.h @@ -0,0 +1,17 @@ +#ifndef _ASM_CRIS_ARCH_PGTABLE_H +#define _ASM_CRIS_ARCH_PGTABLE_H + +/* Define the kernels virtual memory area. */ + +/* See head.S for differences between ARTPEC-3 and ETRAX FS. */ +#ifdef CONFIG_CRIS_MACH_ARTPEC3 +#define VMALLOC_START KSEG_E +#define VMALLOC_END KSEG_F +#else +#define VMALLOC_START KSEG_D +#define VMALLOC_END KSEG_E +#endif + +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) + +#endif /* _ASM_CRIS_ARCH_PGTABLE_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/processor.h b/kernel/arch/cris/include/arch-v32/arch/processor.h new file mode 100644 index 000000000..568759271 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/processor.h @@ -0,0 +1,53 @@ +#ifndef _ASM_CRIS_ARCH_PROCESSOR_H +#define _ASM_CRIS_ARCH_PROCESSOR_H + + +/* Return current instruction pointer. */ +#define current_text_addr() \ + ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;}) + +/* + * Since CRIS doesn't do hardware task-switching this hasn't really anything to + * do with the proccessor itself, it's just here for legacy reasons. This is + * used when task-switching using _resume defined in entry.S. The offsets here + * are hardcoded into _resume, so if this struct is changed, entry.S needs to be + * changed as well. + */ +struct thread_struct { + unsigned long ksp; /* Kernel stack pointer. */ + unsigned long usp; /* User stack pointer. */ + unsigned long ccs; /* Saved flags register. */ +}; + +/* + * User-space process size. This is hardcoded into a few places, so don't + * change it unless everything's clear! + */ +#define TASK_SIZE (0xB0000000UL) + +#define INIT_THREAD { } + +#define KSTK_EIP(tsk) \ +({ \ + unsigned long eip = 0; \ + unsigned long regs = (unsigned long)task_pt_regs(tsk); \ + if (regs > PAGE_SIZE && virt_addr_valid(regs)) \ + eip = ((struct pt_regs *)regs)->erp; \ + eip; \ +}) + +/* + * Give the thread a program location, set user-mode and switch user + * stackpointer. + */ +#define start_thread(regs, ip, usp) \ +do { \ + regs->erp = ip; \ + regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \ + wrusp(usp); \ +} while(0) + +/* Nothing special to do for v32 when handling a kernel bus fault fixup. */ +#define arch_fixup(regs) {}; + +#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/ptrace.h b/kernel/arch/cris/include/arch-v32/arch/ptrace.h new file mode 100644 index 000000000..19773d3bd --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/ptrace.h @@ -0,0 +1,118 @@ +#ifndef _CRIS_ARCH_PTRACE_H +#define _CRIS_ARCH_PTRACE_H + +/* Register numbers in the ptrace system call interface */ + +#define PT_ORIG_R10 0 +#define PT_R0 1 +#define PT_R1 2 +#define PT_R2 3 +#define PT_R3 4 +#define PT_R4 5 +#define PT_R5 6 +#define PT_R6 7 +#define PT_R7 8 +#define PT_R8 9 +#define PT_R9 10 +#define PT_R10 11 +#define PT_R11 12 +#define PT_R12 13 +#define PT_R13 14 +#define PT_ACR 15 +#define PT_SRS 16 +#define PT_MOF 17 +#define PT_SPC 18 +#define PT_CCS 19 +#define PT_SRP 20 +#define PT_ERP 21 /* This is actually the debugged process' PC */ +#define PT_EXS 22 +#define PT_EDA 23 +#define PT_USP 24 /* special case - USP is not in the pt_regs */ +#define PT_PPC 25 /* special case - pseudo PC */ +#define PT_BP 26 /* Base number for BP registers. */ +#define PT_BP_CTRL 26 /* BP control register. */ +#define PT_MAX 40 + +/* Condition code bit numbers. */ +#define C_CCS_BITNR 0 +#define V_CCS_BITNR 1 +#define Z_CCS_BITNR 2 +#define N_CCS_BITNR 3 +#define X_CCS_BITNR 4 +#define I_CCS_BITNR 5 +#define U_CCS_BITNR 6 +#define P_CCS_BITNR 7 +#define R_CCS_BITNR 8 +#define S_CCS_BITNR 9 +#define M_CCS_BITNR 30 +#define Q_CCS_BITNR 31 +#define CCS_SHIFT 10 /* Shift count for each level in CCS */ + +/* pt_regs not only specifices the format in the user-struct during + * ptrace but is also the frame format used in the kernel prologue/epilogues + * themselves + */ + +struct pt_regs { + unsigned long orig_r10; + /* pushed by movem r13, [sp] in SAVE_ALL. */ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long acr; + unsigned long srs; + unsigned long mof; + unsigned long spc; + unsigned long ccs; + unsigned long srp; + unsigned long erp; /* This is actually the debugged process' PC */ + /* For debugging purposes; saved only when needed. */ + unsigned long exs; + unsigned long eda; +}; + +/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) + * when doing a context-switch. it is used (apart from in resume) when a new + * thread is made and we need to make _resume (which is starting it for the + * first time) realise what is going on. + * + * Actually, the use is very close to the thread struct (TSS) in that both the + * switch_stack and the TSS are used to keep thread stuff when switching in + * _resume. + */ + +struct switch_stack { + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long return_ip; /* ip that _resume will return to */ +}; + +#ifdef __KERNEL__ + +#define arch_has_single_step() (1) +#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) +#define instruction_pointer(regs) ((regs)->erp) +#define profile_pc(regs) instruction_pointer(regs) + +#endif /* __KERNEL__ */ + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/swab.h b/kernel/arch/cris/include/arch-v32/arch/swab.h new file mode 100644 index 000000000..9a4ea5e20 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/swab.h @@ -0,0 +1,24 @@ +#ifndef _ASM_CRIS_ARCH_SWAB_H +#define _ASM_CRIS_ARCH_SWAB_H + +#include + +#define __SWAB_64_THRU_32__ + +static inline __const__ __u32 +__arch_swab32(__u32 x) +{ + __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x)); + return (x); +} +#define __arch_swab32 __arch_swab32 + +static inline __const__ __u16 +__arch_swab16(__u16 x) +{ + __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x)); + return (x); +} +#define __arch_swab16 __arch_swab16 + +#endif /* _ASM_CRIS_ARCH_SWAB_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/system.h b/kernel/arch/cris/include/arch-v32/arch/system.h new file mode 100644 index 000000000..db853fb3a --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/system.h @@ -0,0 +1,37 @@ +#ifndef _ASM_CRIS_ARCH_SYSTEM_H +#define _ASM_CRIS_ARCH_SYSTEM_H + + +/* Read the CPU version register. */ +static inline unsigned long rdvr(void) +{ + unsigned char vr; + + __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr)); + return vr; +} + +#define cris_machine_name "crisv32" + +/* Read the user-mode stack pointer. */ +static inline unsigned long rdusp(void) +{ + unsigned long usp; + + __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp)); + return usp; +} + +/* Read the current stack pointer. */ +static inline unsigned long rdsp(void) +{ + unsigned long sp; + + __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp)); + return sp; +} + +/* Write the user-mode stack pointer. */ +#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp)) + +#endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/thread_info.h b/kernel/arch/cris/include/arch-v32/arch/thread_info.h new file mode 100644 index 000000000..d6936956a --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/thread_info.h @@ -0,0 +1,13 @@ +#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H +#define _ASM_CRIS_ARCH_THREAD_INFO_H + +/* Return a thread_info struct. */ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + + __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL)); + return ti; +} + +#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/timex.h b/kernel/arch/cris/include/arch-v32/arch/timex.h new file mode 100644 index 000000000..2591d3c5e --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/timex.h @@ -0,0 +1,31 @@ +#ifndef _ASM_CRIS_ARCH_TIMEX_H +#define _ASM_CRIS_ARCH_TIMEX_H + +#include +#include +#include + +/* + * The clock runs at 100MHz, we divide it by 1000000. If you change anything + * here you must check time.c as well. + */ + +#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */ + +/* The timer0 values gives 10 ns resolution but interrupts at HZ. */ +#define TIMER0_FREQ (CLOCK_TICK_RATE) +#define TIMER0_DIV (TIMER0_FREQ/(HZ)) + +/* Convert the value in step of 10 ns to 1us without overflow: */ +#define GET_JIFFIES_USEC() \ + ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100) + +extern unsigned long get_ns_in_jiffie(void); + +static inline unsigned long get_us_in_jiffie_highres(void) +{ + return get_ns_in_jiffie() / 1000; +} + +#endif + diff --git a/kernel/arch/cris/include/arch-v32/arch/tlb.h b/kernel/arch/cris/include/arch-v32/arch/tlb.h new file mode 100644 index 000000000..4effb1253 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/tlb.h @@ -0,0 +1,14 @@ +#ifndef _CRIS_ARCH_TLB_H +#define _CRIS_ARCH_TLB_H + +/* + * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used + * to store the "process" it belongs to (=> fast mm context switch). The + * last page_id is never used so we can make TLB entries that never matches. + */ +#define NUM_TLB_ENTRIES 64 +#define NUM_PAGEID 256 +#define INVALID_PAGEID 255 +#define NO_CONTEXT -1 + +#endif /* _CRIS_ARCH_TLB_H */ diff --git a/kernel/arch/cris/include/arch-v32/arch/uaccess.h b/kernel/arch/cris/include/arch-v32/arch/uaccess.h new file mode 100644 index 000000000..319601970 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/uaccess.h @@ -0,0 +1,747 @@ +/* + * Authors: Hans-Peter Nilsson (hp@axis.com) + * + */ +#ifndef _CRIS_ARCH_UACCESS_H +#define _CRIS_ARCH_UACCESS_H + +/* + * We don't tell gcc that we are accessing memory, but this is OK + * because we do not write to any memory gcc knows about, so there + * are no aliasing issues. + * + * Note that PC at a fault is the address *at* the faulting + * instruction for CRISv32. + */ +#define __put_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + "2: "op" %1,[%2]\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 4b\n" \ + " nop\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err) \ + : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __put_user_asm_64(x, addr, err) do { \ + int dummy_for_put_user_asm_64_; \ + __asm__ __volatile__( \ + "2: move.d %M2,[%1+]\n" \ + "4: move.d %H2,[%1]\n" \ + "5:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %4,%0\n" \ + " jump 5b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \ + : "r" (x), "1" (addr), "g" (-EFAULT), \ + "0" (err)); \ + } while (0) + +/* See comment before __put_user_asm. */ + +#define __get_user_asm(x, addr, err, op) \ + __asm__ __volatile__( \ + "2: "op" [%2],%1\n" \ + "4:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %3,%0\n" \ + " jump 4b\n" \ + " moveq 0,%1\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x) \ + : "r" (addr), "g" (-EFAULT), "0" (err)) + +#define __get_user_asm_64(x, addr, err) do { \ + int dummy_for_get_user_asm_64_; \ + __asm__ __volatile__( \ + "2: move.d [%2+],%M1\n" \ + "4: move.d [%2],%H1\n" \ + "5:\n" \ + " .section .fixup,\"ax\"\n" \ + "3: move.d %4,%0\n" \ + " jump 5b\n" \ + " moveq 0,%1\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .dword 2b,3b\n" \ + " .dword 4b,3b\n" \ + " .previous\n" \ + : "=r" (err), "=r" (x), \ + "=b" (dummy_for_get_user_asm_64_) \ + : "2" (addr), "g" (-EFAULT), "0" (err));\ + } while (0) + +/* + * Copy a null terminated string from userspace. + * + * Must return: + * -EFAULT for an exception + * count if we hit the buffer limit + * bytes copied if we hit a null byte + * (without the null byte) + */ +static inline long +__do_strncpy_from_user(char *dst, const char *src, long count) +{ + long res; + + if (count == 0) + return 0; + + /* + * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. + * So do we. + * + * This code is deduced from: + * + * char tmp2; + * long tmp1, tmp3; + * tmp1 = count; + * while ((*dst++ = (tmp2 = *src++)) != 0 + * && --tmp1) + * ; + * + * res = count - tmp1; + * + * with tweaks. + */ + + __asm__ __volatile__ ( + " move.d %3,%0\n" + "5: move.b [%2+],$acr\n" + "1: beq 6f\n" + " move.b $acr,[%1+]\n" + + " subq 1,%0\n" + "2: bne 1b\n" + " move.b [%2+],$acr\n" + + "6: sub.d %3,%0\n" + " neg.d %0,%0\n" + "3:\n" + " .section .fixup,\"ax\"\n" + "4: move.d %7,%0\n" + " jump 3b\n" + " nop\n" + + /* The address for a fault at the first move is trivial. + The address for a fault at the second move is that of + the preceding branch insn, since the move insn is in + its delay-slot. Just so you don't get confused... */ + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 5b,4b\n" + " .dword 2b,4b\n" + " .previous" + : "=r" (res), "=b" (dst), "=b" (src), "=r" (count) + : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) + : "acr"); + + return res; +} + +/* A few copy asms to build up the more complex ones from. + + Note again, a post-increment is performed regardless of whether a bus + fault occurred in that instruction, and PC for a faulted insn is the + address for the insn, or for the preceding branch when in a delay-slot. */ + +#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + COPY \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous\n" \ + : "=b" (to), "=b" (from), "=r" (ret) \ + : "0" (to), "1" (from), "2" (ret) \ + : "acr", "memory") + +#define __asm_copy_from_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + "2: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "3: addq 1,%2\n" \ + " jump 1b\n" \ + " clear.b [%0+]\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + "2: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "3: addq 2,%2\n" \ + " jump 1b\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_2(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_3(to, from, ret) \ + __asm_copy_from_user_2x_cont(to, from, ret, \ + "4: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + "2: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "3: addq 4,%2\n" \ + " jump 1b\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_from_user_4(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_5(to, from, ret) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + "4: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + COPY \ + "4: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "5: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_6(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_7(to, from, ret) \ + __asm_copy_from_user_6x_cont(to, from, ret, \ + "6: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_4x_cont(to, from, ret, \ + COPY \ + "4: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "5: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_from_user_8(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_9(to, from, ret) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + "6: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + COPY \ + "6: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "7: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_10(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_11(to, from, ret) \ + __asm_copy_from_user_10x_cont(to, from, ret, \ + "8: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_8x_cont(to, from, ret, \ + COPY \ + "6: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "7: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_from_user_12(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_13(to, from, ret) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + "8: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + COPY \ + "8: move.w [%1+],$acr\n" \ + " move.w $acr,[%0+]\n", \ + FIXUP \ + "9: addq 2,%2\n" \ + " clear.w [%0+]\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_14(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_15(to, from, ret) \ + __asm_copy_from_user_14x_cont(to, from, ret, \ + "10: move.b [%1+],$acr\n" \ + " move.b $acr,[%0+]\n", \ + "11: addq 1,%2\n" \ + " clear.b [%0+]\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_12x_cont(to, from, ret, \ + COPY \ + "8: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "9: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_from_user_16(to, from, ret) \ + __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_16x_cont(to, from, ret, \ + COPY \ + "10: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "11: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_copy_from_user_20(to, from, ret) \ + __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_from_user_20x_cont(to, from, ret, \ + COPY \ + "12: move.d [%1+],$acr\n" \ + " move.d $acr,[%0+]\n", \ + FIXUP \ + "13: addq 4,%2\n" \ + " clear.d [%0+]\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_copy_from_user_24(to, from, ret) \ + __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") + +/* And now, the to-user ones. */ + +#define __asm_copy_to_user_1(to, from, ret) \ + __asm_copy_user_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "2: move.b $acr,[%0+]\n", \ + "3: jump 1b\n" \ + " addq 1,%2\n", \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "2: move.w $acr,[%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 2,%2\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_2(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_3(to, from, ret) \ + __asm_copy_to_user_2x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "4: move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_user_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "2: move.d $acr,[%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 4,%2\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_copy_to_user_4(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_5(to, from, ret) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "4: move.b $acr,[%0+]\n", \ + "5: addq 1,%2\n", \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "4: move.w $acr,[%0+]\n", \ + FIXUP \ + "5: addq 2,%2\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_6(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_7(to, from, ret) \ + __asm_copy_to_user_6x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "6: move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_4x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "4: move.d $acr,[%0+]\n", \ + FIXUP \ + "5: addq 4,%2\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_copy_to_user_8(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_9(to, from, ret) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "6: move.b $acr,[%0+]\n", \ + "7: addq 1,%2\n", \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "6: move.w $acr,[%0+]\n", \ + FIXUP \ + "7: addq 2,%2\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_10(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_11(to, from, ret) \ + __asm_copy_to_user_10x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "8: move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_8x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "6: move.d $acr,[%0+]\n", \ + FIXUP \ + "7: addq 4,%2\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_copy_to_user_12(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_13(to, from, ret) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "8: move.b $acr,[%0+]\n", \ + "9: addq 1,%2\n", \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + COPY \ + " move.w [%1+],$acr\n" \ + "8: move.w $acr,[%0+]\n", \ + FIXUP \ + "9: addq 2,%2\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_14(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_15(to, from, ret) \ + __asm_copy_to_user_14x_cont(to, from, ret, \ + " move.b [%1+],$acr\n" \ + "10: move.b $acr,[%0+]\n", \ + "11: addq 1,%2\n", \ + " .dword 10b,11b\n") + +#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_12x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "8: move.d $acr,[%0+]\n", \ + FIXUP \ + "9: addq 4,%2\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_copy_to_user_16(to, from, ret) \ + __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_16x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "10: move.d $acr,[%0+]\n", \ + FIXUP \ + "11: addq 4,%2\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_copy_to_user_20(to, from, ret) \ + __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") + +#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ + __asm_copy_to_user_20x_cont(to, from, ret, \ + COPY \ + " move.d [%1+],$acr\n" \ + "12: move.d $acr,[%0+]\n", \ + FIXUP \ + "13: addq 4,%2\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_copy_to_user_24(to, from, ret) \ + __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") + +/* Define a few clearing asms with exception handlers. */ + +/* This frame-asm is like the __asm_copy_user_cont one, but has one less + input. */ + +#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm__ __volatile__ ( \ + CLEAR \ + "1:\n" \ + " .section .fixup,\"ax\"\n" \ + FIXUP \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + TENTRY \ + " .previous" \ + : "=b" (to), "=r" (ret) \ + : "0" (to), "1" (ret) \ + : "memory") + +#define __asm_clear_1(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.b [%0+]\n", \ + "3: jump 1b\n" \ + " addq 1,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_2(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.w [%0+]\n", \ + "3: jump 1b\n" \ + " addq 2,%1\n", \ + " .dword 2b,3b\n") + +#define __asm_clear_3(to, ret) \ + __asm_clear(to, ret, \ + "2: clear.w [%0+]\n" \ + "3: clear.b [%0+]\n", \ + "4: addq 2,%1\n" \ + "5: jump 1b\n" \ + " addq 1,%1\n", \ + " .dword 2b,4b\n" \ + " .dword 3b,5b\n") + +#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear(to, ret, \ + CLEAR \ + "2: clear.d [%0+]\n", \ + FIXUP \ + "3: jump 1b\n" \ + " addq 4,%1\n", \ + TENTRY \ + " .dword 2b,3b\n") + +#define __asm_clear_4(to, ret) \ + __asm_clear_4x_cont(to, ret, "", "", "") + +#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_4x_cont(to, ret, \ + CLEAR \ + "4: clear.d [%0+]\n", \ + FIXUP \ + "5: addq 4,%1\n", \ + TENTRY \ + " .dword 4b,5b\n") + +#define __asm_clear_8(to, ret) \ + __asm_clear_8x_cont(to, ret, "", "", "") + +#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_8x_cont(to, ret, \ + CLEAR \ + "6: clear.d [%0+]\n", \ + FIXUP \ + "7: addq 4,%1\n", \ + TENTRY \ + " .dword 6b,7b\n") + +#define __asm_clear_12(to, ret) \ + __asm_clear_12x_cont(to, ret, "", "", "") + +#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_12x_cont(to, ret, \ + CLEAR \ + "8: clear.d [%0+]\n", \ + FIXUP \ + "9: addq 4,%1\n", \ + TENTRY \ + " .dword 8b,9b\n") + +#define __asm_clear_16(to, ret) \ + __asm_clear_16x_cont(to, ret, "", "", "") + +#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_16x_cont(to, ret, \ + CLEAR \ + "10: clear.d [%0+]\n", \ + FIXUP \ + "11: addq 4,%1\n", \ + TENTRY \ + " .dword 10b,11b\n") + +#define __asm_clear_20(to, ret) \ + __asm_clear_20x_cont(to, ret, "", "", "") + +#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ + __asm_clear_20x_cont(to, ret, \ + CLEAR \ + "12: clear.d [%0+]\n", \ + FIXUP \ + "13: addq 4,%1\n", \ + TENTRY \ + " .dword 12b,13b\n") + +#define __asm_clear_24(to, ret) \ + __asm_clear_24x_cont(to, ret, "", "", "") + +/* + * Return the size of a string (including the ending 0) + * + * Return length of string in userspace including terminating 0 + * or 0 for error. Return a value greater than N if too long. + */ + +static inline long +strnlen_user(const char *s, long n) +{ + long res, tmp1; + + if (!access_ok(VERIFY_READ, s, 0)) + return 0; + + /* + * This code is deduced from: + * + * tmp1 = n; + * while (tmp1-- > 0 && *s++) + * ; + * + * res = n - tmp1; + * + * (with tweaks). + */ + + __asm__ __volatile__ ( + " move.d %1,$acr\n" + " cmpq 0,$acr\n" + "0:\n" + " ble 1f\n" + " subq 1,$acr\n" + + "4: test.b [%0+]\n" + " bne 0b\n" + " cmpq 0,$acr\n" + "1:\n" + " move.d %1,%0\n" + " sub.d $acr,%0\n" + "2:\n" + " .section .fixup,\"ax\"\n" + + "3: jump 2b\n" + " clear.d %0\n" + + " .previous\n" + " .section __ex_table,\"a\"\n" + " .dword 4b,3b\n" + " .previous\n" + : "=r" (res), "=r" (tmp1) + : "0" (s), "1" (n) + : "acr"); + + return res; +} + +#endif diff --git a/kernel/arch/cris/include/arch-v32/arch/unistd.h b/kernel/arch/cris/include/arch-v32/arch/unistd.h new file mode 100644 index 000000000..0051114c6 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/arch/unistd.h @@ -0,0 +1,155 @@ +#ifndef _ASM_CRIS_ARCH_UNISTD_H_ +#define _ASM_CRIS_ARCH_UNISTD_H_ + +/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ +/* + * Don't remove the .ifnc tests; they are an insurance against + * any hard-to-spot gcc register allocation bugs. + */ +#define _syscall0(type,name) \ +type name(void) \ +{ \ + register long __a __asm__ ("r10"); \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall1(type,name,type1,arg1) \ +type name(type1 arg1) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall2(type,name,type1,arg1,type2,arg2) \ +type name(type1 arg1,type2 arg2) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ +type name(type1 arg1,type2 arg2,type3 arg3) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ +type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d)\ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __e __asm__ ("mof") = (long) arg5; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "h" (__e) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ + type5,arg5,type6,arg6) \ +type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ +{ \ + register long __a __asm__ ("r10") = (long) arg1; \ + register long __b __asm__ ("r11") = (long) arg2; \ + register long __c __asm__ ("r12") = (long) arg3; \ + register long __d __asm__ ("r13") = (long) arg4; \ + register long __e __asm__ ("mof") = (long) arg5; \ + register long __f __asm__ ("srp") = (long) arg6; \ + register long __n_ __asm__ ("r9") = (__NR_##name); \ + __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \ + ".err\n\t" \ + ".endif\n\t" \ + "break 13" \ + : "=r" (__a) \ + : "r" (__n_), "0" (__a), "r" (__b), \ + "r" (__c), "r" (__d), "h" (__e), "x" (__f) \ + : "memory"); \ + if (__a >= 0) \ + return (type) __a; \ + errno = -__a; \ + return (type) -1; \ +} + +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h new file mode 100644 index 000000000..65e9d6ff0 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h @@ -0,0 +1,34 @@ +#ifndef _ASM_CRIS_ARCH_ARBITER_H +#define _ASM_CRIS_ARCH_ARBITER_H + +#define EXT_REGION 0 +#define INT_REGION 1 + +typedef void (watch_callback)(void); + +enum { + arbiter_all_dmas = 0x7fe, + arbiter_cpu = 0x1800, + arbiter_all_clients = 0x7fff +}; + +enum { + arbiter_bar_all_clients = 0x1ff +}; + +enum { + arbiter_all_read = 0x55, + arbiter_all_write = 0xaa, + arbiter_all_accesses = 0xff +}; + +#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli)) + +int crisv32_arbiter_allocate_bandwidth(int client, int region, + unsigned long bandwidth); +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback * cb); +int crisv32_arbiter_unwatch(int id); + +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/dma.h new file mode 100644 index 000000000..f01dca1ad --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/dma.h @@ -0,0 +1,58 @@ +#ifndef _ASM_ARCH_CRIS_DMA_H +#define _ASM_ARCH_CRIS_DMA_H + +/* Defines for using and allocating dma channels. */ + +#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ + +#define NETWORK_ETH_TX_DMA_NBR 0 /* Ethernet 0 out. */ +#define NETWORK_ETH_RX_DMA_NBR 1 /* Ethernet 0 in. */ + +#define IO_PROC_DMA_TX_DMA_NBR 4 /* IO processor DMA0 out. */ +#define IO_PROC_DMA_RX_DMA_NBR 5 /* IO processor DMA0 in. */ + +#define ASYNC_SER3_TX_DMA_NBR 2 /* Asynchronous serial port 3 out. */ +#define ASYNC_SER3_RX_DMA_NBR 3 /* Asynchronous serial port 3 in. */ + +#define ASYNC_SER2_TX_DMA_NBR 6 /* Asynchronous serial port 2 out. */ +#define ASYNC_SER2_RX_DMA_NBR 7 /* Asynchronous serial port 2 in. */ + +#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ +#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ + +#define SYNC_SER_TX_DMA_NBR 6 /* Synchronous serial port 0 out. */ +#define SYNC_SER_RX_DMA_NBR 7 /* Synchronous serial port 0 in. */ + +#define ASYNC_SER0_TX_DMA_NBR 0 /* Asynchronous serial port 0 out. */ +#define ASYNC_SER0_RX_DMA_NBR 1 /* Asynchronous serial port 0 in. */ + +#define STRCOP_TX_DMA_NBR 2 /* Stream co-processor out. */ +#define STRCOP_RX_DMA_NBR 3 /* Stream co-processor in. */ + +#define dma_eth0 dma_eth +#define dma_eth1 dma_eth + +enum dma_owner { + dma_eth, + dma_ser0, + dma_ser1, + dma_ser2, + dma_ser3, + dma_ser4, + dma_iop, + dma_sser, + dma_strp, + dma_h264, + dma_jpeg +}; + +int crisv32_request_dma(unsigned int dmanr, const char *device_id, + unsigned options, unsigned bandwidth, enum dma_owner owner); +void crisv32_free_dma(unsigned int dmanr); + +/* Masks used by crisv32_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR 1 +#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) +#define DMA_INT_MEM 4 + +#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h new file mode 100644 index 000000000..02855adf6 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h @@ -0,0 +1,164 @@ +#ifndef __clkgen_defs_asm_h +#define __clkgen_defs_asm_h + +/* + * This file is autogenerated from + * file: clkgen.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope clkgen, type r */ +#define reg_clkgen_r_bootsel___boot_mode___lsb 0 +#define reg_clkgen_r_bootsel___boot_mode___width 5 +#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 +#define reg_clkgen_r_bootsel___intern_main_clk___width 1 +#define reg_clkgen_r_bootsel___intern_main_clk___bit 5 +#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 +#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 +#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 +#define reg_clkgen_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope clkgen, type rw */ +#define reg_clkgen_rw_clk_ctrl___pll___lsb 0 +#define reg_clkgen_rw_clk_ctrl___pll___width 1 +#define reg_clkgen_rw_clk_ctrl___pll___bit 0 +#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 +#define reg_clkgen_rw_clk_ctrl___cpu___width 1 +#define reg_clkgen_rw_clk_ctrl___cpu___bit 1 +#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 +#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 +#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 +#define reg_clkgen_rw_clk_ctrl___vin___lsb 3 +#define reg_clkgen_rw_clk_ctrl___vin___width 1 +#define reg_clkgen_rw_clk_ctrl___vin___bit 3 +#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 +#define reg_clkgen_rw_clk_ctrl___sclr___width 1 +#define reg_clkgen_rw_clk_ctrl___sclr___bit 4 +#define reg_clkgen_rw_clk_ctrl___h264___lsb 5 +#define reg_clkgen_rw_clk_ctrl___h264___width 1 +#define reg_clkgen_rw_clk_ctrl___h264___bit 5 +#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 +#define reg_clkgen_rw_clk_ctrl___ddr2___width 1 +#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 +#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 +#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 +#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 +#define reg_clkgen_rw_clk_ctrl___eth___lsb 8 +#define reg_clkgen_rw_clk_ctrl___eth___width 1 +#define reg_clkgen_rw_clk_ctrl___eth___bit 8 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 +#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 +#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 +#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 +#define reg_clkgen_rw_clk_ctrl___jpeg___width 1 +#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 +#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 +#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 +#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 +#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 +#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 +#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 +#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 +#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 +#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 +#define reg_clkgen_rw_clk_ctrl_offset 4 + + +/* Constants */ +#define regk_clkgen_eth1000_rx 0x0000000c +#define regk_clkgen_eth1000_tx 0x0000000e +#define regk_clkgen_eth100_rx 0x0000001d +#define regk_clkgen_eth100_rx_half 0x0000001c +#define regk_clkgen_eth100_tx 0x0000001f +#define regk_clkgen_eth100_tx_half 0x0000001e +#define regk_clkgen_nand_3_2 0x00000000 +#define regk_clkgen_nand_3_2_0x30 0x00000002 +#define regk_clkgen_nand_3_2_0x30_pll 0x00000012 +#define regk_clkgen_nand_3_2_pll 0x00000010 +#define regk_clkgen_nand_3_3 0x00000001 +#define regk_clkgen_nand_3_3_0x30 0x00000003 +#define regk_clkgen_nand_3_3_0x30_pll 0x00000013 +#define regk_clkgen_nand_3_3_pll 0x00000011 +#define regk_clkgen_nand_4_2 0x00000004 +#define regk_clkgen_nand_4_2_0x30 0x00000006 +#define regk_clkgen_nand_4_2_0x30_pll 0x00000016 +#define regk_clkgen_nand_4_2_pll 0x00000014 +#define regk_clkgen_nand_4_3 0x00000005 +#define regk_clkgen_nand_4_3_0x30 0x00000007 +#define regk_clkgen_nand_4_3_0x30_pll 0x00000017 +#define regk_clkgen_nand_4_3_pll 0x00000015 +#define regk_clkgen_nand_5_2 0x00000008 +#define regk_clkgen_nand_5_2_0x30 0x0000000a +#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a +#define regk_clkgen_nand_5_2_pll 0x00000018 +#define regk_clkgen_nand_5_3 0x00000009 +#define regk_clkgen_nand_5_3_0x30 0x0000000b +#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b +#define regk_clkgen_nand_5_3_pll 0x00000019 +#define regk_clkgen_no 0x00000000 +#define regk_clkgen_rw_clk_ctrl_default 0x00000002 +#define regk_clkgen_ser 0x0000000d +#define regk_clkgen_ser_pll 0x0000000f +#define regk_clkgen_yes 0x00000001 +#endif /* __clkgen_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h new file mode 100644 index 000000000..b12be03ed --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h @@ -0,0 +1,266 @@ +#ifndef __ddr2_defs_asm_h +#define __ddr2_defs_asm_h + +/* + * This file is autogenerated from + * file: ddr2.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_cfg, scope ddr2, type rw */ +#define reg_ddr2_rw_cfg___col_width___lsb 0 +#define reg_ddr2_rw_cfg___col_width___width 4 +#define reg_ddr2_rw_cfg___nr_banks___lsb 4 +#define reg_ddr2_rw_cfg___nr_banks___width 1 +#define reg_ddr2_rw_cfg___nr_banks___bit 4 +#define reg_ddr2_rw_cfg___bw___lsb 5 +#define reg_ddr2_rw_cfg___bw___width 1 +#define reg_ddr2_rw_cfg___bw___bit 5 +#define reg_ddr2_rw_cfg___nr_ref___lsb 6 +#define reg_ddr2_rw_cfg___nr_ref___width 4 +#define reg_ddr2_rw_cfg___ref_interval___lsb 10 +#define reg_ddr2_rw_cfg___ref_interval___width 11 +#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 +#define reg_ddr2_rw_cfg___odt_ctrl___width 2 +#define reg_ddr2_rw_cfg___odt_mem___lsb 23 +#define reg_ddr2_rw_cfg___odt_mem___width 1 +#define reg_ddr2_rw_cfg___odt_mem___bit 23 +#define reg_ddr2_rw_cfg___imp_strength___lsb 24 +#define reg_ddr2_rw_cfg___imp_strength___width 1 +#define reg_ddr2_rw_cfg___imp_strength___bit 24 +#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 +#define reg_ddr2_rw_cfg___auto_imp_cal___width 1 +#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 +#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 +#define reg_ddr2_rw_cfg___imp_cal_override___width 1 +#define reg_ddr2_rw_cfg___imp_cal_override___bit 26 +#define reg_ddr2_rw_cfg___dll_override___lsb 27 +#define reg_ddr2_rw_cfg___dll_override___width 1 +#define reg_ddr2_rw_cfg___dll_override___bit 27 +#define reg_ddr2_rw_cfg_offset 0 + +/* Register rw_timing, scope ddr2, type rw */ +#define reg_ddr2_rw_timing___wr___lsb 0 +#define reg_ddr2_rw_timing___wr___width 3 +#define reg_ddr2_rw_timing___rcd___lsb 3 +#define reg_ddr2_rw_timing___rcd___width 3 +#define reg_ddr2_rw_timing___rp___lsb 6 +#define reg_ddr2_rw_timing___rp___width 3 +#define reg_ddr2_rw_timing___ras___lsb 9 +#define reg_ddr2_rw_timing___ras___width 4 +#define reg_ddr2_rw_timing___rfc___lsb 13 +#define reg_ddr2_rw_timing___rfc___width 7 +#define reg_ddr2_rw_timing___rc___lsb 20 +#define reg_ddr2_rw_timing___rc___width 5 +#define reg_ddr2_rw_timing___rtp___lsb 25 +#define reg_ddr2_rw_timing___rtp___width 2 +#define reg_ddr2_rw_timing___rtw___lsb 27 +#define reg_ddr2_rw_timing___rtw___width 3 +#define reg_ddr2_rw_timing___wtr___lsb 30 +#define reg_ddr2_rw_timing___wtr___width 2 +#define reg_ddr2_rw_timing_offset 4 + +/* Register rw_latency, scope ddr2, type rw */ +#define reg_ddr2_rw_latency___cas___lsb 0 +#define reg_ddr2_rw_latency___cas___width 3 +#define reg_ddr2_rw_latency___additive___lsb 3 +#define reg_ddr2_rw_latency___additive___width 3 +#define reg_ddr2_rw_latency_offset 8 + +/* Register rw_phy_cfg, scope ddr2, type rw */ +#define reg_ddr2_rw_phy_cfg___en___lsb 0 +#define reg_ddr2_rw_phy_cfg___en___width 1 +#define reg_ddr2_rw_phy_cfg___en___bit 0 +#define reg_ddr2_rw_phy_cfg_offset 12 + +/* Register rw_phy_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_phy_ctrl___rst___lsb 0 +#define reg_ddr2_rw_phy_ctrl___rst___width 1 +#define reg_ddr2_rw_phy_ctrl___rst___bit 0 +#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 +#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 +#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 +#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 +#define reg_ddr2_rw_phy_ctrl___cal_start___width 1 +#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 +#define reg_ddr2_rw_phy_ctrl_offset 16 + +/* Register rw_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_ctrl___mrs_data___lsb 0 +#define reg_ddr2_rw_ctrl___mrs_data___width 16 +#define reg_ddr2_rw_ctrl___cmd___lsb 16 +#define reg_ddr2_rw_ctrl___cmd___width 8 +#define reg_ddr2_rw_ctrl_offset 20 + +/* Register rw_pwr_down, scope ddr2, type rw */ +#define reg_ddr2_rw_pwr_down___self_ref___lsb 0 +#define reg_ddr2_rw_pwr_down___self_ref___width 2 +#define reg_ddr2_rw_pwr_down___phy_en___lsb 2 +#define reg_ddr2_rw_pwr_down___phy_en___width 1 +#define reg_ddr2_rw_pwr_down___phy_en___bit 2 +#define reg_ddr2_rw_pwr_down_offset 24 + +/* Register r_stat, scope ddr2, type r */ +#define reg_ddr2_r_stat___dll_lock___lsb 0 +#define reg_ddr2_r_stat___dll_lock___width 1 +#define reg_ddr2_r_stat___dll_lock___bit 0 +#define reg_ddr2_r_stat___dll_delay_code___lsb 1 +#define reg_ddr2_r_stat___dll_delay_code___width 7 +#define reg_ddr2_r_stat___imp_cal_done___lsb 8 +#define reg_ddr2_r_stat___imp_cal_done___width 1 +#define reg_ddr2_r_stat___imp_cal_done___bit 8 +#define reg_ddr2_r_stat___imp_cal_fault___lsb 9 +#define reg_ddr2_r_stat___imp_cal_fault___width 1 +#define reg_ddr2_r_stat___imp_cal_fault___bit 9 +#define reg_ddr2_r_stat___cal_imp_pu___lsb 10 +#define reg_ddr2_r_stat___cal_imp_pu___width 4 +#define reg_ddr2_r_stat___cal_imp_pd___lsb 14 +#define reg_ddr2_r_stat___cal_imp_pd___width 4 +#define reg_ddr2_r_stat_offset 28 + +/* Register rw_imp_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 +#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 +#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 +#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 +#define reg_ddr2_rw_imp_ctrl_offset 32 + +#define STRIDE_ddr2_rw_dll_ctrl 4 +/* Register rw_dll_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_dll_ctrl___mode___lsb 0 +#define reg_ddr2_rw_dll_ctrl___mode___width 1 +#define reg_ddr2_rw_dll_ctrl___mode___bit 0 +#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 +#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 +#define reg_ddr2_rw_dll_ctrl_offset 36 + +#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 +/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ +#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 +#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 +#define reg_ddr2_rw_dqs_dll_ctrl_offset 52 + + +/* Constants */ +#define regk_ddr2_al0 0x00000000 +#define regk_ddr2_al1 0x00000008 +#define regk_ddr2_al2 0x00000010 +#define regk_ddr2_al3 0x00000018 +#define regk_ddr2_al4 0x00000020 +#define regk_ddr2_auto 0x00000003 +#define regk_ddr2_bank4 0x00000000 +#define regk_ddr2_bank8 0x00000001 +#define regk_ddr2_bl4 0x00000002 +#define regk_ddr2_bl8 0x00000003 +#define regk_ddr2_bt_il 0x00000008 +#define regk_ddr2_bt_seq 0x00000000 +#define regk_ddr2_bw16 0x00000001 +#define regk_ddr2_bw32 0x00000000 +#define regk_ddr2_cas2 0x00000020 +#define regk_ddr2_cas3 0x00000030 +#define regk_ddr2_cas4 0x00000040 +#define regk_ddr2_cas5 0x00000050 +#define regk_ddr2_deselect 0x000000c0 +#define regk_ddr2_dic_weak 0x00000002 +#define regk_ddr2_direct 0x00000001 +#define regk_ddr2_dis 0x00000000 +#define regk_ddr2_dll_dis 0x00000001 +#define regk_ddr2_dll_en 0x00000000 +#define regk_ddr2_dll_rst 0x00000100 +#define regk_ddr2_emrs 0x00000081 +#define regk_ddr2_emrs2 0x00000082 +#define regk_ddr2_emrs3 0x00000083 +#define regk_ddr2_full 0x00000001 +#define regk_ddr2_hi_ref_rate 0x00000080 +#define regk_ddr2_mrs 0x00000080 +#define regk_ddr2_no 0x00000000 +#define regk_ddr2_nop 0x000000b8 +#define regk_ddr2_ocd_adj 0x00000200 +#define regk_ddr2_ocd_default 0x00000380 +#define regk_ddr2_ocd_drive0 0x00000100 +#define regk_ddr2_ocd_drive1 0x00000080 +#define regk_ddr2_ocd_exit 0x00000000 +#define regk_ddr2_odt_dis 0x00000000 +#define regk_ddr2_offs 0x00000000 +#define regk_ddr2_pre 0x00000090 +#define regk_ddr2_pre_all 0x00000400 +#define regk_ddr2_pwr_down_fast 0x00000000 +#define regk_ddr2_pwr_down_slow 0x00001000 +#define regk_ddr2_ref 0x00000088 +#define regk_ddr2_rtt150 0x00000040 +#define regk_ddr2_rtt50 0x00000044 +#define regk_ddr2_rtt75 0x00000004 +#define regk_ddr2_rw_cfg_default 0x00186000 +#define regk_ddr2_rw_dll_ctrl_default 0x00000000 +#define regk_ddr2_rw_dll_ctrl_size 0x00000004 +#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 +#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 +#define regk_ddr2_rw_latency_default 0x00000000 +#define regk_ddr2_rw_phy_cfg_default 0x00000000 +#define regk_ddr2_rw_pwr_down_default 0x00000000 +#define regk_ddr2_rw_timing_default 0x00000000 +#define regk_ddr2_s1Gb 0x0000001a +#define regk_ddr2_s256Mb 0x0000000f +#define regk_ddr2_s2Gb 0x00000027 +#define regk_ddr2_s4Gb 0x00000042 +#define regk_ddr2_s512Mb 0x00000015 +#define regk_ddr2_temp0_85 0x00000618 +#define regk_ddr2_temp85_95 0x0000030c +#define regk_ddr2_term150 0x00000002 +#define regk_ddr2_term50 0x00000003 +#define regk_ddr2_term75 0x00000001 +#define regk_ddr2_test 0x00000080 +#define regk_ddr2_weak 0x00000000 +#define regk_ddr2_wr2 0x00000200 +#define regk_ddr2_wr3 0x00000400 +#define regk_ddr2_yes 0x00000001 +#endif /* __ddr2_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000..df6714fda --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,849 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: gio.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 32 +#define reg_gio_r_pa_din_offset 0 + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 32 +#define reg_gio_rw_pa_dout_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 32 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_pa_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte0_dout___data___lsb 0 +#define reg_gio_rw_pa_byte0_dout___data___width 8 +#define reg_gio_rw_pa_byte0_dout_offset 12 + +/* Register rw_pa_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte0_oe___oe___width 8 +#define reg_gio_rw_pa_byte0_oe_offset 16 + +/* Register rw_pa_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte1_dout___data___lsb 0 +#define reg_gio_rw_pa_byte1_dout___data___width 8 +#define reg_gio_rw_pa_byte1_dout_offset 20 + +/* Register rw_pa_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte1_oe___oe___width 8 +#define reg_gio_rw_pa_byte1_oe_offset 24 + +/* Register rw_pa_byte2_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte2_dout___data___lsb 0 +#define reg_gio_rw_pa_byte2_dout___data___width 8 +#define reg_gio_rw_pa_byte2_dout_offset 28 + +/* Register rw_pa_byte2_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte2_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte2_oe___oe___width 8 +#define reg_gio_rw_pa_byte2_oe_offset 32 + +/* Register rw_pa_byte3_dout, scope gio, type rw */ +#define reg_gio_rw_pa_byte3_dout___data___lsb 0 +#define reg_gio_rw_pa_byte3_dout___data___width 8 +#define reg_gio_rw_pa_byte3_dout_offset 36 + +/* Register rw_pa_byte3_oe, scope gio, type rw */ +#define reg_gio_rw_pa_byte3_oe___oe___lsb 0 +#define reg_gio_rw_pa_byte3_oe___oe___width 8 +#define reg_gio_rw_pa_byte3_oe_offset 40 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 32 +#define reg_gio_r_pb_din_offset 44 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 32 +#define reg_gio_rw_pb_dout_offset 48 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 32 +#define reg_gio_rw_pb_oe_offset 52 + +/* Register rw_pb_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte0_dout___data___lsb 0 +#define reg_gio_rw_pb_byte0_dout___data___width 8 +#define reg_gio_rw_pb_byte0_dout_offset 56 + +/* Register rw_pb_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte0_oe___oe___width 8 +#define reg_gio_rw_pb_byte0_oe_offset 60 + +/* Register rw_pb_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte1_dout___data___lsb 0 +#define reg_gio_rw_pb_byte1_dout___data___width 8 +#define reg_gio_rw_pb_byte1_dout_offset 64 + +/* Register rw_pb_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte1_oe___oe___width 8 +#define reg_gio_rw_pb_byte1_oe_offset 68 + +/* Register rw_pb_byte2_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte2_dout___data___lsb 0 +#define reg_gio_rw_pb_byte2_dout___data___width 8 +#define reg_gio_rw_pb_byte2_dout_offset 72 + +/* Register rw_pb_byte2_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte2_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte2_oe___oe___width 8 +#define reg_gio_rw_pb_byte2_oe_offset 76 + +/* Register rw_pb_byte3_dout, scope gio, type rw */ +#define reg_gio_rw_pb_byte3_dout___data___lsb 0 +#define reg_gio_rw_pb_byte3_dout___data___width 8 +#define reg_gio_rw_pb_byte3_dout_offset 80 + +/* Register rw_pb_byte3_oe, scope gio, type rw */ +#define reg_gio_rw_pb_byte3_oe___oe___lsb 0 +#define reg_gio_rw_pb_byte3_oe___oe___width 8 +#define reg_gio_rw_pb_byte3_oe_offset 84 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 16 +#define reg_gio_r_pc_din_offset 88 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 16 +#define reg_gio_rw_pc_dout_offset 92 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 16 +#define reg_gio_rw_pc_oe_offset 96 + +/* Register rw_pc_byte0_dout, scope gio, type rw */ +#define reg_gio_rw_pc_byte0_dout___data___lsb 0 +#define reg_gio_rw_pc_byte0_dout___data___width 8 +#define reg_gio_rw_pc_byte0_dout_offset 100 + +/* Register rw_pc_byte0_oe, scope gio, type rw */ +#define reg_gio_rw_pc_byte0_oe___oe___lsb 0 +#define reg_gio_rw_pc_byte0_oe___oe___width 8 +#define reg_gio_rw_pc_byte0_oe_offset 104 + +/* Register rw_pc_byte1_dout, scope gio, type rw */ +#define reg_gio_rw_pc_byte1_dout___data___lsb 0 +#define reg_gio_rw_pc_byte1_dout___data___width 8 +#define reg_gio_rw_pc_byte1_dout_offset 108 + +/* Register rw_pc_byte1_oe, scope gio, type rw */ +#define reg_gio_rw_pc_byte1_oe___oe___lsb 0 +#define reg_gio_rw_pc_byte1_oe___oe___width 8 +#define reg_gio_rw_pc_byte1_oe_offset 112 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 32 +#define reg_gio_r_pd_din_offset 116 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___intr0___lsb 0 +#define reg_gio_rw_intr_cfg___intr0___width 3 +#define reg_gio_rw_intr_cfg___intr1___lsb 3 +#define reg_gio_rw_intr_cfg___intr1___width 3 +#define reg_gio_rw_intr_cfg___intr2___lsb 6 +#define reg_gio_rw_intr_cfg___intr2___width 3 +#define reg_gio_rw_intr_cfg___intr3___lsb 9 +#define reg_gio_rw_intr_cfg___intr3___width 3 +#define reg_gio_rw_intr_cfg___intr4___lsb 12 +#define reg_gio_rw_intr_cfg___intr4___width 3 +#define reg_gio_rw_intr_cfg___intr5___lsb 15 +#define reg_gio_rw_intr_cfg___intr5___width 3 +#define reg_gio_rw_intr_cfg___intr6___lsb 18 +#define reg_gio_rw_intr_cfg___intr6___width 3 +#define reg_gio_rw_intr_cfg___intr7___lsb 21 +#define reg_gio_rw_intr_cfg___intr7___width 3 +#define reg_gio_rw_intr_cfg_offset 120 + +/* Register rw_intr_pins, scope gio, type rw */ +#define reg_gio_rw_intr_pins___intr0___lsb 0 +#define reg_gio_rw_intr_pins___intr0___width 4 +#define reg_gio_rw_intr_pins___intr1___lsb 4 +#define reg_gio_rw_intr_pins___intr1___width 4 +#define reg_gio_rw_intr_pins___intr2___lsb 8 +#define reg_gio_rw_intr_pins___intr2___width 4 +#define reg_gio_rw_intr_pins___intr3___lsb 12 +#define reg_gio_rw_intr_pins___intr3___width 4 +#define reg_gio_rw_intr_pins___intr4___lsb 16 +#define reg_gio_rw_intr_pins___intr4___width 4 +#define reg_gio_rw_intr_pins___intr5___lsb 20 +#define reg_gio_rw_intr_pins___intr5___width 4 +#define reg_gio_rw_intr_pins___intr6___lsb 24 +#define reg_gio_rw_intr_pins___intr6___width 4 +#define reg_gio_rw_intr_pins___intr7___lsb 28 +#define reg_gio_rw_intr_pins___intr7___width 4 +#define reg_gio_rw_intr_pins_offset 124 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___intr0___lsb 0 +#define reg_gio_rw_intr_mask___intr0___width 1 +#define reg_gio_rw_intr_mask___intr0___bit 0 +#define reg_gio_rw_intr_mask___intr1___lsb 1 +#define reg_gio_rw_intr_mask___intr1___width 1 +#define reg_gio_rw_intr_mask___intr1___bit 1 +#define reg_gio_rw_intr_mask___intr2___lsb 2 +#define reg_gio_rw_intr_mask___intr2___width 1 +#define reg_gio_rw_intr_mask___intr2___bit 2 +#define reg_gio_rw_intr_mask___intr3___lsb 3 +#define reg_gio_rw_intr_mask___intr3___width 1 +#define reg_gio_rw_intr_mask___intr3___bit 3 +#define reg_gio_rw_intr_mask___intr4___lsb 4 +#define reg_gio_rw_intr_mask___intr4___width 1 +#define reg_gio_rw_intr_mask___intr4___bit 4 +#define reg_gio_rw_intr_mask___intr5___lsb 5 +#define reg_gio_rw_intr_mask___intr5___width 1 +#define reg_gio_rw_intr_mask___intr5___bit 5 +#define reg_gio_rw_intr_mask___intr6___lsb 6 +#define reg_gio_rw_intr_mask___intr6___width 1 +#define reg_gio_rw_intr_mask___intr6___bit 6 +#define reg_gio_rw_intr_mask___intr7___lsb 7 +#define reg_gio_rw_intr_mask___intr7___width 1 +#define reg_gio_rw_intr_mask___intr7___bit 7 +#define reg_gio_rw_intr_mask___i2c0_done___lsb 8 +#define reg_gio_rw_intr_mask___i2c0_done___width 1 +#define reg_gio_rw_intr_mask___i2c0_done___bit 8 +#define reg_gio_rw_intr_mask___i2c1_done___lsb 9 +#define reg_gio_rw_intr_mask___i2c1_done___width 1 +#define reg_gio_rw_intr_mask___i2c1_done___bit 9 +#define reg_gio_rw_intr_mask_offset 128 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___intr0___lsb 0 +#define reg_gio_rw_ack_intr___intr0___width 1 +#define reg_gio_rw_ack_intr___intr0___bit 0 +#define reg_gio_rw_ack_intr___intr1___lsb 1 +#define reg_gio_rw_ack_intr___intr1___width 1 +#define reg_gio_rw_ack_intr___intr1___bit 1 +#define reg_gio_rw_ack_intr___intr2___lsb 2 +#define reg_gio_rw_ack_intr___intr2___width 1 +#define reg_gio_rw_ack_intr___intr2___bit 2 +#define reg_gio_rw_ack_intr___intr3___lsb 3 +#define reg_gio_rw_ack_intr___intr3___width 1 +#define reg_gio_rw_ack_intr___intr3___bit 3 +#define reg_gio_rw_ack_intr___intr4___lsb 4 +#define reg_gio_rw_ack_intr___intr4___width 1 +#define reg_gio_rw_ack_intr___intr4___bit 4 +#define reg_gio_rw_ack_intr___intr5___lsb 5 +#define reg_gio_rw_ack_intr___intr5___width 1 +#define reg_gio_rw_ack_intr___intr5___bit 5 +#define reg_gio_rw_ack_intr___intr6___lsb 6 +#define reg_gio_rw_ack_intr___intr6___width 1 +#define reg_gio_rw_ack_intr___intr6___bit 6 +#define reg_gio_rw_ack_intr___intr7___lsb 7 +#define reg_gio_rw_ack_intr___intr7___width 1 +#define reg_gio_rw_ack_intr___intr7___bit 7 +#define reg_gio_rw_ack_intr___i2c0_done___lsb 8 +#define reg_gio_rw_ack_intr___i2c0_done___width 1 +#define reg_gio_rw_ack_intr___i2c0_done___bit 8 +#define reg_gio_rw_ack_intr___i2c1_done___lsb 9 +#define reg_gio_rw_ack_intr___i2c1_done___width 1 +#define reg_gio_rw_ack_intr___i2c1_done___bit 9 +#define reg_gio_rw_ack_intr_offset 132 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___intr0___lsb 0 +#define reg_gio_r_intr___intr0___width 1 +#define reg_gio_r_intr___intr0___bit 0 +#define reg_gio_r_intr___intr1___lsb 1 +#define reg_gio_r_intr___intr1___width 1 +#define reg_gio_r_intr___intr1___bit 1 +#define reg_gio_r_intr___intr2___lsb 2 +#define reg_gio_r_intr___intr2___width 1 +#define reg_gio_r_intr___intr2___bit 2 +#define reg_gio_r_intr___intr3___lsb 3 +#define reg_gio_r_intr___intr3___width 1 +#define reg_gio_r_intr___intr3___bit 3 +#define reg_gio_r_intr___intr4___lsb 4 +#define reg_gio_r_intr___intr4___width 1 +#define reg_gio_r_intr___intr4___bit 4 +#define reg_gio_r_intr___intr5___lsb 5 +#define reg_gio_r_intr___intr5___width 1 +#define reg_gio_r_intr___intr5___bit 5 +#define reg_gio_r_intr___intr6___lsb 6 +#define reg_gio_r_intr___intr6___width 1 +#define reg_gio_r_intr___intr6___bit 6 +#define reg_gio_r_intr___intr7___lsb 7 +#define reg_gio_r_intr___intr7___width 1 +#define reg_gio_r_intr___intr7___bit 7 +#define reg_gio_r_intr___i2c0_done___lsb 8 +#define reg_gio_r_intr___i2c0_done___width 1 +#define reg_gio_r_intr___i2c0_done___bit 8 +#define reg_gio_r_intr___i2c1_done___lsb 9 +#define reg_gio_r_intr___i2c1_done___width 1 +#define reg_gio_r_intr___i2c1_done___bit 9 +#define reg_gio_r_intr_offset 136 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___intr0___lsb 0 +#define reg_gio_r_masked_intr___intr0___width 1 +#define reg_gio_r_masked_intr___intr0___bit 0 +#define reg_gio_r_masked_intr___intr1___lsb 1 +#define reg_gio_r_masked_intr___intr1___width 1 +#define reg_gio_r_masked_intr___intr1___bit 1 +#define reg_gio_r_masked_intr___intr2___lsb 2 +#define reg_gio_r_masked_intr___intr2___width 1 +#define reg_gio_r_masked_intr___intr2___bit 2 +#define reg_gio_r_masked_intr___intr3___lsb 3 +#define reg_gio_r_masked_intr___intr3___width 1 +#define reg_gio_r_masked_intr___intr3___bit 3 +#define reg_gio_r_masked_intr___intr4___lsb 4 +#define reg_gio_r_masked_intr___intr4___width 1 +#define reg_gio_r_masked_intr___intr4___bit 4 +#define reg_gio_r_masked_intr___intr5___lsb 5 +#define reg_gio_r_masked_intr___intr5___width 1 +#define reg_gio_r_masked_intr___intr5___bit 5 +#define reg_gio_r_masked_intr___intr6___lsb 6 +#define reg_gio_r_masked_intr___intr6___width 1 +#define reg_gio_r_masked_intr___intr6___bit 6 +#define reg_gio_r_masked_intr___intr7___lsb 7 +#define reg_gio_r_masked_intr___intr7___width 1 +#define reg_gio_r_masked_intr___intr7___bit 7 +#define reg_gio_r_masked_intr___i2c0_done___lsb 8 +#define reg_gio_r_masked_intr___i2c0_done___width 1 +#define reg_gio_r_masked_intr___i2c0_done___bit 8 +#define reg_gio_r_masked_intr___i2c1_done___lsb 9 +#define reg_gio_r_masked_intr___i2c1_done___width 1 +#define reg_gio_r_masked_intr___i2c1_done___bit 9 +#define reg_gio_r_masked_intr_offset 140 + +/* Register rw_i2c0_start, scope gio, type rw */ +#define reg_gio_rw_i2c0_start___run___lsb 0 +#define reg_gio_rw_i2c0_start___run___width 1 +#define reg_gio_rw_i2c0_start___run___bit 0 +#define reg_gio_rw_i2c0_start_offset 144 + +/* Register rw_i2c0_cfg, scope gio, type rw */ +#define reg_gio_rw_i2c0_cfg___en___lsb 0 +#define reg_gio_rw_i2c0_cfg___en___width 1 +#define reg_gio_rw_i2c0_cfg___en___bit 0 +#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 +#define reg_gio_rw_i2c0_cfg___bit_order___width 1 +#define reg_gio_rw_i2c0_cfg___bit_order___bit 1 +#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 +#define reg_gio_rw_i2c0_cfg___scl_io___width 1 +#define reg_gio_rw_i2c0_cfg___scl_io___bit 2 +#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 +#define reg_gio_rw_i2c0_cfg___scl_inv___width 1 +#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 +#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 +#define reg_gio_rw_i2c0_cfg___sda_io___width 1 +#define reg_gio_rw_i2c0_cfg___sda_io___bit 4 +#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 +#define reg_gio_rw_i2c0_cfg___sda_idle___width 1 +#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 +#define reg_gio_rw_i2c0_cfg_offset 148 + +/* Register rw_i2c0_ctrl, scope gio, type rw */ +#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 +#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 +#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 +#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 +#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 +#define reg_gio_rw_i2c0_ctrl___extra_start___width 3 +#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 +#define reg_gio_rw_i2c0_ctrl___early_end___width 1 +#define reg_gio_rw_i2c0_ctrl___early_end___bit 15 +#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 +#define reg_gio_rw_i2c0_ctrl___start_stop___width 1 +#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 +#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 +#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 +#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 +#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 +#define reg_gio_rw_i2c0_ctrl___start_bit___width 1 +#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 +#define reg_gio_rw_i2c0_ctrl___freq___lsb 25 +#define reg_gio_rw_i2c0_ctrl___freq___width 2 +#define reg_gio_rw_i2c0_ctrl_offset 152 + +/* Register rw_i2c0_data, scope gio, type rw */ +#define reg_gio_rw_i2c0_data___data0___lsb 0 +#define reg_gio_rw_i2c0_data___data0___width 8 +#define reg_gio_rw_i2c0_data___data1___lsb 8 +#define reg_gio_rw_i2c0_data___data1___width 8 +#define reg_gio_rw_i2c0_data___data2___lsb 16 +#define reg_gio_rw_i2c0_data___data2___width 8 +#define reg_gio_rw_i2c0_data___data3___lsb 24 +#define reg_gio_rw_i2c0_data___data3___width 8 +#define reg_gio_rw_i2c0_data_offset 156 + +/* Register rw_i2c0_data2, scope gio, type rw */ +#define reg_gio_rw_i2c0_data2___data4___lsb 0 +#define reg_gio_rw_i2c0_data2___data4___width 8 +#define reg_gio_rw_i2c0_data2___data5___lsb 8 +#define reg_gio_rw_i2c0_data2___data5___width 8 +#define reg_gio_rw_i2c0_data2___start_val___lsb 16 +#define reg_gio_rw_i2c0_data2___start_val___width 6 +#define reg_gio_rw_i2c0_data2___ack_val___lsb 22 +#define reg_gio_rw_i2c0_data2___ack_val___width 6 +#define reg_gio_rw_i2c0_data2_offset 160 + +/* Register rw_i2c1_start, scope gio, type rw */ +#define reg_gio_rw_i2c1_start___run___lsb 0 +#define reg_gio_rw_i2c1_start___run___width 1 +#define reg_gio_rw_i2c1_start___run___bit 0 +#define reg_gio_rw_i2c1_start_offset 164 + +/* Register rw_i2c1_cfg, scope gio, type rw */ +#define reg_gio_rw_i2c1_cfg___en___lsb 0 +#define reg_gio_rw_i2c1_cfg___en___width 1 +#define reg_gio_rw_i2c1_cfg___en___bit 0 +#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 +#define reg_gio_rw_i2c1_cfg___bit_order___width 1 +#define reg_gio_rw_i2c1_cfg___bit_order___bit 1 +#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 +#define reg_gio_rw_i2c1_cfg___scl_io___width 1 +#define reg_gio_rw_i2c1_cfg___scl_io___bit 2 +#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 +#define reg_gio_rw_i2c1_cfg___scl_inv___width 1 +#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 +#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 +#define reg_gio_rw_i2c1_cfg___sda0_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 +#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 +#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 +#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 +#define reg_gio_rw_i2c1_cfg___sda1_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 +#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 +#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 +#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 +#define reg_gio_rw_i2c1_cfg___sda2_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 +#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 +#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 +#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 +#define reg_gio_rw_i2c1_cfg___sda3_io___width 1 +#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 +#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 +#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 +#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 +#define reg_gio_rw_i2c1_cfg___sda_sel___width 2 +#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 +#define reg_gio_rw_i2c1_cfg___sen_idle___width 1 +#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 +#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 +#define reg_gio_rw_i2c1_cfg___sen_inv___width 1 +#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 +#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 +#define reg_gio_rw_i2c1_cfg___sen_sel___width 2 +#define reg_gio_rw_i2c1_cfg_offset 168 + +/* Register rw_i2c1_ctrl, scope gio, type rw */ +#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 +#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 +#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 +#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 +#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 +#define reg_gio_rw_i2c1_ctrl___extra_start___width 3 +#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 +#define reg_gio_rw_i2c1_ctrl___early_end___width 1 +#define reg_gio_rw_i2c1_ctrl___early_end___bit 15 +#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 +#define reg_gio_rw_i2c1_ctrl___start_stop___width 1 +#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 +#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 +#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 +#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 +#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 +#define reg_gio_rw_i2c1_ctrl___start_bit___width 1 +#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 +#define reg_gio_rw_i2c1_ctrl___freq___lsb 25 +#define reg_gio_rw_i2c1_ctrl___freq___width 2 +#define reg_gio_rw_i2c1_ctrl_offset 172 + +/* Register rw_i2c1_data, scope gio, type rw */ +#define reg_gio_rw_i2c1_data___data0___lsb 0 +#define reg_gio_rw_i2c1_data___data0___width 8 +#define reg_gio_rw_i2c1_data___data1___lsb 8 +#define reg_gio_rw_i2c1_data___data1___width 8 +#define reg_gio_rw_i2c1_data___data2___lsb 16 +#define reg_gio_rw_i2c1_data___data2___width 8 +#define reg_gio_rw_i2c1_data___data3___lsb 24 +#define reg_gio_rw_i2c1_data___data3___width 8 +#define reg_gio_rw_i2c1_data_offset 176 + +/* Register rw_i2c1_data2, scope gio, type rw */ +#define reg_gio_rw_i2c1_data2___data4___lsb 0 +#define reg_gio_rw_i2c1_data2___data4___width 8 +#define reg_gio_rw_i2c1_data2___data5___lsb 8 +#define reg_gio_rw_i2c1_data2___data5___width 8 +#define reg_gio_rw_i2c1_data2___start_val___lsb 16 +#define reg_gio_rw_i2c1_data2___start_val___width 6 +#define reg_gio_rw_i2c1_data2___ack_val___lsb 22 +#define reg_gio_rw_i2c1_data2___ack_val___width 6 +#define reg_gio_rw_i2c1_data2_offset 180 + +/* Register r_ppwm_stat, scope gio, type r */ +#define reg_gio_r_ppwm_stat___freq___lsb 0 +#define reg_gio_r_ppwm_stat___freq___width 2 +#define reg_gio_r_ppwm_stat_offset 184 + +/* Register rw_ppwm_data, scope gio, type rw */ +#define reg_gio_rw_ppwm_data___data___lsb 0 +#define reg_gio_rw_ppwm_data___data___width 8 +#define reg_gio_rw_ppwm_data_offset 188 + +/* Register rw_pwm0_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm0_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm0_ctrl___mode___width 2 +#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm0_ctrl_offset 192 + +/* Register rw_pwm0_var, scope gio, type rw */ +#define reg_gio_rw_pwm0_var___lo___lsb 0 +#define reg_gio_rw_pwm0_var___lo___width 13 +#define reg_gio_rw_pwm0_var___hi___lsb 13 +#define reg_gio_rw_pwm0_var___hi___width 13 +#define reg_gio_rw_pwm0_var_offset 196 + +/* Register rw_pwm0_data, scope gio, type rw */ +#define reg_gio_rw_pwm0_data___data___lsb 0 +#define reg_gio_rw_pwm0_data___data___width 8 +#define reg_gio_rw_pwm0_data_offset 200 + +/* Register rw_pwm1_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm1_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm1_ctrl___mode___width 2 +#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm1_ctrl_offset 204 + +/* Register rw_pwm1_var, scope gio, type rw */ +#define reg_gio_rw_pwm1_var___lo___lsb 0 +#define reg_gio_rw_pwm1_var___lo___width 13 +#define reg_gio_rw_pwm1_var___hi___lsb 13 +#define reg_gio_rw_pwm1_var___hi___width 13 +#define reg_gio_rw_pwm1_var_offset 208 + +/* Register rw_pwm1_data, scope gio, type rw */ +#define reg_gio_rw_pwm1_data___data___lsb 0 +#define reg_gio_rw_pwm1_data___data___width 8 +#define reg_gio_rw_pwm1_data_offset 212 + +/* Register rw_pwm2_ctrl, scope gio, type rw */ +#define reg_gio_rw_pwm2_ctrl___mode___lsb 0 +#define reg_gio_rw_pwm2_ctrl___mode___width 2 +#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 +#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 +#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 +#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 +#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 +#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 +#define reg_gio_rw_pwm2_ctrl_offset 216 + +/* Register rw_pwm2_var, scope gio, type rw */ +#define reg_gio_rw_pwm2_var___lo___lsb 0 +#define reg_gio_rw_pwm2_var___lo___width 13 +#define reg_gio_rw_pwm2_var___hi___lsb 13 +#define reg_gio_rw_pwm2_var___hi___width 13 +#define reg_gio_rw_pwm2_var_offset 220 + +/* Register rw_pwm2_data, scope gio, type rw */ +#define reg_gio_rw_pwm2_data___data___lsb 0 +#define reg_gio_rw_pwm2_data___data___width 8 +#define reg_gio_rw_pwm2_data_offset 224 + +/* Register rw_pwm_in_cfg, scope gio, type rw */ +#define reg_gio_rw_pwm_in_cfg___pin___lsb 0 +#define reg_gio_rw_pwm_in_cfg___pin___width 3 +#define reg_gio_rw_pwm_in_cfg_offset 228 + +/* Register r_pwm_in_lo, scope gio, type r */ +#define reg_gio_r_pwm_in_lo___data___lsb 0 +#define reg_gio_r_pwm_in_lo___data___width 32 +#define reg_gio_r_pwm_in_lo_offset 232 + +/* Register r_pwm_in_hi, scope gio, type r */ +#define reg_gio_r_pwm_in_hi___data___lsb 0 +#define reg_gio_r_pwm_in_hi___data___width 32 +#define reg_gio_r_pwm_in_hi_offset 236 + +/* Register r_pwm_in_cnt, scope gio, type r */ +#define reg_gio_r_pwm_in_cnt___data___lsb 0 +#define reg_gio_r_pwm_in_cnt___data___width 32 +#define reg_gio_r_pwm_in_cnt_offset 240 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_f100k 0x00000000 +#define regk_gio_f1562 0x00000000 +#define regk_gio_f195 0x00000003 +#define regk_gio_f1m 0x00000002 +#define regk_gio_f390 0x00000002 +#define regk_gio_f400k 0x00000001 +#define regk_gio_f5m 0x00000003 +#define regk_gio_f781 0x00000001 +#define regk_gio_hi 0x00000001 +#define regk_gio_in 0x00000000 +#define regk_gio_intr_pa0 0x00000000 +#define regk_gio_intr_pa1 0x00000000 +#define regk_gio_intr_pa10 0x00000001 +#define regk_gio_intr_pa11 0x00000001 +#define regk_gio_intr_pa12 0x00000001 +#define regk_gio_intr_pa13 0x00000001 +#define regk_gio_intr_pa14 0x00000001 +#define regk_gio_intr_pa15 0x00000001 +#define regk_gio_intr_pa16 0x00000002 +#define regk_gio_intr_pa17 0x00000002 +#define regk_gio_intr_pa18 0x00000002 +#define regk_gio_intr_pa19 0x00000002 +#define regk_gio_intr_pa2 0x00000000 +#define regk_gio_intr_pa20 0x00000002 +#define regk_gio_intr_pa21 0x00000002 +#define regk_gio_intr_pa22 0x00000002 +#define regk_gio_intr_pa23 0x00000002 +#define regk_gio_intr_pa24 0x00000003 +#define regk_gio_intr_pa25 0x00000003 +#define regk_gio_intr_pa26 0x00000003 +#define regk_gio_intr_pa27 0x00000003 +#define regk_gio_intr_pa28 0x00000003 +#define regk_gio_intr_pa29 0x00000003 +#define regk_gio_intr_pa3 0x00000000 +#define regk_gio_intr_pa30 0x00000003 +#define regk_gio_intr_pa31 0x00000003 +#define regk_gio_intr_pa4 0x00000000 +#define regk_gio_intr_pa5 0x00000000 +#define regk_gio_intr_pa6 0x00000000 +#define regk_gio_intr_pa7 0x00000000 +#define regk_gio_intr_pa8 0x00000001 +#define regk_gio_intr_pa9 0x00000001 +#define regk_gio_intr_pb0 0x00000004 +#define regk_gio_intr_pb1 0x00000004 +#define regk_gio_intr_pb10 0x00000005 +#define regk_gio_intr_pb11 0x00000005 +#define regk_gio_intr_pb12 0x00000005 +#define regk_gio_intr_pb13 0x00000005 +#define regk_gio_intr_pb14 0x00000005 +#define regk_gio_intr_pb15 0x00000005 +#define regk_gio_intr_pb16 0x00000006 +#define regk_gio_intr_pb17 0x00000006 +#define regk_gio_intr_pb18 0x00000006 +#define regk_gio_intr_pb19 0x00000006 +#define regk_gio_intr_pb2 0x00000004 +#define regk_gio_intr_pb20 0x00000006 +#define regk_gio_intr_pb21 0x00000006 +#define regk_gio_intr_pb22 0x00000006 +#define regk_gio_intr_pb23 0x00000006 +#define regk_gio_intr_pb24 0x00000007 +#define regk_gio_intr_pb25 0x00000007 +#define regk_gio_intr_pb26 0x00000007 +#define regk_gio_intr_pb27 0x00000007 +#define regk_gio_intr_pb28 0x00000007 +#define regk_gio_intr_pb29 0x00000007 +#define regk_gio_intr_pb3 0x00000004 +#define regk_gio_intr_pb30 0x00000007 +#define regk_gio_intr_pb31 0x00000007 +#define regk_gio_intr_pb4 0x00000004 +#define regk_gio_intr_pb5 0x00000004 +#define regk_gio_intr_pb6 0x00000004 +#define regk_gio_intr_pb7 0x00000004 +#define regk_gio_intr_pb8 0x00000005 +#define regk_gio_intr_pb9 0x00000005 +#define regk_gio_intr_pc0 0x00000008 +#define regk_gio_intr_pc1 0x00000008 +#define regk_gio_intr_pc10 0x00000009 +#define regk_gio_intr_pc11 0x00000009 +#define regk_gio_intr_pc12 0x00000009 +#define regk_gio_intr_pc13 0x00000009 +#define regk_gio_intr_pc14 0x00000009 +#define regk_gio_intr_pc15 0x00000009 +#define regk_gio_intr_pc2 0x00000008 +#define regk_gio_intr_pc3 0x00000008 +#define regk_gio_intr_pc4 0x00000008 +#define regk_gio_intr_pc5 0x00000008 +#define regk_gio_intr_pc6 0x00000008 +#define regk_gio_intr_pc7 0x00000008 +#define regk_gio_intr_pc8 0x00000009 +#define regk_gio_intr_pc9 0x00000009 +#define regk_gio_intr_pd0 0x0000000c +#define regk_gio_intr_pd1 0x0000000c +#define regk_gio_intr_pd10 0x0000000d +#define regk_gio_intr_pd11 0x0000000d +#define regk_gio_intr_pd12 0x0000000d +#define regk_gio_intr_pd13 0x0000000d +#define regk_gio_intr_pd14 0x0000000d +#define regk_gio_intr_pd15 0x0000000d +#define regk_gio_intr_pd16 0x0000000e +#define regk_gio_intr_pd17 0x0000000e +#define regk_gio_intr_pd18 0x0000000e +#define regk_gio_intr_pd19 0x0000000e +#define regk_gio_intr_pd2 0x0000000c +#define regk_gio_intr_pd20 0x0000000e +#define regk_gio_intr_pd21 0x0000000e +#define regk_gio_intr_pd22 0x0000000e +#define regk_gio_intr_pd23 0x0000000e +#define regk_gio_intr_pd24 0x0000000f +#define regk_gio_intr_pd25 0x0000000f +#define regk_gio_intr_pd26 0x0000000f +#define regk_gio_intr_pd27 0x0000000f +#define regk_gio_intr_pd28 0x0000000f +#define regk_gio_intr_pd29 0x0000000f +#define regk_gio_intr_pd3 0x0000000c +#define regk_gio_intr_pd30 0x0000000f +#define regk_gio_intr_pd31 0x0000000f +#define regk_gio_intr_pd4 0x0000000c +#define regk_gio_intr_pd5 0x0000000c +#define regk_gio_intr_pd6 0x0000000c +#define regk_gio_intr_pd7 0x0000000c +#define regk_gio_intr_pd8 0x0000000d +#define regk_gio_intr_pd9 0x0000000d +#define regk_gio_lo 0x00000002 +#define regk_gio_lsb 0x00000000 +#define regk_gio_msb 0x00000001 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_no_switch 0x0000003f +#define regk_gio_none 0x00000007 +#define regk_gio_off 0x00000000 +#define regk_gio_opendrain 0x00000000 +#define regk_gio_out 0x00000001 +#define regk_gio_posedge 0x00000005 +#define regk_gio_pwm_hfp 0x00000002 +#define regk_gio_pwm_pa0 0x00000001 +#define regk_gio_pwm_pa19 0x00000004 +#define regk_gio_pwm_pa6 0x00000002 +#define regk_gio_pwm_pa7 0x00000003 +#define regk_gio_pwm_pb26 0x00000005 +#define regk_gio_pwm_pd23 0x00000006 +#define regk_gio_pwm_pd31 0x00000007 +#define regk_gio_pwm_std 0x00000001 +#define regk_gio_pwm_var 0x00000003 +#define regk_gio_rw_i2c0_cfg_default 0x00000020 +#define regk_gio_rw_i2c0_ctrl_default 0x00010000 +#define regk_gio_rw_i2c0_start_default 0x00000000 +#define regk_gio_rw_i2c1_cfg_default 0x00000aa0 +#define regk_gio_rw_i2c1_ctrl_default 0x00010000 +#define regk_gio_rw_i2c1_start_default 0x00000000 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_ppwm_data_default 0x00000000 +#define regk_gio_rw_pwm0_ctrl_default 0x00000000 +#define regk_gio_rw_pwm1_ctrl_default 0x00000000 +#define regk_gio_rw_pwm2_ctrl_default 0x00000000 +#define regk_gio_rw_pwm_in_cfg_default 0x00000000 +#define regk_gio_sda0 0x00000000 +#define regk_gio_sda1 0x00000001 +#define regk_gio_sda2 0x00000002 +#define regk_gio_sda3 0x00000003 +#define regk_gio_sen 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 000000000..c3dc9c666 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h @@ -0,0 +1,572 @@ +#ifndef __pinmux_defs_asm_h +#define __pinmux_defs_asm_h + +/* + * This file is autogenerated from + * file: pinmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_hwprot, scope pinmux, type rw */ +#define reg_pinmux_rw_hwprot___eth___lsb 0 +#define reg_pinmux_rw_hwprot___eth___width 1 +#define reg_pinmux_rw_hwprot___eth___bit 0 +#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1 +#define reg_pinmux_rw_hwprot___eth_mdio___width 1 +#define reg_pinmux_rw_hwprot___eth_mdio___bit 1 +#define reg_pinmux_rw_hwprot___geth___lsb 2 +#define reg_pinmux_rw_hwprot___geth___width 1 +#define reg_pinmux_rw_hwprot___geth___bit 2 +#define reg_pinmux_rw_hwprot___tg___lsb 3 +#define reg_pinmux_rw_hwprot___tg___width 1 +#define reg_pinmux_rw_hwprot___tg___bit 3 +#define reg_pinmux_rw_hwprot___tg_clk___lsb 4 +#define reg_pinmux_rw_hwprot___tg_clk___width 1 +#define reg_pinmux_rw_hwprot___tg_clk___bit 4 +#define reg_pinmux_rw_hwprot___vout___lsb 5 +#define reg_pinmux_rw_hwprot___vout___width 1 +#define reg_pinmux_rw_hwprot___vout___bit 5 +#define reg_pinmux_rw_hwprot___vout_sync___lsb 6 +#define reg_pinmux_rw_hwprot___vout_sync___width 1 +#define reg_pinmux_rw_hwprot___vout_sync___bit 6 +#define reg_pinmux_rw_hwprot___ser1___lsb 7 +#define reg_pinmux_rw_hwprot___ser1___width 1 +#define reg_pinmux_rw_hwprot___ser1___bit 7 +#define reg_pinmux_rw_hwprot___ser2___lsb 8 +#define reg_pinmux_rw_hwprot___ser2___width 1 +#define reg_pinmux_rw_hwprot___ser2___bit 8 +#define reg_pinmux_rw_hwprot___ser3___lsb 9 +#define reg_pinmux_rw_hwprot___ser3___width 1 +#define reg_pinmux_rw_hwprot___ser3___bit 9 +#define reg_pinmux_rw_hwprot___ser4___lsb 10 +#define reg_pinmux_rw_hwprot___ser4___width 1 +#define reg_pinmux_rw_hwprot___ser4___bit 10 +#define reg_pinmux_rw_hwprot___sser___lsb 11 +#define reg_pinmux_rw_hwprot___sser___width 1 +#define reg_pinmux_rw_hwprot___sser___bit 11 +#define reg_pinmux_rw_hwprot___pwm0___lsb 12 +#define reg_pinmux_rw_hwprot___pwm0___width 1 +#define reg_pinmux_rw_hwprot___pwm0___bit 12 +#define reg_pinmux_rw_hwprot___pwm1___lsb 13 +#define reg_pinmux_rw_hwprot___pwm1___width 1 +#define reg_pinmux_rw_hwprot___pwm1___bit 13 +#define reg_pinmux_rw_hwprot___pwm2___lsb 14 +#define reg_pinmux_rw_hwprot___pwm2___width 1 +#define reg_pinmux_rw_hwprot___pwm2___bit 14 +#define reg_pinmux_rw_hwprot___timer0___lsb 15 +#define reg_pinmux_rw_hwprot___timer0___width 1 +#define reg_pinmux_rw_hwprot___timer0___bit 15 +#define reg_pinmux_rw_hwprot___timer1___lsb 16 +#define reg_pinmux_rw_hwprot___timer1___width 1 +#define reg_pinmux_rw_hwprot___timer1___bit 16 +#define reg_pinmux_rw_hwprot___pio___lsb 17 +#define reg_pinmux_rw_hwprot___pio___width 1 +#define reg_pinmux_rw_hwprot___pio___bit 17 +#define reg_pinmux_rw_hwprot___i2c0___lsb 18 +#define reg_pinmux_rw_hwprot___i2c0___width 1 +#define reg_pinmux_rw_hwprot___i2c0___bit 18 +#define reg_pinmux_rw_hwprot___i2c1___lsb 19 +#define reg_pinmux_rw_hwprot___i2c1___width 1 +#define reg_pinmux_rw_hwprot___i2c1___bit 19 +#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20 +#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20 +#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21 +#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21 +#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22 +#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22 +#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23 +#define reg_pinmux_rw_hwprot___i2c1_sen___width 1 +#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23 +#define reg_pinmux_rw_hwprot_offset 0 + +/* Register rw_gio_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pa___pa0___lsb 0 +#define reg_pinmux_rw_gio_pa___pa0___width 1 +#define reg_pinmux_rw_gio_pa___pa0___bit 0 +#define reg_pinmux_rw_gio_pa___pa1___lsb 1 +#define reg_pinmux_rw_gio_pa___pa1___width 1 +#define reg_pinmux_rw_gio_pa___pa1___bit 1 +#define reg_pinmux_rw_gio_pa___pa2___lsb 2 +#define reg_pinmux_rw_gio_pa___pa2___width 1 +#define reg_pinmux_rw_gio_pa___pa2___bit 2 +#define reg_pinmux_rw_gio_pa___pa3___lsb 3 +#define reg_pinmux_rw_gio_pa___pa3___width 1 +#define reg_pinmux_rw_gio_pa___pa3___bit 3 +#define reg_pinmux_rw_gio_pa___pa4___lsb 4 +#define reg_pinmux_rw_gio_pa___pa4___width 1 +#define reg_pinmux_rw_gio_pa___pa4___bit 4 +#define reg_pinmux_rw_gio_pa___pa5___lsb 5 +#define reg_pinmux_rw_gio_pa___pa5___width 1 +#define reg_pinmux_rw_gio_pa___pa5___bit 5 +#define reg_pinmux_rw_gio_pa___pa6___lsb 6 +#define reg_pinmux_rw_gio_pa___pa6___width 1 +#define reg_pinmux_rw_gio_pa___pa6___bit 6 +#define reg_pinmux_rw_gio_pa___pa7___lsb 7 +#define reg_pinmux_rw_gio_pa___pa7___width 1 +#define reg_pinmux_rw_gio_pa___pa7___bit 7 +#define reg_pinmux_rw_gio_pa___pa8___lsb 8 +#define reg_pinmux_rw_gio_pa___pa8___width 1 +#define reg_pinmux_rw_gio_pa___pa8___bit 8 +#define reg_pinmux_rw_gio_pa___pa9___lsb 9 +#define reg_pinmux_rw_gio_pa___pa9___width 1 +#define reg_pinmux_rw_gio_pa___pa9___bit 9 +#define reg_pinmux_rw_gio_pa___pa10___lsb 10 +#define reg_pinmux_rw_gio_pa___pa10___width 1 +#define reg_pinmux_rw_gio_pa___pa10___bit 10 +#define reg_pinmux_rw_gio_pa___pa11___lsb 11 +#define reg_pinmux_rw_gio_pa___pa11___width 1 +#define reg_pinmux_rw_gio_pa___pa11___bit 11 +#define reg_pinmux_rw_gio_pa___pa12___lsb 12 +#define reg_pinmux_rw_gio_pa___pa12___width 1 +#define reg_pinmux_rw_gio_pa___pa12___bit 12 +#define reg_pinmux_rw_gio_pa___pa13___lsb 13 +#define reg_pinmux_rw_gio_pa___pa13___width 1 +#define reg_pinmux_rw_gio_pa___pa13___bit 13 +#define reg_pinmux_rw_gio_pa___pa14___lsb 14 +#define reg_pinmux_rw_gio_pa___pa14___width 1 +#define reg_pinmux_rw_gio_pa___pa14___bit 14 +#define reg_pinmux_rw_gio_pa___pa15___lsb 15 +#define reg_pinmux_rw_gio_pa___pa15___width 1 +#define reg_pinmux_rw_gio_pa___pa15___bit 15 +#define reg_pinmux_rw_gio_pa___pa16___lsb 16 +#define reg_pinmux_rw_gio_pa___pa16___width 1 +#define reg_pinmux_rw_gio_pa___pa16___bit 16 +#define reg_pinmux_rw_gio_pa___pa17___lsb 17 +#define reg_pinmux_rw_gio_pa___pa17___width 1 +#define reg_pinmux_rw_gio_pa___pa17___bit 17 +#define reg_pinmux_rw_gio_pa___pa18___lsb 18 +#define reg_pinmux_rw_gio_pa___pa18___width 1 +#define reg_pinmux_rw_gio_pa___pa18___bit 18 +#define reg_pinmux_rw_gio_pa___pa19___lsb 19 +#define reg_pinmux_rw_gio_pa___pa19___width 1 +#define reg_pinmux_rw_gio_pa___pa19___bit 19 +#define reg_pinmux_rw_gio_pa___pa20___lsb 20 +#define reg_pinmux_rw_gio_pa___pa20___width 1 +#define reg_pinmux_rw_gio_pa___pa20___bit 20 +#define reg_pinmux_rw_gio_pa___pa21___lsb 21 +#define reg_pinmux_rw_gio_pa___pa21___width 1 +#define reg_pinmux_rw_gio_pa___pa21___bit 21 +#define reg_pinmux_rw_gio_pa___pa22___lsb 22 +#define reg_pinmux_rw_gio_pa___pa22___width 1 +#define reg_pinmux_rw_gio_pa___pa22___bit 22 +#define reg_pinmux_rw_gio_pa___pa23___lsb 23 +#define reg_pinmux_rw_gio_pa___pa23___width 1 +#define reg_pinmux_rw_gio_pa___pa23___bit 23 +#define reg_pinmux_rw_gio_pa___pa24___lsb 24 +#define reg_pinmux_rw_gio_pa___pa24___width 1 +#define reg_pinmux_rw_gio_pa___pa24___bit 24 +#define reg_pinmux_rw_gio_pa___pa25___lsb 25 +#define reg_pinmux_rw_gio_pa___pa25___width 1 +#define reg_pinmux_rw_gio_pa___pa25___bit 25 +#define reg_pinmux_rw_gio_pa___pa26___lsb 26 +#define reg_pinmux_rw_gio_pa___pa26___width 1 +#define reg_pinmux_rw_gio_pa___pa26___bit 26 +#define reg_pinmux_rw_gio_pa___pa27___lsb 27 +#define reg_pinmux_rw_gio_pa___pa27___width 1 +#define reg_pinmux_rw_gio_pa___pa27___bit 27 +#define reg_pinmux_rw_gio_pa___pa28___lsb 28 +#define reg_pinmux_rw_gio_pa___pa28___width 1 +#define reg_pinmux_rw_gio_pa___pa28___bit 28 +#define reg_pinmux_rw_gio_pa___pa29___lsb 29 +#define reg_pinmux_rw_gio_pa___pa29___width 1 +#define reg_pinmux_rw_gio_pa___pa29___bit 29 +#define reg_pinmux_rw_gio_pa___pa30___lsb 30 +#define reg_pinmux_rw_gio_pa___pa30___width 1 +#define reg_pinmux_rw_gio_pa___pa30___bit 30 +#define reg_pinmux_rw_gio_pa___pa31___lsb 31 +#define reg_pinmux_rw_gio_pa___pa31___width 1 +#define reg_pinmux_rw_gio_pa___pa31___bit 31 +#define reg_pinmux_rw_gio_pa_offset 4 + +/* Register rw_gio_pb, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pb___pb0___lsb 0 +#define reg_pinmux_rw_gio_pb___pb0___width 1 +#define reg_pinmux_rw_gio_pb___pb0___bit 0 +#define reg_pinmux_rw_gio_pb___pb1___lsb 1 +#define reg_pinmux_rw_gio_pb___pb1___width 1 +#define reg_pinmux_rw_gio_pb___pb1___bit 1 +#define reg_pinmux_rw_gio_pb___pb2___lsb 2 +#define reg_pinmux_rw_gio_pb___pb2___width 1 +#define reg_pinmux_rw_gio_pb___pb2___bit 2 +#define reg_pinmux_rw_gio_pb___pb3___lsb 3 +#define reg_pinmux_rw_gio_pb___pb3___width 1 +#define reg_pinmux_rw_gio_pb___pb3___bit 3 +#define reg_pinmux_rw_gio_pb___pb4___lsb 4 +#define reg_pinmux_rw_gio_pb___pb4___width 1 +#define reg_pinmux_rw_gio_pb___pb4___bit 4 +#define reg_pinmux_rw_gio_pb___pb5___lsb 5 +#define reg_pinmux_rw_gio_pb___pb5___width 1 +#define reg_pinmux_rw_gio_pb___pb5___bit 5 +#define reg_pinmux_rw_gio_pb___pb6___lsb 6 +#define reg_pinmux_rw_gio_pb___pb6___width 1 +#define reg_pinmux_rw_gio_pb___pb6___bit 6 +#define reg_pinmux_rw_gio_pb___pb7___lsb 7 +#define reg_pinmux_rw_gio_pb___pb7___width 1 +#define reg_pinmux_rw_gio_pb___pb7___bit 7 +#define reg_pinmux_rw_gio_pb___pb8___lsb 8 +#define reg_pinmux_rw_gio_pb___pb8___width 1 +#define reg_pinmux_rw_gio_pb___pb8___bit 8 +#define reg_pinmux_rw_gio_pb___pb9___lsb 9 +#define reg_pinmux_rw_gio_pb___pb9___width 1 +#define reg_pinmux_rw_gio_pb___pb9___bit 9 +#define reg_pinmux_rw_gio_pb___pb10___lsb 10 +#define reg_pinmux_rw_gio_pb___pb10___width 1 +#define reg_pinmux_rw_gio_pb___pb10___bit 10 +#define reg_pinmux_rw_gio_pb___pb11___lsb 11 +#define reg_pinmux_rw_gio_pb___pb11___width 1 +#define reg_pinmux_rw_gio_pb___pb11___bit 11 +#define reg_pinmux_rw_gio_pb___pb12___lsb 12 +#define reg_pinmux_rw_gio_pb___pb12___width 1 +#define reg_pinmux_rw_gio_pb___pb12___bit 12 +#define reg_pinmux_rw_gio_pb___pb13___lsb 13 +#define reg_pinmux_rw_gio_pb___pb13___width 1 +#define reg_pinmux_rw_gio_pb___pb13___bit 13 +#define reg_pinmux_rw_gio_pb___pb14___lsb 14 +#define reg_pinmux_rw_gio_pb___pb14___width 1 +#define reg_pinmux_rw_gio_pb___pb14___bit 14 +#define reg_pinmux_rw_gio_pb___pb15___lsb 15 +#define reg_pinmux_rw_gio_pb___pb15___width 1 +#define reg_pinmux_rw_gio_pb___pb15___bit 15 +#define reg_pinmux_rw_gio_pb___pb16___lsb 16 +#define reg_pinmux_rw_gio_pb___pb16___width 1 +#define reg_pinmux_rw_gio_pb___pb16___bit 16 +#define reg_pinmux_rw_gio_pb___pb17___lsb 17 +#define reg_pinmux_rw_gio_pb___pb17___width 1 +#define reg_pinmux_rw_gio_pb___pb17___bit 17 +#define reg_pinmux_rw_gio_pb___pb18___lsb 18 +#define reg_pinmux_rw_gio_pb___pb18___width 1 +#define reg_pinmux_rw_gio_pb___pb18___bit 18 +#define reg_pinmux_rw_gio_pb___pb19___lsb 19 +#define reg_pinmux_rw_gio_pb___pb19___width 1 +#define reg_pinmux_rw_gio_pb___pb19___bit 19 +#define reg_pinmux_rw_gio_pb___pb20___lsb 20 +#define reg_pinmux_rw_gio_pb___pb20___width 1 +#define reg_pinmux_rw_gio_pb___pb20___bit 20 +#define reg_pinmux_rw_gio_pb___pb21___lsb 21 +#define reg_pinmux_rw_gio_pb___pb21___width 1 +#define reg_pinmux_rw_gio_pb___pb21___bit 21 +#define reg_pinmux_rw_gio_pb___pb22___lsb 22 +#define reg_pinmux_rw_gio_pb___pb22___width 1 +#define reg_pinmux_rw_gio_pb___pb22___bit 22 +#define reg_pinmux_rw_gio_pb___pb23___lsb 23 +#define reg_pinmux_rw_gio_pb___pb23___width 1 +#define reg_pinmux_rw_gio_pb___pb23___bit 23 +#define reg_pinmux_rw_gio_pb___pb24___lsb 24 +#define reg_pinmux_rw_gio_pb___pb24___width 1 +#define reg_pinmux_rw_gio_pb___pb24___bit 24 +#define reg_pinmux_rw_gio_pb___pb25___lsb 25 +#define reg_pinmux_rw_gio_pb___pb25___width 1 +#define reg_pinmux_rw_gio_pb___pb25___bit 25 +#define reg_pinmux_rw_gio_pb___pb26___lsb 26 +#define reg_pinmux_rw_gio_pb___pb26___width 1 +#define reg_pinmux_rw_gio_pb___pb26___bit 26 +#define reg_pinmux_rw_gio_pb___pb27___lsb 27 +#define reg_pinmux_rw_gio_pb___pb27___width 1 +#define reg_pinmux_rw_gio_pb___pb27___bit 27 +#define reg_pinmux_rw_gio_pb___pb28___lsb 28 +#define reg_pinmux_rw_gio_pb___pb28___width 1 +#define reg_pinmux_rw_gio_pb___pb28___bit 28 +#define reg_pinmux_rw_gio_pb___pb29___lsb 29 +#define reg_pinmux_rw_gio_pb___pb29___width 1 +#define reg_pinmux_rw_gio_pb___pb29___bit 29 +#define reg_pinmux_rw_gio_pb___pb30___lsb 30 +#define reg_pinmux_rw_gio_pb___pb30___width 1 +#define reg_pinmux_rw_gio_pb___pb30___bit 30 +#define reg_pinmux_rw_gio_pb___pb31___lsb 31 +#define reg_pinmux_rw_gio_pb___pb31___width 1 +#define reg_pinmux_rw_gio_pb___pb31___bit 31 +#define reg_pinmux_rw_gio_pb_offset 8 + +/* Register rw_gio_pc, scope pinmux, type rw */ +#define reg_pinmux_rw_gio_pc___pc0___lsb 0 +#define reg_pinmux_rw_gio_pc___pc0___width 1 +#define reg_pinmux_rw_gio_pc___pc0___bit 0 +#define reg_pinmux_rw_gio_pc___pc1___lsb 1 +#define reg_pinmux_rw_gio_pc___pc1___width 1 +#define reg_pinmux_rw_gio_pc___pc1___bit 1 +#define reg_pinmux_rw_gio_pc___pc2___lsb 2 +#define reg_pinmux_rw_gio_pc___pc2___width 1 +#define reg_pinmux_rw_gio_pc___pc2___bit 2 +#define reg_pinmux_rw_gio_pc___pc3___lsb 3 +#define reg_pinmux_rw_gio_pc___pc3___width 1 +#define reg_pinmux_rw_gio_pc___pc3___bit 3 +#define reg_pinmux_rw_gio_pc___pc4___lsb 4 +#define reg_pinmux_rw_gio_pc___pc4___width 1 +#define reg_pinmux_rw_gio_pc___pc4___bit 4 +#define reg_pinmux_rw_gio_pc___pc5___lsb 5 +#define reg_pinmux_rw_gio_pc___pc5___width 1 +#define reg_pinmux_rw_gio_pc___pc5___bit 5 +#define reg_pinmux_rw_gio_pc___pc6___lsb 6 +#define reg_pinmux_rw_gio_pc___pc6___width 1 +#define reg_pinmux_rw_gio_pc___pc6___bit 6 +#define reg_pinmux_rw_gio_pc___pc7___lsb 7 +#define reg_pinmux_rw_gio_pc___pc7___width 1 +#define reg_pinmux_rw_gio_pc___pc7___bit 7 +#define reg_pinmux_rw_gio_pc___pc8___lsb 8 +#define reg_pinmux_rw_gio_pc___pc8___width 1 +#define reg_pinmux_rw_gio_pc___pc8___bit 8 +#define reg_pinmux_rw_gio_pc___pc9___lsb 9 +#define reg_pinmux_rw_gio_pc___pc9___width 1 +#define reg_pinmux_rw_gio_pc___pc9___bit 9 +#define reg_pinmux_rw_gio_pc___pc10___lsb 10 +#define reg_pinmux_rw_gio_pc___pc10___width 1 +#define reg_pinmux_rw_gio_pc___pc10___bit 10 +#define reg_pinmux_rw_gio_pc___pc11___lsb 11 +#define reg_pinmux_rw_gio_pc___pc11___width 1 +#define reg_pinmux_rw_gio_pc___pc11___bit 11 +#define reg_pinmux_rw_gio_pc___pc12___lsb 12 +#define reg_pinmux_rw_gio_pc___pc12___width 1 +#define reg_pinmux_rw_gio_pc___pc12___bit 12 +#define reg_pinmux_rw_gio_pc___pc13___lsb 13 +#define reg_pinmux_rw_gio_pc___pc13___width 1 +#define reg_pinmux_rw_gio_pc___pc13___bit 13 +#define reg_pinmux_rw_gio_pc___pc14___lsb 14 +#define reg_pinmux_rw_gio_pc___pc14___width 1 +#define reg_pinmux_rw_gio_pc___pc14___bit 14 +#define reg_pinmux_rw_gio_pc___pc15___lsb 15 +#define reg_pinmux_rw_gio_pc___pc15___width 1 +#define reg_pinmux_rw_gio_pc___pc15___bit 15 +#define reg_pinmux_rw_gio_pc_offset 12 + +/* Register rw_iop_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pa___pa0___lsb 0 +#define reg_pinmux_rw_iop_pa___pa0___width 1 +#define reg_pinmux_rw_iop_pa___pa0___bit 0 +#define reg_pinmux_rw_iop_pa___pa1___lsb 1 +#define reg_pinmux_rw_iop_pa___pa1___width 1 +#define reg_pinmux_rw_iop_pa___pa1___bit 1 +#define reg_pinmux_rw_iop_pa___pa2___lsb 2 +#define reg_pinmux_rw_iop_pa___pa2___width 1 +#define reg_pinmux_rw_iop_pa___pa2___bit 2 +#define reg_pinmux_rw_iop_pa___pa3___lsb 3 +#define reg_pinmux_rw_iop_pa___pa3___width 1 +#define reg_pinmux_rw_iop_pa___pa3___bit 3 +#define reg_pinmux_rw_iop_pa___pa4___lsb 4 +#define reg_pinmux_rw_iop_pa___pa4___width 1 +#define reg_pinmux_rw_iop_pa___pa4___bit 4 +#define reg_pinmux_rw_iop_pa___pa5___lsb 5 +#define reg_pinmux_rw_iop_pa___pa5___width 1 +#define reg_pinmux_rw_iop_pa___pa5___bit 5 +#define reg_pinmux_rw_iop_pa___pa6___lsb 6 +#define reg_pinmux_rw_iop_pa___pa6___width 1 +#define reg_pinmux_rw_iop_pa___pa6___bit 6 +#define reg_pinmux_rw_iop_pa___pa7___lsb 7 +#define reg_pinmux_rw_iop_pa___pa7___width 1 +#define reg_pinmux_rw_iop_pa___pa7___bit 7 +#define reg_pinmux_rw_iop_pa___pa8___lsb 8 +#define reg_pinmux_rw_iop_pa___pa8___width 1 +#define reg_pinmux_rw_iop_pa___pa8___bit 8 +#define reg_pinmux_rw_iop_pa___pa9___lsb 9 +#define reg_pinmux_rw_iop_pa___pa9___width 1 +#define reg_pinmux_rw_iop_pa___pa9___bit 9 +#define reg_pinmux_rw_iop_pa___pa10___lsb 10 +#define reg_pinmux_rw_iop_pa___pa10___width 1 +#define reg_pinmux_rw_iop_pa___pa10___bit 10 +#define reg_pinmux_rw_iop_pa___pa11___lsb 11 +#define reg_pinmux_rw_iop_pa___pa11___width 1 +#define reg_pinmux_rw_iop_pa___pa11___bit 11 +#define reg_pinmux_rw_iop_pa___pa12___lsb 12 +#define reg_pinmux_rw_iop_pa___pa12___width 1 +#define reg_pinmux_rw_iop_pa___pa12___bit 12 +#define reg_pinmux_rw_iop_pa___pa13___lsb 13 +#define reg_pinmux_rw_iop_pa___pa13___width 1 +#define reg_pinmux_rw_iop_pa___pa13___bit 13 +#define reg_pinmux_rw_iop_pa___pa14___lsb 14 +#define reg_pinmux_rw_iop_pa___pa14___width 1 +#define reg_pinmux_rw_iop_pa___pa14___bit 14 +#define reg_pinmux_rw_iop_pa___pa15___lsb 15 +#define reg_pinmux_rw_iop_pa___pa15___width 1 +#define reg_pinmux_rw_iop_pa___pa15___bit 15 +#define reg_pinmux_rw_iop_pa___pa16___lsb 16 +#define reg_pinmux_rw_iop_pa___pa16___width 1 +#define reg_pinmux_rw_iop_pa___pa16___bit 16 +#define reg_pinmux_rw_iop_pa___pa17___lsb 17 +#define reg_pinmux_rw_iop_pa___pa17___width 1 +#define reg_pinmux_rw_iop_pa___pa17___bit 17 +#define reg_pinmux_rw_iop_pa___pa18___lsb 18 +#define reg_pinmux_rw_iop_pa___pa18___width 1 +#define reg_pinmux_rw_iop_pa___pa18___bit 18 +#define reg_pinmux_rw_iop_pa___pa19___lsb 19 +#define reg_pinmux_rw_iop_pa___pa19___width 1 +#define reg_pinmux_rw_iop_pa___pa19___bit 19 +#define reg_pinmux_rw_iop_pa___pa20___lsb 20 +#define reg_pinmux_rw_iop_pa___pa20___width 1 +#define reg_pinmux_rw_iop_pa___pa20___bit 20 +#define reg_pinmux_rw_iop_pa___pa21___lsb 21 +#define reg_pinmux_rw_iop_pa___pa21___width 1 +#define reg_pinmux_rw_iop_pa___pa21___bit 21 +#define reg_pinmux_rw_iop_pa___pa22___lsb 22 +#define reg_pinmux_rw_iop_pa___pa22___width 1 +#define reg_pinmux_rw_iop_pa___pa22___bit 22 +#define reg_pinmux_rw_iop_pa___pa23___lsb 23 +#define reg_pinmux_rw_iop_pa___pa23___width 1 +#define reg_pinmux_rw_iop_pa___pa23___bit 23 +#define reg_pinmux_rw_iop_pa___pa24___lsb 24 +#define reg_pinmux_rw_iop_pa___pa24___width 1 +#define reg_pinmux_rw_iop_pa___pa24___bit 24 +#define reg_pinmux_rw_iop_pa___pa25___lsb 25 +#define reg_pinmux_rw_iop_pa___pa25___width 1 +#define reg_pinmux_rw_iop_pa___pa25___bit 25 +#define reg_pinmux_rw_iop_pa___pa26___lsb 26 +#define reg_pinmux_rw_iop_pa___pa26___width 1 +#define reg_pinmux_rw_iop_pa___pa26___bit 26 +#define reg_pinmux_rw_iop_pa___pa27___lsb 27 +#define reg_pinmux_rw_iop_pa___pa27___width 1 +#define reg_pinmux_rw_iop_pa___pa27___bit 27 +#define reg_pinmux_rw_iop_pa___pa28___lsb 28 +#define reg_pinmux_rw_iop_pa___pa28___width 1 +#define reg_pinmux_rw_iop_pa___pa28___bit 28 +#define reg_pinmux_rw_iop_pa___pa29___lsb 29 +#define reg_pinmux_rw_iop_pa___pa29___width 1 +#define reg_pinmux_rw_iop_pa___pa29___bit 29 +#define reg_pinmux_rw_iop_pa___pa30___lsb 30 +#define reg_pinmux_rw_iop_pa___pa30___width 1 +#define reg_pinmux_rw_iop_pa___pa30___bit 30 +#define reg_pinmux_rw_iop_pa___pa31___lsb 31 +#define reg_pinmux_rw_iop_pa___pa31___width 1 +#define reg_pinmux_rw_iop_pa___pa31___bit 31 +#define reg_pinmux_rw_iop_pa_offset 16 + +/* Register rw_iop_pb, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pb___pb0___lsb 0 +#define reg_pinmux_rw_iop_pb___pb0___width 1 +#define reg_pinmux_rw_iop_pb___pb0___bit 0 +#define reg_pinmux_rw_iop_pb___pb1___lsb 1 +#define reg_pinmux_rw_iop_pb___pb1___width 1 +#define reg_pinmux_rw_iop_pb___pb1___bit 1 +#define reg_pinmux_rw_iop_pb___pb2___lsb 2 +#define reg_pinmux_rw_iop_pb___pb2___width 1 +#define reg_pinmux_rw_iop_pb___pb2___bit 2 +#define reg_pinmux_rw_iop_pb___pb3___lsb 3 +#define reg_pinmux_rw_iop_pb___pb3___width 1 +#define reg_pinmux_rw_iop_pb___pb3___bit 3 +#define reg_pinmux_rw_iop_pb___pb4___lsb 4 +#define reg_pinmux_rw_iop_pb___pb4___width 1 +#define reg_pinmux_rw_iop_pb___pb4___bit 4 +#define reg_pinmux_rw_iop_pb___pb5___lsb 5 +#define reg_pinmux_rw_iop_pb___pb5___width 1 +#define reg_pinmux_rw_iop_pb___pb5___bit 5 +#define reg_pinmux_rw_iop_pb___pb6___lsb 6 +#define reg_pinmux_rw_iop_pb___pb6___width 1 +#define reg_pinmux_rw_iop_pb___pb6___bit 6 +#define reg_pinmux_rw_iop_pb___pb7___lsb 7 +#define reg_pinmux_rw_iop_pb___pb7___width 1 +#define reg_pinmux_rw_iop_pb___pb7___bit 7 +#define reg_pinmux_rw_iop_pb_offset 20 + +/* Register rw_iop_pio, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_pio___d0___lsb 0 +#define reg_pinmux_rw_iop_pio___d0___width 1 +#define reg_pinmux_rw_iop_pio___d0___bit 0 +#define reg_pinmux_rw_iop_pio___d1___lsb 1 +#define reg_pinmux_rw_iop_pio___d1___width 1 +#define reg_pinmux_rw_iop_pio___d1___bit 1 +#define reg_pinmux_rw_iop_pio___d2___lsb 2 +#define reg_pinmux_rw_iop_pio___d2___width 1 +#define reg_pinmux_rw_iop_pio___d2___bit 2 +#define reg_pinmux_rw_iop_pio___d3___lsb 3 +#define reg_pinmux_rw_iop_pio___d3___width 1 +#define reg_pinmux_rw_iop_pio___d3___bit 3 +#define reg_pinmux_rw_iop_pio___d4___lsb 4 +#define reg_pinmux_rw_iop_pio___d4___width 1 +#define reg_pinmux_rw_iop_pio___d4___bit 4 +#define reg_pinmux_rw_iop_pio___d5___lsb 5 +#define reg_pinmux_rw_iop_pio___d5___width 1 +#define reg_pinmux_rw_iop_pio___d5___bit 5 +#define reg_pinmux_rw_iop_pio___d6___lsb 6 +#define reg_pinmux_rw_iop_pio___d6___width 1 +#define reg_pinmux_rw_iop_pio___d6___bit 6 +#define reg_pinmux_rw_iop_pio___d7___lsb 7 +#define reg_pinmux_rw_iop_pio___d7___width 1 +#define reg_pinmux_rw_iop_pio___d7___bit 7 +#define reg_pinmux_rw_iop_pio___rd_n___lsb 8 +#define reg_pinmux_rw_iop_pio___rd_n___width 1 +#define reg_pinmux_rw_iop_pio___rd_n___bit 8 +#define reg_pinmux_rw_iop_pio___wr_n___lsb 9 +#define reg_pinmux_rw_iop_pio___wr_n___width 1 +#define reg_pinmux_rw_iop_pio___wr_n___bit 9 +#define reg_pinmux_rw_iop_pio___a0___lsb 10 +#define reg_pinmux_rw_iop_pio___a0___width 1 +#define reg_pinmux_rw_iop_pio___a0___bit 10 +#define reg_pinmux_rw_iop_pio___a1___lsb 11 +#define reg_pinmux_rw_iop_pio___a1___width 1 +#define reg_pinmux_rw_iop_pio___a1___bit 11 +#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12 +#define reg_pinmux_rw_iop_pio___ce0_n___width 1 +#define reg_pinmux_rw_iop_pio___ce0_n___bit 12 +#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13 +#define reg_pinmux_rw_iop_pio___ce1_n___width 1 +#define reg_pinmux_rw_iop_pio___ce1_n___bit 13 +#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14 +#define reg_pinmux_rw_iop_pio___ce2_n___width 1 +#define reg_pinmux_rw_iop_pio___ce2_n___bit 14 +#define reg_pinmux_rw_iop_pio___rdy___lsb 15 +#define reg_pinmux_rw_iop_pio___rdy___width 1 +#define reg_pinmux_rw_iop_pio___rdy___bit 15 +#define reg_pinmux_rw_iop_pio_offset 24 + +/* Register rw_iop_usb, scope pinmux, type rw */ +#define reg_pinmux_rw_iop_usb___usb0___lsb 0 +#define reg_pinmux_rw_iop_usb___usb0___width 1 +#define reg_pinmux_rw_iop_usb___usb0___bit 0 +#define reg_pinmux_rw_iop_usb_offset 28 + + +/* Constants */ +#define regk_pinmux_no 0x00000000 +#define regk_pinmux_rw_gio_pa_default 0x00000000 +#define regk_pinmux_rw_gio_pb_default 0x00000000 +#define regk_pinmux_rw_gio_pc_default 0x00000000 +#define regk_pinmux_rw_hwprot_default 0x00000000 +#define regk_pinmux_rw_iop_pa_default 0x00000000 +#define regk_pinmux_rw_iop_pb_default 0x00000000 +#define regk_pinmux_rw_iop_pio_default 0x00000000 +#define regk_pinmux_rw_iop_usb_default 0x00000001 +#define regk_pinmux_yes 0x00000001 +#endif /* __pinmux_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h new file mode 100644 index 000000000..3907ef492 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h @@ -0,0 +1,337 @@ +#ifndef __pio_defs_asm_h +#define __pio_defs_asm_h + +/* + * This file is autogenerated from + * file: pio.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_data, scope pio, type rw */ +#define reg_pio_rw_data_offset 64 + +/* Register rw_io_access0, scope pio, type rw */ +#define reg_pio_rw_io_access0___data___lsb 0 +#define reg_pio_rw_io_access0___data___width 8 +#define reg_pio_rw_io_access0_offset 0 + +/* Register rw_io_access1, scope pio, type rw */ +#define reg_pio_rw_io_access1___data___lsb 0 +#define reg_pio_rw_io_access1___data___width 8 +#define reg_pio_rw_io_access1_offset 4 + +/* Register rw_io_access2, scope pio, type rw */ +#define reg_pio_rw_io_access2___data___lsb 0 +#define reg_pio_rw_io_access2___data___width 8 +#define reg_pio_rw_io_access2_offset 8 + +/* Register rw_io_access3, scope pio, type rw */ +#define reg_pio_rw_io_access3___data___lsb 0 +#define reg_pio_rw_io_access3___data___width 8 +#define reg_pio_rw_io_access3_offset 12 + +/* Register rw_io_access4, scope pio, type rw */ +#define reg_pio_rw_io_access4___data___lsb 0 +#define reg_pio_rw_io_access4___data___width 8 +#define reg_pio_rw_io_access4_offset 16 + +/* Register rw_io_access5, scope pio, type rw */ +#define reg_pio_rw_io_access5___data___lsb 0 +#define reg_pio_rw_io_access5___data___width 8 +#define reg_pio_rw_io_access5_offset 20 + +/* Register rw_io_access6, scope pio, type rw */ +#define reg_pio_rw_io_access6___data___lsb 0 +#define reg_pio_rw_io_access6___data___width 8 +#define reg_pio_rw_io_access6_offset 24 + +/* Register rw_io_access7, scope pio, type rw */ +#define reg_pio_rw_io_access7___data___lsb 0 +#define reg_pio_rw_io_access7___data___width 8 +#define reg_pio_rw_io_access7_offset 28 + +/* Register rw_io_access8, scope pio, type rw */ +#define reg_pio_rw_io_access8___data___lsb 0 +#define reg_pio_rw_io_access8___data___width 8 +#define reg_pio_rw_io_access8_offset 32 + +/* Register rw_io_access9, scope pio, type rw */ +#define reg_pio_rw_io_access9___data___lsb 0 +#define reg_pio_rw_io_access9___data___width 8 +#define reg_pio_rw_io_access9_offset 36 + +/* Register rw_io_access10, scope pio, type rw */ +#define reg_pio_rw_io_access10___data___lsb 0 +#define reg_pio_rw_io_access10___data___width 8 +#define reg_pio_rw_io_access10_offset 40 + +/* Register rw_io_access11, scope pio, type rw */ +#define reg_pio_rw_io_access11___data___lsb 0 +#define reg_pio_rw_io_access11___data___width 8 +#define reg_pio_rw_io_access11_offset 44 + +/* Register rw_io_access12, scope pio, type rw */ +#define reg_pio_rw_io_access12___data___lsb 0 +#define reg_pio_rw_io_access12___data___width 8 +#define reg_pio_rw_io_access12_offset 48 + +/* Register rw_io_access13, scope pio, type rw */ +#define reg_pio_rw_io_access13___data___lsb 0 +#define reg_pio_rw_io_access13___data___width 8 +#define reg_pio_rw_io_access13_offset 52 + +/* Register rw_io_access14, scope pio, type rw */ +#define reg_pio_rw_io_access14___data___lsb 0 +#define reg_pio_rw_io_access14___data___width 8 +#define reg_pio_rw_io_access14_offset 56 + +/* Register rw_io_access15, scope pio, type rw */ +#define reg_pio_rw_io_access15___data___lsb 0 +#define reg_pio_rw_io_access15___data___width 8 +#define reg_pio_rw_io_access15_offset 60 + +/* Register rw_ce0_cfg, scope pio, type rw */ +#define reg_pio_rw_ce0_cfg___lw___lsb 0 +#define reg_pio_rw_ce0_cfg___lw___width 6 +#define reg_pio_rw_ce0_cfg___ew___lsb 6 +#define reg_pio_rw_ce0_cfg___ew___width 3 +#define reg_pio_rw_ce0_cfg___zw___lsb 9 +#define reg_pio_rw_ce0_cfg___zw___width 3 +#define reg_pio_rw_ce0_cfg___aw___lsb 12 +#define reg_pio_rw_ce0_cfg___aw___width 2 +#define reg_pio_rw_ce0_cfg___mode___lsb 14 +#define reg_pio_rw_ce0_cfg___mode___width 2 +#define reg_pio_rw_ce0_cfg_offset 68 + +/* Register rw_ce1_cfg, scope pio, type rw */ +#define reg_pio_rw_ce1_cfg___lw___lsb 0 +#define reg_pio_rw_ce1_cfg___lw___width 6 +#define reg_pio_rw_ce1_cfg___ew___lsb 6 +#define reg_pio_rw_ce1_cfg___ew___width 3 +#define reg_pio_rw_ce1_cfg___zw___lsb 9 +#define reg_pio_rw_ce1_cfg___zw___width 3 +#define reg_pio_rw_ce1_cfg___aw___lsb 12 +#define reg_pio_rw_ce1_cfg___aw___width 2 +#define reg_pio_rw_ce1_cfg___mode___lsb 14 +#define reg_pio_rw_ce1_cfg___mode___width 2 +#define reg_pio_rw_ce1_cfg_offset 72 + +/* Register rw_ce2_cfg, scope pio, type rw */ +#define reg_pio_rw_ce2_cfg___lw___lsb 0 +#define reg_pio_rw_ce2_cfg___lw___width 6 +#define reg_pio_rw_ce2_cfg___ew___lsb 6 +#define reg_pio_rw_ce2_cfg___ew___width 3 +#define reg_pio_rw_ce2_cfg___zw___lsb 9 +#define reg_pio_rw_ce2_cfg___zw___width 3 +#define reg_pio_rw_ce2_cfg___aw___lsb 12 +#define reg_pio_rw_ce2_cfg___aw___width 2 +#define reg_pio_rw_ce2_cfg___mode___lsb 14 +#define reg_pio_rw_ce2_cfg___mode___width 2 +#define reg_pio_rw_ce2_cfg_offset 76 + +/* Register rw_dout, scope pio, type rw */ +#define reg_pio_rw_dout___data___lsb 0 +#define reg_pio_rw_dout___data___width 8 +#define reg_pio_rw_dout___rd_n___lsb 8 +#define reg_pio_rw_dout___rd_n___width 1 +#define reg_pio_rw_dout___rd_n___bit 8 +#define reg_pio_rw_dout___wr_n___lsb 9 +#define reg_pio_rw_dout___wr_n___width 1 +#define reg_pio_rw_dout___wr_n___bit 9 +#define reg_pio_rw_dout___a0___lsb 10 +#define reg_pio_rw_dout___a0___width 1 +#define reg_pio_rw_dout___a0___bit 10 +#define reg_pio_rw_dout___a1___lsb 11 +#define reg_pio_rw_dout___a1___width 1 +#define reg_pio_rw_dout___a1___bit 11 +#define reg_pio_rw_dout___ce0_n___lsb 12 +#define reg_pio_rw_dout___ce0_n___width 1 +#define reg_pio_rw_dout___ce0_n___bit 12 +#define reg_pio_rw_dout___ce1_n___lsb 13 +#define reg_pio_rw_dout___ce1_n___width 1 +#define reg_pio_rw_dout___ce1_n___bit 13 +#define reg_pio_rw_dout___ce2_n___lsb 14 +#define reg_pio_rw_dout___ce2_n___width 1 +#define reg_pio_rw_dout___ce2_n___bit 14 +#define reg_pio_rw_dout___rdy___lsb 15 +#define reg_pio_rw_dout___rdy___width 1 +#define reg_pio_rw_dout___rdy___bit 15 +#define reg_pio_rw_dout_offset 80 + +/* Register rw_oe, scope pio, type rw */ +#define reg_pio_rw_oe___data___lsb 0 +#define reg_pio_rw_oe___data___width 8 +#define reg_pio_rw_oe___rd_n___lsb 8 +#define reg_pio_rw_oe___rd_n___width 1 +#define reg_pio_rw_oe___rd_n___bit 8 +#define reg_pio_rw_oe___wr_n___lsb 9 +#define reg_pio_rw_oe___wr_n___width 1 +#define reg_pio_rw_oe___wr_n___bit 9 +#define reg_pio_rw_oe___a0___lsb 10 +#define reg_pio_rw_oe___a0___width 1 +#define reg_pio_rw_oe___a0___bit 10 +#define reg_pio_rw_oe___a1___lsb 11 +#define reg_pio_rw_oe___a1___width 1 +#define reg_pio_rw_oe___a1___bit 11 +#define reg_pio_rw_oe___ce0_n___lsb 12 +#define reg_pio_rw_oe___ce0_n___width 1 +#define reg_pio_rw_oe___ce0_n___bit 12 +#define reg_pio_rw_oe___ce1_n___lsb 13 +#define reg_pio_rw_oe___ce1_n___width 1 +#define reg_pio_rw_oe___ce1_n___bit 13 +#define reg_pio_rw_oe___ce2_n___lsb 14 +#define reg_pio_rw_oe___ce2_n___width 1 +#define reg_pio_rw_oe___ce2_n___bit 14 +#define reg_pio_rw_oe___rdy___lsb 15 +#define reg_pio_rw_oe___rdy___width 1 +#define reg_pio_rw_oe___rdy___bit 15 +#define reg_pio_rw_oe_offset 84 + +/* Register rw_man_ctrl, scope pio, type rw */ +#define reg_pio_rw_man_ctrl___data___lsb 0 +#define reg_pio_rw_man_ctrl___data___width 8 +#define reg_pio_rw_man_ctrl___rd_n___lsb 8 +#define reg_pio_rw_man_ctrl___rd_n___width 1 +#define reg_pio_rw_man_ctrl___rd_n___bit 8 +#define reg_pio_rw_man_ctrl___wr_n___lsb 9 +#define reg_pio_rw_man_ctrl___wr_n___width 1 +#define reg_pio_rw_man_ctrl___wr_n___bit 9 +#define reg_pio_rw_man_ctrl___a0___lsb 10 +#define reg_pio_rw_man_ctrl___a0___width 1 +#define reg_pio_rw_man_ctrl___a0___bit 10 +#define reg_pio_rw_man_ctrl___a1___lsb 11 +#define reg_pio_rw_man_ctrl___a1___width 1 +#define reg_pio_rw_man_ctrl___a1___bit 11 +#define reg_pio_rw_man_ctrl___ce0_n___lsb 12 +#define reg_pio_rw_man_ctrl___ce0_n___width 1 +#define reg_pio_rw_man_ctrl___ce0_n___bit 12 +#define reg_pio_rw_man_ctrl___ce1_n___lsb 13 +#define reg_pio_rw_man_ctrl___ce1_n___width 1 +#define reg_pio_rw_man_ctrl___ce1_n___bit 13 +#define reg_pio_rw_man_ctrl___ce2_n___lsb 14 +#define reg_pio_rw_man_ctrl___ce2_n___width 1 +#define reg_pio_rw_man_ctrl___ce2_n___bit 14 +#define reg_pio_rw_man_ctrl___rdy___lsb 15 +#define reg_pio_rw_man_ctrl___rdy___width 1 +#define reg_pio_rw_man_ctrl___rdy___bit 15 +#define reg_pio_rw_man_ctrl_offset 88 + +/* Register r_din, scope pio, type r */ +#define reg_pio_r_din___data___lsb 0 +#define reg_pio_r_din___data___width 8 +#define reg_pio_r_din___rd_n___lsb 8 +#define reg_pio_r_din___rd_n___width 1 +#define reg_pio_r_din___rd_n___bit 8 +#define reg_pio_r_din___wr_n___lsb 9 +#define reg_pio_r_din___wr_n___width 1 +#define reg_pio_r_din___wr_n___bit 9 +#define reg_pio_r_din___a0___lsb 10 +#define reg_pio_r_din___a0___width 1 +#define reg_pio_r_din___a0___bit 10 +#define reg_pio_r_din___a1___lsb 11 +#define reg_pio_r_din___a1___width 1 +#define reg_pio_r_din___a1___bit 11 +#define reg_pio_r_din___ce0_n___lsb 12 +#define reg_pio_r_din___ce0_n___width 1 +#define reg_pio_r_din___ce0_n___bit 12 +#define reg_pio_r_din___ce1_n___lsb 13 +#define reg_pio_r_din___ce1_n___width 1 +#define reg_pio_r_din___ce1_n___bit 13 +#define reg_pio_r_din___ce2_n___lsb 14 +#define reg_pio_r_din___ce2_n___width 1 +#define reg_pio_r_din___ce2_n___bit 14 +#define reg_pio_r_din___rdy___lsb 15 +#define reg_pio_r_din___rdy___width 1 +#define reg_pio_r_din___rdy___bit 15 +#define reg_pio_r_din_offset 92 + +/* Register r_stat, scope pio, type r */ +#define reg_pio_r_stat___busy___lsb 0 +#define reg_pio_r_stat___busy___width 1 +#define reg_pio_r_stat___busy___bit 0 +#define reg_pio_r_stat_offset 96 + +/* Register rw_intr_mask, scope pio, type rw */ +#define reg_pio_rw_intr_mask___rdy___lsb 0 +#define reg_pio_rw_intr_mask___rdy___width 1 +#define reg_pio_rw_intr_mask___rdy___bit 0 +#define reg_pio_rw_intr_mask_offset 100 + +/* Register rw_ack_intr, scope pio, type rw */ +#define reg_pio_rw_ack_intr___rdy___lsb 0 +#define reg_pio_rw_ack_intr___rdy___width 1 +#define reg_pio_rw_ack_intr___rdy___bit 0 +#define reg_pio_rw_ack_intr_offset 104 + +/* Register r_intr, scope pio, type r */ +#define reg_pio_r_intr___rdy___lsb 0 +#define reg_pio_r_intr___rdy___width 1 +#define reg_pio_r_intr___rdy___bit 0 +#define reg_pio_r_intr_offset 108 + +/* Register r_masked_intr, scope pio, type r */ +#define reg_pio_r_masked_intr___rdy___lsb 0 +#define reg_pio_r_masked_intr___rdy___width 1 +#define reg_pio_r_masked_intr___rdy___bit 0 +#define reg_pio_r_masked_intr_offset 112 + + +/* Constants */ +#define regk_pio_a2 0x00000003 +#define regk_pio_no 0x00000000 +#define regk_pio_normal 0x00000000 +#define regk_pio_rd 0x00000001 +#define regk_pio_rw_ce0_cfg_default 0x00000000 +#define regk_pio_rw_ce1_cfg_default 0x00000000 +#define regk_pio_rw_ce2_cfg_default 0x00000000 +#define regk_pio_rw_intr_mask_default 0x00000000 +#define regk_pio_rw_man_ctrl_default 0x00000000 +#define regk_pio_rw_oe_default 0x00000000 +#define regk_pio_wr 0x00000002 +#define regk_pio_wr_ce2 0x00000003 +#define regk_pio_yes 0x00000001 +#define regk_pio_yes_all 0x000000ff +#endif /* __pio_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h new file mode 100644 index 000000000..89439e961 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h @@ -0,0 +1,99 @@ +#ifndef __reg_map_asm_h +#define __reg_map_asm_h + +/* + * This file is autogenerated from + * file: reg.rmap + * + * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +#define regi_ccd 0xb0000000 +#define regi_ccd_top 0xb0000000 +#define regi_ccd_dp 0xb0000400 +#define regi_ccd_stat 0xb0000800 +#define regi_ccd_tg 0xb0001000 +#define regi_cfg 0xb0002000 +#define regi_clkgen 0xb0004000 +#define regi_ddr2_ctrl 0xb0006000 +#define regi_dma0 0xb0008000 +#define regi_dma1 0xb000a000 +#define regi_dma11 0xb000c000 +#define regi_dma2 0xb000e000 +#define regi_dma3 0xb0010000 +#define regi_dma4 0xb0012000 +#define regi_dma5 0xb0014000 +#define regi_dma6 0xb0016000 +#define regi_dma7 0xb0018000 +#define regi_dma9 0xb001a000 +#define regi_eth 0xb001c000 +#define regi_gio 0xb0020000 +#define regi_h264 0xb0022000 +#define regi_hist 0xb0026000 +#define regi_iop 0xb0028000 +#define regi_iop_version 0xb0028000 +#define regi_iop_fifo_in_extra 0xb0028040 +#define regi_iop_fifo_out_extra 0xb0028080 +#define regi_iop_trigger_grp0 0xb00280c0 +#define regi_iop_trigger_grp1 0xb0028100 +#define regi_iop_trigger_grp2 0xb0028140 +#define regi_iop_trigger_grp3 0xb0028180 +#define regi_iop_trigger_grp4 0xb00281c0 +#define regi_iop_trigger_grp5 0xb0028200 +#define regi_iop_trigger_grp6 0xb0028240 +#define regi_iop_trigger_grp7 0xb0028280 +#define regi_iop_crc_par 0xb0028300 +#define regi_iop_dmc_in 0xb0028380 +#define regi_iop_dmc_out 0xb0028400 +#define regi_iop_fifo_in 0xb0028480 +#define regi_iop_fifo_out 0xb0028500 +#define regi_iop_scrc_in 0xb0028580 +#define regi_iop_scrc_out 0xb0028600 +#define regi_iop_timer_grp0 0xb0028680 +#define regi_iop_timer_grp1 0xb0028700 +#define regi_iop_sap_in 0xb0028800 +#define regi_iop_sap_out 0xb0028900 +#define regi_iop_spu 0xb0028a00 +#define regi_iop_sw_cfg 0xb0028b00 +#define regi_iop_sw_cpu 0xb0028c00 +#define regi_iop_sw_mpu 0xb0028d00 +#define regi_iop_sw_spu 0xb0028e00 +#define regi_iop_mpu 0xb0029000 +#define regi_irq 0xb002a000 +#define regi_jpeg 0xb002c000 +#define regi_l2cache 0xb0030000 +#define regi_marb_bar 0xb0032000 +#define regi_marb_bar_bp0 0xb0032140 +#define regi_marb_bar_bp1 0xb0032180 +#define regi_marb_bar_bp2 0xb00321c0 +#define regi_marb_bar_bp3 0xb0032200 +#define regi_marb_foo 0xb0034000 +#define regi_marb_foo_bp0 0xb0034280 +#define regi_marb_foo_bp1 0xb00342c0 +#define regi_marb_foo_bp2 0xb0034300 +#define regi_marb_foo_bp3 0xb0034340 +#define regi_pinmux 0xb0038000 +#define regi_pio 0xb0036000 +#define regi_sclr 0xb003a000 +#define regi_sclr_fifo 0xb003c000 +#define regi_ser0 0xb003e000 +#define regi_ser1 0xb0040000 +#define regi_ser2 0xb0042000 +#define regi_ser3 0xb0044000 +#define regi_ser4 0xb0046000 +#define regi_sser 0xb0048000 +#define regi_strcop 0xb004a000 +#define regi_strdma0 0xb004e000 +#define regi_strdma1 0xb0050000 +#define regi_strdma2 0xb0052000 +#define regi_strdma3 0xb0054000 +#define regi_strdma5 0xb0056000 +#define regi_strmux 0xb004c000 +#define regi_timer0 0xb0058000 +#define regi_timer1 0xb005a000 +#define regi_trace 0xb005c000 +#define regi_vin 0xb005e000 +#define regi_vout 0xb0060000 +#endif /* __reg_map_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000..b129e826f --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,228 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: timer.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_f90 0x00000003 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_vclk 0x00000002 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h new file mode 100644 index 000000000..c1e9ba93b --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h @@ -0,0 +1,159 @@ +#ifndef __clkgen_defs_h +#define __clkgen_defs_h + +/* + * This file is autogenerated from + * file: clkgen.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope clkgen */ + +/* Register r_bootsel, scope clkgen, type r */ +typedef struct { + unsigned int boot_mode : 5; + unsigned int intern_main_clk : 1; + unsigned int extern_usb2_clk : 1; + unsigned int dummy1 : 25; +} reg_clkgen_r_bootsel; +#define REG_RD_ADDR_clkgen_r_bootsel 0 + +/* Register rw_clk_ctrl, scope clkgen, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop_usb : 1; + unsigned int vin : 1; + unsigned int sclr : 1; + unsigned int h264 : 1; + unsigned int ddr2 : 1; + unsigned int vout_hist : 1; + unsigned int eth : 1; + unsigned int ccd_tg_200 : 1; + unsigned int dma0_1_eth : 1; + unsigned int ccd_tg_100 : 1; + unsigned int jpeg : 1; + unsigned int sser_ser_dma6_7 : 1; + unsigned int strdma0_2_video : 1; + unsigned int dma2_3_strcop : 1; + unsigned int dma4_5_iop : 1; + unsigned int dma9_11 : 1; + unsigned int memarb_bar_ddr : 1; + unsigned int sclr_h264 : 1; + unsigned int dummy1 : 12; +} reg_clkgen_rw_clk_ctrl; +#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4 +#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4 + + +/* Constants */ +enum { + regk_clkgen_eth1000_rx = 0x0000000c, + regk_clkgen_eth1000_tx = 0x0000000e, + regk_clkgen_eth100_rx = 0x0000001d, + regk_clkgen_eth100_rx_half = 0x0000001c, + regk_clkgen_eth100_tx = 0x0000001f, + regk_clkgen_eth100_tx_half = 0x0000001e, + regk_clkgen_nand_3_2 = 0x00000000, + regk_clkgen_nand_3_2_0x30 = 0x00000002, + regk_clkgen_nand_3_2_0x30_pll = 0x00000012, + regk_clkgen_nand_3_2_pll = 0x00000010, + regk_clkgen_nand_3_3 = 0x00000001, + regk_clkgen_nand_3_3_0x30 = 0x00000003, + regk_clkgen_nand_3_3_0x30_pll = 0x00000013, + regk_clkgen_nand_3_3_pll = 0x00000011, + regk_clkgen_nand_4_2 = 0x00000004, + regk_clkgen_nand_4_2_0x30 = 0x00000006, + regk_clkgen_nand_4_2_0x30_pll = 0x00000016, + regk_clkgen_nand_4_2_pll = 0x00000014, + regk_clkgen_nand_4_3 = 0x00000005, + regk_clkgen_nand_4_3_0x30 = 0x00000007, + regk_clkgen_nand_4_3_0x30_pll = 0x00000017, + regk_clkgen_nand_4_3_pll = 0x00000015, + regk_clkgen_nand_5_2 = 0x00000008, + regk_clkgen_nand_5_2_0x30 = 0x0000000a, + regk_clkgen_nand_5_2_0x30_pll = 0x0000001a, + regk_clkgen_nand_5_2_pll = 0x00000018, + regk_clkgen_nand_5_3 = 0x00000009, + regk_clkgen_nand_5_3_0x30 = 0x0000000b, + regk_clkgen_nand_5_3_0x30_pll = 0x0000001b, + regk_clkgen_nand_5_3_pll = 0x00000019, + regk_clkgen_no = 0x00000000, + regk_clkgen_rw_clk_ctrl_default = 0x00000002, + regk_clkgen_ser = 0x0000000d, + regk_clkgen_ser_pll = 0x0000000f, + regk_clkgen_yes = 0x00000001 +}; +#endif /* __clkgen_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h new file mode 100644 index 000000000..0f30e8bf9 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h @@ -0,0 +1,281 @@ +#ifndef __ddr2_defs_h +#define __ddr2_defs_h + +/* + * This file is autogenerated from + * file: ddr2.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope ddr2 */ + +/* Register rw_cfg, scope ddr2, type rw */ +typedef struct { + unsigned int col_width : 4; + unsigned int nr_banks : 1; + unsigned int bw : 1; + unsigned int nr_ref : 4; + unsigned int ref_interval : 11; + unsigned int odt_ctrl : 2; + unsigned int odt_mem : 1; + unsigned int imp_strength : 1; + unsigned int auto_imp_cal : 1; + unsigned int imp_cal_override : 1; + unsigned int dll_override : 1; + unsigned int dummy1 : 4; +} reg_ddr2_rw_cfg; +#define REG_RD_ADDR_ddr2_rw_cfg 0 +#define REG_WR_ADDR_ddr2_rw_cfg 0 + +/* Register rw_timing, scope ddr2, type rw */ +typedef struct { + unsigned int wr : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int ras : 4; + unsigned int rfc : 7; + unsigned int rc : 5; + unsigned int rtp : 2; + unsigned int rtw : 3; + unsigned int wtr : 2; +} reg_ddr2_rw_timing; +#define REG_RD_ADDR_ddr2_rw_timing 4 +#define REG_WR_ADDR_ddr2_rw_timing 4 + +/* Register rw_latency, scope ddr2, type rw */ +typedef struct { + unsigned int cas : 3; + unsigned int additive : 3; + unsigned int dummy1 : 26; +} reg_ddr2_rw_latency; +#define REG_RD_ADDR_ddr2_rw_latency 8 +#define REG_WR_ADDR_ddr2_rw_latency 8 + +/* Register rw_phy_cfg, scope ddr2, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_ddr2_rw_phy_cfg; +#define REG_RD_ADDR_ddr2_rw_phy_cfg 12 +#define REG_WR_ADDR_ddr2_rw_phy_cfg 12 + +/* Register rw_phy_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int rst : 1; + unsigned int cal_rst : 1; + unsigned int cal_start : 1; + unsigned int dummy1 : 29; +} reg_ddr2_rw_phy_ctrl; +#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 +#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 + +/* Register rw_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int mrs_data : 16; + unsigned int cmd : 8; + unsigned int dummy1 : 8; +} reg_ddr2_rw_ctrl; +#define REG_RD_ADDR_ddr2_rw_ctrl 20 +#define REG_WR_ADDR_ddr2_rw_ctrl 20 + +/* Register rw_pwr_down, scope ddr2, type rw */ +typedef struct { + unsigned int self_ref : 2; + unsigned int phy_en : 1; + unsigned int dummy1 : 29; +} reg_ddr2_rw_pwr_down; +#define REG_RD_ADDR_ddr2_rw_pwr_down 24 +#define REG_WR_ADDR_ddr2_rw_pwr_down 24 + +/* Register r_stat, scope ddr2, type r */ +typedef struct { + unsigned int dll_lock : 1; + unsigned int dll_delay_code : 7; + unsigned int imp_cal_done : 1; + unsigned int imp_cal_fault : 1; + unsigned int cal_imp_pu : 4; + unsigned int cal_imp_pd : 4; + unsigned int dummy1 : 14; +} reg_ddr2_r_stat; +#define REG_RD_ADDR_ddr2_r_stat 28 + +/* Register rw_imp_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int imp_pu : 4; + unsigned int imp_pd : 4; + unsigned int dummy1 : 24; +} reg_ddr2_rw_imp_ctrl; +#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 +#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 + +#define STRIDE_ddr2_rw_dll_ctrl 4 +/* Register rw_dll_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int mode : 1; + unsigned int clk_delay : 7; + unsigned int dummy1 : 24; +} reg_ddr2_rw_dll_ctrl; +#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 +#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 + +#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 +/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ +typedef struct { + unsigned int dqs90_delay : 7; + unsigned int dqs180_delay : 7; + unsigned int dqs270_delay : 7; + unsigned int dqs360_delay : 7; + unsigned int dummy1 : 4; +} reg_ddr2_rw_dqs_dll_ctrl; +#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 +#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 + + +/* Constants */ +enum { + regk_ddr2_al0 = 0x00000000, + regk_ddr2_al1 = 0x00000008, + regk_ddr2_al2 = 0x00000010, + regk_ddr2_al3 = 0x00000018, + regk_ddr2_al4 = 0x00000020, + regk_ddr2_auto = 0x00000003, + regk_ddr2_bank4 = 0x00000000, + regk_ddr2_bank8 = 0x00000001, + regk_ddr2_bl4 = 0x00000002, + regk_ddr2_bl8 = 0x00000003, + regk_ddr2_bt_il = 0x00000008, + regk_ddr2_bt_seq = 0x00000000, + regk_ddr2_bw16 = 0x00000001, + regk_ddr2_bw32 = 0x00000000, + regk_ddr2_cas2 = 0x00000020, + regk_ddr2_cas3 = 0x00000030, + regk_ddr2_cas4 = 0x00000040, + regk_ddr2_cas5 = 0x00000050, + regk_ddr2_deselect = 0x000000c0, + regk_ddr2_dic_weak = 0x00000002, + regk_ddr2_direct = 0x00000001, + regk_ddr2_dis = 0x00000000, + regk_ddr2_dll_dis = 0x00000001, + regk_ddr2_dll_en = 0x00000000, + regk_ddr2_dll_rst = 0x00000100, + regk_ddr2_emrs = 0x00000081, + regk_ddr2_emrs2 = 0x00000082, + regk_ddr2_emrs3 = 0x00000083, + regk_ddr2_full = 0x00000001, + regk_ddr2_hi_ref_rate = 0x00000080, + regk_ddr2_mrs = 0x00000080, + regk_ddr2_no = 0x00000000, + regk_ddr2_nop = 0x000000b8, + regk_ddr2_ocd_adj = 0x00000200, + regk_ddr2_ocd_default = 0x00000380, + regk_ddr2_ocd_drive0 = 0x00000100, + regk_ddr2_ocd_drive1 = 0x00000080, + regk_ddr2_ocd_exit = 0x00000000, + regk_ddr2_odt_dis = 0x00000000, + regk_ddr2_offs = 0x00000000, + regk_ddr2_pre = 0x00000090, + regk_ddr2_pre_all = 0x00000400, + regk_ddr2_pwr_down_fast = 0x00000000, + regk_ddr2_pwr_down_slow = 0x00001000, + regk_ddr2_ref = 0x00000088, + regk_ddr2_rtt150 = 0x00000040, + regk_ddr2_rtt50 = 0x00000044, + regk_ddr2_rtt75 = 0x00000004, + regk_ddr2_rw_cfg_default = 0x00186000, + regk_ddr2_rw_dll_ctrl_default = 0x00000000, + regk_ddr2_rw_dll_ctrl_size = 0x00000004, + regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, + regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, + regk_ddr2_rw_latency_default = 0x00000000, + regk_ddr2_rw_phy_cfg_default = 0x00000000, + regk_ddr2_rw_pwr_down_default = 0x00000000, + regk_ddr2_rw_timing_default = 0x00000000, + regk_ddr2_s1Gb = 0x0000001a, + regk_ddr2_s256Mb = 0x0000000f, + regk_ddr2_s2Gb = 0x00000027, + regk_ddr2_s4Gb = 0x00000042, + regk_ddr2_s512Mb = 0x00000015, + regk_ddr2_temp0_85 = 0x00000618, + regk_ddr2_temp85_95 = 0x0000030c, + regk_ddr2_term150 = 0x00000002, + regk_ddr2_term50 = 0x00000003, + regk_ddr2_term75 = 0x00000001, + regk_ddr2_test = 0x00000080, + regk_ddr2_weak = 0x00000000, + regk_ddr2_wr2 = 0x00000200, + regk_ddr2_wr3 = 0x00000400, + regk_ddr2_yes = 0x00000001 +}; +#endif /* __ddr2_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h new file mode 100644 index 000000000..5d88e0db2 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h @@ -0,0 +1,837 @@ +#ifndef __gio_defs_h +#define __gio_defs_h + +/* + * This file is autogenerated from + * file: gio.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope gio */ + +/* Register r_pa_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pa_din; +#define REG_RD_ADDR_gio_r_pa_din 0 + +/* Register rw_pa_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 32; +} reg_gio_rw_pa_dout; +#define REG_RD_ADDR_gio_rw_pa_dout 4 +#define REG_WR_ADDR_gio_rw_pa_dout 4 + +/* Register rw_pa_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 32; +} reg_gio_rw_pa_oe; +#define REG_RD_ADDR_gio_rw_pa_oe 8 +#define REG_WR_ADDR_gio_rw_pa_oe 8 + +/* Register rw_pa_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte0_dout; +#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 +#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 + +/* Register rw_pa_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte0_oe; +#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 +#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 + +/* Register rw_pa_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte1_dout; +#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 +#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 + +/* Register rw_pa_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte1_oe; +#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 +#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 + +/* Register rw_pa_byte2_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte2_dout; +#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 +#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 + +/* Register rw_pa_byte2_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte2_oe; +#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 +#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 + +/* Register rw_pa_byte3_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte3_dout; +#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 +#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 + +/* Register rw_pa_byte3_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_byte3_oe; +#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 +#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 + +/* Register r_pb_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pb_din; +#define REG_RD_ADDR_gio_r_pb_din 44 + +/* Register rw_pb_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 32; +} reg_gio_rw_pb_dout; +#define REG_RD_ADDR_gio_rw_pb_dout 48 +#define REG_WR_ADDR_gio_rw_pb_dout 48 + +/* Register rw_pb_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 32; +} reg_gio_rw_pb_oe; +#define REG_RD_ADDR_gio_rw_pb_oe 52 +#define REG_WR_ADDR_gio_rw_pb_oe 52 + +/* Register rw_pb_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte0_dout; +#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 +#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 + +/* Register rw_pb_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte0_oe; +#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 +#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 + +/* Register rw_pb_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte1_dout; +#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 +#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 + +/* Register rw_pb_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte1_oe; +#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 +#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 + +/* Register rw_pb_byte2_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte2_dout; +#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 +#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 + +/* Register rw_pb_byte2_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte2_oe; +#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 +#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 + +/* Register rw_pb_byte3_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte3_dout; +#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 +#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 + +/* Register rw_pb_byte3_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pb_byte3_oe; +#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 +#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 + +/* Register r_pc_din, scope gio, type r */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_gio_r_pc_din; +#define REG_RD_ADDR_gio_r_pc_din 88 + +/* Register rw_pc_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 16; + unsigned int dummy1 : 16; +} reg_gio_rw_pc_dout; +#define REG_RD_ADDR_gio_rw_pc_dout 92 +#define REG_WR_ADDR_gio_rw_pc_dout 92 + +/* Register rw_pc_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 16; + unsigned int dummy1 : 16; +} reg_gio_rw_pc_oe; +#define REG_RD_ADDR_gio_rw_pc_oe 96 +#define REG_WR_ADDR_gio_rw_pc_oe 96 + +/* Register rw_pc_byte0_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte0_dout; +#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 +#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 + +/* Register rw_pc_byte0_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte0_oe; +#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 +#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 + +/* Register rw_pc_byte1_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte1_dout; +#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 +#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 + +/* Register rw_pc_byte1_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pc_byte1_oe; +#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 +#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 + +/* Register r_pd_din, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pd_din; +#define REG_RD_ADDR_gio_r_pd_din 116 + +/* Register rw_intr_cfg, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 3; + unsigned int intr1 : 3; + unsigned int intr2 : 3; + unsigned int intr3 : 3; + unsigned int intr4 : 3; + unsigned int intr5 : 3; + unsigned int intr6 : 3; + unsigned int intr7 : 3; + unsigned int dummy1 : 8; +} reg_gio_rw_intr_cfg; +#define REG_RD_ADDR_gio_rw_intr_cfg 120 +#define REG_WR_ADDR_gio_rw_intr_cfg 120 + +/* Register rw_intr_pins, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 4; + unsigned int intr1 : 4; + unsigned int intr2 : 4; + unsigned int intr3 : 4; + unsigned int intr4 : 4; + unsigned int intr5 : 4; + unsigned int intr6 : 4; + unsigned int intr7 : 4; +} reg_gio_rw_intr_pins; +#define REG_RD_ADDR_gio_rw_intr_pins 124 +#define REG_WR_ADDR_gio_rw_intr_pins 124 + +/* Register rw_intr_mask, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_rw_intr_mask; +#define REG_RD_ADDR_gio_rw_intr_mask 128 +#define REG_WR_ADDR_gio_rw_intr_mask 128 + +/* Register rw_ack_intr, scope gio, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_rw_ack_intr; +#define REG_RD_ADDR_gio_rw_ack_intr 132 +#define REG_WR_ADDR_gio_rw_ack_intr 132 + +/* Register r_intr, scope gio, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_r_intr; +#define REG_RD_ADDR_gio_r_intr 136 + +/* Register r_masked_intr, scope gio, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int i2c0_done : 1; + unsigned int i2c1_done : 1; + unsigned int dummy1 : 22; +} reg_gio_r_masked_intr; +#define REG_RD_ADDR_gio_r_masked_intr 140 + +/* Register rw_i2c0_start, scope gio, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_gio_rw_i2c0_start; +#define REG_RD_ADDR_gio_rw_i2c0_start 144 +#define REG_WR_ADDR_gio_rw_i2c0_start 144 + +/* Register rw_i2c0_cfg, scope gio, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int bit_order : 1; + unsigned int scl_io : 1; + unsigned int scl_inv : 1; + unsigned int sda_io : 1; + unsigned int sda_idle : 1; + unsigned int dummy1 : 26; +} reg_gio_rw_i2c0_cfg; +#define REG_RD_ADDR_gio_rw_i2c0_cfg 148 +#define REG_WR_ADDR_gio_rw_i2c0_cfg 148 + +/* Register rw_i2c0_ctrl, scope gio, type rw */ +typedef struct { + unsigned int trf_bits : 6; + unsigned int switch_dir : 6; + unsigned int extra_start : 3; + unsigned int early_end : 1; + unsigned int start_stop : 1; + unsigned int ack_dir0 : 1; + unsigned int ack_dir1 : 1; + unsigned int ack_dir2 : 1; + unsigned int ack_dir3 : 1; + unsigned int ack_dir4 : 1; + unsigned int ack_dir5 : 1; + unsigned int ack_bit : 1; + unsigned int start_bit : 1; + unsigned int freq : 2; + unsigned int dummy1 : 5; +} reg_gio_rw_i2c0_ctrl; +#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 +#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 + +/* Register rw_i2c0_data, scope gio, type rw */ +typedef struct { + unsigned int data0 : 8; + unsigned int data1 : 8; + unsigned int data2 : 8; + unsigned int data3 : 8; +} reg_gio_rw_i2c0_data; +#define REG_RD_ADDR_gio_rw_i2c0_data 156 +#define REG_WR_ADDR_gio_rw_i2c0_data 156 + +/* Register rw_i2c0_data2, scope gio, type rw */ +typedef struct { + unsigned int data4 : 8; + unsigned int data5 : 8; + unsigned int start_val : 6; + unsigned int ack_val : 6; + unsigned int dummy1 : 4; +} reg_gio_rw_i2c0_data2; +#define REG_RD_ADDR_gio_rw_i2c0_data2 160 +#define REG_WR_ADDR_gio_rw_i2c0_data2 160 + +/* Register rw_i2c1_start, scope gio, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_gio_rw_i2c1_start; +#define REG_RD_ADDR_gio_rw_i2c1_start 164 +#define REG_WR_ADDR_gio_rw_i2c1_start 164 + +/* Register rw_i2c1_cfg, scope gio, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int bit_order : 1; + unsigned int scl_io : 1; + unsigned int scl_inv : 1; + unsigned int sda0_io : 1; + unsigned int sda0_idle : 1; + unsigned int sda1_io : 1; + unsigned int sda1_idle : 1; + unsigned int sda2_io : 1; + unsigned int sda2_idle : 1; + unsigned int sda3_io : 1; + unsigned int sda3_idle : 1; + unsigned int sda_sel : 2; + unsigned int sen_idle : 1; + unsigned int sen_inv : 1; + unsigned int sen_sel : 2; + unsigned int dummy1 : 14; +} reg_gio_rw_i2c1_cfg; +#define REG_RD_ADDR_gio_rw_i2c1_cfg 168 +#define REG_WR_ADDR_gio_rw_i2c1_cfg 168 + +/* Register rw_i2c1_ctrl, scope gio, type rw */ +typedef struct { + unsigned int trf_bits : 6; + unsigned int switch_dir : 6; + unsigned int extra_start : 3; + unsigned int early_end : 1; + unsigned int start_stop : 1; + unsigned int ack_dir0 : 1; + unsigned int ack_dir1 : 1; + unsigned int ack_dir2 : 1; + unsigned int ack_dir3 : 1; + unsigned int ack_dir4 : 1; + unsigned int ack_dir5 : 1; + unsigned int ack_bit : 1; + unsigned int start_bit : 1; + unsigned int freq : 2; + unsigned int dummy1 : 5; +} reg_gio_rw_i2c1_ctrl; +#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 +#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 + +/* Register rw_i2c1_data, scope gio, type rw */ +typedef struct { + unsigned int data0 : 8; + unsigned int data1 : 8; + unsigned int data2 : 8; + unsigned int data3 : 8; +} reg_gio_rw_i2c1_data; +#define REG_RD_ADDR_gio_rw_i2c1_data 176 +#define REG_WR_ADDR_gio_rw_i2c1_data 176 + +/* Register rw_i2c1_data2, scope gio, type rw */ +typedef struct { + unsigned int data4 : 8; + unsigned int data5 : 8; + unsigned int start_val : 6; + unsigned int ack_val : 6; + unsigned int dummy1 : 4; +} reg_gio_rw_i2c1_data2; +#define REG_RD_ADDR_gio_rw_i2c1_data2 180 +#define REG_WR_ADDR_gio_rw_i2c1_data2 180 + +/* Register r_ppwm_stat, scope gio, type r */ +typedef struct { + unsigned int freq : 2; + unsigned int dummy1 : 30; +} reg_gio_r_ppwm_stat; +#define REG_RD_ADDR_gio_r_ppwm_stat 184 + +/* Register rw_ppwm_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_ppwm_data; +#define REG_RD_ADDR_gio_rw_ppwm_data 188 +#define REG_WR_ADDR_gio_rw_ppwm_data 188 + +/* Register rw_pwm0_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm0_ctrl; +#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 +#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 + +/* Register rw_pwm0_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm0_var; +#define REG_RD_ADDR_gio_rw_pwm0_var 196 +#define REG_WR_ADDR_gio_rw_pwm0_var 196 + +/* Register rw_pwm0_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm0_data; +#define REG_RD_ADDR_gio_rw_pwm0_data 200 +#define REG_WR_ADDR_gio_rw_pwm0_data 200 + +/* Register rw_pwm1_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm1_ctrl; +#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 +#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 + +/* Register rw_pwm1_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm1_var; +#define REG_RD_ADDR_gio_rw_pwm1_var 208 +#define REG_WR_ADDR_gio_rw_pwm1_var 208 + +/* Register rw_pwm1_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm1_data; +#define REG_RD_ADDR_gio_rw_pwm1_data 212 +#define REG_WR_ADDR_gio_rw_pwm1_data 212 + +/* Register rw_pwm2_ctrl, scope gio, type rw */ +typedef struct { + unsigned int mode : 2; + unsigned int ccd_override : 1; + unsigned int ccd_val : 1; + unsigned int dummy1 : 28; +} reg_gio_rw_pwm2_ctrl; +#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 +#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 + +/* Register rw_pwm2_var, scope gio, type rw */ +typedef struct { + unsigned int lo : 13; + unsigned int hi : 13; + unsigned int dummy1 : 6; +} reg_gio_rw_pwm2_var; +#define REG_RD_ADDR_gio_rw_pwm2_var 220 +#define REG_WR_ADDR_gio_rw_pwm2_var 220 + +/* Register rw_pwm2_data, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pwm2_data; +#define REG_RD_ADDR_gio_rw_pwm2_data 224 +#define REG_WR_ADDR_gio_rw_pwm2_data 224 + +/* Register rw_pwm_in_cfg, scope gio, type rw */ +typedef struct { + unsigned int pin : 3; + unsigned int dummy1 : 29; +} reg_gio_rw_pwm_in_cfg; +#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 +#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 + +/* Register r_pwm_in_lo, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_lo; +#define REG_RD_ADDR_gio_r_pwm_in_lo 232 + +/* Register r_pwm_in_hi, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_hi; +#define REG_RD_ADDR_gio_r_pwm_in_hi 236 + +/* Register r_pwm_in_cnt, scope gio, type r */ +typedef struct { + unsigned int data : 32; +} reg_gio_r_pwm_in_cnt; +#define REG_RD_ADDR_gio_r_pwm_in_cnt 240 + + +/* Constants */ +enum { + regk_gio_anyedge = 0x00000007, + regk_gio_f100k = 0x00000000, + regk_gio_f1562 = 0x00000000, + regk_gio_f195 = 0x00000003, + regk_gio_f1m = 0x00000002, + regk_gio_f390 = 0x00000002, + regk_gio_f400k = 0x00000001, + regk_gio_f5m = 0x00000003, + regk_gio_f781 = 0x00000001, + regk_gio_hi = 0x00000001, + regk_gio_in = 0x00000000, + regk_gio_intr_pa0 = 0x00000000, + regk_gio_intr_pa1 = 0x00000000, + regk_gio_intr_pa10 = 0x00000001, + regk_gio_intr_pa11 = 0x00000001, + regk_gio_intr_pa12 = 0x00000001, + regk_gio_intr_pa13 = 0x00000001, + regk_gio_intr_pa14 = 0x00000001, + regk_gio_intr_pa15 = 0x00000001, + regk_gio_intr_pa16 = 0x00000002, + regk_gio_intr_pa17 = 0x00000002, + regk_gio_intr_pa18 = 0x00000002, + regk_gio_intr_pa19 = 0x00000002, + regk_gio_intr_pa2 = 0x00000000, + regk_gio_intr_pa20 = 0x00000002, + regk_gio_intr_pa21 = 0x00000002, + regk_gio_intr_pa22 = 0x00000002, + regk_gio_intr_pa23 = 0x00000002, + regk_gio_intr_pa24 = 0x00000003, + regk_gio_intr_pa25 = 0x00000003, + regk_gio_intr_pa26 = 0x00000003, + regk_gio_intr_pa27 = 0x00000003, + regk_gio_intr_pa28 = 0x00000003, + regk_gio_intr_pa29 = 0x00000003, + regk_gio_intr_pa3 = 0x00000000, + regk_gio_intr_pa30 = 0x00000003, + regk_gio_intr_pa31 = 0x00000003, + regk_gio_intr_pa4 = 0x00000000, + regk_gio_intr_pa5 = 0x00000000, + regk_gio_intr_pa6 = 0x00000000, + regk_gio_intr_pa7 = 0x00000000, + regk_gio_intr_pa8 = 0x00000001, + regk_gio_intr_pa9 = 0x00000001, + regk_gio_intr_pb0 = 0x00000004, + regk_gio_intr_pb1 = 0x00000004, + regk_gio_intr_pb10 = 0x00000005, + regk_gio_intr_pb11 = 0x00000005, + regk_gio_intr_pb12 = 0x00000005, + regk_gio_intr_pb13 = 0x00000005, + regk_gio_intr_pb14 = 0x00000005, + regk_gio_intr_pb15 = 0x00000005, + regk_gio_intr_pb16 = 0x00000006, + regk_gio_intr_pb17 = 0x00000006, + regk_gio_intr_pb18 = 0x00000006, + regk_gio_intr_pb19 = 0x00000006, + regk_gio_intr_pb2 = 0x00000004, + regk_gio_intr_pb20 = 0x00000006, + regk_gio_intr_pb21 = 0x00000006, + regk_gio_intr_pb22 = 0x00000006, + regk_gio_intr_pb23 = 0x00000006, + regk_gio_intr_pb24 = 0x00000007, + regk_gio_intr_pb25 = 0x00000007, + regk_gio_intr_pb26 = 0x00000007, + regk_gio_intr_pb27 = 0x00000007, + regk_gio_intr_pb28 = 0x00000007, + regk_gio_intr_pb29 = 0x00000007, + regk_gio_intr_pb3 = 0x00000004, + regk_gio_intr_pb30 = 0x00000007, + regk_gio_intr_pb31 = 0x00000007, + regk_gio_intr_pb4 = 0x00000004, + regk_gio_intr_pb5 = 0x00000004, + regk_gio_intr_pb6 = 0x00000004, + regk_gio_intr_pb7 = 0x00000004, + regk_gio_intr_pb8 = 0x00000005, + regk_gio_intr_pb9 = 0x00000005, + regk_gio_intr_pc0 = 0x00000008, + regk_gio_intr_pc1 = 0x00000008, + regk_gio_intr_pc10 = 0x00000009, + regk_gio_intr_pc11 = 0x00000009, + regk_gio_intr_pc12 = 0x00000009, + regk_gio_intr_pc13 = 0x00000009, + regk_gio_intr_pc14 = 0x00000009, + regk_gio_intr_pc15 = 0x00000009, + regk_gio_intr_pc2 = 0x00000008, + regk_gio_intr_pc3 = 0x00000008, + regk_gio_intr_pc4 = 0x00000008, + regk_gio_intr_pc5 = 0x00000008, + regk_gio_intr_pc6 = 0x00000008, + regk_gio_intr_pc7 = 0x00000008, + regk_gio_intr_pc8 = 0x00000009, + regk_gio_intr_pc9 = 0x00000009, + regk_gio_intr_pd0 = 0x0000000c, + regk_gio_intr_pd1 = 0x0000000c, + regk_gio_intr_pd10 = 0x0000000d, + regk_gio_intr_pd11 = 0x0000000d, + regk_gio_intr_pd12 = 0x0000000d, + regk_gio_intr_pd13 = 0x0000000d, + regk_gio_intr_pd14 = 0x0000000d, + regk_gio_intr_pd15 = 0x0000000d, + regk_gio_intr_pd16 = 0x0000000e, + regk_gio_intr_pd17 = 0x0000000e, + regk_gio_intr_pd18 = 0x0000000e, + regk_gio_intr_pd19 = 0x0000000e, + regk_gio_intr_pd2 = 0x0000000c, + regk_gio_intr_pd20 = 0x0000000e, + regk_gio_intr_pd21 = 0x0000000e, + regk_gio_intr_pd22 = 0x0000000e, + regk_gio_intr_pd23 = 0x0000000e, + regk_gio_intr_pd24 = 0x0000000f, + regk_gio_intr_pd25 = 0x0000000f, + regk_gio_intr_pd26 = 0x0000000f, + regk_gio_intr_pd27 = 0x0000000f, + regk_gio_intr_pd28 = 0x0000000f, + regk_gio_intr_pd29 = 0x0000000f, + regk_gio_intr_pd3 = 0x0000000c, + regk_gio_intr_pd30 = 0x0000000f, + regk_gio_intr_pd31 = 0x0000000f, + regk_gio_intr_pd4 = 0x0000000c, + regk_gio_intr_pd5 = 0x0000000c, + regk_gio_intr_pd6 = 0x0000000c, + regk_gio_intr_pd7 = 0x0000000c, + regk_gio_intr_pd8 = 0x0000000d, + regk_gio_intr_pd9 = 0x0000000d, + regk_gio_lo = 0x00000002, + regk_gio_lsb = 0x00000000, + regk_gio_msb = 0x00000001, + regk_gio_negedge = 0x00000006, + regk_gio_no = 0x00000000, + regk_gio_no_switch = 0x0000003f, + regk_gio_none = 0x00000007, + regk_gio_off = 0x00000000, + regk_gio_opendrain = 0x00000000, + regk_gio_out = 0x00000001, + regk_gio_posedge = 0x00000005, + regk_gio_pwm_hfp = 0x00000002, + regk_gio_pwm_pa0 = 0x00000001, + regk_gio_pwm_pa19 = 0x00000004, + regk_gio_pwm_pa6 = 0x00000002, + regk_gio_pwm_pa7 = 0x00000003, + regk_gio_pwm_pb26 = 0x00000005, + regk_gio_pwm_pd23 = 0x00000006, + regk_gio_pwm_pd31 = 0x00000007, + regk_gio_pwm_std = 0x00000001, + regk_gio_pwm_var = 0x00000003, + regk_gio_rw_i2c0_cfg_default = 0x00000020, + regk_gio_rw_i2c0_ctrl_default = 0x00010000, + regk_gio_rw_i2c0_start_default = 0x00000000, + regk_gio_rw_i2c1_cfg_default = 0x00000aa0, + regk_gio_rw_i2c1_ctrl_default = 0x00010000, + regk_gio_rw_i2c1_start_default = 0x00000000, + regk_gio_rw_intr_cfg_default = 0x00000000, + regk_gio_rw_intr_mask_default = 0x00000000, + regk_gio_rw_pa_oe_default = 0x00000000, + regk_gio_rw_pb_oe_default = 0x00000000, + regk_gio_rw_pc_oe_default = 0x00000000, + regk_gio_rw_ppwm_data_default = 0x00000000, + regk_gio_rw_pwm0_ctrl_default = 0x00000000, + regk_gio_rw_pwm1_ctrl_default = 0x00000000, + regk_gio_rw_pwm2_ctrl_default = 0x00000000, + regk_gio_rw_pwm_in_cfg_default = 0x00000000, + regk_gio_sda0 = 0x00000000, + regk_gio_sda1 = 0x00000001, + regk_gio_sda2 = 0x00000002, + regk_gio_sda3 = 0x00000003, + regk_gio_sen = 0x00000000, + regk_gio_set = 0x00000003, + regk_gio_yes = 0x00000001 +}; +#endif /* __gio_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h new file mode 100644 index 000000000..bea699aa4 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h @@ -0,0 +1,46 @@ +/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr + from intr_vect.r */ + +#ifndef _INTR_VECT_R +#define _INTR_VECT_R +#define TIMER0_INTR_VECT 0x31 +#define TIMER1_INTR_VECT 0x32 +#define DMA0_INTR_VECT 0x33 +#define DMA1_INTR_VECT 0x34 +#define DMA2_INTR_VECT 0x35 +#define DMA3_INTR_VECT 0x36 +#define DMA4_INTR_VECT 0x37 +#define DMA5_INTR_VECT 0x38 +#define DMA6_INTR_VECT 0x39 +#define DMA7_INTR_VECT 0x3a +#define DMA9_INTR_VECT 0x3b +#define DMA11_INTR_VECT 0x3c +#define GIO_INTR_VECT 0x3d +#define IOP0_INTR_VECT 0x3e +#define IOP1_INTR_VECT 0x3f +#define SER0_INTR_VECT 0x40 +#define SER1_INTR_VECT 0x41 +#define SER2_INTR_VECT 0x42 +#define SER3_INTR_VECT 0x43 +#define SER4_INTR_VECT 0x44 +#define SSER_INTR_VECT 0x45 +#define STRDMA0_INTR_VECT 0x46 +#define STRDMA1_INTR_VECT 0x47 +#define STRDMA2_INTR_VECT 0x48 +#define STRDMA3_INTR_VECT 0x49 +#define STRDMA5_INTR_VECT 0x4a +#define VIN_INTR_VECT 0x4b +#define VOUT_INTR_VECT 0x4c +#define JPEG_INTR_VECT 0x4d +#define H264_INTR_VECT 0x4e +#define HISTO_INTR_VECT 0x4f +#define CCD_INTR_VECT 0x50 +#define ETH_INTR_VECT 0x51 +#define MEMARB_BAR_INTR_VECT 0x52 +#define MEMARB_FOO_INTR_VECT 0x53 +#define PIO_INTR_VECT 0x54 +#define SCLR_INTR_VECT 0x55 +#define SCLR_FIFO_INTR_VECT 0x56 +#define IPI_INTR_VECT 0x57 +#define NBR_INTR_VECT 0x58 +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h new file mode 100644 index 000000000..b820f6347 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h @@ -0,0 +1,341 @@ +#ifndef __intr_vect_defs_h +#define __intr_vect_defs_h + +/* + * This file is autogenerated from + * file: intr_vect.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope intr_vect */ + + +#define STRIDE_intr_vect_rw_mask 4 +/* Register rw_mask0, scope intr_vect, type rw */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_rw_mask0; +#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0 +#define REG_RD_ADDR_intr_vect_rw_mask 0 +#define REG_WR_ADDR_intr_vect_rw_mask 0 +#define REG_RD_ADDR_intr_vect_rw_mask0 0 +#define REG_WR_ADDR_intr_vect_rw_mask0 0 + +#define STRIDE_intr_vect_r_vect 4 +/* Register r_vect0, scope intr_vect, type r */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_r_vect0; +#define reg_intr_vect_r_vect reg_intr_vect_r_vect0 +#define REG_RD_ADDR_intr_vect_r_vect 8 +#define REG_RD_ADDR_intr_vect_r_vect0 8 + +#define STRIDE_intr_vect_r_masked_vect 4 +/* Register r_masked_vect0, scope intr_vect, type r */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_r_masked_vect0; +#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0 +#define REG_RD_ADDR_intr_vect_r_masked_vect0 16 +#define REG_RD_ADDR_intr_vect_r_masked_vect 16 + +#define STRIDE_intr_vect_rw_xmask 4 +/* Register rw_xmask0, scope intr_vect, type rw */ +typedef struct { + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int gio : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int strdma0 : 1; + unsigned int strdma1 : 1; + unsigned int strdma2 : 1; + unsigned int strdma3 : 1; + unsigned int strdma5 : 1; + unsigned int vin : 1; + unsigned int vout : 1; + unsigned int jpeg : 1; + unsigned int h264 : 1; + unsigned int histo : 1; + unsigned int ccd : 1; +} reg_intr_vect_rw_xmask0; +#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0 +#define REG_RD_ADDR_intr_vect_rw_xmask0 24 +#define REG_WR_ADDR_intr_vect_rw_xmask0 24 +#define REG_RD_ADDR_intr_vect_rw_xmask 24 +#define REG_WR_ADDR_intr_vect_rw_xmask 24 + +/* Register rw_mask1, scope intr_vect, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_rw_mask1; +#define REG_RD_ADDR_intr_vect_rw_mask1 4 +#define REG_WR_ADDR_intr_vect_rw_mask1 4 + +/* Register r_vect1, scope intr_vect, type r */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_r_vect1; +#define REG_RD_ADDR_intr_vect_r_vect1 12 + +/* Register r_masked_vect1, scope intr_vect, type r */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_r_masked_vect1; +#define REG_RD_ADDR_intr_vect_r_masked_vect1 20 + +/* Register rw_xmask1, scope intr_vect, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int memarb_bar : 1; + unsigned int memarb_foo : 1; + unsigned int pio : 1; + unsigned int sclr : 1; + unsigned int sclr_fifo : 1; + unsigned int dummy1 : 26; +} reg_intr_vect_rw_xmask1; +#define REG_RD_ADDR_intr_vect_rw_xmask1 28 +#define REG_WR_ADDR_intr_vect_rw_xmask1 28 + +/* Register rw_xmask_ctrl, scope intr_vect, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_rw_xmask_ctrl; +#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32 +#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32 + +/* Register r_nmi, scope intr_vect, type r */ +typedef struct { + unsigned int watchdog0 : 1; + unsigned int watchdog1 : 1; + unsigned int dummy1 : 30; +} reg_intr_vect_r_nmi; +#define REG_RD_ADDR_intr_vect_r_nmi 64 + +/* Register r_guru, scope intr_vect, type r */ +typedef struct { + unsigned int jtag : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_r_guru; +#define REG_RD_ADDR_intr_vect_r_guru 68 + + +/* Register rw_ipi, scope intr_vect, type rw */ +typedef struct +{ + unsigned int vector; +} reg_intr_vect_rw_ipi; +#define REG_RD_ADDR_intr_vect_rw_ipi 72 +#define REG_WR_ADDR_intr_vect_rw_ipi 72 + +/* Constants */ +enum { + regk_intr_vect_no = 0x00000000, + regk_intr_vect_rw_mask0_default = 0x00000000, + regk_intr_vect_rw_mask1_default = 0x00000000, + regk_intr_vect_rw_xmask0_default = 0x00000000, + regk_intr_vect_rw_xmask1_default = 0x00000000, + regk_intr_vect_rw_xmask_ctrl_default = 0x00000000, + regk_intr_vect_yes = 0x00000001 +}; +#endif /* __intr_vect_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h new file mode 100644 index 000000000..d75a74e90 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h @@ -0,0 +1,31 @@ +/* Autogenerated Changes here will be lost! + * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg + */ +#define iop_version 0 +#define iop_fifo_in_extra 64 +#define iop_fifo_out_extra 128 +#define iop_trigger_grp0 192 +#define iop_trigger_grp1 256 +#define iop_trigger_grp2 320 +#define iop_trigger_grp3 384 +#define iop_trigger_grp4 448 +#define iop_trigger_grp5 512 +#define iop_trigger_grp6 576 +#define iop_trigger_grp7 640 +#define iop_crc_par 768 +#define iop_dmc_in 896 +#define iop_dmc_out 1024 +#define iop_fifo_in 1152 +#define iop_fifo_out 1280 +#define iop_scrc_in 1408 +#define iop_scrc_out 1536 +#define iop_timer_grp0 1664 +#define iop_timer_grp1 1792 +#define iop_sap_in 2048 +#define iop_sap_out 2304 +#define iop_spu 2560 +#define iop_sw_cfg 2816 +#define iop_sw_cpu 3072 +#define iop_sw_mpu 3328 +#define iop_sw_spu 3584 +#define iop_mpu 4096 diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h new file mode 100644 index 000000000..7f90b5a04 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h @@ -0,0 +1,109 @@ +#ifndef __iop_sap_in_defs_asm_h +#define __iop_sap_in_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sap_in.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +#define STRIDE_iop_sap_in_rw_bus_byte 4 +/* Register rw_bus_byte, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 +#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 +#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 +#define reg_iop_sap_in_rw_bus_byte___delay___width 2 +#define reg_iop_sap_in_rw_bus_byte_offset 0 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 +#define reg_iop_sap_in_rw_gio___sync_sel___width 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 +#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 +#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 +#define reg_iop_sap_in_rw_gio___sync_edge___width 2 +#define reg_iop_sap_in_rw_gio___delay___lsb 7 +#define reg_iop_sap_in_rw_gio___delay___width 2 +#define reg_iop_sap_in_rw_gio___logic___lsb 9 +#define reg_iop_sap_in_rw_gio___logic___width 2 +#define reg_iop_sap_in_rw_gio_offset 16 + + +/* Constants */ +#define regk_iop_sap_in_and 0x00000002 +#define regk_iop_sap_in_ext_clk200 0x00000003 +#define regk_iop_sap_in_gio0 0x00000000 +#define regk_iop_sap_in_gio12 0x00000003 +#define regk_iop_sap_in_gio16 0x00000004 +#define regk_iop_sap_in_gio20 0x00000005 +#define regk_iop_sap_in_gio24 0x00000006 +#define regk_iop_sap_in_gio28 0x00000007 +#define regk_iop_sap_in_gio4 0x00000001 +#define regk_iop_sap_in_gio8 0x00000002 +#define regk_iop_sap_in_inv 0x00000001 +#define regk_iop_sap_in_neg 0x00000002 +#define regk_iop_sap_in_no 0x00000000 +#define regk_iop_sap_in_no_del_ext_clk200 0x00000002 +#define regk_iop_sap_in_none 0x00000000 +#define regk_iop_sap_in_one 0x00000001 +#define regk_iop_sap_in_or 0x00000003 +#define regk_iop_sap_in_pos 0x00000001 +#define regk_iop_sap_in_pos_neg 0x00000003 +#define regk_iop_sap_in_rw_bus_byte_default 0x00000000 +#define regk_iop_sap_in_rw_bus_byte_size 0x00000004 +#define regk_iop_sap_in_rw_gio_default 0x00000000 +#define regk_iop_sap_in_rw_gio_size 0x00000020 +#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 +#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 +#define regk_iop_sap_in_tmr_clk200 0x00000001 +#define regk_iop_sap_in_two 0x00000002 +#define regk_iop_sap_in_two_clk200 0x00000000 +#endif /* __iop_sap_in_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h new file mode 100644 index 000000000..399bd6564 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __iop_sap_out_defs_asm_h +#define __iop_sap_out_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sap_out.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 +#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 +#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 +#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 +#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 +#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 +#define reg_iop_sap_out_rw_gen_gated_offset 0 + +/* Register rw_bus, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 +#define reg_iop_sap_out_rw_bus___byte0_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 +#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 +#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 +#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 +#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 +#define reg_iop_sap_out_rw_bus___byte1_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 +#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 +#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 +#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 +#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 +#define reg_iop_sap_out_rw_bus___byte2_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 +#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 +#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 +#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 +#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 +#define reg_iop_sap_out_rw_bus___byte3_delay___width 1 +#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 +#define reg_iop_sap_out_rw_bus_offset 4 + +/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 +#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 +#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_lo_oe_offset 8 + +/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 +#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 +#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 +#define reg_iop_sap_out_rw_bus_hi_oe_offset 12 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 +#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 +#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 +#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 +#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 +#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 +#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 +#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 +#define reg_iop_sap_out_rw_gio___out_delay___lsb 7 +#define reg_iop_sap_out_rw_gio___out_delay___width 1 +#define reg_iop_sap_out_rw_gio___out_delay___bit 7 +#define reg_iop_sap_out_rw_gio___out_logic___lsb 8 +#define reg_iop_sap_out_rw_gio___out_logic___width 2 +#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 +#define reg_iop_sap_out_rw_gio___out_logic_src___width 2 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 +#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 +#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 +#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 +#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 +#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 +#define reg_iop_sap_out_rw_gio___oe_delay___width 1 +#define reg_iop_sap_out_rw_gio___oe_delay___bit 19 +#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 +#define reg_iop_sap_out_rw_gio___oe_logic___width 2 +#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 +#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 +#define reg_iop_sap_out_rw_gio_offset 16 + + +/* Constants */ +#define regk_iop_sap_out_always 0x00000001 +#define regk_iop_sap_out_and 0x00000002 +#define regk_iop_sap_out_clk0 0x00000000 +#define regk_iop_sap_out_clk1 0x00000001 +#define regk_iop_sap_out_clk12 0x00000004 +#define regk_iop_sap_out_clk200 0x00000000 +#define regk_iop_sap_out_ext 0x00000002 +#define regk_iop_sap_out_gated 0x00000003 +#define regk_iop_sap_out_gio0 0x00000000 +#define regk_iop_sap_out_gio1 0x00000000 +#define regk_iop_sap_out_gio16 0x00000002 +#define regk_iop_sap_out_gio17 0x00000002 +#define regk_iop_sap_out_gio24 0x00000003 +#define regk_iop_sap_out_gio25 0x00000003 +#define regk_iop_sap_out_gio8 0x00000001 +#define regk_iop_sap_out_gio9 0x00000001 +#define regk_iop_sap_out_gio_out10 0x00000005 +#define regk_iop_sap_out_gio_out18 0x00000006 +#define regk_iop_sap_out_gio_out2 0x00000004 +#define regk_iop_sap_out_gio_out26 0x00000007 +#define regk_iop_sap_out_inv 0x00000001 +#define regk_iop_sap_out_nand 0x00000003 +#define regk_iop_sap_out_no 0x00000000 +#define regk_iop_sap_out_none 0x00000000 +#define regk_iop_sap_out_one 0x00000001 +#define regk_iop_sap_out_rw_bus_default 0x00000000 +#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 +#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 +#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 +#define regk_iop_sap_out_rw_gio_default 0x00000000 +#define regk_iop_sap_out_rw_gio_size 0x00000020 +#define regk_iop_sap_out_spu_gio6 0x00000002 +#define regk_iop_sap_out_spu_gio7 0x00000003 +#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 +#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 +#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 +#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 +#define regk_iop_sap_out_tmr200 0x00000001 +#define regk_iop_sap_out_yes 0x00000001 +#endif /* __iop_sap_out_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h new file mode 100644 index 000000000..3b3949b51 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h @@ -0,0 +1,739 @@ +#ifndef __iop_sw_cfg_defs_asm_h +#define __iop_sw_cfg_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_cfg.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 + +/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 + +/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 + +/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 + +/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 + +/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 + +/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 + +/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 + +/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 + +/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 +#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 +#define reg_iop_sw_cfg_rw_spu_owner_offset 44 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 +#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 + +/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 +#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 +#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 +#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 +#define reg_iop_sw_cfg_rw_bus_mask_offset 88 + +/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 +#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 +#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_mask_offset 96 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 +#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 +#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 +#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 +#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 +#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 +#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 +#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 +#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 +#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 +#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 +#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 +#define reg_iop_sw_cfg_rw_pinmapping_offset 104 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 +#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 +#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 +#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 + +/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 +#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 +#define reg_iop_sw_cfg_rw_spu_cfg_offset 144 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 +#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 +#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 + +/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 +#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 +#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 +#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 +#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 +#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 + + +/* Constants */ +#define regk_iop_sw_cfg_a 0x00000001 +#define regk_iop_sw_cfg_b 0x00000002 +#define regk_iop_sw_cfg_bus 0x00000000 +#define regk_iop_sw_cfg_bus_rot16 0x00000002 +#define regk_iop_sw_cfg_bus_rot24 0x00000003 +#define regk_iop_sw_cfg_bus_rot8 0x00000001 +#define regk_iop_sw_cfg_clk12 0x00000000 +#define regk_iop_sw_cfg_cpu 0x00000000 +#define regk_iop_sw_cfg_gated_clk0 0x0000000e +#define regk_iop_sw_cfg_gated_clk1 0x0000000f +#define regk_iop_sw_cfg_gio0 0x00000004 +#define regk_iop_sw_cfg_gio1 0x00000001 +#define regk_iop_sw_cfg_gio2 0x00000005 +#define regk_iop_sw_cfg_gio3 0x00000002 +#define regk_iop_sw_cfg_gio4 0x00000006 +#define regk_iop_sw_cfg_gio5 0x00000003 +#define regk_iop_sw_cfg_gio6 0x00000007 +#define regk_iop_sw_cfg_gio7 0x00000004 +#define regk_iop_sw_cfg_gio_in18 0x00000002 +#define regk_iop_sw_cfg_gio_in19 0x00000003 +#define regk_iop_sw_cfg_gio_in20 0x00000004 +#define regk_iop_sw_cfg_gio_in21 0x00000005 +#define regk_iop_sw_cfg_gio_in26 0x00000006 +#define regk_iop_sw_cfg_gio_in27 0x00000007 +#define regk_iop_sw_cfg_gio_in4 0x00000000 +#define regk_iop_sw_cfg_gio_in5 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 +#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 +#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 +#define regk_iop_sw_cfg_mpu 0x00000001 +#define regk_iop_sw_cfg_none 0x00000000 +#define regk_iop_sw_cfg_pdp_out 0x00000001 +#define regk_iop_sw_cfg_pdp_out_hi 0x00000001 +#define regk_iop_sw_cfg_pdp_out_lo 0x00000000 +#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 +#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 +#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 +#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 +#define regk_iop_sw_cfg_sdp_out 0x00000004 +#define regk_iop_sw_cfg_size16 0x00000002 +#define regk_iop_sw_cfg_size24 0x00000003 +#define regk_iop_sw_cfg_size32 0x00000004 +#define regk_iop_sw_cfg_size8 0x00000001 +#define regk_iop_sw_cfg_spu 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 +#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 +#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 +#define regk_iop_sw_cfg_spu_g0 0x00000007 +#define regk_iop_sw_cfg_spu_g1 0x00000007 +#define regk_iop_sw_cfg_spu_g2 0x00000007 +#define regk_iop_sw_cfg_spu_g3 0x00000007 +#define regk_iop_sw_cfg_spu_g4 0x00000007 +#define regk_iop_sw_cfg_spu_g5 0x00000007 +#define regk_iop_sw_cfg_spu_g6 0x00000007 +#define regk_iop_sw_cfg_spu_g7 0x00000007 +#define regk_iop_sw_cfg_spu_gio0 0x00000000 +#define regk_iop_sw_cfg_spu_gio1 0x00000001 +#define regk_iop_sw_cfg_spu_gio5 0x00000005 +#define regk_iop_sw_cfg_spu_gio6 0x00000006 +#define regk_iop_sw_cfg_spu_gio7 0x00000007 +#define regk_iop_sw_cfg_spu_gio_out0 0x00000008 +#define regk_iop_sw_cfg_spu_gio_out1 0x00000009 +#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a +#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b +#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c +#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d +#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e +#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f +#define regk_iop_sw_cfg_spu_gioout0 0x00000000 +#define regk_iop_sw_cfg_spu_gioout1 0x00000000 +#define regk_iop_sw_cfg_spu_gioout10 0x00000007 +#define regk_iop_sw_cfg_spu_gioout11 0x00000007 +#define regk_iop_sw_cfg_spu_gioout12 0x00000007 +#define regk_iop_sw_cfg_spu_gioout13 0x00000007 +#define regk_iop_sw_cfg_spu_gioout14 0x00000007 +#define regk_iop_sw_cfg_spu_gioout15 0x00000007 +#define regk_iop_sw_cfg_spu_gioout16 0x00000007 +#define regk_iop_sw_cfg_spu_gioout17 0x00000007 +#define regk_iop_sw_cfg_spu_gioout18 0x00000007 +#define regk_iop_sw_cfg_spu_gioout19 0x00000007 +#define regk_iop_sw_cfg_spu_gioout2 0x00000001 +#define regk_iop_sw_cfg_spu_gioout20 0x00000007 +#define regk_iop_sw_cfg_spu_gioout21 0x00000007 +#define regk_iop_sw_cfg_spu_gioout22 0x00000007 +#define regk_iop_sw_cfg_spu_gioout23 0x00000007 +#define regk_iop_sw_cfg_spu_gioout24 0x00000007 +#define regk_iop_sw_cfg_spu_gioout25 0x00000007 +#define regk_iop_sw_cfg_spu_gioout26 0x00000007 +#define regk_iop_sw_cfg_spu_gioout27 0x00000007 +#define regk_iop_sw_cfg_spu_gioout28 0x00000007 +#define regk_iop_sw_cfg_spu_gioout29 0x00000007 +#define regk_iop_sw_cfg_spu_gioout3 0x00000001 +#define regk_iop_sw_cfg_spu_gioout30 0x00000007 +#define regk_iop_sw_cfg_spu_gioout31 0x00000007 +#define regk_iop_sw_cfg_spu_gioout4 0x00000002 +#define regk_iop_sw_cfg_spu_gioout5 0x00000002 +#define regk_iop_sw_cfg_spu_gioout6 0x00000003 +#define regk_iop_sw_cfg_spu_gioout7 0x00000003 +#define regk_iop_sw_cfg_spu_gioout8 0x00000007 +#define regk_iop_sw_cfg_spu_gioout9 0x00000007 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 +#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 +#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 +#define regk_iop_sw_cfg_timer_grp0 0x00000000 +#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 +#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 +#define regk_iop_sw_cfg_timer_grp1 0x00000000 +#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 +#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 +#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 +#define regk_iop_sw_cfg_trig0_0 0x00000000 +#define regk_iop_sw_cfg_trig0_1 0x00000000 +#define regk_iop_sw_cfg_trig0_2 0x00000000 +#define regk_iop_sw_cfg_trig0_3 0x00000000 +#define regk_iop_sw_cfg_trig1_0 0x00000000 +#define regk_iop_sw_cfg_trig1_1 0x00000000 +#define regk_iop_sw_cfg_trig1_2 0x00000000 +#define regk_iop_sw_cfg_trig1_3 0x00000000 +#define regk_iop_sw_cfg_trig2_0 0x00000001 +#define regk_iop_sw_cfg_trig2_1 0x00000001 +#define regk_iop_sw_cfg_trig2_2 0x00000001 +#define regk_iop_sw_cfg_trig2_3 0x00000001 +#define regk_iop_sw_cfg_trig3_0 0x00000001 +#define regk_iop_sw_cfg_trig3_1 0x00000001 +#define regk_iop_sw_cfg_trig3_2 0x00000001 +#define regk_iop_sw_cfg_trig3_3 0x00000001 +#define regk_iop_sw_cfg_trig4_0 0x00000002 +#define regk_iop_sw_cfg_trig4_1 0x00000002 +#define regk_iop_sw_cfg_trig4_2 0x00000002 +#define regk_iop_sw_cfg_trig4_3 0x00000002 +#define regk_iop_sw_cfg_trig5_0 0x00000002 +#define regk_iop_sw_cfg_trig5_1 0x00000002 +#define regk_iop_sw_cfg_trig5_2 0x00000002 +#define regk_iop_sw_cfg_trig5_3 0x00000002 +#define regk_iop_sw_cfg_trig6_0 0x00000003 +#define regk_iop_sw_cfg_trig6_1 0x00000003 +#define regk_iop_sw_cfg_trig6_2 0x00000003 +#define regk_iop_sw_cfg_trig6_3 0x00000003 +#define regk_iop_sw_cfg_trig7_0 0x00000003 +#define regk_iop_sw_cfg_trig7_1 0x00000003 +#define regk_iop_sw_cfg_trig7_2 0x00000003 +#define regk_iop_sw_cfg_trig7_3 0x00000003 +#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h new file mode 100644 index 000000000..3f4fe1b31 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h @@ -0,0 +1,950 @@ +#ifndef __iop_sw_cpu_defs_asm_h +#define __iop_sw_cpu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_cpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_mpu_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mpu_trace_offset 0 + +/* Register r_spu_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_spu_trace_offset 4 + +/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_cpu_rw_mc_data___val___width 32 +#define reg_iop_sw_cpu_rw_mc_data_offset 16 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_mc_addr_offset 20 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +#define reg_iop_sw_cpu_rs_mc_data_offset 24 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_data_offset 28 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_cpu_r_mc_stat_offset 32 + +/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 + +/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 + +/* Register r_bus_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_bus_in_offset 52 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_gio_in_offset 72 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 +#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 +#define reg_iop_sw_cpu_rw_intr0_mask_offset 76 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_rw_ack_intr0_offset 80 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_r_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_r_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_r_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_r_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_r_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_r_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_r_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_r_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_r_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_r_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_r_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_r_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_r_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_r_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_r_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_r_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_r_intr0_offset 84 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 +#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 +#define reg_iop_sw_cpu_r_masked_intr0_offset 88 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 +#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 +#define reg_iop_sw_cpu_rw_intr1_mask_offset 92 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_rw_ack_intr1_offset 96 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 +#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 +#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 +#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 +#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 +#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 +#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 +#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 +#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 +#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_intr1_offset 100 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 +#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 +#define reg_iop_sw_cpu_r_masked_intr1_offset 104 + + +/* Constants */ +#define regk_iop_sw_cpu_copy 0x00000000 +#define regk_iop_sw_cpu_no 0x00000000 +#define regk_iop_sw_cpu_rd 0x00000002 +#define regk_iop_sw_cpu_reg_copy 0x00000001 +#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 +#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 +#define regk_iop_sw_cpu_wr 0x00000003 +#define regk_iop_sw_cpu_yes 0x00000001 +#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h new file mode 100644 index 000000000..ffcc83b22 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h @@ -0,0 +1,1086 @@ +#ifndef __iop_sw_mpu_defs_asm_h +#define __iop_sw_mpu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_mpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 +#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 +#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 + +/* Register r_spu_trace, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_spu_trace_offset 4 + +/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_mpu_rw_mc_data___val___width 32 +#define reg_iop_sw_mpu_rw_mc_data_offset 16 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_mc_addr_offset 20 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +#define reg_iop_sw_mpu_rs_mc_data_offset 24 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_data_offset 28 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_mpu_r_mc_stat_offset 32 + +/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 + +/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 + +/* Register r_bus_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_bus_in_offset 52 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_gio_in_offset 72 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_rw_cpu_intr_offset 76 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 +#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 +#define reg_iop_sw_mpu_r_cpu_intr_offset 80 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp0_offset 92 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp1_offset 108 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp2_offset 124 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 +#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 +#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 +#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_intr_grp3_offset 140 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 +#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 +#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 + + +/* Constants */ +#define regk_iop_sw_mpu_copy 0x00000000 +#define regk_iop_sw_mpu_cpu 0x00000000 +#define regk_iop_sw_mpu_mpu 0x00000001 +#define regk_iop_sw_mpu_no 0x00000000 +#define regk_iop_sw_mpu_nop 0x00000000 +#define regk_iop_sw_mpu_rd 0x00000002 +#define regk_iop_sw_mpu_reg_copy 0x00000001 +#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 +#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 +#define regk_iop_sw_mpu_set 0x00000001 +#define regk_iop_sw_mpu_spu 0x00000002 +#define regk_iop_sw_mpu_wr 0x00000003 +#define regk_iop_sw_mpu_yes 0x00000001 +#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h new file mode 100644 index 000000000..67a745338 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h @@ -0,0 +1,523 @@ +#ifndef __iop_sw_spu_defs_asm_h +#define __iop_sw_spu_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_sw_spu.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_mpu_trace, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_trace_offset 0 + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 +#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 +#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 +#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 +#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 +#define reg_iop_sw_spu_rw_mc_ctrl_offset 4 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 +#define reg_iop_sw_spu_rw_mc_data___val___width 32 +#define reg_iop_sw_spu_rw_mc_data_offset 8 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mc_addr_offset 12 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +#define reg_iop_sw_spu_rs_mc_data_offset 16 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_data_offset 20 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 +#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 +#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 +#define reg_iop_sw_spu_r_mc_stat_offset 24 + +/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 + +/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 +#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 +#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_offset 32 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 + +/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 +#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 +#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 + +/* Register r_bus_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_bus_in_offset 44 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_set_mask_offset 52 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_gio_in_offset 64 + +/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 + +/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 + +/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 + +/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 +#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 +#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_cpu_intr_offset 116 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_cpu_intr_offset 120 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 +#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 +#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 +#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 +#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 +#define reg_iop_sw_spu_r_hw_intr_offset 124 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_rw_mpu_intr_offset 128 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 +#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 +#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 +#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 +#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 +#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 +#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 +#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 +#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 +#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 +#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 +#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 +#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 +#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 +#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 +#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 +#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 +#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 +#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 +#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 +#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 +#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 +#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 +#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 +#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 +#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 +#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 +#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 +#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 +#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 +#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 +#define reg_iop_sw_spu_r_mpu_intr_offset 132 + + +/* Constants */ +#define regk_iop_sw_spu_copy 0x00000000 +#define regk_iop_sw_spu_no 0x00000000 +#define regk_iop_sw_spu_nop 0x00000000 +#define regk_iop_sw_spu_rd 0x00000002 +#define regk_iop_sw_spu_reg_copy 0x00000001 +#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 +#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 +#define regk_iop_sw_spu_set 0x00000001 +#define regk_iop_sw_spu_wr 0x00000003 +#define regk_iop_sw_spu_yes 0x00000001 +#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h new file mode 100644 index 000000000..4ad671202 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h @@ -0,0 +1,61 @@ +#ifndef __iop_version_defs_asm_h +#define __iop_version_defs_asm_h + +/* + * This file is autogenerated from + * file: iop_version.r + * + * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_version, scope iop_version, type r */ +#define reg_iop_version_r_version___nr___lsb 0 +#define reg_iop_version_r_version___nr___width 8 +#define reg_iop_version_r_version_offset 0 + + +/* Constants */ +#define regk_iop_version_v2_0 0x00000002 +#endif /* __iop_version_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h new file mode 100644 index 000000000..af3196c60 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h @@ -0,0 +1,31 @@ +/* Autogenerated Changes here will be lost! + * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg + */ +#define regi_iop_version (regi_iop + 0) +#define regi_iop_fifo_in_extra (regi_iop + 64) +#define regi_iop_fifo_out_extra (regi_iop + 128) +#define regi_iop_trigger_grp0 (regi_iop + 192) +#define regi_iop_trigger_grp1 (regi_iop + 256) +#define regi_iop_trigger_grp2 (regi_iop + 320) +#define regi_iop_trigger_grp3 (regi_iop + 384) +#define regi_iop_trigger_grp4 (regi_iop + 448) +#define regi_iop_trigger_grp5 (regi_iop + 512) +#define regi_iop_trigger_grp6 (regi_iop + 576) +#define regi_iop_trigger_grp7 (regi_iop + 640) +#define regi_iop_crc_par (regi_iop + 768) +#define regi_iop_dmc_in (regi_iop + 896) +#define regi_iop_dmc_out (regi_iop + 1024) +#define regi_iop_fifo_in (regi_iop + 1152) +#define regi_iop_fifo_out (regi_iop + 1280) +#define regi_iop_scrc_in (regi_iop + 1408) +#define regi_iop_scrc_out (regi_iop + 1536) +#define regi_iop_timer_grp0 (regi_iop + 1664) +#define regi_iop_timer_grp1 (regi_iop + 1792) +#define regi_iop_sap_in (regi_iop + 2048) +#define regi_iop_sap_out (regi_iop + 2304) +#define regi_iop_spu (regi_iop + 2560) +#define regi_iop_sw_cfg (regi_iop + 2816) +#define regi_iop_sw_cpu (regi_iop + 3072) +#define regi_iop_sw_mpu (regi_iop + 3328) +#define regi_iop_sw_spu (regi_iop + 3584) +#define regi_iop_mpu (regi_iop + 4096) diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h new file mode 100644 index 000000000..51dde016c --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h @@ -0,0 +1,141 @@ +#ifndef __iop_sap_in_defs_h +#define __iop_sap_in_defs_h + +/* + * This file is autogenerated from + * file: iop_sap_in.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_in */ + +#define STRIDE_iop_sap_in_rw_bus_byte 4 +/* Register rw_bus_byte, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 2; + unsigned int dummy1 : 23; +} reg_iop_sap_in_rw_bus_byte; +#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 +#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 + +#define STRIDE_iop_sap_in_rw_gio 4 +/* Register rw_gio, scope iop_sap_in, type rw */ +typedef struct { + unsigned int sync_sel : 2; + unsigned int sync_ext_src : 3; + unsigned int sync_edge : 2; + unsigned int delay : 2; + unsigned int logic : 2; + unsigned int dummy1 : 21; +} reg_iop_sap_in_rw_gio; +#define REG_RD_ADDR_iop_sap_in_rw_gio 16 +#define REG_WR_ADDR_iop_sap_in_rw_gio 16 + + +/* Constants */ +enum { + regk_iop_sap_in_and = 0x00000002, + regk_iop_sap_in_ext_clk200 = 0x00000003, + regk_iop_sap_in_gio0 = 0x00000000, + regk_iop_sap_in_gio12 = 0x00000003, + regk_iop_sap_in_gio16 = 0x00000004, + regk_iop_sap_in_gio20 = 0x00000005, + regk_iop_sap_in_gio24 = 0x00000006, + regk_iop_sap_in_gio28 = 0x00000007, + regk_iop_sap_in_gio4 = 0x00000001, + regk_iop_sap_in_gio8 = 0x00000002, + regk_iop_sap_in_inv = 0x00000001, + regk_iop_sap_in_neg = 0x00000002, + regk_iop_sap_in_no = 0x00000000, + regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, + regk_iop_sap_in_none = 0x00000000, + regk_iop_sap_in_one = 0x00000001, + regk_iop_sap_in_or = 0x00000003, + regk_iop_sap_in_pos = 0x00000001, + regk_iop_sap_in_pos_neg = 0x00000003, + regk_iop_sap_in_rw_bus_byte_default = 0x00000000, + regk_iop_sap_in_rw_bus_byte_size = 0x00000004, + regk_iop_sap_in_rw_gio_default = 0x00000000, + regk_iop_sap_in_rw_gio_size = 0x00000020, + regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, + regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, + regk_iop_sap_in_tmr_clk200 = 0x00000001, + regk_iop_sap_in_two = 0x00000002, + regk_iop_sap_in_two_clk200 = 0x00000000 +}; +#endif /* __iop_sap_in_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h new file mode 100644 index 000000000..5af88baa2 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h @@ -0,0 +1,231 @@ +#ifndef __iop_sap_out_defs_h +#define __iop_sap_out_defs_h + +/* + * This file is autogenerated from + * file: iop_sap_out.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sap_out */ + +/* Register rw_gen_gated, scope iop_sap_out, type rw */ +typedef struct { + unsigned int clk0_src : 2; + unsigned int clk0_gate_src : 2; + unsigned int clk0_force_src : 3; + unsigned int clk1_src : 2; + unsigned int clk1_gate_src : 2; + unsigned int clk1_force_src : 3; + unsigned int dummy1 : 18; +} reg_iop_sap_out_rw_gen_gated; +#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 +#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 + +/* Register rw_bus, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 2; + unsigned int byte0_clk_ext : 2; + unsigned int byte0_gated_clk : 1; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_delay : 1; + unsigned int byte1_clk_sel : 2; + unsigned int byte1_clk_ext : 2; + unsigned int byte1_gated_clk : 1; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_delay : 1; + unsigned int byte2_clk_sel : 2; + unsigned int byte2_clk_ext : 2; + unsigned int byte2_gated_clk : 1; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_delay : 1; + unsigned int byte3_clk_sel : 2; + unsigned int byte3_clk_ext : 2; + unsigned int byte3_gated_clk : 1; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_delay : 1; + unsigned int dummy1 : 4; +} reg_iop_sap_out_rw_bus; +#define REG_RD_ADDR_iop_sap_out_rw_bus 4 +#define REG_WR_ADDR_iop_sap_out_rw_bus 4 + +/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte0_clk_sel : 2; + unsigned int byte0_clk_ext : 2; + unsigned int byte0_gated_clk : 1; + unsigned int byte0_clk_inv : 1; + unsigned int byte0_delay : 1; + unsigned int byte0_logic : 2; + unsigned int byte0_logic_src : 2; + unsigned int byte1_clk_sel : 2; + unsigned int byte1_clk_ext : 2; + unsigned int byte1_gated_clk : 1; + unsigned int byte1_clk_inv : 1; + unsigned int byte1_delay : 1; + unsigned int byte1_logic : 2; + unsigned int byte1_logic_src : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus_lo_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 +#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 + +/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ +typedef struct { + unsigned int byte2_clk_sel : 2; + unsigned int byte2_clk_ext : 2; + unsigned int byte2_gated_clk : 1; + unsigned int byte2_clk_inv : 1; + unsigned int byte2_delay : 1; + unsigned int byte2_logic : 2; + unsigned int byte2_logic_src : 2; + unsigned int byte3_clk_sel : 2; + unsigned int byte3_clk_ext : 2; + unsigned int byte3_gated_clk : 1; + unsigned int byte3_clk_inv : 1; + unsigned int byte3_delay : 1; + unsigned int byte3_logic : 2; + unsigned int byte3_logic_src : 2; + unsigned int dummy1 : 10; +} reg_iop_sap_out_rw_bus_hi_oe; +#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 +#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 + +#define STRIDE_iop_sap_out_rw_gio 4 +/* Register rw_gio, scope iop_sap_out, type rw */ +typedef struct { + unsigned int out_clk_sel : 3; + unsigned int out_clk_ext : 2; + unsigned int out_gated_clk : 1; + unsigned int out_clk_inv : 1; + unsigned int out_delay : 1; + unsigned int out_logic : 2; + unsigned int out_logic_src : 2; + unsigned int oe_clk_sel : 3; + unsigned int oe_clk_ext : 2; + unsigned int oe_gated_clk : 1; + unsigned int oe_clk_inv : 1; + unsigned int oe_delay : 1; + unsigned int oe_logic : 2; + unsigned int oe_logic_src : 2; + unsigned int dummy1 : 8; +} reg_iop_sap_out_rw_gio; +#define REG_RD_ADDR_iop_sap_out_rw_gio 16 +#define REG_WR_ADDR_iop_sap_out_rw_gio 16 + + +/* Constants */ +enum { + regk_iop_sap_out_always = 0x00000001, + regk_iop_sap_out_and = 0x00000002, + regk_iop_sap_out_clk0 = 0x00000000, + regk_iop_sap_out_clk1 = 0x00000001, + regk_iop_sap_out_clk12 = 0x00000004, + regk_iop_sap_out_clk200 = 0x00000000, + regk_iop_sap_out_ext = 0x00000002, + regk_iop_sap_out_gated = 0x00000003, + regk_iop_sap_out_gio0 = 0x00000000, + regk_iop_sap_out_gio1 = 0x00000000, + regk_iop_sap_out_gio16 = 0x00000002, + regk_iop_sap_out_gio17 = 0x00000002, + regk_iop_sap_out_gio24 = 0x00000003, + regk_iop_sap_out_gio25 = 0x00000003, + regk_iop_sap_out_gio8 = 0x00000001, + regk_iop_sap_out_gio9 = 0x00000001, + regk_iop_sap_out_gio_out10 = 0x00000005, + regk_iop_sap_out_gio_out18 = 0x00000006, + regk_iop_sap_out_gio_out2 = 0x00000004, + regk_iop_sap_out_gio_out26 = 0x00000007, + regk_iop_sap_out_inv = 0x00000001, + regk_iop_sap_out_nand = 0x00000003, + regk_iop_sap_out_no = 0x00000000, + regk_iop_sap_out_none = 0x00000000, + regk_iop_sap_out_one = 0x00000001, + regk_iop_sap_out_rw_bus_default = 0x00000000, + regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, + regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, + regk_iop_sap_out_rw_gen_gated_default = 0x00000000, + regk_iop_sap_out_rw_gio_default = 0x00000000, + regk_iop_sap_out_rw_gio_size = 0x00000020, + regk_iop_sap_out_spu_gio6 = 0x00000002, + regk_iop_sap_out_spu_gio7 = 0x00000003, + regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, + regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, + regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, + regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, + regk_iop_sap_out_tmr200 = 0x00000001, + regk_iop_sap_out_yes = 0x00000001 +}; +#endif /* __iop_sap_out_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h new file mode 100644 index 000000000..98ac95275 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h @@ -0,0 +1,725 @@ +#ifndef __iop_sw_cfg_defs_h +#define __iop_sw_cfg_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_cfg.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cfg */ + +/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_crc_par_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 +#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 + +/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 + +/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_dmc_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 +#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 + +/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 + +/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_in_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 + +/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 + +/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_fifo_out_extra_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 +#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 + +/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 + +/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_sap_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 +#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 + +/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_in_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 + +/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_scrc_out_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 +#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 + +/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 1; + unsigned int dummy1 : 31; +} reg_iop_sw_cfg_rw_spu_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 + +/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 + +/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_timer_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 + +/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp0_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 + +/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp1_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 + +/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp2_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 + +/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp3_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 + +/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp4_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 + +/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp5_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 + +/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp6_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 + +/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_trigger_grp7_owner; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 + +/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cfg_rw_bus_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 + +/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cfg_rw_bus_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 + +/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 + +/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cfg_rw_gio_oe_mask; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 + +/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus_byte0 : 2; + unsigned int bus_byte1 : 2; + unsigned int bus_byte2 : 2; + unsigned int bus_byte3 : 2; + unsigned int gio3_0 : 2; + unsigned int gio7_4 : 2; + unsigned int gio11_8 : 2; + unsigned int gio15_12 : 2; + unsigned int gio19_16 : 2; + unsigned int gio23_20 : 2; + unsigned int gio27_24 : 2; + unsigned int gio31_28 : 2; + unsigned int dummy1 : 8; +} reg_iop_sw_cfg_rw_pinmapping; +#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 +#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 + +/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus_lo : 2; + unsigned int bus_hi : 2; + unsigned int bus_lo_oe : 2; + unsigned int bus_hi_oe : 2; + unsigned int dummy1 : 24; +} reg_iop_sw_cfg_rw_bus_out_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 +#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 + +/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio0 : 3; + unsigned int gio0_oe : 1; + unsigned int gio1 : 3; + unsigned int gio1_oe : 1; + unsigned int gio2 : 3; + unsigned int gio2_oe : 1; + unsigned int gio3 : 3; + unsigned int gio3_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 + +/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio4 : 3; + unsigned int gio4_oe : 1; + unsigned int gio5 : 3; + unsigned int gio5_oe : 1; + unsigned int gio6 : 3; + unsigned int gio6_oe : 1; + unsigned int gio7 : 3; + unsigned int gio7_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 + +/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio8 : 3; + unsigned int gio8_oe : 1; + unsigned int gio9 : 3; + unsigned int gio9_oe : 1; + unsigned int gio10 : 3; + unsigned int gio10_oe : 1; + unsigned int gio11 : 3; + unsigned int gio11_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 + +/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio12 : 3; + unsigned int gio12_oe : 1; + unsigned int gio13 : 3; + unsigned int gio13_oe : 1; + unsigned int gio14 : 3; + unsigned int gio14_oe : 1; + unsigned int gio15 : 3; + unsigned int gio15_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 + +/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio16 : 3; + unsigned int gio16_oe : 1; + unsigned int gio17 : 3; + unsigned int gio17_oe : 1; + unsigned int gio18 : 3; + unsigned int gio18_oe : 1; + unsigned int gio19 : 3; + unsigned int gio19_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 + +/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio20 : 3; + unsigned int gio20_oe : 1; + unsigned int gio21 : 3; + unsigned int gio21_oe : 1; + unsigned int gio22 : 3; + unsigned int gio22_oe : 1; + unsigned int gio23 : 3; + unsigned int gio23_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 + +/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio24 : 3; + unsigned int gio24_oe : 1; + unsigned int gio25 : 3; + unsigned int gio25_oe : 1; + unsigned int gio26 : 3; + unsigned int gio26_oe : 1; + unsigned int gio27 : 3; + unsigned int gio27_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 + +/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int gio28 : 3; + unsigned int gio28_oe : 1; + unsigned int gio29 : 3; + unsigned int gio29_oe : 1; + unsigned int gio30 : 3; + unsigned int gio30_oe : 1; + unsigned int gio31 : 3; + unsigned int gio31_oe : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 +#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 + +/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int bus0_in : 1; + unsigned int bus1_in : 1; + unsigned int dummy1 : 30; +} reg_iop_sw_cfg_rw_spu_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 +#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 + +/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 2; + unsigned int tmr1_en : 2; + unsigned int tmr2_en : 2; + unsigned int tmr3_en : 2; + unsigned int tmr0_dis : 2; + unsigned int tmr1_dis : 2; + unsigned int tmr2_dis : 2; + unsigned int tmr3_dis : 2; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_timer_grp0_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 + +/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int ext_clk : 3; + unsigned int tmr0_en : 2; + unsigned int tmr1_en : 2; + unsigned int tmr2_en : 2; + unsigned int tmr3_en : 2; + unsigned int tmr0_dis : 2; + unsigned int tmr1_dis : 2; + unsigned int tmr2_dis : 2; + unsigned int tmr3_dis : 2; + unsigned int dummy1 : 13; +} reg_iop_sw_cfg_rw_timer_grp1_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 +#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 + +/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int grp0_dis : 1; + unsigned int grp0_en : 1; + unsigned int grp1_dis : 1; + unsigned int grp1_en : 1; + unsigned int grp2_dis : 1; + unsigned int grp2_en : 1; + unsigned int grp3_dis : 1; + unsigned int grp3_en : 1; + unsigned int grp4_dis : 1; + unsigned int grp4_en : 1; + unsigned int grp5_dis : 1; + unsigned int grp5_en : 1; + unsigned int grp6_dis : 1; + unsigned int grp6_en : 1; + unsigned int grp7_dis : 1; + unsigned int grp7_en : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cfg_rw_trigger_grps_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 +#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 + +/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int out_strb : 4; + unsigned int in_src : 2; + unsigned int in_size : 3; + unsigned int in_last : 2; + unsigned int in_strb : 4; + unsigned int dummy1 : 17; +} reg_iop_sw_cfg_rw_pdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 +#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 + +/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ +typedef struct { + unsigned int sdp_out_strb : 3; + unsigned int sdp_in_data : 3; + unsigned int sdp_in_last : 2; + unsigned int sdp_in_strb : 3; + unsigned int dummy1 : 21; +} reg_iop_sw_cfg_rw_sdp_cfg; +#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 +#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 + + +/* Constants */ +enum { + regk_iop_sw_cfg_a = 0x00000001, + regk_iop_sw_cfg_b = 0x00000002, + regk_iop_sw_cfg_bus = 0x00000000, + regk_iop_sw_cfg_bus_rot16 = 0x00000002, + regk_iop_sw_cfg_bus_rot24 = 0x00000003, + regk_iop_sw_cfg_bus_rot8 = 0x00000001, + regk_iop_sw_cfg_clk12 = 0x00000000, + regk_iop_sw_cfg_cpu = 0x00000000, + regk_iop_sw_cfg_gated_clk0 = 0x0000000e, + regk_iop_sw_cfg_gated_clk1 = 0x0000000f, + regk_iop_sw_cfg_gio0 = 0x00000004, + regk_iop_sw_cfg_gio1 = 0x00000001, + regk_iop_sw_cfg_gio2 = 0x00000005, + regk_iop_sw_cfg_gio3 = 0x00000002, + regk_iop_sw_cfg_gio4 = 0x00000006, + regk_iop_sw_cfg_gio5 = 0x00000003, + regk_iop_sw_cfg_gio6 = 0x00000007, + regk_iop_sw_cfg_gio7 = 0x00000004, + regk_iop_sw_cfg_gio_in18 = 0x00000002, + regk_iop_sw_cfg_gio_in19 = 0x00000003, + regk_iop_sw_cfg_gio_in20 = 0x00000004, + regk_iop_sw_cfg_gio_in21 = 0x00000005, + regk_iop_sw_cfg_gio_in26 = 0x00000006, + regk_iop_sw_cfg_gio_in27 = 0x00000007, + regk_iop_sw_cfg_gio_in4 = 0x00000000, + regk_iop_sw_cfg_gio_in5 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, + regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, + regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, + regk_iop_sw_cfg_mpu = 0x00000001, + regk_iop_sw_cfg_none = 0x00000000, + regk_iop_sw_cfg_pdp_out = 0x00000001, + regk_iop_sw_cfg_pdp_out_hi = 0x00000001, + regk_iop_sw_cfg_pdp_out_lo = 0x00000000, + regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, + regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, + regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, + regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, + regk_iop_sw_cfg_sdp_out = 0x00000004, + regk_iop_sw_cfg_size16 = 0x00000002, + regk_iop_sw_cfg_size24 = 0x00000003, + regk_iop_sw_cfg_size32 = 0x00000004, + regk_iop_sw_cfg_size8 = 0x00000001, + regk_iop_sw_cfg_spu = 0x00000002, + regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, + regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, + regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, + regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, + regk_iop_sw_cfg_spu_g0 = 0x00000007, + regk_iop_sw_cfg_spu_g1 = 0x00000007, + regk_iop_sw_cfg_spu_g2 = 0x00000007, + regk_iop_sw_cfg_spu_g3 = 0x00000007, + regk_iop_sw_cfg_spu_g4 = 0x00000007, + regk_iop_sw_cfg_spu_g5 = 0x00000007, + regk_iop_sw_cfg_spu_g6 = 0x00000007, + regk_iop_sw_cfg_spu_g7 = 0x00000007, + regk_iop_sw_cfg_spu_gio0 = 0x00000000, + regk_iop_sw_cfg_spu_gio1 = 0x00000001, + regk_iop_sw_cfg_spu_gio5 = 0x00000005, + regk_iop_sw_cfg_spu_gio6 = 0x00000006, + regk_iop_sw_cfg_spu_gio7 = 0x00000007, + regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, + regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, + regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, + regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, + regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, + regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, + regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, + regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, + regk_iop_sw_cfg_spu_gioout0 = 0x00000000, + regk_iop_sw_cfg_spu_gioout1 = 0x00000000, + regk_iop_sw_cfg_spu_gioout10 = 0x00000007, + regk_iop_sw_cfg_spu_gioout11 = 0x00000007, + regk_iop_sw_cfg_spu_gioout12 = 0x00000007, + regk_iop_sw_cfg_spu_gioout13 = 0x00000007, + regk_iop_sw_cfg_spu_gioout14 = 0x00000007, + regk_iop_sw_cfg_spu_gioout15 = 0x00000007, + regk_iop_sw_cfg_spu_gioout16 = 0x00000007, + regk_iop_sw_cfg_spu_gioout17 = 0x00000007, + regk_iop_sw_cfg_spu_gioout18 = 0x00000007, + regk_iop_sw_cfg_spu_gioout19 = 0x00000007, + regk_iop_sw_cfg_spu_gioout2 = 0x00000001, + regk_iop_sw_cfg_spu_gioout20 = 0x00000007, + regk_iop_sw_cfg_spu_gioout21 = 0x00000007, + regk_iop_sw_cfg_spu_gioout22 = 0x00000007, + regk_iop_sw_cfg_spu_gioout23 = 0x00000007, + regk_iop_sw_cfg_spu_gioout24 = 0x00000007, + regk_iop_sw_cfg_spu_gioout25 = 0x00000007, + regk_iop_sw_cfg_spu_gioout26 = 0x00000007, + regk_iop_sw_cfg_spu_gioout27 = 0x00000007, + regk_iop_sw_cfg_spu_gioout28 = 0x00000007, + regk_iop_sw_cfg_spu_gioout29 = 0x00000007, + regk_iop_sw_cfg_spu_gioout3 = 0x00000001, + regk_iop_sw_cfg_spu_gioout30 = 0x00000007, + regk_iop_sw_cfg_spu_gioout31 = 0x00000007, + regk_iop_sw_cfg_spu_gioout4 = 0x00000002, + regk_iop_sw_cfg_spu_gioout5 = 0x00000002, + regk_iop_sw_cfg_spu_gioout6 = 0x00000003, + regk_iop_sw_cfg_spu_gioout7 = 0x00000003, + regk_iop_sw_cfg_spu_gioout8 = 0x00000007, + regk_iop_sw_cfg_spu_gioout9 = 0x00000007, + regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, + regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, + regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, + regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, + regk_iop_sw_cfg_timer_grp0 = 0x00000000, + regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, + regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, + regk_iop_sw_cfg_timer_grp1 = 0x00000000, + regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, + regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, + regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, + regk_iop_sw_cfg_trig0_0 = 0x00000000, + regk_iop_sw_cfg_trig0_1 = 0x00000000, + regk_iop_sw_cfg_trig0_2 = 0x00000000, + regk_iop_sw_cfg_trig0_3 = 0x00000000, + regk_iop_sw_cfg_trig1_0 = 0x00000000, + regk_iop_sw_cfg_trig1_1 = 0x00000000, + regk_iop_sw_cfg_trig1_2 = 0x00000000, + regk_iop_sw_cfg_trig1_3 = 0x00000000, + regk_iop_sw_cfg_trig2_0 = 0x00000001, + regk_iop_sw_cfg_trig2_1 = 0x00000001, + regk_iop_sw_cfg_trig2_2 = 0x00000001, + regk_iop_sw_cfg_trig2_3 = 0x00000001, + regk_iop_sw_cfg_trig3_0 = 0x00000001, + regk_iop_sw_cfg_trig3_1 = 0x00000001, + regk_iop_sw_cfg_trig3_2 = 0x00000001, + regk_iop_sw_cfg_trig3_3 = 0x00000001, + regk_iop_sw_cfg_trig4_0 = 0x00000002, + regk_iop_sw_cfg_trig4_1 = 0x00000002, + regk_iop_sw_cfg_trig4_2 = 0x00000002, + regk_iop_sw_cfg_trig4_3 = 0x00000002, + regk_iop_sw_cfg_trig5_0 = 0x00000002, + regk_iop_sw_cfg_trig5_1 = 0x00000002, + regk_iop_sw_cfg_trig5_2 = 0x00000002, + regk_iop_sw_cfg_trig5_3 = 0x00000002, + regk_iop_sw_cfg_trig6_0 = 0x00000003, + regk_iop_sw_cfg_trig6_1 = 0x00000003, + regk_iop_sw_cfg_trig6_2 = 0x00000003, + regk_iop_sw_cfg_trig6_3 = 0x00000003, + regk_iop_sw_cfg_trig7_0 = 0x00000003, + regk_iop_sw_cfg_trig7_1 = 0x00000003, + regk_iop_sw_cfg_trig7_2 = 0x00000003, + regk_iop_sw_cfg_trig7_3 = 0x00000003 +}; +#endif /* __iop_sw_cfg_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h new file mode 100644 index 000000000..a16f55637 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h @@ -0,0 +1,522 @@ +#ifndef __iop_sw_cpu_defs_h +#define __iop_sw_cpu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_cpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_cpu */ + +/* Register r_mpu_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 + +/* Register r_spu_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_spu_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 + +/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; +#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 + +/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_cpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 + +/* Register rw_mc_data, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 + +/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ +typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 +#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 + +/* Register rs_mc_data, scope iop_sw_cpu, type rs */ +typedef unsigned int reg_iop_sw_cpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 + +/* Register r_mc_data, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 + +/* Register r_mc_stat, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_cpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 + +/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 + +/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_cpu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_cpu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 +#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 + +/* Register r_bus_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_bus_in; +#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 + +/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 + +/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_cpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 +#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 + +/* Register r_gio_in, scope iop_sw_cpu, type r */ +typedef unsigned int reg_iop_sw_cpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 + +/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_rw_intr0_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 + +/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_rw_ack_intr0; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 + +/* Register r_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_r_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 + +/* Register r_masked_intr0, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_0 : 1; + unsigned int mpu_1 : 1; + unsigned int mpu_2 : 1; + unsigned int mpu_3 : 1; + unsigned int mpu_4 : 1; + unsigned int mpu_5 : 1; + unsigned int mpu_6 : 1; + unsigned int mpu_7 : 1; + unsigned int mpu_8 : 1; + unsigned int mpu_9 : 1; + unsigned int mpu_10 : 1; + unsigned int mpu_11 : 1; + unsigned int mpu_12 : 1; + unsigned int mpu_13 : 1; + unsigned int mpu_14 : 1; + unsigned int mpu_15 : 1; + unsigned int spu_0 : 1; + unsigned int spu_1 : 1; + unsigned int spu_2 : 1; + unsigned int spu_3 : 1; + unsigned int spu_4 : 1; + unsigned int spu_5 : 1; + unsigned int spu_6 : 1; + unsigned int spu_7 : 1; + unsigned int spu_8 : 1; + unsigned int spu_9 : 1; + unsigned int spu_10 : 1; + unsigned int spu_11 : 1; + unsigned int spu_12 : 1; + unsigned int spu_13 : 1; + unsigned int spu_14 : 1; + unsigned int spu_15 : 1; +} reg_iop_sw_cpu_r_masked_intr0; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 + +/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_rw_intr1_mask; +#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 +#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 + +/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_cpu_rw_ack_intr1; +#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 +#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 + +/* Register r_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 + +/* Register r_masked_intr1, scope iop_sw_cpu, type r */ +typedef struct { + unsigned int mpu_16 : 1; + unsigned int mpu_17 : 1; + unsigned int mpu_18 : 1; + unsigned int mpu_19 : 1; + unsigned int mpu_20 : 1; + unsigned int mpu_21 : 1; + unsigned int mpu_22 : 1; + unsigned int mpu_23 : 1; + unsigned int mpu_24 : 1; + unsigned int mpu_25 : 1; + unsigned int mpu_26 : 1; + unsigned int mpu_27 : 1; + unsigned int mpu_28 : 1; + unsigned int mpu_29 : 1; + unsigned int mpu_30 : 1; + unsigned int mpu_31 : 1; + unsigned int dmc_in : 1; + unsigned int dmc_out : 1; + unsigned int fifo_in : 1; + unsigned int fifo_out : 1; + unsigned int fifo_in_extra : 1; + unsigned int fifo_out_extra : 1; + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; +} reg_iop_sw_cpu_r_masked_intr1; +#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 + + +/* Constants */ +enum { + regk_iop_sw_cpu_copy = 0x00000000, + regk_iop_sw_cpu_no = 0x00000000, + regk_iop_sw_cpu_rd = 0x00000002, + regk_iop_sw_cpu_reg_copy = 0x00000001, + regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, + regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, + regk_iop_sw_cpu_wr = 0x00000003, + regk_iop_sw_cpu_yes = 0x00000001 +}; +#endif /* __iop_sw_cpu_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h new file mode 100644 index 000000000..a2e4e1a33 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h @@ -0,0 +1,648 @@ +#ifndef __iop_sw_mpu_defs_h +#define __iop_sw_mpu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_mpu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_mpu */ + +/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int cfg : 2; + unsigned int dummy1 : 30; +} reg_iop_sw_mpu_rw_sw_cfg_owner; +#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 +#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 + +/* Register r_spu_trace, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_spu_trace; +#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 + +/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; +#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 + +/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_mpu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 + +/* Register rw_mc_data, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 + +/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ +typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 +#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 + +/* Register rs_mc_data, scope iop_sw_mpu, type rs */ +typedef unsigned int reg_iop_sw_mpu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 + +/* Register r_mc_data, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_mc_data; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 + +/* Register r_mc_stat, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_mpu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 + +/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 + +/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_mpu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 + +/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_mpu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 +#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 + +/* Register r_bus_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_bus_in; +#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 + +/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 + +/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 + +/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_mpu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 +#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 + +/* Register r_gio_in, scope iop_sw_mpu, type r */ +typedef unsigned int reg_iop_sw_mpu_r_gio_in; +#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 + +/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 +#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 + +/* Register r_cpu_intr, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int intr16 : 1; + unsigned int intr17 : 1; + unsigned int intr18 : 1; + unsigned int intr19 : 1; + unsigned int intr20 : 1; + unsigned int intr21 : 1; + unsigned int intr22 : 1; + unsigned int intr23 : 1; + unsigned int intr24 : 1; + unsigned int intr25 : 1; + unsigned int intr26 : 1; + unsigned int intr27 : 1; + unsigned int intr28 : 1; + unsigned int intr29 : 1; + unsigned int intr30 : 1; + unsigned int intr31 : 1; +} reg_iop_sw_mpu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 + +/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp0_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 + +/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr1 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr2 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr3 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 + +/* Register r_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 + +/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr0 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr1 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr2 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr3 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp0; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 + +/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp1_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 + +/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr5 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr6 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr7 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 + +/* Register r_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 + +/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr4 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr5 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr6 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr7 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp1; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 + +/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp2_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 + +/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr9 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr10 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr11 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 + +/* Register r_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 + +/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr8 : 1; + unsigned int trigger_grp0 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr9 : 1; + unsigned int trigger_grp1 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int spu_intr10 : 1; + unsigned int trigger_grp2 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr11 : 1; + unsigned int trigger_grp3 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp2; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 + +/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_rw_intr_grp3_mask; +#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 +#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 + +/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int dummy1 : 3; + unsigned int spu_intr13 : 1; + unsigned int dummy2 : 3; + unsigned int spu_intr14 : 1; + unsigned int dummy3 : 3; + unsigned int spu_intr15 : 1; + unsigned int dummy4 : 19; +} reg_iop_sw_mpu_rw_ack_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 +#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 + +/* Register r_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 + +/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ +typedef struct { + unsigned int spu_intr12 : 1; + unsigned int trigger_grp4 : 1; + unsigned int fifo_out_extra : 1; + unsigned int dmc_out : 1; + unsigned int spu_intr13 : 1; + unsigned int trigger_grp5 : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_in : 1; + unsigned int spu_intr14 : 1; + unsigned int trigger_grp6 : 1; + unsigned int timer_grp0 : 1; + unsigned int fifo_out : 1; + unsigned int spu_intr15 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_mpu_r_masked_intr_grp3; +#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 + + +/* Constants */ +enum { + regk_iop_sw_mpu_copy = 0x00000000, + regk_iop_sw_mpu_cpu = 0x00000000, + regk_iop_sw_mpu_mpu = 0x00000001, + regk_iop_sw_mpu_no = 0x00000000, + regk_iop_sw_mpu_nop = 0x00000000, + regk_iop_sw_mpu_rd = 0x00000002, + regk_iop_sw_mpu_reg_copy = 0x00000001, + regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, + regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, + regk_iop_sw_mpu_set = 0x00000001, + regk_iop_sw_mpu_spu = 0x00000002, + regk_iop_sw_mpu_wr = 0x00000003, + regk_iop_sw_mpu_yes = 0x00000001 +}; +#endif /* __iop_sw_mpu_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h new file mode 100644 index 000000000..c8560b865 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h @@ -0,0 +1,441 @@ +#ifndef __iop_sw_spu_defs_h +#define __iop_sw_spu_defs_h + +/* + * This file is autogenerated from + * file: iop_sw_spu.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_sw_spu */ + +/* Register r_mpu_trace, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mpu_trace; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 + +/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int keep_owner : 1; + unsigned int cmd : 2; + unsigned int size : 3; + unsigned int wr_spu_mem : 1; + unsigned int dummy1 : 25; +} reg_iop_sw_spu_rw_mc_ctrl; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 + +/* Register rw_mc_data, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 + +/* Register rw_mc_addr, scope iop_sw_spu, type rw */ +typedef unsigned int reg_iop_sw_spu_rw_mc_addr; +#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 +#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 + +/* Register rs_mc_data, scope iop_sw_spu, type rs */ +typedef unsigned int reg_iop_sw_spu_rs_mc_data; +#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 + +/* Register r_mc_data, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_mc_data; +#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 + +/* Register r_mc_stat, scope iop_sw_spu, type r */ +typedef struct { + unsigned int busy_cpu : 1; + unsigned int busy_mpu : 1; + unsigned int busy_spu : 1; + unsigned int owned_by_cpu : 1; + unsigned int owned_by_mpu : 1; + unsigned int owned_by_spu : 1; + unsigned int dummy1 : 26; +} reg_iop_sw_spu_r_mc_stat; +#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 + +/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 + +/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int byte2 : 8; + unsigned int byte3 : 8; +} reg_iop_sw_spu_rw_bus_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 + +/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 + +/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 1; + unsigned int byte1 : 1; + unsigned int byte2 : 1; + unsigned int byte3 : 1; + unsigned int dummy1 : 28; +} reg_iop_sw_spu_rw_bus_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 + +/* Register r_bus_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_bus_in; +#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 + +/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 + +/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 + +/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_clr_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 + +/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 32; +} reg_iop_sw_spu_rw_gio_oe_set_mask; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 + +/* Register r_gio_in, scope iop_sw_spu, type r */ +typedef unsigned int reg_iop_sw_spu_r_gio_in; +#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 + +/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 + +/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 + +/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte0 : 8; + unsigned int byte1 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 + +/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int byte2 : 8; + unsigned int byte3 : 8; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_bus_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 +#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 + +/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 + +/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 + +/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 + +/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 + +/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 + +/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 + +/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 + +/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int val : 16; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; +#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 +#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 + +/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 +#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 + +/* Register r_cpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_cpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 + +/* Register r_hw_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int trigger_grp0 : 1; + unsigned int trigger_grp1 : 1; + unsigned int trigger_grp2 : 1; + unsigned int trigger_grp3 : 1; + unsigned int trigger_grp4 : 1; + unsigned int trigger_grp5 : 1; + unsigned int trigger_grp6 : 1; + unsigned int trigger_grp7 : 1; + unsigned int timer_grp0 : 1; + unsigned int timer_grp1 : 1; + unsigned int fifo_out : 1; + unsigned int fifo_out_extra : 1; + unsigned int fifo_in : 1; + unsigned int fifo_in_extra : 1; + unsigned int dmc_out : 1; + unsigned int dmc_in : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_hw_intr; +#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 + +/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_rw_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 +#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 + +/* Register r_mpu_intr, scope iop_sw_spu, type r */ +typedef struct { + unsigned int intr0 : 1; + unsigned int intr1 : 1; + unsigned int intr2 : 1; + unsigned int intr3 : 1; + unsigned int intr4 : 1; + unsigned int intr5 : 1; + unsigned int intr6 : 1; + unsigned int intr7 : 1; + unsigned int intr8 : 1; + unsigned int intr9 : 1; + unsigned int intr10 : 1; + unsigned int intr11 : 1; + unsigned int intr12 : 1; + unsigned int intr13 : 1; + unsigned int intr14 : 1; + unsigned int intr15 : 1; + unsigned int dummy1 : 16; +} reg_iop_sw_spu_r_mpu_intr; +#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 + + +/* Constants */ +enum { + regk_iop_sw_spu_copy = 0x00000000, + regk_iop_sw_spu_no = 0x00000000, + regk_iop_sw_spu_nop = 0x00000000, + regk_iop_sw_spu_rd = 0x00000002, + regk_iop_sw_spu_reg_copy = 0x00000001, + regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, + regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, + regk_iop_sw_spu_set = 0x00000001, + regk_iop_sw_spu_wr = 0x00000003, + regk_iop_sw_spu_yes = 0x00000001 +}; +#endif /* __iop_sw_spu_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h new file mode 100644 index 000000000..20de425e6 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h @@ -0,0 +1,96 @@ +#ifndef __iop_version_defs_h +#define __iop_version_defs_h + +/* + * This file is autogenerated from + * file: iop_version.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope iop_version */ + +/* Register r_version, scope iop_version, type r */ +typedef struct { + unsigned int nr : 8; + unsigned int dummy1 : 24; +} reg_iop_version_r_version; +#define REG_RD_ADDR_iop_version_r_version 0 + + +/* Constants */ +enum { + regk_iop_version_v2_0 = 0x00000002 +}; +#endif /* __iop_version_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h new file mode 100644 index 000000000..243ac3c88 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h @@ -0,0 +1,142 @@ +#ifndef __l2cache_defs_h +#define __l2cache_defs_h + +/* + * This file is autogenerated from + * file: l2cache.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope l2cache */ + +/* Register rw_cfg, scope l2cache, type rw */ +typedef struct { + unsigned int en : 1; + unsigned int dummy1 : 31; +} reg_l2cache_rw_cfg; +#define REG_RD_ADDR_l2cache_rw_cfg 0 +#define REG_WR_ADDR_l2cache_rw_cfg 0 + +/* Register rw_ctrl, scope l2cache, type rw */ +typedef struct { + unsigned int dummy1 : 7; + unsigned int cbase : 9; + unsigned int dummy2 : 4; + unsigned int csize : 10; + unsigned int dummy3 : 2; +} reg_l2cache_rw_ctrl; +#define REG_RD_ADDR_l2cache_rw_ctrl 4 +#define REG_WR_ADDR_l2cache_rw_ctrl 4 + +/* Register rw_idxop, scope l2cache, type rw */ +typedef struct { + unsigned int idx : 10; + unsigned int dummy1 : 14; + unsigned int way : 3; + unsigned int dummy2 : 2; + unsigned int cmd : 3; +} reg_l2cache_rw_idxop; +#define REG_RD_ADDR_l2cache_rw_idxop 8 +#define REG_WR_ADDR_l2cache_rw_idxop 8 + +/* Register rw_addrop_addr, scope l2cache, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_l2cache_rw_addrop_addr; +#define REG_RD_ADDR_l2cache_rw_addrop_addr 12 +#define REG_WR_ADDR_l2cache_rw_addrop_addr 12 + +/* Register rw_addrop_ctrl, scope l2cache, type rw */ +typedef struct { + unsigned int size : 16; + unsigned int dummy1 : 13; + unsigned int cmd : 3; +} reg_l2cache_rw_addrop_ctrl; +#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 +#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 + + +/* Constants */ +enum { + regk_l2cache_flush = 0x00000001, + regk_l2cache_no = 0x00000000, + regk_l2cache_rw_addrop_addr_default = 0x00000000, + regk_l2cache_rw_addrop_ctrl_default = 0x00000000, + regk_l2cache_rw_cfg_default = 0x00000000, + regk_l2cache_rw_ctrl_default = 0x00000000, + regk_l2cache_rw_idxop_default = 0x00000000, + regk_l2cache_yes = 0x00000001 +}; +#endif /* __l2cache_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h new file mode 100644 index 000000000..c0e7628cb --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h @@ -0,0 +1,482 @@ +#ifndef __marb_bar_defs_h +#define __marb_bar_defs_h + +/* + * This file is autogenerated from + * file: marb_bar.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bar */ + +#define STRIDE_marb_bar_rw_ddr2_slots 4 +/* Register rw_ddr2_slots, scope marb_bar, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_ddr2_slots; +#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 +#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 + +/* Register rw_h264_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_h264_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 +#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 + +/* Register rw_h264_wr_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_h264_wr_burst; +#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 +#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 + +/* Register rw_ccd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_ccd_burst; +#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 +#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 + +/* Register rw_vin_wr_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vin_wr_burst; +#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 +#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 + +/* Register rw_vin_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vin_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 +#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 + +/* Register rw_sclr_rd_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_sclr_rd_burst; +#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 +#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 + +/* Register rw_vout_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_vout_burst; +#define REG_RD_ADDR_marb_bar_rw_vout_burst 280 +#define REG_WR_ADDR_marb_bar_rw_vout_burst 280 + +/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_sclr_fifo_burst; +#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 +#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 + +/* Register rw_l2cache_burst, scope marb_bar, type rw */ +typedef struct { + unsigned int ddr2_bsize : 2; + unsigned int dummy1 : 30; +} reg_marb_bar_rw_l2cache_burst; +#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 +#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 + +/* Register rw_intr_mask, scope marb_bar, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_intr_mask; +#define REG_RD_ADDR_marb_bar_rw_intr_mask 292 +#define REG_WR_ADDR_marb_bar_rw_intr_mask 292 + +/* Register rw_ack_intr, scope marb_bar, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_rw_ack_intr; +#define REG_RD_ADDR_marb_bar_rw_ack_intr 296 +#define REG_WR_ADDR_marb_bar_rw_ack_intr 296 + +/* Register r_intr, scope marb_bar, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_r_intr; +#define REG_RD_ADDR_marb_bar_r_intr 300 + +/* Register r_masked_intr, scope marb_bar, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_bar_r_masked_intr; +#define REG_RD_ADDR_marb_bar_r_masked_intr 304 + +/* Register rw_stop_mask, scope marb_bar, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_rw_stop_mask; +#define REG_RD_ADDR_marb_bar_rw_stop_mask 308 +#define REG_WR_ADDR_marb_bar_rw_stop_mask 308 + +/* Register r_stopped, scope marb_bar, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_r_stopped; +#define REG_RD_ADDR_marb_bar_r_stopped 312 + +/* Register rw_no_snoop, scope marb_bar, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_rw_no_snoop; +#define REG_RD_ADDR_marb_bar_rw_no_snoop 576 +#define REG_WR_ADDR_marb_bar_rw_no_snoop 576 + + +/* Constants */ +enum { + regk_marb_bar_ccd = 0x00000002, + regk_marb_bar_h264_rd = 0x00000000, + regk_marb_bar_h264_wr = 0x00000001, + regk_marb_bar_l2cache = 0x00000008, + regk_marb_bar_no = 0x00000000, + regk_marb_bar_r_stopped_default = 0x00000000, + regk_marb_bar_rw_ccd_burst_default = 0x00000000, + regk_marb_bar_rw_ddr2_slots_default = 0x00000000, + regk_marb_bar_rw_ddr2_slots_size = 0x00000040, + regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, + regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, + regk_marb_bar_rw_intr_mask_default = 0x00000000, + regk_marb_bar_rw_l2cache_burst_default = 0x00000000, + regk_marb_bar_rw_no_snoop_default = 0x00000000, + regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, + regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, + regk_marb_bar_rw_stop_mask_default = 0x00000000, + regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, + regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, + regk_marb_bar_rw_vout_burst_default = 0x00000000, + regk_marb_bar_sclr_fifo = 0x00000007, + regk_marb_bar_sclr_rd = 0x00000005, + regk_marb_bar_vin_rd = 0x00000004, + regk_marb_bar_vin_wr = 0x00000003, + regk_marb_bar_vout = 0x00000006, + regk_marb_bar_yes = 0x00000001 +}; +#endif /* __marb_bar_defs_h */ +#ifndef __marb_bar_bp_defs_h +#define __marb_bar_bp_defs_h + +/* + * This file is autogenerated from + * file: marb_bar.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bar_bp */ + +/* Register rw_first_addr, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bar_bp_rw_op; +#define REG_RD_ADDR_marb_bar_bp_rw_op 8 +#define REG_WR_ADDR_marb_bar_bp_rw_op 8 + +/* Register rw_clients, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_rw_clients; +#define REG_RD_ADDR_marb_bar_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bar_bp_rw_clients 12 + +/* Register rw_options, scope marb_bar_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bar_bp_rw_options; +#define REG_RD_ADDR_marb_bar_bp_rw_options 16 +#define REG_WR_ADDR_marb_bar_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bar_bp, type r */ +typedef unsigned int reg_marb_bar_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bar_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bar_bp_r_brk_op; +#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bar_bp, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bar_bp, type r */ +typedef struct { + unsigned int h264_rd : 1; + unsigned int h264_wr : 1; + unsigned int ccd : 1; + unsigned int vin_wr : 1; + unsigned int vin_rd : 1; + unsigned int sclr_rd : 1; + unsigned int vout : 1; + unsigned int sclr_fifo : 1; + unsigned int l2cache : 1; + unsigned int dummy1 : 23; +} reg_marb_bar_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bar_bp, type r */ +typedef unsigned int reg_marb_bar_bp_r_brk_size; +#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bar_bp, type rw */ +typedef unsigned int reg_marb_bar_bp_rw_ack; +#define REG_RD_ADDR_marb_bar_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bar_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bar_bp_no = 0x00000000, + regk_marb_bar_bp_rw_op_default = 0x00000000, + regk_marb_bar_bp_rw_options_default = 0x00000000, + regk_marb_bar_bp_yes = 0x00000001 +}; +#endif /* __marb_bar_bp_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h new file mode 100644 index 000000000..2baa833f1 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h @@ -0,0 +1,626 @@ +#ifndef __marb_foo_defs_h +#define __marb_foo_defs_h + +/* + * This file is autogenerated from + * file: marb_foo.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_foo */ + +#define STRIDE_marb_foo_rw_intm_slots 4 +/* Register rw_intm_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_intm_slots; +#define REG_RD_ADDR_marb_foo_rw_intm_slots 0 +#define REG_WR_ADDR_marb_foo_rw_intm_slots 0 + +#define STRIDE_marb_foo_rw_l2_slots 4 +/* Register rw_l2_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_l2_slots; +#define REG_RD_ADDR_marb_foo_rw_l2_slots 256 +#define REG_WR_ADDR_marb_foo_rw_l2_slots 256 + +#define STRIDE_marb_foo_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb_foo, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_regs_slots; +#define REG_RD_ADDR_marb_foo_rw_regs_slots 512 +#define REG_WR_ADDR_marb_foo_rw_regs_slots 512 + +/* Register rw_sclr_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_sclr_burst; +#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528 +#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528 + +/* Register rw_dma0_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma0_burst; +#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532 +#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532 + +/* Register rw_dma1_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma1_burst; +#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536 +#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536 + +/* Register rw_dma2_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma2_burst; +#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540 +#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540 + +/* Register rw_dma3_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma3_burst; +#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544 +#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544 + +/* Register rw_dma4_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma4_burst; +#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548 +#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548 + +/* Register rw_dma5_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma5_burst; +#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552 +#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552 + +/* Register rw_dma6_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma6_burst; +#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556 +#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556 + +/* Register rw_dma7_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma7_burst; +#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560 +#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560 + +/* Register rw_dma9_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma9_burst; +#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564 +#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564 + +/* Register rw_dma11_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_dma11_burst; +#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568 +#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568 + +/* Register rw_cpui_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_cpui_burst; +#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572 +#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572 + +/* Register rw_cpud_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_cpud_burst; +#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576 +#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576 + +/* Register rw_iop_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_iop_burst; +#define REG_RD_ADDR_marb_foo_rw_iop_burst 580 +#define REG_WR_ADDR_marb_foo_rw_iop_burst 580 + +/* Register rw_ccdstat_burst, scope marb_foo, type rw */ +typedef struct { + unsigned int intm_bsize : 2; + unsigned int l2_bsize : 2; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_ccdstat_burst; +#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584 +#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584 + +/* Register rw_intr_mask, scope marb_foo, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_intr_mask; +#define REG_RD_ADDR_marb_foo_rw_intr_mask 588 +#define REG_WR_ADDR_marb_foo_rw_intr_mask 588 + +/* Register rw_ack_intr, scope marb_foo, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_rw_ack_intr; +#define REG_RD_ADDR_marb_foo_rw_ack_intr 592 +#define REG_WR_ADDR_marb_foo_rw_ack_intr 592 + +/* Register r_intr, scope marb_foo, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_r_intr; +#define REG_RD_ADDR_marb_foo_r_intr 596 + +/* Register r_masked_intr, scope marb_foo, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_foo_r_masked_intr; +#define REG_RD_ADDR_marb_foo_r_masked_intr 600 + +/* Register rw_stop_mask, scope marb_foo, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_rw_stop_mask; +#define REG_RD_ADDR_marb_foo_rw_stop_mask 604 +#define REG_WR_ADDR_marb_foo_rw_stop_mask 604 + +/* Register r_stopped, scope marb_foo, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_r_stopped; +#define REG_RD_ADDR_marb_foo_r_stopped 608 + +/* Register rw_no_snoop, scope marb_foo, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_rw_no_snoop; +#define REG_RD_ADDR_marb_foo_rw_no_snoop 896 +#define REG_WR_ADDR_marb_foo_rw_no_snoop 896 + +/* Register rw_no_snoop_rq, scope marb_foo, type rw */ +typedef struct { + unsigned int dummy1 : 11; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 19; +} reg_marb_foo_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900 +#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900 + + +/* Constants */ +enum { + regk_marb_foo_ccdstat = 0x0000000e, + regk_marb_foo_cpud = 0x0000000c, + regk_marb_foo_cpui = 0x0000000b, + regk_marb_foo_dma0 = 0x00000001, + regk_marb_foo_dma1 = 0x00000002, + regk_marb_foo_dma11 = 0x0000000a, + regk_marb_foo_dma2 = 0x00000003, + regk_marb_foo_dma3 = 0x00000004, + regk_marb_foo_dma4 = 0x00000005, + regk_marb_foo_dma5 = 0x00000006, + regk_marb_foo_dma6 = 0x00000007, + regk_marb_foo_dma7 = 0x00000008, + regk_marb_foo_dma9 = 0x00000009, + regk_marb_foo_iop = 0x0000000d, + regk_marb_foo_no = 0x00000000, + regk_marb_foo_r_stopped_default = 0x00000000, + regk_marb_foo_rw_ccdstat_burst_default = 0x00000000, + regk_marb_foo_rw_cpud_burst_default = 0x00000000, + regk_marb_foo_rw_cpui_burst_default = 0x00000000, + regk_marb_foo_rw_dma0_burst_default = 0x00000000, + regk_marb_foo_rw_dma11_burst_default = 0x00000000, + regk_marb_foo_rw_dma1_burst_default = 0x00000000, + regk_marb_foo_rw_dma2_burst_default = 0x00000000, + regk_marb_foo_rw_dma3_burst_default = 0x00000000, + regk_marb_foo_rw_dma4_burst_default = 0x00000000, + regk_marb_foo_rw_dma5_burst_default = 0x00000000, + regk_marb_foo_rw_dma6_burst_default = 0x00000000, + regk_marb_foo_rw_dma7_burst_default = 0x00000000, + regk_marb_foo_rw_dma9_burst_default = 0x00000000, + regk_marb_foo_rw_intm_slots_default = 0x00000000, + regk_marb_foo_rw_intm_slots_size = 0x00000040, + regk_marb_foo_rw_intr_mask_default = 0x00000000, + regk_marb_foo_rw_iop_burst_default = 0x00000000, + regk_marb_foo_rw_l2_slots_default = 0x00000000, + regk_marb_foo_rw_l2_slots_size = 0x00000040, + regk_marb_foo_rw_no_snoop_default = 0x00000000, + regk_marb_foo_rw_no_snoop_rq_default = 0x00000000, + regk_marb_foo_rw_regs_slots_default = 0x00000000, + regk_marb_foo_rw_regs_slots_size = 0x00000004, + regk_marb_foo_rw_sclr_burst_default = 0x00000000, + regk_marb_foo_rw_stop_mask_default = 0x00000000, + regk_marb_foo_sclr = 0x00000000, + regk_marb_foo_yes = 0x00000001 +}; +#endif /* __marb_foo_defs_h */ +#ifndef __marb_foo_bp_defs_h +#define __marb_foo_bp_defs_h + +/* + * This file is autogenerated from + * file: marb_foo.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_foo_bp */ + +/* Register rw_first_addr, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_first_addr; +#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_last_addr; +#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_foo_bp_rw_op; +#define REG_RD_ADDR_marb_foo_bp_rw_op 8 +#define REG_WR_ADDR_marb_foo_bp_rw_op 8 + +/* Register rw_clients, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_rw_clients; +#define REG_RD_ADDR_marb_foo_bp_rw_clients 12 +#define REG_WR_ADDR_marb_foo_bp_rw_clients 12 + +/* Register rw_options, scope marb_foo_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_foo_bp_rw_options; +#define REG_RD_ADDR_marb_foo_bp_rw_options 16 +#define REG_WR_ADDR_marb_foo_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_foo_bp, type r */ +typedef unsigned int reg_marb_foo_bp_r_brk_addr; +#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_foo_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_foo_bp_r_brk_op; +#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_foo_bp, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_r_brk_clients; +#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_foo_bp, type r */ +typedef struct { + unsigned int sclr : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma9 : 1; + unsigned int dma11 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int ccdstat : 1; + unsigned int dummy1 : 17; +} reg_marb_foo_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_foo_bp, type r */ +typedef unsigned int reg_marb_foo_bp_r_brk_size; +#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_foo_bp, type rw */ +typedef unsigned int reg_marb_foo_bp_rw_ack; +#define REG_RD_ADDR_marb_foo_bp_rw_ack 40 +#define REG_WR_ADDR_marb_foo_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_foo_bp_no = 0x00000000, + regk_marb_foo_bp_rw_op_default = 0x00000000, + regk_marb_foo_bp_rw_options_default = 0x00000000, + regk_marb_foo_bp_yes = 0x00000001 +}; +#endif /* __marb_foo_bp_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h new file mode 100644 index 000000000..4b96cd2cb --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h @@ -0,0 +1,312 @@ +#ifndef __pinmux_defs_h +#define __pinmux_defs_h + +/* + * This file is autogenerated from + * file: pinmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pinmux */ + +/* Register rw_hwprot, scope pinmux, type rw */ +typedef struct { + unsigned int eth : 1; + unsigned int eth_mdio : 1; + unsigned int geth : 1; + unsigned int tg : 1; + unsigned int tg_clk : 1; + unsigned int vout : 1; + unsigned int vout_sync : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int ser4 : 1; + unsigned int sser : 1; + unsigned int pwm0 : 1; + unsigned int pwm1 : 1; + unsigned int pwm2 : 1; + unsigned int timer0 : 1; + unsigned int timer1 : 1; + unsigned int pio : 1; + unsigned int i2c0 : 1; + unsigned int i2c1 : 1; + unsigned int i2c1_sda1 : 1; + unsigned int i2c1_sda2 : 1; + unsigned int i2c1_sda3 : 1; + unsigned int i2c1_sen : 1; + unsigned int dummy1 : 8; +} reg_pinmux_rw_hwprot; +#define REG_RD_ADDR_pinmux_rw_hwprot 0 +#define REG_WR_ADDR_pinmux_rw_hwprot 0 + +/* Register rw_gio_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int pa8 : 1; + unsigned int pa9 : 1; + unsigned int pa10 : 1; + unsigned int pa11 : 1; + unsigned int pa12 : 1; + unsigned int pa13 : 1; + unsigned int pa14 : 1; + unsigned int pa15 : 1; + unsigned int pa16 : 1; + unsigned int pa17 : 1; + unsigned int pa18 : 1; + unsigned int pa19 : 1; + unsigned int pa20 : 1; + unsigned int pa21 : 1; + unsigned int pa22 : 1; + unsigned int pa23 : 1; + unsigned int pa24 : 1; + unsigned int pa25 : 1; + unsigned int pa26 : 1; + unsigned int pa27 : 1; + unsigned int pa28 : 1; + unsigned int pa29 : 1; + unsigned int pa30 : 1; + unsigned int pa31 : 1; +} reg_pinmux_rw_gio_pa; +#define REG_RD_ADDR_pinmux_rw_gio_pa 4 +#define REG_WR_ADDR_pinmux_rw_gio_pa 4 + +/* Register rw_gio_pb, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int pb18 : 1; + unsigned int pb19 : 1; + unsigned int pb20 : 1; + unsigned int pb21 : 1; + unsigned int pb22 : 1; + unsigned int pb23 : 1; + unsigned int pb24 : 1; + unsigned int pb25 : 1; + unsigned int pb26 : 1; + unsigned int pb27 : 1; + unsigned int pb28 : 1; + unsigned int pb29 : 1; + unsigned int pb30 : 1; + unsigned int pb31 : 1; +} reg_pinmux_rw_gio_pb; +#define REG_RD_ADDR_pinmux_rw_gio_pb 8 +#define REG_WR_ADDR_pinmux_rw_gio_pb 8 + +/* Register rw_gio_pc, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_gio_pc; +#define REG_RD_ADDR_pinmux_rw_gio_pc 12 +#define REG_WR_ADDR_pinmux_rw_gio_pc 12 + +/* Register rw_iop_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int pa8 : 1; + unsigned int pa9 : 1; + unsigned int pa10 : 1; + unsigned int pa11 : 1; + unsigned int pa12 : 1; + unsigned int pa13 : 1; + unsigned int pa14 : 1; + unsigned int pa15 : 1; + unsigned int pa16 : 1; + unsigned int pa17 : 1; + unsigned int pa18 : 1; + unsigned int pa19 : 1; + unsigned int pa20 : 1; + unsigned int pa21 : 1; + unsigned int pa22 : 1; + unsigned int pa23 : 1; + unsigned int pa24 : 1; + unsigned int pa25 : 1; + unsigned int pa26 : 1; + unsigned int pa27 : 1; + unsigned int pa28 : 1; + unsigned int pa29 : 1; + unsigned int pa30 : 1; + unsigned int pa31 : 1; +} reg_pinmux_rw_iop_pa; +#define REG_RD_ADDR_pinmux_rw_iop_pa 16 +#define REG_WR_ADDR_pinmux_rw_iop_pa 16 + +/* Register rw_iop_pb, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int dummy1 : 24; +} reg_pinmux_rw_iop_pb; +#define REG_RD_ADDR_pinmux_rw_iop_pb 20 +#define REG_WR_ADDR_pinmux_rw_iop_pb 20 + +/* Register rw_iop_pio, scope pinmux, type rw */ +typedef struct { + unsigned int d0 : 1; + unsigned int d1 : 1; + unsigned int d2 : 1; + unsigned int d3 : 1; + unsigned int d4 : 1; + unsigned int d5 : 1; + unsigned int d6 : 1; + unsigned int d7 : 1; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_iop_pio; +#define REG_RD_ADDR_pinmux_rw_iop_pio 24 +#define REG_WR_ADDR_pinmux_rw_iop_pio 24 + +/* Register rw_iop_usb, scope pinmux, type rw */ +typedef struct { + unsigned int usb0 : 1; + unsigned int dummy1 : 31; +} reg_pinmux_rw_iop_usb; +#define REG_RD_ADDR_pinmux_rw_iop_usb 28 +#define REG_WR_ADDR_pinmux_rw_iop_usb 28 + + +/* Constants */ +enum { + regk_pinmux_no = 0x00000000, + regk_pinmux_rw_gio_pa_default = 0x00000000, + regk_pinmux_rw_gio_pb_default = 0x00000000, + regk_pinmux_rw_gio_pc_default = 0x00000000, + regk_pinmux_rw_hwprot_default = 0x00000000, + regk_pinmux_rw_iop_pa_default = 0x00000000, + regk_pinmux_rw_iop_pb_default = 0x00000000, + regk_pinmux_rw_iop_pio_default = 0x00000000, + regk_pinmux_rw_iop_usb_default = 0x00000001, + regk_pinmux_yes = 0x00000001 +}; +#endif /* __pinmux_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h new file mode 100644 index 000000000..2d8e4b4cc --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h @@ -0,0 +1,371 @@ +#ifndef __pio_defs_h +#define __pio_defs_h + +/* + * This file is autogenerated from + * file: pio.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pio */ + +/* Register rw_data, scope pio, type rw */ +typedef unsigned int reg_pio_rw_data; +#define REG_RD_ADDR_pio_rw_data 64 +#define REG_WR_ADDR_pio_rw_data 64 + +/* Register rw_io_access0, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access0; +#define REG_RD_ADDR_pio_rw_io_access0 0 +#define REG_WR_ADDR_pio_rw_io_access0 0 + +/* Register rw_io_access1, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access1; +#define REG_RD_ADDR_pio_rw_io_access1 4 +#define REG_WR_ADDR_pio_rw_io_access1 4 + +/* Register rw_io_access2, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access2; +#define REG_RD_ADDR_pio_rw_io_access2 8 +#define REG_WR_ADDR_pio_rw_io_access2 8 + +/* Register rw_io_access3, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access3; +#define REG_RD_ADDR_pio_rw_io_access3 12 +#define REG_WR_ADDR_pio_rw_io_access3 12 + +/* Register rw_io_access4, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access4; +#define REG_RD_ADDR_pio_rw_io_access4 16 +#define REG_WR_ADDR_pio_rw_io_access4 16 + +/* Register rw_io_access5, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access5; +#define REG_RD_ADDR_pio_rw_io_access5 20 +#define REG_WR_ADDR_pio_rw_io_access5 20 + +/* Register rw_io_access6, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access6; +#define REG_RD_ADDR_pio_rw_io_access6 24 +#define REG_WR_ADDR_pio_rw_io_access6 24 + +/* Register rw_io_access7, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access7; +#define REG_RD_ADDR_pio_rw_io_access7 28 +#define REG_WR_ADDR_pio_rw_io_access7 28 + +/* Register rw_io_access8, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access8; +#define REG_RD_ADDR_pio_rw_io_access8 32 +#define REG_WR_ADDR_pio_rw_io_access8 32 + +/* Register rw_io_access9, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access9; +#define REG_RD_ADDR_pio_rw_io_access9 36 +#define REG_WR_ADDR_pio_rw_io_access9 36 + +/* Register rw_io_access10, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access10; +#define REG_RD_ADDR_pio_rw_io_access10 40 +#define REG_WR_ADDR_pio_rw_io_access10 40 + +/* Register rw_io_access11, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access11; +#define REG_RD_ADDR_pio_rw_io_access11 44 +#define REG_WR_ADDR_pio_rw_io_access11 44 + +/* Register rw_io_access12, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access12; +#define REG_RD_ADDR_pio_rw_io_access12 48 +#define REG_WR_ADDR_pio_rw_io_access12 48 + +/* Register rw_io_access13, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access13; +#define REG_RD_ADDR_pio_rw_io_access13 52 +#define REG_WR_ADDR_pio_rw_io_access13 52 + +/* Register rw_io_access14, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access14; +#define REG_RD_ADDR_pio_rw_io_access14 56 +#define REG_WR_ADDR_pio_rw_io_access14 56 + +/* Register rw_io_access15, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_pio_rw_io_access15; +#define REG_RD_ADDR_pio_rw_io_access15 60 +#define REG_WR_ADDR_pio_rw_io_access15 60 + +/* Register rw_ce0_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce0_cfg; +#define REG_RD_ADDR_pio_rw_ce0_cfg 68 +#define REG_WR_ADDR_pio_rw_ce0_cfg 68 + +/* Register rw_ce1_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce1_cfg; +#define REG_RD_ADDR_pio_rw_ce1_cfg 72 +#define REG_WR_ADDR_pio_rw_ce1_cfg 72 + +/* Register rw_ce2_cfg, scope pio, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int mode : 2; + unsigned int dummy1 : 16; +} reg_pio_rw_ce2_cfg; +#define REG_RD_ADDR_pio_rw_ce2_cfg 76 +#define REG_WR_ADDR_pio_rw_ce2_cfg 76 + +/* Register rw_dout, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_dout; +#define REG_RD_ADDR_pio_rw_dout 80 +#define REG_WR_ADDR_pio_rw_dout 80 + +/* Register rw_oe, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_oe; +#define REG_RD_ADDR_pio_rw_oe 84 +#define REG_WR_ADDR_pio_rw_oe 84 + +/* Register rw_man_ctrl, scope pio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_rw_man_ctrl; +#define REG_RD_ADDR_pio_rw_man_ctrl 88 +#define REG_WR_ADDR_pio_rw_man_ctrl 88 + +/* Register r_din, scope pio, type r */ +typedef struct { + unsigned int data : 8; + unsigned int rd_n : 1; + unsigned int wr_n : 1; + unsigned int a0 : 1; + unsigned int a1 : 1; + unsigned int ce0_n : 1; + unsigned int ce1_n : 1; + unsigned int ce2_n : 1; + unsigned int rdy : 1; + unsigned int dummy1 : 16; +} reg_pio_r_din; +#define REG_RD_ADDR_pio_r_din 92 + +/* Register r_stat, scope pio, type r */ +typedef struct { + unsigned int busy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_stat; +#define REG_RD_ADDR_pio_r_stat 96 + +/* Register rw_intr_mask, scope pio, type rw */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_rw_intr_mask; +#define REG_RD_ADDR_pio_rw_intr_mask 100 +#define REG_WR_ADDR_pio_rw_intr_mask 100 + +/* Register rw_ack_intr, scope pio, type rw */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_rw_ack_intr; +#define REG_RD_ADDR_pio_rw_ack_intr 104 +#define REG_WR_ADDR_pio_rw_ack_intr 104 + +/* Register r_intr, scope pio, type r */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_intr; +#define REG_RD_ADDR_pio_r_intr 108 + +/* Register r_masked_intr, scope pio, type r */ +typedef struct { + unsigned int rdy : 1; + unsigned int dummy1 : 31; +} reg_pio_r_masked_intr; +#define REG_RD_ADDR_pio_r_masked_intr 112 + + +/* Constants */ +enum { + regk_pio_a2 = 0x00000003, + regk_pio_no = 0x00000000, + regk_pio_normal = 0x00000000, + regk_pio_rd = 0x00000001, + regk_pio_rw_ce0_cfg_default = 0x00000000, + regk_pio_rw_ce1_cfg_default = 0x00000000, + regk_pio_rw_ce2_cfg_default = 0x00000000, + regk_pio_rw_intr_mask_default = 0x00000000, + regk_pio_rw_man_ctrl_default = 0x00000000, + regk_pio_rw_oe_default = 0x00000000, + regk_pio_wr = 0x00000002, + regk_pio_wr_ce2 = 0x00000003, + regk_pio_yes = 0x00000001, + regk_pio_yes_all = 0x000000ff +}; +#endif /* __pio_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h new file mode 100644 index 000000000..36e59d6e9 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h @@ -0,0 +1,103 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: reg.rmap + * + * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +typedef enum { + regi_ccd = 0xb0000000, + regi_ccd_top = 0xb0000000, + regi_ccd_dp = 0xb0000400, + regi_ccd_stat = 0xb0000800, + regi_ccd_tg = 0xb0001000, + regi_cfg = 0xb0002000, + regi_clkgen = 0xb0004000, + regi_ddr2_ctrl = 0xb0006000, + regi_dma0 = 0xb0008000, + regi_dma1 = 0xb000a000, + regi_dma11 = 0xb000c000, + regi_dma2 = 0xb000e000, + regi_dma3 = 0xb0010000, + regi_dma4 = 0xb0012000, + regi_dma5 = 0xb0014000, + regi_dma6 = 0xb0016000, + regi_dma7 = 0xb0018000, + regi_dma9 = 0xb001a000, + regi_eth = 0xb001c000, + regi_gio = 0xb0020000, + regi_h264 = 0xb0022000, + regi_hist = 0xb0026000, + regi_iop = 0xb0028000, + regi_iop_version = 0xb0028000, + regi_iop_fifo_in_extra = 0xb0028040, + regi_iop_fifo_out_extra = 0xb0028080, + regi_iop_trigger_grp0 = 0xb00280c0, + regi_iop_trigger_grp1 = 0xb0028100, + regi_iop_trigger_grp2 = 0xb0028140, + regi_iop_trigger_grp3 = 0xb0028180, + regi_iop_trigger_grp4 = 0xb00281c0, + regi_iop_trigger_grp5 = 0xb0028200, + regi_iop_trigger_grp6 = 0xb0028240, + regi_iop_trigger_grp7 = 0xb0028280, + regi_iop_crc_par = 0xb0028300, + regi_iop_dmc_in = 0xb0028380, + regi_iop_dmc_out = 0xb0028400, + regi_iop_fifo_in = 0xb0028480, + regi_iop_fifo_out = 0xb0028500, + regi_iop_scrc_in = 0xb0028580, + regi_iop_scrc_out = 0xb0028600, + regi_iop_timer_grp0 = 0xb0028680, + regi_iop_timer_grp1 = 0xb0028700, + regi_iop_sap_in = 0xb0028800, + regi_iop_sap_out = 0xb0028900, + regi_iop_spu = 0xb0028a00, + regi_iop_sw_cfg = 0xb0028b00, + regi_iop_sw_cpu = 0xb0028c00, + regi_iop_sw_mpu = 0xb0028d00, + regi_iop_sw_spu = 0xb0028e00, + regi_iop_mpu = 0xb0029000, + regi_irq = 0xb002a000, + regi_irq2 = 0xb006a000, + regi_jpeg = 0xb002c000, + regi_l2cache = 0xb0030000, + regi_marb_bar = 0xb0032000, + regi_marb_bar_bp0 = 0xb0032140, + regi_marb_bar_bp1 = 0xb0032180, + regi_marb_bar_bp2 = 0xb00321c0, + regi_marb_bar_bp3 = 0xb0032200, + regi_marb_foo = 0xb0034000, + regi_marb_foo_bp0 = 0xb0034280, + regi_marb_foo_bp1 = 0xb00342c0, + regi_marb_foo_bp2 = 0xb0034300, + regi_marb_foo_bp3 = 0xb0034340, + regi_pinmux = 0xb0038000, + regi_pio = 0xb0036000, + regi_sclr = 0xb003a000, + regi_sclr_fifo = 0xb003c000, + regi_ser0 = 0xb003e000, + regi_ser1 = 0xb0040000, + regi_ser2 = 0xb0042000, + regi_ser3 = 0xb0044000, + regi_ser4 = 0xb0046000, + regi_sser = 0xb0048000, + regi_strcop = 0xb004a000, + regi_strdma0 = 0xb004e000, + regi_strdma1 = 0xb0050000, + regi_strdma2 = 0xb0052000, + regi_strdma3 = 0xb0054000, + regi_strdma5 = 0xb0056000, + regi_strmux = 0xb004c000, + regi_timer0 = 0xb0058000, + regi_timer1 = 0xb005a000, + regi_timer2 = 0xb006e000, + regi_trace = 0xb005c000, + regi_vin = 0xb005e000, + regi_vout = 0xb0060000 +} reg_scope_instances; +#endif /* __reg_map_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h new file mode 100644 index 000000000..14f718a4e --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h @@ -0,0 +1,120 @@ +#ifndef __strmux_defs_h +#define __strmux_defs_h + +/* + * This file is autogenerated from + * file: strmux.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strmux */ + +/* Register rw_cfg, scope strmux, type rw */ +typedef struct { + unsigned int dma0 : 2; + unsigned int dma1 : 2; + unsigned int dma2 : 2; + unsigned int dma3 : 2; + unsigned int dma4 : 2; + unsigned int dma5 : 2; + unsigned int dma6 : 2; + unsigned int dma7 : 2; + unsigned int dummy1 : 2; + unsigned int dma9 : 2; + unsigned int dummy2 : 2; + unsigned int dma11 : 2; + unsigned int dummy3 : 8; +} reg_strmux_rw_cfg; +#define REG_RD_ADDR_strmux_rw_cfg 0 +#define REG_WR_ADDR_strmux_rw_cfg 0 + + +/* Constants */ +enum { + regk_strmux_eth = 0x00000001, + regk_strmux_h264 = 0x00000001, + regk_strmux_iop = 0x00000001, + regk_strmux_jpeg = 0x00000001, + regk_strmux_off = 0x00000000, + regk_strmux_rw_cfg_default = 0x00000000, + regk_strmux_ser0 = 0x00000002, + regk_strmux_ser1 = 0x00000002, + regk_strmux_ser2 = 0x00000002, + regk_strmux_ser3 = 0x00000002, + regk_strmux_ser4 = 0x00000002, + regk_strmux_sser = 0x00000001, + regk_strmux_strcop = 0x00000001 +}; +#endif /* __strmux_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h new file mode 100644 index 000000000..2c33e097d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h @@ -0,0 +1,265 @@ +#ifndef __timer_defs_h +#define __timer_defs_h + +/* + * This file is autogenerated from + * file: timer.r + * + * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope timer */ + +/* Register rw_tmr0_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr0_div; +#define REG_RD_ADDR_timer_rw_tmr0_div 0 +#define REG_WR_ADDR_timer_rw_tmr0_div 0 + +/* Register r_tmr0_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr0_data; +#define REG_RD_ADDR_timer_r_tmr0_data 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr0_ctrl; +#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 +#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr1_div; +#define REG_RD_ADDR_timer_rw_tmr1_div 16 +#define REG_WR_ADDR_timer_rw_tmr1_div 16 + +/* Register r_tmr1_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr1_data; +#define REG_RD_ADDR_timer_r_tmr1_data 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr1_ctrl; +#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 +#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 + +/* Register rs_cnt_data, scope timer, type rs */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_rs_cnt_data; +#define REG_RD_ADDR_timer_rs_cnt_data 32 + +/* Register r_cnt_data, scope timer, type r */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_r_cnt_data; +#define REG_RD_ADDR_timer_r_cnt_data 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +typedef struct { + unsigned int clk : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_cnt_cfg; +#define REG_RD_ADDR_timer_rw_cnt_cfg 40 +#define REG_WR_ADDR_timer_rw_cnt_cfg 40 + +/* Register rw_trig, scope timer, type rw */ +typedef unsigned int reg_timer_rw_trig; +#define REG_RD_ADDR_timer_rw_trig 48 +#define REG_WR_ADDR_timer_rw_trig 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_trig_cfg; +#define REG_RD_ADDR_timer_rw_trig_cfg 52 +#define REG_WR_ADDR_timer_rw_trig_cfg 52 + +/* Register r_time, scope timer, type r */ +typedef unsigned int reg_timer_r_time; +#define REG_RD_ADDR_timer_r_time 56 + +/* Register rw_out, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_out; +#define REG_RD_ADDR_timer_rw_out 60 +#define REG_WR_ADDR_timer_rw_out 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int key : 7; + unsigned int dummy1 : 16; +} reg_timer_rw_wd_ctrl; +#define REG_RD_ADDR_timer_rw_wd_ctrl 64 +#define REG_WR_ADDR_timer_rw_wd_ctrl 64 + +/* Register r_wd_stat, scope timer, type r */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int dummy1 : 23; +} reg_timer_r_wd_stat; +#define REG_RD_ADDR_timer_r_wd_stat 68 + +/* Register rw_intr_mask, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_intr_mask; +#define REG_RD_ADDR_timer_rw_intr_mask 72 +#define REG_WR_ADDR_timer_rw_intr_mask 72 + +/* Register rw_ack_intr, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_ack_intr; +#define REG_RD_ADDR_timer_rw_ack_intr 76 +#define REG_WR_ADDR_timer_rw_ack_intr 76 + +/* Register r_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_intr; +#define REG_RD_ADDR_timer_r_intr 80 + +/* Register r_masked_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_masked_intr; +#define REG_RD_ADDR_timer_r_masked_intr 84 + +/* Register rw_test, scope timer, type rw */ +typedef struct { + unsigned int dis : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_timer_rw_test; +#define REG_RD_ADDR_timer_rw_test 88 +#define REG_WR_ADDR_timer_rw_test 88 + + +/* Constants */ +enum { + regk_timer_ext = 0x00000001, + regk_timer_f100 = 0x00000007, + regk_timer_f29_493 = 0x00000004, + regk_timer_f32 = 0x00000005, + regk_timer_f32_768 = 0x00000006, + regk_timer_f90 = 0x00000003, + regk_timer_hold = 0x00000001, + regk_timer_ld = 0x00000000, + regk_timer_no = 0x00000000, + regk_timer_off = 0x00000000, + regk_timer_run = 0x00000002, + regk_timer_rw_cnt_cfg_default = 0x00000000, + regk_timer_rw_intr_mask_default = 0x00000000, + regk_timer_rw_out_default = 0x00000000, + regk_timer_rw_test_default = 0x00000000, + regk_timer_rw_tmr0_ctrl_default = 0x00000000, + regk_timer_rw_tmr1_ctrl_default = 0x00000000, + regk_timer_rw_trig_cfg_default = 0x00000000, + regk_timer_start = 0x00000001, + regk_timer_stop = 0x00000000, + regk_timer_time = 0x00000001, + regk_timer_tmr0 = 0x00000002, + regk_timer_tmr1 = 0x00000003, + regk_timer_vclk = 0x00000002, + regk_timer_yes = 0x00000001 +}; +#endif /* __timer_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/memmap.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/memmap.h new file mode 100644 index 000000000..7e15c9eb4 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/memmap.h @@ -0,0 +1,10 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_INTMEM_START (0x38000000) +#define MEM_INTMEM_SIZE (0x00018000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h b/kernel/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h new file mode 100644 index 000000000..db42a7254 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h @@ -0,0 +1,45 @@ +#ifndef _ASM_CRIS_ARCH_PINMUX_H +#define _ASM_CRIS_ARCH_PINMUX_H + +#define PORT_A 0 +#define PORT_B 1 +#define PORT_C 2 + +enum pin_mode { + pinmux_none = 0, + pinmux_fixed, + pinmux_gpio, + pinmux_iop +}; + +enum fixed_function { + pinmux_eth, + pinmux_geth, + pinmux_tg_ccd, + pinmux_tg_cmos, + pinmux_vout, + pinmux_ser1, + pinmux_ser2, + pinmux_ser3, + pinmux_ser4, + pinmux_sser, + pinmux_pio, + pinmux_pwm0, + pinmux_pwm1, + pinmux_pwm2, + pinmux_i2c0, + pinmux_i2c1, + pinmux_i2c1_3wire, + pinmux_i2c1_sda1, + pinmux_i2c1_sda2, + pinmux_i2c1_sda3, +}; + +int crisv32_pinmux_init(void); +int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); +int crisv32_pinmux_alloc_fixed(enum fixed_function function); +int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); +int crisv32_pinmux_dealloc_fixed(enum fixed_function function); +void crisv32_pinmux_dump(void); + +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-a3/mach/startup.inc b/kernel/arch/cris/include/arch-v32/mach-a3/mach/startup.inc new file mode 100644 index 000000000..2d52bcc96 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-a3/mach/startup.inc @@ -0,0 +1,84 @@ +#ifndef STARTUP_INC_INCLUDED +#define STARTUP_INC_INCLUDED + +#include +#include +#include +#include +#include + + .macro GIO_SET_P BITS, OUTREG + bmi 1f ; btstq: bit -> N flag + nop + or.d \BITS, \OUTREG +1: + .endm + + .macro GIO_INIT + move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 + move.d $r0, [$r1] + + move.d 0xFFFFFFFF, $r0 + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 + move.d $r0, [$r1] + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 + move.d $r0, [$r1] + + ;; If eth_mdio, eth, geth bits are set in hwprot, don't + ;; set them to gpio, as this means they have been configured + ;; earlier and shouldn't be changed. + move.d 0xFC000000, $r2 ; pins 25..0 are eth_mdio, eth, geth + move.d REG_ADDR(pinmux, regi_pinmux, rw_hwprot), $r1 + move.d [$r1], $r0 + btstq REG_BIT(pinmux, rw_hwprot, eth), $r0 + GIO_SET_P 0x00FFFF00, $r2 ;; pins 8..23 are eth + btstq REG_BIT(pinmux, rw_hwprot, eth_mdio), $r0 + GIO_SET_P 0x03000000, $r2 ;; pins 24..25 are eth_mdio + btstq REG_BIT(pinmux, rw_hwprot, geth), $r0 + GIO_SET_P 0x000000FF, $r2 ;; pins 0..7 are geth + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 + move.d $r2, [$r1] + .endm + + .macro START_CLOCKS + move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 + move.d [$r1], $r0 + or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ + REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ + REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 + move.d $r0, [$r1] + .endm + + .macro SETUP_WAIT_STATES + move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 + move.d $r1, [$r0] + .endm +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h new file mode 100644 index 000000000..a2e0ec8fa --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h @@ -0,0 +1,28 @@ +#ifndef _ASM_CRIS_ARCH_ARBITER_H +#define _ASM_CRIS_ARCH_ARBITER_H + +#define EXT_REGION 0 +#define INT_REGION 1 + +typedef void (watch_callback)(void); + +enum { + arbiter_all_dmas = 0x3ff, + arbiter_cpu = 0xc00, + arbiter_all_clients = 0x3fff +}; + +enum { + arbiter_all_read = 0x55, + arbiter_all_write = 0xaa, + arbiter_all_accesses = 0xff +}; + +int crisv32_arbiter_allocate_bandwidth(int client, int region, + unsigned long bandwidth); +int crisv32_arbiter_watch(unsigned long start, unsigned long size, + unsigned long clients, unsigned long accesses, + watch_callback * cb); +int crisv32_arbiter_unwatch(int id); + +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/dma.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/dma.h new file mode 100644 index 000000000..a8c592925 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/dma.h @@ -0,0 +1,79 @@ +#ifndef _ASM_ARCH_CRIS_DMA_H +#define _ASM_ARCH_CRIS_DMA_H + +/* Defines for using and allocating dma channels. */ + +#define MAX_DMA_CHANNELS 10 + +#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ +#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ + +#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ +#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ + +#define ATA_TX_DMA_NBR 2 /* ATA interface out. */ +#define ATA_RX_DMA_NBR 3 /* ATA interface in. */ + +#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ +#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ + +#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ +#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ + +#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ +#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ + +#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ +#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ + +#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ +#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ + +#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ +#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ + +#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ +#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ + +#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ +#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ + +#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ +#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ + +#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ +#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ + +#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ +#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ + +enum dma_owner { + dma_eth0, + dma_eth1, + dma_iop0, + dma_iop1, + dma_ser0, + dma_ser1, + dma_ser2, + dma_ser3, + dma_sser0, + dma_sser1, + dma_ata, + dma_strp, + dma_ext0, + dma_ext1, + dma_ext2, + dma_ext3 +}; + +int crisv32_request_dma(unsigned int dmanr, const char *device_id, + unsigned options, unsigned bandwidth, + enum dma_owner owner); +void crisv32_free_dma(unsigned int dmanr); + +/* Masks used by crisv32_request_dma options: */ +#define DMA_VERBOSE_ON_ERROR 1 +#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) +#define DMA_INT_MEM 4 + +#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h new file mode 100644 index 000000000..0a409c928 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h @@ -0,0 +1,319 @@ +#ifndef __bif_core_defs_asm_h +#define __bif_core_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp1_cfg___lw___width 6 +#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp1_cfg___ew___width 3 +#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp1_cfg___zw___width 3 +#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp1_cfg___aw___width 2 +#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp1_cfg___dw___width 2 +#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp1_cfg___ewb___width 2 +#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp1_cfg___bw___width 1 +#define reg_bif_core_rw_grp1_cfg___bw___bit 18 +#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp1_cfg___mode___width 1 +#define reg_bif_core_rw_grp1_cfg___mode___bit 21 +#define reg_bif_core_rw_grp1_cfg_offset 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp2_cfg___lw___width 6 +#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp2_cfg___ew___width 3 +#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp2_cfg___zw___width 3 +#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp2_cfg___aw___width 2 +#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp2_cfg___dw___width 2 +#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp2_cfg___ewb___width 2 +#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp2_cfg___bw___width 1 +#define reg_bif_core_rw_grp2_cfg___bw___bit 18 +#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp2_cfg___mode___width 1 +#define reg_bif_core_rw_grp2_cfg___mode___bit 21 +#define reg_bif_core_rw_grp2_cfg_offset 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp3_cfg___lw___width 6 +#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp3_cfg___ew___width 3 +#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp3_cfg___zw___width 3 +#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp3_cfg___aw___width 2 +#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp3_cfg___dw___width 2 +#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp3_cfg___ewb___width 2 +#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp3_cfg___bw___width 1 +#define reg_bif_core_rw_grp3_cfg___bw___bit 18 +#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp3_cfg___mode___width 1 +#define reg_bif_core_rw_grp3_cfg___mode___bit 21 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 +#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 +#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 +#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 +#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 +#define reg_bif_core_rw_grp3_cfg_offset 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 +#define reg_bif_core_rw_grp4_cfg___lw___width 6 +#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 +#define reg_bif_core_rw_grp4_cfg___ew___width 3 +#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 +#define reg_bif_core_rw_grp4_cfg___zw___width 3 +#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 +#define reg_bif_core_rw_grp4_cfg___aw___width 2 +#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 +#define reg_bif_core_rw_grp4_cfg___dw___width 2 +#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 +#define reg_bif_core_rw_grp4_cfg___ewb___width 2 +#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 +#define reg_bif_core_rw_grp4_cfg___bw___width 1 +#define reg_bif_core_rw_grp4_cfg___bw___bit 18 +#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 +#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 +#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 +#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 +#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 +#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 +#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 +#define reg_bif_core_rw_grp4_cfg___mode___width 1 +#define reg_bif_core_rw_grp4_cfg___mode___bit 21 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 +#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 +#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 +#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 +#define reg_bif_core_rw_grp4_cfg_offset 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 +#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 +#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 +#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 +#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 +#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 +#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 +#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_timing___cl___lsb 0 +#define reg_bif_core_rw_sdram_timing___cl___width 3 +#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 +#define reg_bif_core_rw_sdram_timing___rcd___width 3 +#define reg_bif_core_rw_sdram_timing___rp___lsb 6 +#define reg_bif_core_rw_sdram_timing___rp___width 3 +#define reg_bif_core_rw_sdram_timing___rc___lsb 9 +#define reg_bif_core_rw_sdram_timing___rc___width 2 +#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 +#define reg_bif_core_rw_sdram_timing___dpl___width 2 +#define reg_bif_core_rw_sdram_timing___pde___lsb 13 +#define reg_bif_core_rw_sdram_timing___pde___width 1 +#define reg_bif_core_rw_sdram_timing___pde___bit 13 +#define reg_bif_core_rw_sdram_timing___ref___lsb 14 +#define reg_bif_core_rw_sdram_timing___ref___width 2 +#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 +#define reg_bif_core_rw_sdram_timing___cpd___width 1 +#define reg_bif_core_rw_sdram_timing___cpd___bit 16 +#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 +#define reg_bif_core_rw_sdram_timing___sdcke___width 1 +#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 +#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 +#define reg_bif_core_rw_sdram_timing___sdclk___width 1 +#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 +#define reg_bif_core_rw_sdram_timing_offset 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 +#define reg_bif_core_rw_sdram_cmd___cmd___width 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 +#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 +#define reg_bif_core_rw_sdram_cmd_offset 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 +#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_rs_sdram_ref_stat_offset 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 +#define reg_bif_core_r_sdram_ref_stat___ok___width 1 +#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 +#define reg_bif_core_r_sdram_ref_stat_offset 36 + + +/* Constants */ +#define regk_bif_core_bank2 0x00000000 +#define regk_bif_core_bank4 0x00000001 +#define regk_bif_core_bit10 0x0000000a +#define regk_bif_core_bit11 0x0000000b +#define regk_bif_core_bit12 0x0000000c +#define regk_bif_core_bit13 0x0000000d +#define regk_bif_core_bit14 0x0000000e +#define regk_bif_core_bit15 0x0000000f +#define regk_bif_core_bit16 0x00000010 +#define regk_bif_core_bit17 0x00000011 +#define regk_bif_core_bit18 0x00000012 +#define regk_bif_core_bit19 0x00000013 +#define regk_bif_core_bit20 0x00000014 +#define regk_bif_core_bit21 0x00000015 +#define regk_bif_core_bit22 0x00000016 +#define regk_bif_core_bit23 0x00000017 +#define regk_bif_core_bit24 0x00000018 +#define regk_bif_core_bit25 0x00000019 +#define regk_bif_core_bit26 0x0000001a +#define regk_bif_core_bit27 0x0000001b +#define regk_bif_core_bit28 0x0000001c +#define regk_bif_core_bit29 0x0000001d +#define regk_bif_core_bit9 0x00000009 +#define regk_bif_core_bw16 0x00000001 +#define regk_bif_core_bw32 0x00000000 +#define regk_bif_core_bwe 0x00000000 +#define regk_bif_core_cwe 0x00000001 +#define regk_bif_core_e15us 0x00000001 +#define regk_bif_core_e7800ns 0x00000002 +#define regk_bif_core_grp0 0x00000000 +#define regk_bif_core_grp1 0x00000001 +#define regk_bif_core_mrs 0x00000003 +#define regk_bif_core_no 0x00000000 +#define regk_bif_core_none 0x00000000 +#define regk_bif_core_nop 0x00000000 +#define regk_bif_core_off 0x00000000 +#define regk_bif_core_pre 0x00000002 +#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rd 0x00000002 +#define regk_bif_core_ref 0x00000001 +#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 +#define regk_bif_core_rw_grp1_cfg_default 0x000006cf +#define regk_bif_core_rw_grp2_cfg_default 0x000006cf +#define regk_bif_core_rw_grp3_cfg_default 0x000006cf +#define regk_bif_core_rw_grp4_cfg_default 0x000006cf +#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 +#define regk_bif_core_slf 0x00000004 +#define regk_bif_core_wr 0x00000001 +#define regk_bif_core_yes 0x00000001 +#endif /* __bif_core_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h new file mode 100644 index 000000000..a9908dfc2 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h @@ -0,0 +1,131 @@ +#ifndef __config_defs_asm_h +#define __config_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r + * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register r_bootsel, scope config, type r */ +#define reg_config_r_bootsel___boot_mode___lsb 0 +#define reg_config_r_bootsel___boot_mode___width 3 +#define reg_config_r_bootsel___full_duplex___lsb 3 +#define reg_config_r_bootsel___full_duplex___width 1 +#define reg_config_r_bootsel___full_duplex___bit 3 +#define reg_config_r_bootsel___user___lsb 4 +#define reg_config_r_bootsel___user___width 1 +#define reg_config_r_bootsel___user___bit 4 +#define reg_config_r_bootsel___pll___lsb 5 +#define reg_config_r_bootsel___pll___width 1 +#define reg_config_r_bootsel___pll___bit 5 +#define reg_config_r_bootsel___flash_bw___lsb 6 +#define reg_config_r_bootsel___flash_bw___width 1 +#define reg_config_r_bootsel___flash_bw___bit 6 +#define reg_config_r_bootsel_offset 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +#define reg_config_rw_clk_ctrl___pll___lsb 0 +#define reg_config_rw_clk_ctrl___pll___width 1 +#define reg_config_rw_clk_ctrl___pll___bit 0 +#define reg_config_rw_clk_ctrl___cpu___lsb 1 +#define reg_config_rw_clk_ctrl___cpu___width 1 +#define reg_config_rw_clk_ctrl___cpu___bit 1 +#define reg_config_rw_clk_ctrl___iop___lsb 2 +#define reg_config_rw_clk_ctrl___iop___width 1 +#define reg_config_rw_clk_ctrl___iop___bit 2 +#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 +#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 +#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 +#define reg_config_rw_clk_ctrl___dma23___lsb 4 +#define reg_config_rw_clk_ctrl___dma23___width 1 +#define reg_config_rw_clk_ctrl___dma23___bit 4 +#define reg_config_rw_clk_ctrl___dma45___lsb 5 +#define reg_config_rw_clk_ctrl___dma45___width 1 +#define reg_config_rw_clk_ctrl___dma45___bit 5 +#define reg_config_rw_clk_ctrl___dma67___lsb 6 +#define reg_config_rw_clk_ctrl___dma67___width 1 +#define reg_config_rw_clk_ctrl___dma67___bit 6 +#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 +#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 +#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 +#define reg_config_rw_clk_ctrl___bif___lsb 8 +#define reg_config_rw_clk_ctrl___bif___width 1 +#define reg_config_rw_clk_ctrl___bif___bit 8 +#define reg_config_rw_clk_ctrl___fix_io___lsb 9 +#define reg_config_rw_clk_ctrl___fix_io___width 1 +#define reg_config_rw_clk_ctrl___fix_io___bit 9 +#define reg_config_rw_clk_ctrl_offset 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 +#define reg_config_rw_pad_ctrl___usb_susp___width 1 +#define reg_config_rw_pad_ctrl___usb_susp___bit 0 +#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 +#define reg_config_rw_pad_ctrl___phyrst_n___width 1 +#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 +#define reg_config_rw_pad_ctrl_offset 8 + + +/* Constants */ +#define regk_config_bw16 0x00000000 +#define regk_config_bw32 0x00000001 +#define regk_config_master 0x00000005 +#define regk_config_nand 0x00000003 +#define regk_config_net_rx 0x00000001 +#define regk_config_net_tx_rx 0x00000002 +#define regk_config_no 0x00000000 +#define regk_config_none 0x00000007 +#define regk_config_nor 0x00000000 +#define regk_config_rw_clk_ctrl_default 0x00000002 +#define regk_config_rw_pad_ctrl_default 0x00000000 +#define regk_config_ser 0x00000004 +#define regk_config_slave 0x00000006 +#define regk_config_yes 0x00000001 +#endif /* __config_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h new file mode 100644 index 000000000..be4c63936 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h @@ -0,0 +1,276 @@ +#ifndef __gio_defs_asm_h +#define __gio_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa_dout, scope gio, type rw */ +#define reg_gio_rw_pa_dout___data___lsb 0 +#define reg_gio_rw_pa_dout___data___width 8 +#define reg_gio_rw_pa_dout_offset 0 + +/* Register r_pa_din, scope gio, type r */ +#define reg_gio_r_pa_din___data___lsb 0 +#define reg_gio_r_pa_din___data___width 8 +#define reg_gio_r_pa_din_offset 4 + +/* Register rw_pa_oe, scope gio, type rw */ +#define reg_gio_rw_pa_oe___oe___lsb 0 +#define reg_gio_rw_pa_oe___oe___width 8 +#define reg_gio_rw_pa_oe_offset 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +#define reg_gio_rw_intr_cfg___pa0___lsb 0 +#define reg_gio_rw_intr_cfg___pa0___width 3 +#define reg_gio_rw_intr_cfg___pa1___lsb 3 +#define reg_gio_rw_intr_cfg___pa1___width 3 +#define reg_gio_rw_intr_cfg___pa2___lsb 6 +#define reg_gio_rw_intr_cfg___pa2___width 3 +#define reg_gio_rw_intr_cfg___pa3___lsb 9 +#define reg_gio_rw_intr_cfg___pa3___width 3 +#define reg_gio_rw_intr_cfg___pa4___lsb 12 +#define reg_gio_rw_intr_cfg___pa4___width 3 +#define reg_gio_rw_intr_cfg___pa5___lsb 15 +#define reg_gio_rw_intr_cfg___pa5___width 3 +#define reg_gio_rw_intr_cfg___pa6___lsb 18 +#define reg_gio_rw_intr_cfg___pa6___width 3 +#define reg_gio_rw_intr_cfg___pa7___lsb 21 +#define reg_gio_rw_intr_cfg___pa7___width 3 +#define reg_gio_rw_intr_cfg_offset 12 + +/* Register rw_intr_mask, scope gio, type rw */ +#define reg_gio_rw_intr_mask___pa0___lsb 0 +#define reg_gio_rw_intr_mask___pa0___width 1 +#define reg_gio_rw_intr_mask___pa0___bit 0 +#define reg_gio_rw_intr_mask___pa1___lsb 1 +#define reg_gio_rw_intr_mask___pa1___width 1 +#define reg_gio_rw_intr_mask___pa1___bit 1 +#define reg_gio_rw_intr_mask___pa2___lsb 2 +#define reg_gio_rw_intr_mask___pa2___width 1 +#define reg_gio_rw_intr_mask___pa2___bit 2 +#define reg_gio_rw_intr_mask___pa3___lsb 3 +#define reg_gio_rw_intr_mask___pa3___width 1 +#define reg_gio_rw_intr_mask___pa3___bit 3 +#define reg_gio_rw_intr_mask___pa4___lsb 4 +#define reg_gio_rw_intr_mask___pa4___width 1 +#define reg_gio_rw_intr_mask___pa4___bit 4 +#define reg_gio_rw_intr_mask___pa5___lsb 5 +#define reg_gio_rw_intr_mask___pa5___width 1 +#define reg_gio_rw_intr_mask___pa5___bit 5 +#define reg_gio_rw_intr_mask___pa6___lsb 6 +#define reg_gio_rw_intr_mask___pa6___width 1 +#define reg_gio_rw_intr_mask___pa6___bit 6 +#define reg_gio_rw_intr_mask___pa7___lsb 7 +#define reg_gio_rw_intr_mask___pa7___width 1 +#define reg_gio_rw_intr_mask___pa7___bit 7 +#define reg_gio_rw_intr_mask_offset 16 + +/* Register rw_ack_intr, scope gio, type rw */ +#define reg_gio_rw_ack_intr___pa0___lsb 0 +#define reg_gio_rw_ack_intr___pa0___width 1 +#define reg_gio_rw_ack_intr___pa0___bit 0 +#define reg_gio_rw_ack_intr___pa1___lsb 1 +#define reg_gio_rw_ack_intr___pa1___width 1 +#define reg_gio_rw_ack_intr___pa1___bit 1 +#define reg_gio_rw_ack_intr___pa2___lsb 2 +#define reg_gio_rw_ack_intr___pa2___width 1 +#define reg_gio_rw_ack_intr___pa2___bit 2 +#define reg_gio_rw_ack_intr___pa3___lsb 3 +#define reg_gio_rw_ack_intr___pa3___width 1 +#define reg_gio_rw_ack_intr___pa3___bit 3 +#define reg_gio_rw_ack_intr___pa4___lsb 4 +#define reg_gio_rw_ack_intr___pa4___width 1 +#define reg_gio_rw_ack_intr___pa4___bit 4 +#define reg_gio_rw_ack_intr___pa5___lsb 5 +#define reg_gio_rw_ack_intr___pa5___width 1 +#define reg_gio_rw_ack_intr___pa5___bit 5 +#define reg_gio_rw_ack_intr___pa6___lsb 6 +#define reg_gio_rw_ack_intr___pa6___width 1 +#define reg_gio_rw_ack_intr___pa6___bit 6 +#define reg_gio_rw_ack_intr___pa7___lsb 7 +#define reg_gio_rw_ack_intr___pa7___width 1 +#define reg_gio_rw_ack_intr___pa7___bit 7 +#define reg_gio_rw_ack_intr_offset 20 + +/* Register r_intr, scope gio, type r */ +#define reg_gio_r_intr___pa0___lsb 0 +#define reg_gio_r_intr___pa0___width 1 +#define reg_gio_r_intr___pa0___bit 0 +#define reg_gio_r_intr___pa1___lsb 1 +#define reg_gio_r_intr___pa1___width 1 +#define reg_gio_r_intr___pa1___bit 1 +#define reg_gio_r_intr___pa2___lsb 2 +#define reg_gio_r_intr___pa2___width 1 +#define reg_gio_r_intr___pa2___bit 2 +#define reg_gio_r_intr___pa3___lsb 3 +#define reg_gio_r_intr___pa3___width 1 +#define reg_gio_r_intr___pa3___bit 3 +#define reg_gio_r_intr___pa4___lsb 4 +#define reg_gio_r_intr___pa4___width 1 +#define reg_gio_r_intr___pa4___bit 4 +#define reg_gio_r_intr___pa5___lsb 5 +#define reg_gio_r_intr___pa5___width 1 +#define reg_gio_r_intr___pa5___bit 5 +#define reg_gio_r_intr___pa6___lsb 6 +#define reg_gio_r_intr___pa6___width 1 +#define reg_gio_r_intr___pa6___bit 6 +#define reg_gio_r_intr___pa7___lsb 7 +#define reg_gio_r_intr___pa7___width 1 +#define reg_gio_r_intr___pa7___bit 7 +#define reg_gio_r_intr_offset 24 + +/* Register r_masked_intr, scope gio, type r */ +#define reg_gio_r_masked_intr___pa0___lsb 0 +#define reg_gio_r_masked_intr___pa0___width 1 +#define reg_gio_r_masked_intr___pa0___bit 0 +#define reg_gio_r_masked_intr___pa1___lsb 1 +#define reg_gio_r_masked_intr___pa1___width 1 +#define reg_gio_r_masked_intr___pa1___bit 1 +#define reg_gio_r_masked_intr___pa2___lsb 2 +#define reg_gio_r_masked_intr___pa2___width 1 +#define reg_gio_r_masked_intr___pa2___bit 2 +#define reg_gio_r_masked_intr___pa3___lsb 3 +#define reg_gio_r_masked_intr___pa3___width 1 +#define reg_gio_r_masked_intr___pa3___bit 3 +#define reg_gio_r_masked_intr___pa4___lsb 4 +#define reg_gio_r_masked_intr___pa4___width 1 +#define reg_gio_r_masked_intr___pa4___bit 4 +#define reg_gio_r_masked_intr___pa5___lsb 5 +#define reg_gio_r_masked_intr___pa5___width 1 +#define reg_gio_r_masked_intr___pa5___bit 5 +#define reg_gio_r_masked_intr___pa6___lsb 6 +#define reg_gio_r_masked_intr___pa6___width 1 +#define reg_gio_r_masked_intr___pa6___bit 6 +#define reg_gio_r_masked_intr___pa7___lsb 7 +#define reg_gio_r_masked_intr___pa7___width 1 +#define reg_gio_r_masked_intr___pa7___bit 7 +#define reg_gio_r_masked_intr_offset 28 + +/* Register rw_pb_dout, scope gio, type rw */ +#define reg_gio_rw_pb_dout___data___lsb 0 +#define reg_gio_rw_pb_dout___data___width 18 +#define reg_gio_rw_pb_dout_offset 32 + +/* Register r_pb_din, scope gio, type r */ +#define reg_gio_r_pb_din___data___lsb 0 +#define reg_gio_r_pb_din___data___width 18 +#define reg_gio_r_pb_din_offset 36 + +/* Register rw_pb_oe, scope gio, type rw */ +#define reg_gio_rw_pb_oe___oe___lsb 0 +#define reg_gio_rw_pb_oe___oe___width 18 +#define reg_gio_rw_pb_oe_offset 40 + +/* Register rw_pc_dout, scope gio, type rw */ +#define reg_gio_rw_pc_dout___data___lsb 0 +#define reg_gio_rw_pc_dout___data___width 18 +#define reg_gio_rw_pc_dout_offset 48 + +/* Register r_pc_din, scope gio, type r */ +#define reg_gio_r_pc_din___data___lsb 0 +#define reg_gio_r_pc_din___data___width 18 +#define reg_gio_r_pc_din_offset 52 + +/* Register rw_pc_oe, scope gio, type rw */ +#define reg_gio_rw_pc_oe___oe___lsb 0 +#define reg_gio_rw_pc_oe___oe___width 18 +#define reg_gio_rw_pc_oe_offset 56 + +/* Register rw_pd_dout, scope gio, type rw */ +#define reg_gio_rw_pd_dout___data___lsb 0 +#define reg_gio_rw_pd_dout___data___width 18 +#define reg_gio_rw_pd_dout_offset 64 + +/* Register r_pd_din, scope gio, type r */ +#define reg_gio_r_pd_din___data___lsb 0 +#define reg_gio_r_pd_din___data___width 18 +#define reg_gio_r_pd_din_offset 68 + +/* Register rw_pd_oe, scope gio, type rw */ +#define reg_gio_rw_pd_oe___oe___lsb 0 +#define reg_gio_rw_pd_oe___oe___width 18 +#define reg_gio_rw_pd_oe_offset 72 + +/* Register rw_pe_dout, scope gio, type rw */ +#define reg_gio_rw_pe_dout___data___lsb 0 +#define reg_gio_rw_pe_dout___data___width 18 +#define reg_gio_rw_pe_dout_offset 80 + +/* Register r_pe_din, scope gio, type r */ +#define reg_gio_r_pe_din___data___lsb 0 +#define reg_gio_r_pe_din___data___width 18 +#define reg_gio_r_pe_din_offset 84 + +/* Register rw_pe_oe, scope gio, type rw */ +#define reg_gio_rw_pe_oe___oe___lsb 0 +#define reg_gio_rw_pe_oe___oe___width 18 +#define reg_gio_rw_pe_oe_offset 88 + + +/* Constants */ +#define regk_gio_anyedge 0x00000007 +#define regk_gio_hi 0x00000001 +#define regk_gio_lo 0x00000002 +#define regk_gio_negedge 0x00000006 +#define regk_gio_no 0x00000000 +#define regk_gio_off 0x00000000 +#define regk_gio_posedge 0x00000005 +#define regk_gio_rw_intr_cfg_default 0x00000000 +#define regk_gio_rw_intr_mask_default 0x00000000 +#define regk_gio_rw_pa_oe_default 0x00000000 +#define regk_gio_rw_pb_oe_default 0x00000000 +#define regk_gio_rw_pc_oe_default 0x00000000 +#define regk_gio_rw_pd_oe_default 0x00000000 +#define regk_gio_rw_pe_oe_default 0x00000000 +#define regk_gio_set 0x00000003 +#define regk_gio_yes 0x00000001 +#endif /* __gio_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h new file mode 100644 index 000000000..30cf5a936 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h @@ -0,0 +1,632 @@ +#ifndef __pinmux_defs_asm_h +#define __pinmux_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp + * last modfied: Mon Apr 11 16:09:11 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_pa, scope pinmux, type rw */ +#define reg_pinmux_rw_pa___pa0___lsb 0 +#define reg_pinmux_rw_pa___pa0___width 1 +#define reg_pinmux_rw_pa___pa0___bit 0 +#define reg_pinmux_rw_pa___pa1___lsb 1 +#define reg_pinmux_rw_pa___pa1___width 1 +#define reg_pinmux_rw_pa___pa1___bit 1 +#define reg_pinmux_rw_pa___pa2___lsb 2 +#define reg_pinmux_rw_pa___pa2___width 1 +#define reg_pinmux_rw_pa___pa2___bit 2 +#define reg_pinmux_rw_pa___pa3___lsb 3 +#define reg_pinmux_rw_pa___pa3___width 1 +#define reg_pinmux_rw_pa___pa3___bit 3 +#define reg_pinmux_rw_pa___pa4___lsb 4 +#define reg_pinmux_rw_pa___pa4___width 1 +#define reg_pinmux_rw_pa___pa4___bit 4 +#define reg_pinmux_rw_pa___pa5___lsb 5 +#define reg_pinmux_rw_pa___pa5___width 1 +#define reg_pinmux_rw_pa___pa5___bit 5 +#define reg_pinmux_rw_pa___pa6___lsb 6 +#define reg_pinmux_rw_pa___pa6___width 1 +#define reg_pinmux_rw_pa___pa6___bit 6 +#define reg_pinmux_rw_pa___pa7___lsb 7 +#define reg_pinmux_rw_pa___pa7___width 1 +#define reg_pinmux_rw_pa___pa7___bit 7 +#define reg_pinmux_rw_pa___csp2_n___lsb 8 +#define reg_pinmux_rw_pa___csp2_n___width 1 +#define reg_pinmux_rw_pa___csp2_n___bit 8 +#define reg_pinmux_rw_pa___csp3_n___lsb 9 +#define reg_pinmux_rw_pa___csp3_n___width 1 +#define reg_pinmux_rw_pa___csp3_n___bit 9 +#define reg_pinmux_rw_pa___csp5_n___lsb 10 +#define reg_pinmux_rw_pa___csp5_n___width 1 +#define reg_pinmux_rw_pa___csp5_n___bit 10 +#define reg_pinmux_rw_pa___csp6_n___lsb 11 +#define reg_pinmux_rw_pa___csp6_n___width 1 +#define reg_pinmux_rw_pa___csp6_n___bit 11 +#define reg_pinmux_rw_pa___hsh4___lsb 12 +#define reg_pinmux_rw_pa___hsh4___width 1 +#define reg_pinmux_rw_pa___hsh4___bit 12 +#define reg_pinmux_rw_pa___hsh5___lsb 13 +#define reg_pinmux_rw_pa___hsh5___width 1 +#define reg_pinmux_rw_pa___hsh5___bit 13 +#define reg_pinmux_rw_pa___hsh6___lsb 14 +#define reg_pinmux_rw_pa___hsh6___width 1 +#define reg_pinmux_rw_pa___hsh6___bit 14 +#define reg_pinmux_rw_pa___hsh7___lsb 15 +#define reg_pinmux_rw_pa___hsh7___width 1 +#define reg_pinmux_rw_pa___hsh7___bit 15 +#define reg_pinmux_rw_pa_offset 0 + +/* Register rw_hwprot, scope pinmux, type rw */ +#define reg_pinmux_rw_hwprot___ser1___lsb 0 +#define reg_pinmux_rw_hwprot___ser1___width 1 +#define reg_pinmux_rw_hwprot___ser1___bit 0 +#define reg_pinmux_rw_hwprot___ser2___lsb 1 +#define reg_pinmux_rw_hwprot___ser2___width 1 +#define reg_pinmux_rw_hwprot___ser2___bit 1 +#define reg_pinmux_rw_hwprot___ser3___lsb 2 +#define reg_pinmux_rw_hwprot___ser3___width 1 +#define reg_pinmux_rw_hwprot___ser3___bit 2 +#define reg_pinmux_rw_hwprot___sser0___lsb 3 +#define reg_pinmux_rw_hwprot___sser0___width 1 +#define reg_pinmux_rw_hwprot___sser0___bit 3 +#define reg_pinmux_rw_hwprot___sser1___lsb 4 +#define reg_pinmux_rw_hwprot___sser1___width 1 +#define reg_pinmux_rw_hwprot___sser1___bit 4 +#define reg_pinmux_rw_hwprot___ata0___lsb 5 +#define reg_pinmux_rw_hwprot___ata0___width 1 +#define reg_pinmux_rw_hwprot___ata0___bit 5 +#define reg_pinmux_rw_hwprot___ata1___lsb 6 +#define reg_pinmux_rw_hwprot___ata1___width 1 +#define reg_pinmux_rw_hwprot___ata1___bit 6 +#define reg_pinmux_rw_hwprot___ata2___lsb 7 +#define reg_pinmux_rw_hwprot___ata2___width 1 +#define reg_pinmux_rw_hwprot___ata2___bit 7 +#define reg_pinmux_rw_hwprot___ata3___lsb 8 +#define reg_pinmux_rw_hwprot___ata3___width 1 +#define reg_pinmux_rw_hwprot___ata3___bit 8 +#define reg_pinmux_rw_hwprot___ata___lsb 9 +#define reg_pinmux_rw_hwprot___ata___width 1 +#define reg_pinmux_rw_hwprot___ata___bit 9 +#define reg_pinmux_rw_hwprot___eth1___lsb 10 +#define reg_pinmux_rw_hwprot___eth1___width 1 +#define reg_pinmux_rw_hwprot___eth1___bit 10 +#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 +#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 +#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 +#define reg_pinmux_rw_hwprot___timer___lsb 12 +#define reg_pinmux_rw_hwprot___timer___width 1 +#define reg_pinmux_rw_hwprot___timer___bit 12 +#define reg_pinmux_rw_hwprot___p21___lsb 13 +#define reg_pinmux_rw_hwprot___p21___width 1 +#define reg_pinmux_rw_hwprot___p21___bit 13 +#define reg_pinmux_rw_hwprot_offset 4 + +/* Register rw_pb_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pb_gio___pb0___lsb 0 +#define reg_pinmux_rw_pb_gio___pb0___width 1 +#define reg_pinmux_rw_pb_gio___pb0___bit 0 +#define reg_pinmux_rw_pb_gio___pb1___lsb 1 +#define reg_pinmux_rw_pb_gio___pb1___width 1 +#define reg_pinmux_rw_pb_gio___pb1___bit 1 +#define reg_pinmux_rw_pb_gio___pb2___lsb 2 +#define reg_pinmux_rw_pb_gio___pb2___width 1 +#define reg_pinmux_rw_pb_gio___pb2___bit 2 +#define reg_pinmux_rw_pb_gio___pb3___lsb 3 +#define reg_pinmux_rw_pb_gio___pb3___width 1 +#define reg_pinmux_rw_pb_gio___pb3___bit 3 +#define reg_pinmux_rw_pb_gio___pb4___lsb 4 +#define reg_pinmux_rw_pb_gio___pb4___width 1 +#define reg_pinmux_rw_pb_gio___pb4___bit 4 +#define reg_pinmux_rw_pb_gio___pb5___lsb 5 +#define reg_pinmux_rw_pb_gio___pb5___width 1 +#define reg_pinmux_rw_pb_gio___pb5___bit 5 +#define reg_pinmux_rw_pb_gio___pb6___lsb 6 +#define reg_pinmux_rw_pb_gio___pb6___width 1 +#define reg_pinmux_rw_pb_gio___pb6___bit 6 +#define reg_pinmux_rw_pb_gio___pb7___lsb 7 +#define reg_pinmux_rw_pb_gio___pb7___width 1 +#define reg_pinmux_rw_pb_gio___pb7___bit 7 +#define reg_pinmux_rw_pb_gio___pb8___lsb 8 +#define reg_pinmux_rw_pb_gio___pb8___width 1 +#define reg_pinmux_rw_pb_gio___pb8___bit 8 +#define reg_pinmux_rw_pb_gio___pb9___lsb 9 +#define reg_pinmux_rw_pb_gio___pb9___width 1 +#define reg_pinmux_rw_pb_gio___pb9___bit 9 +#define reg_pinmux_rw_pb_gio___pb10___lsb 10 +#define reg_pinmux_rw_pb_gio___pb10___width 1 +#define reg_pinmux_rw_pb_gio___pb10___bit 10 +#define reg_pinmux_rw_pb_gio___pb11___lsb 11 +#define reg_pinmux_rw_pb_gio___pb11___width 1 +#define reg_pinmux_rw_pb_gio___pb11___bit 11 +#define reg_pinmux_rw_pb_gio___pb12___lsb 12 +#define reg_pinmux_rw_pb_gio___pb12___width 1 +#define reg_pinmux_rw_pb_gio___pb12___bit 12 +#define reg_pinmux_rw_pb_gio___pb13___lsb 13 +#define reg_pinmux_rw_pb_gio___pb13___width 1 +#define reg_pinmux_rw_pb_gio___pb13___bit 13 +#define reg_pinmux_rw_pb_gio___pb14___lsb 14 +#define reg_pinmux_rw_pb_gio___pb14___width 1 +#define reg_pinmux_rw_pb_gio___pb14___bit 14 +#define reg_pinmux_rw_pb_gio___pb15___lsb 15 +#define reg_pinmux_rw_pb_gio___pb15___width 1 +#define reg_pinmux_rw_pb_gio___pb15___bit 15 +#define reg_pinmux_rw_pb_gio___pb16___lsb 16 +#define reg_pinmux_rw_pb_gio___pb16___width 1 +#define reg_pinmux_rw_pb_gio___pb16___bit 16 +#define reg_pinmux_rw_pb_gio___pb17___lsb 17 +#define reg_pinmux_rw_pb_gio___pb17___width 1 +#define reg_pinmux_rw_pb_gio___pb17___bit 17 +#define reg_pinmux_rw_pb_gio_offset 8 + +/* Register rw_pb_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pb_iop___pb0___lsb 0 +#define reg_pinmux_rw_pb_iop___pb0___width 1 +#define reg_pinmux_rw_pb_iop___pb0___bit 0 +#define reg_pinmux_rw_pb_iop___pb1___lsb 1 +#define reg_pinmux_rw_pb_iop___pb1___width 1 +#define reg_pinmux_rw_pb_iop___pb1___bit 1 +#define reg_pinmux_rw_pb_iop___pb2___lsb 2 +#define reg_pinmux_rw_pb_iop___pb2___width 1 +#define reg_pinmux_rw_pb_iop___pb2___bit 2 +#define reg_pinmux_rw_pb_iop___pb3___lsb 3 +#define reg_pinmux_rw_pb_iop___pb3___width 1 +#define reg_pinmux_rw_pb_iop___pb3___bit 3 +#define reg_pinmux_rw_pb_iop___pb4___lsb 4 +#define reg_pinmux_rw_pb_iop___pb4___width 1 +#define reg_pinmux_rw_pb_iop___pb4___bit 4 +#define reg_pinmux_rw_pb_iop___pb5___lsb 5 +#define reg_pinmux_rw_pb_iop___pb5___width 1 +#define reg_pinmux_rw_pb_iop___pb5___bit 5 +#define reg_pinmux_rw_pb_iop___pb6___lsb 6 +#define reg_pinmux_rw_pb_iop___pb6___width 1 +#define reg_pinmux_rw_pb_iop___pb6___bit 6 +#define reg_pinmux_rw_pb_iop___pb7___lsb 7 +#define reg_pinmux_rw_pb_iop___pb7___width 1 +#define reg_pinmux_rw_pb_iop___pb7___bit 7 +#define reg_pinmux_rw_pb_iop___pb8___lsb 8 +#define reg_pinmux_rw_pb_iop___pb8___width 1 +#define reg_pinmux_rw_pb_iop___pb8___bit 8 +#define reg_pinmux_rw_pb_iop___pb9___lsb 9 +#define reg_pinmux_rw_pb_iop___pb9___width 1 +#define reg_pinmux_rw_pb_iop___pb9___bit 9 +#define reg_pinmux_rw_pb_iop___pb10___lsb 10 +#define reg_pinmux_rw_pb_iop___pb10___width 1 +#define reg_pinmux_rw_pb_iop___pb10___bit 10 +#define reg_pinmux_rw_pb_iop___pb11___lsb 11 +#define reg_pinmux_rw_pb_iop___pb11___width 1 +#define reg_pinmux_rw_pb_iop___pb11___bit 11 +#define reg_pinmux_rw_pb_iop___pb12___lsb 12 +#define reg_pinmux_rw_pb_iop___pb12___width 1 +#define reg_pinmux_rw_pb_iop___pb12___bit 12 +#define reg_pinmux_rw_pb_iop___pb13___lsb 13 +#define reg_pinmux_rw_pb_iop___pb13___width 1 +#define reg_pinmux_rw_pb_iop___pb13___bit 13 +#define reg_pinmux_rw_pb_iop___pb14___lsb 14 +#define reg_pinmux_rw_pb_iop___pb14___width 1 +#define reg_pinmux_rw_pb_iop___pb14___bit 14 +#define reg_pinmux_rw_pb_iop___pb15___lsb 15 +#define reg_pinmux_rw_pb_iop___pb15___width 1 +#define reg_pinmux_rw_pb_iop___pb15___bit 15 +#define reg_pinmux_rw_pb_iop___pb16___lsb 16 +#define reg_pinmux_rw_pb_iop___pb16___width 1 +#define reg_pinmux_rw_pb_iop___pb16___bit 16 +#define reg_pinmux_rw_pb_iop___pb17___lsb 17 +#define reg_pinmux_rw_pb_iop___pb17___width 1 +#define reg_pinmux_rw_pb_iop___pb17___bit 17 +#define reg_pinmux_rw_pb_iop_offset 12 + +/* Register rw_pc_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pc_gio___pc0___lsb 0 +#define reg_pinmux_rw_pc_gio___pc0___width 1 +#define reg_pinmux_rw_pc_gio___pc0___bit 0 +#define reg_pinmux_rw_pc_gio___pc1___lsb 1 +#define reg_pinmux_rw_pc_gio___pc1___width 1 +#define reg_pinmux_rw_pc_gio___pc1___bit 1 +#define reg_pinmux_rw_pc_gio___pc2___lsb 2 +#define reg_pinmux_rw_pc_gio___pc2___width 1 +#define reg_pinmux_rw_pc_gio___pc2___bit 2 +#define reg_pinmux_rw_pc_gio___pc3___lsb 3 +#define reg_pinmux_rw_pc_gio___pc3___width 1 +#define reg_pinmux_rw_pc_gio___pc3___bit 3 +#define reg_pinmux_rw_pc_gio___pc4___lsb 4 +#define reg_pinmux_rw_pc_gio___pc4___width 1 +#define reg_pinmux_rw_pc_gio___pc4___bit 4 +#define reg_pinmux_rw_pc_gio___pc5___lsb 5 +#define reg_pinmux_rw_pc_gio___pc5___width 1 +#define reg_pinmux_rw_pc_gio___pc5___bit 5 +#define reg_pinmux_rw_pc_gio___pc6___lsb 6 +#define reg_pinmux_rw_pc_gio___pc6___width 1 +#define reg_pinmux_rw_pc_gio___pc6___bit 6 +#define reg_pinmux_rw_pc_gio___pc7___lsb 7 +#define reg_pinmux_rw_pc_gio___pc7___width 1 +#define reg_pinmux_rw_pc_gio___pc7___bit 7 +#define reg_pinmux_rw_pc_gio___pc8___lsb 8 +#define reg_pinmux_rw_pc_gio___pc8___width 1 +#define reg_pinmux_rw_pc_gio___pc8___bit 8 +#define reg_pinmux_rw_pc_gio___pc9___lsb 9 +#define reg_pinmux_rw_pc_gio___pc9___width 1 +#define reg_pinmux_rw_pc_gio___pc9___bit 9 +#define reg_pinmux_rw_pc_gio___pc10___lsb 10 +#define reg_pinmux_rw_pc_gio___pc10___width 1 +#define reg_pinmux_rw_pc_gio___pc10___bit 10 +#define reg_pinmux_rw_pc_gio___pc11___lsb 11 +#define reg_pinmux_rw_pc_gio___pc11___width 1 +#define reg_pinmux_rw_pc_gio___pc11___bit 11 +#define reg_pinmux_rw_pc_gio___pc12___lsb 12 +#define reg_pinmux_rw_pc_gio___pc12___width 1 +#define reg_pinmux_rw_pc_gio___pc12___bit 12 +#define reg_pinmux_rw_pc_gio___pc13___lsb 13 +#define reg_pinmux_rw_pc_gio___pc13___width 1 +#define reg_pinmux_rw_pc_gio___pc13___bit 13 +#define reg_pinmux_rw_pc_gio___pc14___lsb 14 +#define reg_pinmux_rw_pc_gio___pc14___width 1 +#define reg_pinmux_rw_pc_gio___pc14___bit 14 +#define reg_pinmux_rw_pc_gio___pc15___lsb 15 +#define reg_pinmux_rw_pc_gio___pc15___width 1 +#define reg_pinmux_rw_pc_gio___pc15___bit 15 +#define reg_pinmux_rw_pc_gio___pc16___lsb 16 +#define reg_pinmux_rw_pc_gio___pc16___width 1 +#define reg_pinmux_rw_pc_gio___pc16___bit 16 +#define reg_pinmux_rw_pc_gio___pc17___lsb 17 +#define reg_pinmux_rw_pc_gio___pc17___width 1 +#define reg_pinmux_rw_pc_gio___pc17___bit 17 +#define reg_pinmux_rw_pc_gio_offset 16 + +/* Register rw_pc_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pc_iop___pc0___lsb 0 +#define reg_pinmux_rw_pc_iop___pc0___width 1 +#define reg_pinmux_rw_pc_iop___pc0___bit 0 +#define reg_pinmux_rw_pc_iop___pc1___lsb 1 +#define reg_pinmux_rw_pc_iop___pc1___width 1 +#define reg_pinmux_rw_pc_iop___pc1___bit 1 +#define reg_pinmux_rw_pc_iop___pc2___lsb 2 +#define reg_pinmux_rw_pc_iop___pc2___width 1 +#define reg_pinmux_rw_pc_iop___pc2___bit 2 +#define reg_pinmux_rw_pc_iop___pc3___lsb 3 +#define reg_pinmux_rw_pc_iop___pc3___width 1 +#define reg_pinmux_rw_pc_iop___pc3___bit 3 +#define reg_pinmux_rw_pc_iop___pc4___lsb 4 +#define reg_pinmux_rw_pc_iop___pc4___width 1 +#define reg_pinmux_rw_pc_iop___pc4___bit 4 +#define reg_pinmux_rw_pc_iop___pc5___lsb 5 +#define reg_pinmux_rw_pc_iop___pc5___width 1 +#define reg_pinmux_rw_pc_iop___pc5___bit 5 +#define reg_pinmux_rw_pc_iop___pc6___lsb 6 +#define reg_pinmux_rw_pc_iop___pc6___width 1 +#define reg_pinmux_rw_pc_iop___pc6___bit 6 +#define reg_pinmux_rw_pc_iop___pc7___lsb 7 +#define reg_pinmux_rw_pc_iop___pc7___width 1 +#define reg_pinmux_rw_pc_iop___pc7___bit 7 +#define reg_pinmux_rw_pc_iop___pc8___lsb 8 +#define reg_pinmux_rw_pc_iop___pc8___width 1 +#define reg_pinmux_rw_pc_iop___pc8___bit 8 +#define reg_pinmux_rw_pc_iop___pc9___lsb 9 +#define reg_pinmux_rw_pc_iop___pc9___width 1 +#define reg_pinmux_rw_pc_iop___pc9___bit 9 +#define reg_pinmux_rw_pc_iop___pc10___lsb 10 +#define reg_pinmux_rw_pc_iop___pc10___width 1 +#define reg_pinmux_rw_pc_iop___pc10___bit 10 +#define reg_pinmux_rw_pc_iop___pc11___lsb 11 +#define reg_pinmux_rw_pc_iop___pc11___width 1 +#define reg_pinmux_rw_pc_iop___pc11___bit 11 +#define reg_pinmux_rw_pc_iop___pc12___lsb 12 +#define reg_pinmux_rw_pc_iop___pc12___width 1 +#define reg_pinmux_rw_pc_iop___pc12___bit 12 +#define reg_pinmux_rw_pc_iop___pc13___lsb 13 +#define reg_pinmux_rw_pc_iop___pc13___width 1 +#define reg_pinmux_rw_pc_iop___pc13___bit 13 +#define reg_pinmux_rw_pc_iop___pc14___lsb 14 +#define reg_pinmux_rw_pc_iop___pc14___width 1 +#define reg_pinmux_rw_pc_iop___pc14___bit 14 +#define reg_pinmux_rw_pc_iop___pc15___lsb 15 +#define reg_pinmux_rw_pc_iop___pc15___width 1 +#define reg_pinmux_rw_pc_iop___pc15___bit 15 +#define reg_pinmux_rw_pc_iop___pc16___lsb 16 +#define reg_pinmux_rw_pc_iop___pc16___width 1 +#define reg_pinmux_rw_pc_iop___pc16___bit 16 +#define reg_pinmux_rw_pc_iop___pc17___lsb 17 +#define reg_pinmux_rw_pc_iop___pc17___width 1 +#define reg_pinmux_rw_pc_iop___pc17___bit 17 +#define reg_pinmux_rw_pc_iop_offset 20 + +/* Register rw_pd_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pd_gio___pd0___lsb 0 +#define reg_pinmux_rw_pd_gio___pd0___width 1 +#define reg_pinmux_rw_pd_gio___pd0___bit 0 +#define reg_pinmux_rw_pd_gio___pd1___lsb 1 +#define reg_pinmux_rw_pd_gio___pd1___width 1 +#define reg_pinmux_rw_pd_gio___pd1___bit 1 +#define reg_pinmux_rw_pd_gio___pd2___lsb 2 +#define reg_pinmux_rw_pd_gio___pd2___width 1 +#define reg_pinmux_rw_pd_gio___pd2___bit 2 +#define reg_pinmux_rw_pd_gio___pd3___lsb 3 +#define reg_pinmux_rw_pd_gio___pd3___width 1 +#define reg_pinmux_rw_pd_gio___pd3___bit 3 +#define reg_pinmux_rw_pd_gio___pd4___lsb 4 +#define reg_pinmux_rw_pd_gio___pd4___width 1 +#define reg_pinmux_rw_pd_gio___pd4___bit 4 +#define reg_pinmux_rw_pd_gio___pd5___lsb 5 +#define reg_pinmux_rw_pd_gio___pd5___width 1 +#define reg_pinmux_rw_pd_gio___pd5___bit 5 +#define reg_pinmux_rw_pd_gio___pd6___lsb 6 +#define reg_pinmux_rw_pd_gio___pd6___width 1 +#define reg_pinmux_rw_pd_gio___pd6___bit 6 +#define reg_pinmux_rw_pd_gio___pd7___lsb 7 +#define reg_pinmux_rw_pd_gio___pd7___width 1 +#define reg_pinmux_rw_pd_gio___pd7___bit 7 +#define reg_pinmux_rw_pd_gio___pd8___lsb 8 +#define reg_pinmux_rw_pd_gio___pd8___width 1 +#define reg_pinmux_rw_pd_gio___pd8___bit 8 +#define reg_pinmux_rw_pd_gio___pd9___lsb 9 +#define reg_pinmux_rw_pd_gio___pd9___width 1 +#define reg_pinmux_rw_pd_gio___pd9___bit 9 +#define reg_pinmux_rw_pd_gio___pd10___lsb 10 +#define reg_pinmux_rw_pd_gio___pd10___width 1 +#define reg_pinmux_rw_pd_gio___pd10___bit 10 +#define reg_pinmux_rw_pd_gio___pd11___lsb 11 +#define reg_pinmux_rw_pd_gio___pd11___width 1 +#define reg_pinmux_rw_pd_gio___pd11___bit 11 +#define reg_pinmux_rw_pd_gio___pd12___lsb 12 +#define reg_pinmux_rw_pd_gio___pd12___width 1 +#define reg_pinmux_rw_pd_gio___pd12___bit 12 +#define reg_pinmux_rw_pd_gio___pd13___lsb 13 +#define reg_pinmux_rw_pd_gio___pd13___width 1 +#define reg_pinmux_rw_pd_gio___pd13___bit 13 +#define reg_pinmux_rw_pd_gio___pd14___lsb 14 +#define reg_pinmux_rw_pd_gio___pd14___width 1 +#define reg_pinmux_rw_pd_gio___pd14___bit 14 +#define reg_pinmux_rw_pd_gio___pd15___lsb 15 +#define reg_pinmux_rw_pd_gio___pd15___width 1 +#define reg_pinmux_rw_pd_gio___pd15___bit 15 +#define reg_pinmux_rw_pd_gio___pd16___lsb 16 +#define reg_pinmux_rw_pd_gio___pd16___width 1 +#define reg_pinmux_rw_pd_gio___pd16___bit 16 +#define reg_pinmux_rw_pd_gio___pd17___lsb 17 +#define reg_pinmux_rw_pd_gio___pd17___width 1 +#define reg_pinmux_rw_pd_gio___pd17___bit 17 +#define reg_pinmux_rw_pd_gio_offset 24 + +/* Register rw_pd_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pd_iop___pd0___lsb 0 +#define reg_pinmux_rw_pd_iop___pd0___width 1 +#define reg_pinmux_rw_pd_iop___pd0___bit 0 +#define reg_pinmux_rw_pd_iop___pd1___lsb 1 +#define reg_pinmux_rw_pd_iop___pd1___width 1 +#define reg_pinmux_rw_pd_iop___pd1___bit 1 +#define reg_pinmux_rw_pd_iop___pd2___lsb 2 +#define reg_pinmux_rw_pd_iop___pd2___width 1 +#define reg_pinmux_rw_pd_iop___pd2___bit 2 +#define reg_pinmux_rw_pd_iop___pd3___lsb 3 +#define reg_pinmux_rw_pd_iop___pd3___width 1 +#define reg_pinmux_rw_pd_iop___pd3___bit 3 +#define reg_pinmux_rw_pd_iop___pd4___lsb 4 +#define reg_pinmux_rw_pd_iop___pd4___width 1 +#define reg_pinmux_rw_pd_iop___pd4___bit 4 +#define reg_pinmux_rw_pd_iop___pd5___lsb 5 +#define reg_pinmux_rw_pd_iop___pd5___width 1 +#define reg_pinmux_rw_pd_iop___pd5___bit 5 +#define reg_pinmux_rw_pd_iop___pd6___lsb 6 +#define reg_pinmux_rw_pd_iop___pd6___width 1 +#define reg_pinmux_rw_pd_iop___pd6___bit 6 +#define reg_pinmux_rw_pd_iop___pd7___lsb 7 +#define reg_pinmux_rw_pd_iop___pd7___width 1 +#define reg_pinmux_rw_pd_iop___pd7___bit 7 +#define reg_pinmux_rw_pd_iop___pd8___lsb 8 +#define reg_pinmux_rw_pd_iop___pd8___width 1 +#define reg_pinmux_rw_pd_iop___pd8___bit 8 +#define reg_pinmux_rw_pd_iop___pd9___lsb 9 +#define reg_pinmux_rw_pd_iop___pd9___width 1 +#define reg_pinmux_rw_pd_iop___pd9___bit 9 +#define reg_pinmux_rw_pd_iop___pd10___lsb 10 +#define reg_pinmux_rw_pd_iop___pd10___width 1 +#define reg_pinmux_rw_pd_iop___pd10___bit 10 +#define reg_pinmux_rw_pd_iop___pd11___lsb 11 +#define reg_pinmux_rw_pd_iop___pd11___width 1 +#define reg_pinmux_rw_pd_iop___pd11___bit 11 +#define reg_pinmux_rw_pd_iop___pd12___lsb 12 +#define reg_pinmux_rw_pd_iop___pd12___width 1 +#define reg_pinmux_rw_pd_iop___pd12___bit 12 +#define reg_pinmux_rw_pd_iop___pd13___lsb 13 +#define reg_pinmux_rw_pd_iop___pd13___width 1 +#define reg_pinmux_rw_pd_iop___pd13___bit 13 +#define reg_pinmux_rw_pd_iop___pd14___lsb 14 +#define reg_pinmux_rw_pd_iop___pd14___width 1 +#define reg_pinmux_rw_pd_iop___pd14___bit 14 +#define reg_pinmux_rw_pd_iop___pd15___lsb 15 +#define reg_pinmux_rw_pd_iop___pd15___width 1 +#define reg_pinmux_rw_pd_iop___pd15___bit 15 +#define reg_pinmux_rw_pd_iop___pd16___lsb 16 +#define reg_pinmux_rw_pd_iop___pd16___width 1 +#define reg_pinmux_rw_pd_iop___pd16___bit 16 +#define reg_pinmux_rw_pd_iop___pd17___lsb 17 +#define reg_pinmux_rw_pd_iop___pd17___width 1 +#define reg_pinmux_rw_pd_iop___pd17___bit 17 +#define reg_pinmux_rw_pd_iop_offset 28 + +/* Register rw_pe_gio, scope pinmux, type rw */ +#define reg_pinmux_rw_pe_gio___pe0___lsb 0 +#define reg_pinmux_rw_pe_gio___pe0___width 1 +#define reg_pinmux_rw_pe_gio___pe0___bit 0 +#define reg_pinmux_rw_pe_gio___pe1___lsb 1 +#define reg_pinmux_rw_pe_gio___pe1___width 1 +#define reg_pinmux_rw_pe_gio___pe1___bit 1 +#define reg_pinmux_rw_pe_gio___pe2___lsb 2 +#define reg_pinmux_rw_pe_gio___pe2___width 1 +#define reg_pinmux_rw_pe_gio___pe2___bit 2 +#define reg_pinmux_rw_pe_gio___pe3___lsb 3 +#define reg_pinmux_rw_pe_gio___pe3___width 1 +#define reg_pinmux_rw_pe_gio___pe3___bit 3 +#define reg_pinmux_rw_pe_gio___pe4___lsb 4 +#define reg_pinmux_rw_pe_gio___pe4___width 1 +#define reg_pinmux_rw_pe_gio___pe4___bit 4 +#define reg_pinmux_rw_pe_gio___pe5___lsb 5 +#define reg_pinmux_rw_pe_gio___pe5___width 1 +#define reg_pinmux_rw_pe_gio___pe5___bit 5 +#define reg_pinmux_rw_pe_gio___pe6___lsb 6 +#define reg_pinmux_rw_pe_gio___pe6___width 1 +#define reg_pinmux_rw_pe_gio___pe6___bit 6 +#define reg_pinmux_rw_pe_gio___pe7___lsb 7 +#define reg_pinmux_rw_pe_gio___pe7___width 1 +#define reg_pinmux_rw_pe_gio___pe7___bit 7 +#define reg_pinmux_rw_pe_gio___pe8___lsb 8 +#define reg_pinmux_rw_pe_gio___pe8___width 1 +#define reg_pinmux_rw_pe_gio___pe8___bit 8 +#define reg_pinmux_rw_pe_gio___pe9___lsb 9 +#define reg_pinmux_rw_pe_gio___pe9___width 1 +#define reg_pinmux_rw_pe_gio___pe9___bit 9 +#define reg_pinmux_rw_pe_gio___pe10___lsb 10 +#define reg_pinmux_rw_pe_gio___pe10___width 1 +#define reg_pinmux_rw_pe_gio___pe10___bit 10 +#define reg_pinmux_rw_pe_gio___pe11___lsb 11 +#define reg_pinmux_rw_pe_gio___pe11___width 1 +#define reg_pinmux_rw_pe_gio___pe11___bit 11 +#define reg_pinmux_rw_pe_gio___pe12___lsb 12 +#define reg_pinmux_rw_pe_gio___pe12___width 1 +#define reg_pinmux_rw_pe_gio___pe12___bit 12 +#define reg_pinmux_rw_pe_gio___pe13___lsb 13 +#define reg_pinmux_rw_pe_gio___pe13___width 1 +#define reg_pinmux_rw_pe_gio___pe13___bit 13 +#define reg_pinmux_rw_pe_gio___pe14___lsb 14 +#define reg_pinmux_rw_pe_gio___pe14___width 1 +#define reg_pinmux_rw_pe_gio___pe14___bit 14 +#define reg_pinmux_rw_pe_gio___pe15___lsb 15 +#define reg_pinmux_rw_pe_gio___pe15___width 1 +#define reg_pinmux_rw_pe_gio___pe15___bit 15 +#define reg_pinmux_rw_pe_gio___pe16___lsb 16 +#define reg_pinmux_rw_pe_gio___pe16___width 1 +#define reg_pinmux_rw_pe_gio___pe16___bit 16 +#define reg_pinmux_rw_pe_gio___pe17___lsb 17 +#define reg_pinmux_rw_pe_gio___pe17___width 1 +#define reg_pinmux_rw_pe_gio___pe17___bit 17 +#define reg_pinmux_rw_pe_gio_offset 32 + +/* Register rw_pe_iop, scope pinmux, type rw */ +#define reg_pinmux_rw_pe_iop___pe0___lsb 0 +#define reg_pinmux_rw_pe_iop___pe0___width 1 +#define reg_pinmux_rw_pe_iop___pe0___bit 0 +#define reg_pinmux_rw_pe_iop___pe1___lsb 1 +#define reg_pinmux_rw_pe_iop___pe1___width 1 +#define reg_pinmux_rw_pe_iop___pe1___bit 1 +#define reg_pinmux_rw_pe_iop___pe2___lsb 2 +#define reg_pinmux_rw_pe_iop___pe2___width 1 +#define reg_pinmux_rw_pe_iop___pe2___bit 2 +#define reg_pinmux_rw_pe_iop___pe3___lsb 3 +#define reg_pinmux_rw_pe_iop___pe3___width 1 +#define reg_pinmux_rw_pe_iop___pe3___bit 3 +#define reg_pinmux_rw_pe_iop___pe4___lsb 4 +#define reg_pinmux_rw_pe_iop___pe4___width 1 +#define reg_pinmux_rw_pe_iop___pe4___bit 4 +#define reg_pinmux_rw_pe_iop___pe5___lsb 5 +#define reg_pinmux_rw_pe_iop___pe5___width 1 +#define reg_pinmux_rw_pe_iop___pe5___bit 5 +#define reg_pinmux_rw_pe_iop___pe6___lsb 6 +#define reg_pinmux_rw_pe_iop___pe6___width 1 +#define reg_pinmux_rw_pe_iop___pe6___bit 6 +#define reg_pinmux_rw_pe_iop___pe7___lsb 7 +#define reg_pinmux_rw_pe_iop___pe7___width 1 +#define reg_pinmux_rw_pe_iop___pe7___bit 7 +#define reg_pinmux_rw_pe_iop___pe8___lsb 8 +#define reg_pinmux_rw_pe_iop___pe8___width 1 +#define reg_pinmux_rw_pe_iop___pe8___bit 8 +#define reg_pinmux_rw_pe_iop___pe9___lsb 9 +#define reg_pinmux_rw_pe_iop___pe9___width 1 +#define reg_pinmux_rw_pe_iop___pe9___bit 9 +#define reg_pinmux_rw_pe_iop___pe10___lsb 10 +#define reg_pinmux_rw_pe_iop___pe10___width 1 +#define reg_pinmux_rw_pe_iop___pe10___bit 10 +#define reg_pinmux_rw_pe_iop___pe11___lsb 11 +#define reg_pinmux_rw_pe_iop___pe11___width 1 +#define reg_pinmux_rw_pe_iop___pe11___bit 11 +#define reg_pinmux_rw_pe_iop___pe12___lsb 12 +#define reg_pinmux_rw_pe_iop___pe12___width 1 +#define reg_pinmux_rw_pe_iop___pe12___bit 12 +#define reg_pinmux_rw_pe_iop___pe13___lsb 13 +#define reg_pinmux_rw_pe_iop___pe13___width 1 +#define reg_pinmux_rw_pe_iop___pe13___bit 13 +#define reg_pinmux_rw_pe_iop___pe14___lsb 14 +#define reg_pinmux_rw_pe_iop___pe14___width 1 +#define reg_pinmux_rw_pe_iop___pe14___bit 14 +#define reg_pinmux_rw_pe_iop___pe15___lsb 15 +#define reg_pinmux_rw_pe_iop___pe15___width 1 +#define reg_pinmux_rw_pe_iop___pe15___bit 15 +#define reg_pinmux_rw_pe_iop___pe16___lsb 16 +#define reg_pinmux_rw_pe_iop___pe16___width 1 +#define reg_pinmux_rw_pe_iop___pe16___bit 16 +#define reg_pinmux_rw_pe_iop___pe17___lsb 17 +#define reg_pinmux_rw_pe_iop___pe17___width 1 +#define reg_pinmux_rw_pe_iop___pe17___bit 17 +#define reg_pinmux_rw_pe_iop_offset 36 + +/* Register rw_usb_phy, scope pinmux, type rw */ +#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 +#define reg_pinmux_rw_usb_phy___en_usb0___width 1 +#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 +#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 +#define reg_pinmux_rw_usb_phy___en_usb1___width 1 +#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 +#define reg_pinmux_rw_usb_phy_offset 40 + + +/* Constants */ +#define regk_pinmux_no 0x00000000 +#define regk_pinmux_rw_hwprot_default 0x00000000 +#define regk_pinmux_rw_pa_default 0x00000000 +#define regk_pinmux_rw_pb_gio_default 0x00000000 +#define regk_pinmux_rw_pb_iop_default 0x00000000 +#define regk_pinmux_rw_pc_gio_default 0x00000000 +#define regk_pinmux_rw_pc_iop_default 0x00000000 +#define regk_pinmux_rw_pd_gio_default 0x00000000 +#define regk_pinmux_rw_pd_iop_default 0x00000000 +#define regk_pinmux_rw_pe_gio_default 0x00000000 +#define regk_pinmux_rw_pe_iop_default 0x00000000 +#define regk_pinmux_rw_usb_phy_default 0x00000000 +#define regk_pinmux_yes 0x00000001 +#endif /* __pinmux_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h new file mode 100644 index 000000000..87517aebd --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h @@ -0,0 +1,96 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: ../../mod/fakereg.rmap + * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp + * last modified: Wed Feb 11 20:53:25 2004 + * file: ../../rtl/global.rmap + * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp + * last modified: Mon Aug 18 17:08:23 2003 + * file: ../../mod/modreg.rmap + * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp + * last modified: Fri Feb 20 16:40:04 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap + * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +#define regi_artpec_mod 0xb7044000 +#define regi_ata 0xb0032000 +#define regi_ata_mod 0xb7006000 +#define regi_barber 0xb701a000 +#define regi_bif_core 0xb0014000 +#define regi_bif_dma 0xb0016000 +#define regi_bif_slave 0xb0018000 +#define regi_bif_slave_ext 0xac000000 +#define regi_bus_master 0xb703c000 +#define regi_config 0xb003c000 +#define regi_dma0 0xb0000000 +#define regi_dma1 0xb0002000 +#define regi_dma2 0xb0004000 +#define regi_dma3 0xb0006000 +#define regi_dma4 0xb0008000 +#define regi_dma5 0xb000a000 +#define regi_dma6 0xb000c000 +#define regi_dma7 0xb000e000 +#define regi_dma8 0xb0010000 +#define regi_dma9 0xb0012000 +#define regi_eth0 0xb0034000 +#define regi_eth1 0xb0036000 +#define regi_eth_mod 0xb7004000 +#define regi_eth_mod1 0xb701c000 +#define regi_eth_strmod 0xb7008000 +#define regi_eth_strmod1 0xb7032000 +#define regi_ext_dma 0xb703a000 +#define regi_ext_mem 0xb7046000 +#define regi_gen_io 0xb7016000 +#define regi_gio 0xb001a000 +#define regi_hook 0xb7000000 +#define regi_iop 0xb0020000 +#define regi_irq 0xb001c000 +#define regi_irq_nmi 0xb701e000 +#define regi_marb 0xb003e000 +#define regi_marb_bp0 0xb003e240 +#define regi_marb_bp1 0xb003e280 +#define regi_marb_bp2 0xb003e2c0 +#define regi_marb_bp3 0xb003e300 +#define regi_nand_mod 0xb7014000 +#define regi_p21 0xb002e000 +#define regi_p21_mod 0xb7042000 +#define regi_pci_mod 0xb7010000 +#define regi_pin_test 0xb7018000 +#define regi_pinmux 0xb0038000 +#define regi_sdram_chk 0xb703e000 +#define regi_sdram_mod 0xb7012000 +#define regi_ser0 0xb0026000 +#define regi_ser1 0xb0028000 +#define regi_ser2 0xb002a000 +#define regi_ser3 0xb002c000 +#define regi_ser_mod0 0xb7020000 +#define regi_ser_mod1 0xb7022000 +#define regi_ser_mod2 0xb7024000 +#define regi_ser_mod3 0xb7026000 +#define regi_smif_stat 0xb700e000 +#define regi_sser0 0xb0022000 +#define regi_sser1 0xb0024000 +#define regi_sser_mod0 0xb700a000 +#define regi_sser_mod1 0xb700c000 +#define regi_strcop 0xb0030000 +#define regi_strmux 0xb003a000 +#define regi_strmux_tst 0xb7040000 +#define regi_tap 0xb7002000 +#define regi_timer 0xb001e000 +#define regi_timer_mod 0xb7034000 +#define regi_trace 0xb0040000 +#define regi_usb0 0xb7028000 +#define regi_usb1 0xb702a000 +#define regi_usb2 0xb702c000 +#define regi_usb3 0xb702e000 +#define regi_usb_dev 0xb7030000 +#define regi_utmi_mod0 0xb7036000 +#define regi_utmi_mod1 0xb7038000 +#endif /* __reg_map_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h new file mode 100644 index 000000000..e1197194d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h @@ -0,0 +1,229 @@ +#ifndef __timer_defs_asm_h +#define __timer_defs_asm_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ + +#ifndef REG_FIELD +#define REG_FIELD( scope, reg, field, value ) \ + REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_FIELD_X_( value, shift ) ((value) << shift) +#endif + +#ifndef REG_STATE +#define REG_STATE( scope, reg, field, symbolic_value ) \ + REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) +#define REG_STATE_X_( k, shift ) (k << shift) +#endif + +#ifndef REG_MASK +#define REG_MASK( scope, reg, field ) \ + REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) +#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) +#endif + +#ifndef REG_LSB +#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb +#endif + +#ifndef REG_BIT +#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) +#define REG_ADDR_X_( inst, offs ) ((inst) + offs) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ + STRIDE_##scope##_##reg ) +#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ + ((inst) + offs + (index) * stride) +#endif + +/* Register rw_tmr0_div, scope timer, type rw */ +#define reg_timer_rw_tmr0_div_offset 0 + +/* Register r_tmr0_data, scope timer, type r */ +#define reg_timer_r_tmr0_data_offset 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr0_ctrl___op___lsb 0 +#define reg_timer_rw_tmr0_ctrl___op___width 2 +#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr0_ctrl___freq___width 3 +#define reg_timer_rw_tmr0_ctrl_offset 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +#define reg_timer_rw_tmr1_div_offset 16 + +/* Register r_tmr1_data, scope timer, type r */ +#define reg_timer_r_tmr1_data_offset 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +#define reg_timer_rw_tmr1_ctrl___op___lsb 0 +#define reg_timer_rw_tmr1_ctrl___op___width 2 +#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 +#define reg_timer_rw_tmr1_ctrl___freq___width 3 +#define reg_timer_rw_tmr1_ctrl_offset 24 + +/* Register rs_cnt_data, scope timer, type rs */ +#define reg_timer_rs_cnt_data___tmr___lsb 0 +#define reg_timer_rs_cnt_data___tmr___width 24 +#define reg_timer_rs_cnt_data___cnt___lsb 24 +#define reg_timer_rs_cnt_data___cnt___width 8 +#define reg_timer_rs_cnt_data_offset 32 + +/* Register r_cnt_data, scope timer, type r */ +#define reg_timer_r_cnt_data___tmr___lsb 0 +#define reg_timer_r_cnt_data___tmr___width 24 +#define reg_timer_r_cnt_data___cnt___lsb 24 +#define reg_timer_r_cnt_data___cnt___width 8 +#define reg_timer_r_cnt_data_offset 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +#define reg_timer_rw_cnt_cfg___clk___lsb 0 +#define reg_timer_rw_cnt_cfg___clk___width 2 +#define reg_timer_rw_cnt_cfg_offset 40 + +/* Register rw_trig, scope timer, type rw */ +#define reg_timer_rw_trig_offset 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +#define reg_timer_rw_trig_cfg___tmr___lsb 0 +#define reg_timer_rw_trig_cfg___tmr___width 2 +#define reg_timer_rw_trig_cfg_offset 52 + +/* Register r_time, scope timer, type r */ +#define reg_timer_r_time_offset 56 + +/* Register rw_out, scope timer, type rw */ +#define reg_timer_rw_out___tmr___lsb 0 +#define reg_timer_rw_out___tmr___width 2 +#define reg_timer_rw_out_offset 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +#define reg_timer_rw_wd_ctrl___cnt___lsb 0 +#define reg_timer_rw_wd_ctrl___cnt___width 8 +#define reg_timer_rw_wd_ctrl___cmd___lsb 8 +#define reg_timer_rw_wd_ctrl___cmd___width 1 +#define reg_timer_rw_wd_ctrl___cmd___bit 8 +#define reg_timer_rw_wd_ctrl___key___lsb 9 +#define reg_timer_rw_wd_ctrl___key___width 7 +#define reg_timer_rw_wd_ctrl_offset 64 + +/* Register r_wd_stat, scope timer, type r */ +#define reg_timer_r_wd_stat___cnt___lsb 0 +#define reg_timer_r_wd_stat___cnt___width 8 +#define reg_timer_r_wd_stat___cmd___lsb 8 +#define reg_timer_r_wd_stat___cmd___width 1 +#define reg_timer_r_wd_stat___cmd___bit 8 +#define reg_timer_r_wd_stat_offset 68 + +/* Register rw_intr_mask, scope timer, type rw */ +#define reg_timer_rw_intr_mask___tmr0___lsb 0 +#define reg_timer_rw_intr_mask___tmr0___width 1 +#define reg_timer_rw_intr_mask___tmr0___bit 0 +#define reg_timer_rw_intr_mask___tmr1___lsb 1 +#define reg_timer_rw_intr_mask___tmr1___width 1 +#define reg_timer_rw_intr_mask___tmr1___bit 1 +#define reg_timer_rw_intr_mask___cnt___lsb 2 +#define reg_timer_rw_intr_mask___cnt___width 1 +#define reg_timer_rw_intr_mask___cnt___bit 2 +#define reg_timer_rw_intr_mask___trig___lsb 3 +#define reg_timer_rw_intr_mask___trig___width 1 +#define reg_timer_rw_intr_mask___trig___bit 3 +#define reg_timer_rw_intr_mask_offset 72 + +/* Register rw_ack_intr, scope timer, type rw */ +#define reg_timer_rw_ack_intr___tmr0___lsb 0 +#define reg_timer_rw_ack_intr___tmr0___width 1 +#define reg_timer_rw_ack_intr___tmr0___bit 0 +#define reg_timer_rw_ack_intr___tmr1___lsb 1 +#define reg_timer_rw_ack_intr___tmr1___width 1 +#define reg_timer_rw_ack_intr___tmr1___bit 1 +#define reg_timer_rw_ack_intr___cnt___lsb 2 +#define reg_timer_rw_ack_intr___cnt___width 1 +#define reg_timer_rw_ack_intr___cnt___bit 2 +#define reg_timer_rw_ack_intr___trig___lsb 3 +#define reg_timer_rw_ack_intr___trig___width 1 +#define reg_timer_rw_ack_intr___trig___bit 3 +#define reg_timer_rw_ack_intr_offset 76 + +/* Register r_intr, scope timer, type r */ +#define reg_timer_r_intr___tmr0___lsb 0 +#define reg_timer_r_intr___tmr0___width 1 +#define reg_timer_r_intr___tmr0___bit 0 +#define reg_timer_r_intr___tmr1___lsb 1 +#define reg_timer_r_intr___tmr1___width 1 +#define reg_timer_r_intr___tmr1___bit 1 +#define reg_timer_r_intr___cnt___lsb 2 +#define reg_timer_r_intr___cnt___width 1 +#define reg_timer_r_intr___cnt___bit 2 +#define reg_timer_r_intr___trig___lsb 3 +#define reg_timer_r_intr___trig___width 1 +#define reg_timer_r_intr___trig___bit 3 +#define reg_timer_r_intr_offset 80 + +/* Register r_masked_intr, scope timer, type r */ +#define reg_timer_r_masked_intr___tmr0___lsb 0 +#define reg_timer_r_masked_intr___tmr0___width 1 +#define reg_timer_r_masked_intr___tmr0___bit 0 +#define reg_timer_r_masked_intr___tmr1___lsb 1 +#define reg_timer_r_masked_intr___tmr1___width 1 +#define reg_timer_r_masked_intr___tmr1___bit 1 +#define reg_timer_r_masked_intr___cnt___lsb 2 +#define reg_timer_r_masked_intr___cnt___width 1 +#define reg_timer_r_masked_intr___cnt___bit 2 +#define reg_timer_r_masked_intr___trig___lsb 3 +#define reg_timer_r_masked_intr___trig___width 1 +#define reg_timer_r_masked_intr___trig___bit 3 +#define reg_timer_r_masked_intr_offset 84 + +/* Register rw_test, scope timer, type rw */ +#define reg_timer_rw_test___dis___lsb 0 +#define reg_timer_rw_test___dis___width 1 +#define reg_timer_rw_test___dis___bit 0 +#define reg_timer_rw_test___en___lsb 1 +#define reg_timer_rw_test___en___width 1 +#define reg_timer_rw_test___en___bit 1 +#define reg_timer_rw_test_offset 88 + + +/* Constants */ +#define regk_timer_ext 0x00000001 +#define regk_timer_f100 0x00000007 +#define regk_timer_f29_493 0x00000004 +#define regk_timer_f32 0x00000005 +#define regk_timer_f32_768 0x00000006 +#define regk_timer_hold 0x00000001 +#define regk_timer_ld 0x00000000 +#define regk_timer_no 0x00000000 +#define regk_timer_off 0x00000000 +#define regk_timer_run 0x00000002 +#define regk_timer_rw_cnt_cfg_default 0x00000000 +#define regk_timer_rw_intr_mask_default 0x00000000 +#define regk_timer_rw_out_default 0x00000000 +#define regk_timer_rw_test_default 0x00000000 +#define regk_timer_rw_tmr0_ctrl_default 0x00000000 +#define regk_timer_rw_tmr1_ctrl_default 0x00000000 +#define regk_timer_rw_trig_cfg_default 0x00000000 +#define regk_timer_start 0x00000001 +#define regk_timer_stop 0x00000000 +#define regk_timer_time 0x00000001 +#define regk_timer_tmr0 0x00000002 +#define regk_timer_tmr1 0x00000003 +#define regk_timer_yes 0x00000001 +#endif /* __timer_defs_asm_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h new file mode 100644 index 000000000..44362a62b --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h @@ -0,0 +1,284 @@ +#ifndef __bif_core_defs_h +#define __bif_core_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_core_regs.r + * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r + * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_core */ + +/* Register rw_grp1_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp1_cfg; +#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 +#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 + +/* Register rw_grp2_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 10; +} reg_bif_core_rw_grp2_cfg; +#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 +#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 + +/* Register rw_grp3_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 2; + unsigned int gated_csp0 : 2; + unsigned int gated_csp1 : 2; + unsigned int gated_csp2 : 2; + unsigned int gated_csp3 : 2; +} reg_bif_core_rw_grp3_cfg; +#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 +#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 + +/* Register rw_grp4_cfg, scope bif_core, type rw */ +typedef struct { + unsigned int lw : 6; + unsigned int ew : 3; + unsigned int zw : 3; + unsigned int aw : 2; + unsigned int dw : 2; + unsigned int ewb : 2; + unsigned int bw : 1; + unsigned int wr_extend : 1; + unsigned int erc_en : 1; + unsigned int mode : 1; + unsigned int dummy1 : 4; + unsigned int gated_csp4 : 2; + unsigned int gated_csp5 : 2; + unsigned int gated_csp6 : 2; +} reg_bif_core_rw_grp4_cfg; +#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 +#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 + +/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int grp_sel : 5; + unsigned int dummy1 : 12; +} reg_bif_core_rw_sdram_cfg_grp0; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 + +/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ +typedef struct { + unsigned int bank_sel : 5; + unsigned int ca : 3; + unsigned int type : 1; + unsigned int bw : 1; + unsigned int sh : 3; + unsigned int wmm : 1; + unsigned int sh16 : 1; + unsigned int dummy1 : 17; +} reg_bif_core_rw_sdram_cfg_grp1; +#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 +#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 + +/* Register rw_sdram_timing, scope bif_core, type rw */ +typedef struct { + unsigned int cl : 3; + unsigned int rcd : 3; + unsigned int rp : 3; + unsigned int rc : 2; + unsigned int dpl : 2; + unsigned int pde : 1; + unsigned int ref : 2; + unsigned int cpd : 1; + unsigned int sdcke : 1; + unsigned int sdclk : 1; + unsigned int dummy1 : 13; +} reg_bif_core_rw_sdram_timing; +#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 +#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 + +/* Register rw_sdram_cmd, scope bif_core, type rw */ +typedef struct { + unsigned int cmd : 3; + unsigned int mrs_data : 15; + unsigned int dummy1 : 14; +} reg_bif_core_rw_sdram_cmd; +#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 +#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 + +/* Register rs_sdram_ref_stat, scope bif_core, type rs */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_rs_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 + +/* Register r_sdram_ref_stat, scope bif_core, type r */ +typedef struct { + unsigned int ok : 1; + unsigned int dummy1 : 31; +} reg_bif_core_r_sdram_ref_stat; +#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 + + +/* Constants */ +enum { + regk_bif_core_bank2 = 0x00000000, + regk_bif_core_bank4 = 0x00000001, + regk_bif_core_bit10 = 0x0000000a, + regk_bif_core_bit11 = 0x0000000b, + regk_bif_core_bit12 = 0x0000000c, + regk_bif_core_bit13 = 0x0000000d, + regk_bif_core_bit14 = 0x0000000e, + regk_bif_core_bit15 = 0x0000000f, + regk_bif_core_bit16 = 0x00000010, + regk_bif_core_bit17 = 0x00000011, + regk_bif_core_bit18 = 0x00000012, + regk_bif_core_bit19 = 0x00000013, + regk_bif_core_bit20 = 0x00000014, + regk_bif_core_bit21 = 0x00000015, + regk_bif_core_bit22 = 0x00000016, + regk_bif_core_bit23 = 0x00000017, + regk_bif_core_bit24 = 0x00000018, + regk_bif_core_bit25 = 0x00000019, + regk_bif_core_bit26 = 0x0000001a, + regk_bif_core_bit27 = 0x0000001b, + regk_bif_core_bit28 = 0x0000001c, + regk_bif_core_bit29 = 0x0000001d, + regk_bif_core_bit9 = 0x00000009, + regk_bif_core_bw16 = 0x00000001, + regk_bif_core_bw32 = 0x00000000, + regk_bif_core_bwe = 0x00000000, + regk_bif_core_cwe = 0x00000001, + regk_bif_core_e15us = 0x00000001, + regk_bif_core_e7800ns = 0x00000002, + regk_bif_core_grp0 = 0x00000000, + regk_bif_core_grp1 = 0x00000001, + regk_bif_core_mrs = 0x00000003, + regk_bif_core_no = 0x00000000, + regk_bif_core_none = 0x00000000, + regk_bif_core_nop = 0x00000000, + regk_bif_core_off = 0x00000000, + regk_bif_core_pre = 0x00000002, + regk_bif_core_r_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rd = 0x00000002, + regk_bif_core_ref = 0x00000001, + regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, + regk_bif_core_rw_grp1_cfg_default = 0x000006cf, + regk_bif_core_rw_grp2_cfg_default = 0x000006cf, + regk_bif_core_rw_grp3_cfg_default = 0x000006cf, + regk_bif_core_rw_grp4_cfg_default = 0x000006cf, + regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, + regk_bif_core_slf = 0x00000004, + regk_bif_core_wr = 0x00000001, + regk_bif_core_yes = 0x00000001 +}; +#endif /* __bif_core_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h new file mode 100644 index 000000000..3cb51a09d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h @@ -0,0 +1,473 @@ +#ifndef __bif_dma_defs_h +#define __bif_dma_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_dma_regs.r + * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp + * last modfied: Mon Apr 11 16:06:33 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r + * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_dma */ + +/* Register rw_ch0_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch0_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 +#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 + +/* Register rw_ch0_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch0_addr; +#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 +#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 + +/* Register rw_ch0_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch0_start; +#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 +#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 + +/* Register rw_ch0_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch0_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 +#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 + +/* Register r_ch0_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch0_stat; +#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 + +/* Register rw_ch1_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch1_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 +#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 + +/* Register rw_ch1_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch1_addr; +#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 +#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 + +/* Register rw_ch1_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch1_start; +#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 +#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 + +/* Register rw_ch1_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch1_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 +#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 + +/* Register r_ch1_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch1_stat; +#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 + +/* Register rw_ch2_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_pad : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int wr_all : 1; + unsigned int dummy1 : 12; +} reg_bif_dma_rw_ch2_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 +#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 + +/* Register rw_ch2_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch2_addr; +#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 +#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 + +/* Register rw_ch2_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch2_start; +#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 +#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 + +/* Register rw_ch2_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch2_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 +#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 + +/* Register r_ch2_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch2_stat; +#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 + +/* Register rw_ch3_ctrl, scope bif_dma, type rw */ +typedef struct { + unsigned int bw : 2; + unsigned int burst_len : 1; + unsigned int cont : 1; + unsigned int end_discard : 1; + unsigned int cnt : 1; + unsigned int dreq_pin : 3; + unsigned int dreq_mode : 2; + unsigned int tc_in_pin : 3; + unsigned int tc_in_mode : 2; + unsigned int bus_mode : 2; + unsigned int rate_en : 1; + unsigned int dummy1 : 13; +} reg_bif_dma_rw_ch3_ctrl; +#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 +#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 + +/* Register rw_ch3_addr, scope bif_dma, type rw */ +typedef struct { + unsigned int addr : 32; +} reg_bif_dma_rw_ch3_addr; +#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 +#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 + +/* Register rw_ch3_start, scope bif_dma, type rw */ +typedef struct { + unsigned int run : 1; + unsigned int dummy1 : 31; +} reg_bif_dma_rw_ch3_start; +#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 +#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 + +/* Register rw_ch3_cnt, scope bif_dma, type rw */ +typedef struct { + unsigned int start_cnt : 16; + unsigned int dummy1 : 16; +} reg_bif_dma_rw_ch3_cnt; +#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 +#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 + +/* Register r_ch3_stat, scope bif_dma, type r */ +typedef struct { + unsigned int cnt : 16; + unsigned int dummy1 : 15; + unsigned int run : 1; +} reg_bif_dma_r_ch3_stat; +#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 + +/* Register rw_intr_mask, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_intr_mask; +#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 +#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 + +/* Register rw_ack_intr, scope bif_dma, type rw */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_rw_ack_intr; +#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 +#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 + +/* Register r_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_intr; +#define REG_RD_ADDR_bif_dma_r_intr 136 + +/* Register r_masked_intr, scope bif_dma, type r */ +typedef struct { + unsigned int ext_dma0 : 1; + unsigned int ext_dma1 : 1; + unsigned int ext_dma2 : 1; + unsigned int ext_dma3 : 1; + unsigned int dummy1 : 28; +} reg_bif_dma_r_masked_intr; +#define REG_RD_ADDR_bif_dma_r_masked_intr 140 + +/* Register rw_pin0_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin0_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 +#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 + +/* Register rw_pin1_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin1_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 +#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 + +/* Register rw_pin2_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin2_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 +#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 + +/* Register rw_pin3_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin3_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 +#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 + +/* Register rw_pin4_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin4_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 +#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 + +/* Register rw_pin5_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin5_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 +#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 + +/* Register rw_pin6_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin6_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 +#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 + +/* Register rw_pin7_cfg, scope bif_dma, type rw */ +typedef struct { + unsigned int master_ch : 2; + unsigned int master_mode : 3; + unsigned int slave_ch : 2; + unsigned int slave_mode : 3; + unsigned int dummy1 : 22; +} reg_bif_dma_rw_pin7_cfg; +#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 +#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 + +/* Register r_pin_stat, scope bif_dma, type r */ +typedef struct { + unsigned int pin0 : 1; + unsigned int pin1 : 1; + unsigned int pin2 : 1; + unsigned int pin3 : 1; + unsigned int pin4 : 1; + unsigned int pin5 : 1; + unsigned int pin6 : 1; + unsigned int pin7 : 1; + unsigned int dummy1 : 24; +} reg_bif_dma_r_pin_stat; +#define REG_RD_ADDR_bif_dma_r_pin_stat 192 + + +/* Constants */ +enum { + regk_bif_dma_as_master = 0x00000001, + regk_bif_dma_as_slave = 0x00000001, + regk_bif_dma_burst1 = 0x00000000, + regk_bif_dma_burst8 = 0x00000001, + regk_bif_dma_bw16 = 0x00000001, + regk_bif_dma_bw32 = 0x00000002, + regk_bif_dma_bw8 = 0x00000000, + regk_bif_dma_dack = 0x00000006, + regk_bif_dma_dack_inv = 0x00000007, + regk_bif_dma_force = 0x00000001, + regk_bif_dma_hi = 0x00000003, + regk_bif_dma_inv = 0x00000003, + regk_bif_dma_lo = 0x00000002, + regk_bif_dma_master = 0x00000001, + regk_bif_dma_no = 0x00000000, + regk_bif_dma_norm = 0x00000002, + regk_bif_dma_off = 0x00000000, + regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch0_start_default = 0x00000000, + regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch1_start_default = 0x00000000, + regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch2_start_default = 0x00000000, + regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, + regk_bif_dma_rw_ch3_start_default = 0x00000000, + regk_bif_dma_rw_intr_mask_default = 0x00000000, + regk_bif_dma_rw_pin0_cfg_default = 0x00000000, + regk_bif_dma_rw_pin1_cfg_default = 0x00000000, + regk_bif_dma_rw_pin2_cfg_default = 0x00000000, + regk_bif_dma_rw_pin3_cfg_default = 0x00000000, + regk_bif_dma_rw_pin4_cfg_default = 0x00000000, + regk_bif_dma_rw_pin5_cfg_default = 0x00000000, + regk_bif_dma_rw_pin6_cfg_default = 0x00000000, + regk_bif_dma_rw_pin7_cfg_default = 0x00000000, + regk_bif_dma_slave = 0x00000002, + regk_bif_dma_sreq = 0x00000006, + regk_bif_dma_sreq_inv = 0x00000007, + regk_bif_dma_tc = 0x00000004, + regk_bif_dma_tc_inv = 0x00000005, + regk_bif_dma_yes = 0x00000001 +}; +#endif /* __bif_dma_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h new file mode 100644 index 000000000..0c434585a --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h @@ -0,0 +1,249 @@ +#ifndef __bif_slave_defs_h +#define __bif_slave_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/bif/rtl/bif_slave_regs.r + * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp + * last modfied: Mon Apr 11 16:06:34 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r + * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope bif_slave */ + +/* Register rw_slave_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int slave_id : 3; + unsigned int use_slave_id : 1; + unsigned int boot_rdy : 1; + unsigned int loopback : 1; + unsigned int dis : 1; + unsigned int dummy1 : 25; +} reg_bif_slave_rw_slave_cfg; +#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 +#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 + +/* Register r_slave_mode, scope bif_slave, type r */ +typedef struct { + unsigned int ch0_mode : 1; + unsigned int ch1_mode : 1; + unsigned int ch2_mode : 1; + unsigned int ch3_mode : 1; + unsigned int dummy1 : 28; +} reg_bif_slave_r_slave_mode; +#define REG_RD_ADDR_bif_slave_r_slave_mode 4 + +/* Register rw_ch0_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch0_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 +#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 + +/* Register rw_ch1_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch1_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 +#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 + +/* Register rw_ch2_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch2_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 +#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 + +/* Register rw_ch3_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int rd_hold : 2; + unsigned int access_mode : 1; + unsigned int access_ctrl : 1; + unsigned int data_cs : 2; + unsigned int dummy1 : 26; +} reg_bif_slave_rw_ch3_cfg; +#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 +#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 + +/* Register rw_arb_cfg, scope bif_slave, type rw */ +typedef struct { + unsigned int brin_mode : 1; + unsigned int brout_mode : 3; + unsigned int bg_mode : 3; + unsigned int release : 2; + unsigned int acquire : 1; + unsigned int settle_time : 2; + unsigned int dram_ctrl : 1; + unsigned int dummy1 : 19; +} reg_bif_slave_rw_arb_cfg; +#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 +#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 + +/* Register r_arb_stat, scope bif_slave, type r */ +typedef struct { + unsigned int init_mode : 1; + unsigned int mode : 1; + unsigned int brin : 1; + unsigned int brout : 1; + unsigned int bg : 1; + unsigned int dummy1 : 27; +} reg_bif_slave_r_arb_stat; +#define REG_RD_ADDR_bif_slave_r_arb_stat 36 + +/* Register rw_intr_mask, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_intr_mask; +#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 +#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 + +/* Register rw_ack_intr, scope bif_slave, type rw */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_rw_ack_intr; +#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 +#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 + +/* Register r_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_intr; +#define REG_RD_ADDR_bif_slave_r_intr 72 + +/* Register r_masked_intr, scope bif_slave, type r */ +typedef struct { + unsigned int bus_release : 1; + unsigned int bus_acquire : 1; + unsigned int dummy1 : 30; +} reg_bif_slave_r_masked_intr; +#define REG_RD_ADDR_bif_slave_r_masked_intr 76 + + +/* Constants */ +enum { + regk_bif_slave_active_hi = 0x00000003, + regk_bif_slave_active_lo = 0x00000002, + regk_bif_slave_addr = 0x00000000, + regk_bif_slave_always = 0x00000001, + regk_bif_slave_at_idle = 0x00000002, + regk_bif_slave_burst_end = 0x00000003, + regk_bif_slave_dma = 0x00000001, + regk_bif_slave_hi = 0x00000003, + regk_bif_slave_inv = 0x00000001, + regk_bif_slave_lo = 0x00000002, + regk_bif_slave_local = 0x00000001, + regk_bif_slave_master = 0x00000000, + regk_bif_slave_mode_reg = 0x00000001, + regk_bif_slave_no = 0x00000000, + regk_bif_slave_norm = 0x00000000, + regk_bif_slave_on_access = 0x00000000, + regk_bif_slave_rw_arb_cfg_default = 0x00000000, + regk_bif_slave_rw_ch0_cfg_default = 0x00000000, + regk_bif_slave_rw_ch1_cfg_default = 0x00000000, + regk_bif_slave_rw_ch2_cfg_default = 0x00000000, + regk_bif_slave_rw_ch3_cfg_default = 0x00000000, + regk_bif_slave_rw_intr_mask_default = 0x00000000, + regk_bif_slave_rw_slave_cfg_default = 0x00000000, + regk_bif_slave_shared = 0x00000000, + regk_bif_slave_slave = 0x00000001, + regk_bif_slave_t0ns = 0x00000003, + regk_bif_slave_t10ns = 0x00000002, + regk_bif_slave_t20ns = 0x00000003, + regk_bif_slave_t30ns = 0x00000002, + regk_bif_slave_t40ns = 0x00000001, + regk_bif_slave_t50ns = 0x00000000, + regk_bif_slave_yes = 0x00000001, + regk_bif_slave_z = 0x00000004 +}; +#endif /* __bif_slave_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h new file mode 100644 index 000000000..abc5f2070 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h @@ -0,0 +1,142 @@ +#ifndef __config_defs_h +#define __config_defs_h + +/* + * This file is autogenerated from + * file: ../../rtl/config_regs.r + * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp + * last modfied: Thu Mar 4 12:34:39 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r + * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope config */ + +/* Register r_bootsel, scope config, type r */ +typedef struct { + unsigned int boot_mode : 3; + unsigned int full_duplex : 1; + unsigned int user : 1; + unsigned int pll : 1; + unsigned int flash_bw : 1; + unsigned int dummy1 : 25; +} reg_config_r_bootsel; +#define REG_RD_ADDR_config_r_bootsel 0 + +/* Register rw_clk_ctrl, scope config, type rw */ +typedef struct { + unsigned int pll : 1; + unsigned int cpu : 1; + unsigned int iop : 1; + unsigned int dma01_eth0 : 1; + unsigned int dma23 : 1; + unsigned int dma45 : 1; + unsigned int dma67 : 1; + unsigned int dma89_strcop : 1; + unsigned int bif : 1; + unsigned int fix_io : 1; + unsigned int dummy1 : 22; +} reg_config_rw_clk_ctrl; +#define REG_RD_ADDR_config_rw_clk_ctrl 4 +#define REG_WR_ADDR_config_rw_clk_ctrl 4 + +/* Register rw_pad_ctrl, scope config, type rw */ +typedef struct { + unsigned int usb_susp : 1; + unsigned int phyrst_n : 1; + unsigned int dummy1 : 30; +} reg_config_rw_pad_ctrl; +#define REG_RD_ADDR_config_rw_pad_ctrl 8 +#define REG_WR_ADDR_config_rw_pad_ctrl 8 + + +/* Constants */ +enum { + regk_config_bw16 = 0x00000000, + regk_config_bw32 = 0x00000001, + regk_config_master = 0x00000005, + regk_config_nand = 0x00000003, + regk_config_net_rx = 0x00000001, + regk_config_net_tx_rx = 0x00000002, + regk_config_no = 0x00000000, + regk_config_none = 0x00000007, + regk_config_nor = 0x00000000, + regk_config_rw_clk_ctrl_default = 0x00000002, + regk_config_rw_pad_ctrl_default = 0x00000000, + regk_config_ser = 0x00000004, + regk_config_slave = 0x00000006, + regk_config_yes = 0x00000001 +}; +#endif /* __config_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h new file mode 100644 index 000000000..26aa3efcf --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h @@ -0,0 +1,295 @@ +#ifndef __gio_defs_h +#define __gio_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/gio/rtl/gio_regs.r + * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp + * last modfied: Mon Apr 11 16:07:47 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r + * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope gio */ + +/* Register rw_pa_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_dout; +#define REG_RD_ADDR_gio_rw_pa_dout 0 +#define REG_WR_ADDR_gio_rw_pa_dout 0 + +/* Register r_pa_din, scope gio, type r */ +typedef struct { + unsigned int data : 8; + unsigned int dummy1 : 24; +} reg_gio_r_pa_din; +#define REG_RD_ADDR_gio_r_pa_din 4 + +/* Register rw_pa_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 8; + unsigned int dummy1 : 24; +} reg_gio_rw_pa_oe; +#define REG_RD_ADDR_gio_rw_pa_oe 8 +#define REG_WR_ADDR_gio_rw_pa_oe 8 + +/* Register rw_intr_cfg, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 3; + unsigned int pa1 : 3; + unsigned int pa2 : 3; + unsigned int pa3 : 3; + unsigned int pa4 : 3; + unsigned int pa5 : 3; + unsigned int pa6 : 3; + unsigned int pa7 : 3; + unsigned int dummy1 : 8; +} reg_gio_rw_intr_cfg; +#define REG_RD_ADDR_gio_rw_intr_cfg 12 +#define REG_WR_ADDR_gio_rw_intr_cfg 12 + +/* Register rw_intr_mask, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_rw_intr_mask; +#define REG_RD_ADDR_gio_rw_intr_mask 16 +#define REG_WR_ADDR_gio_rw_intr_mask 16 + +/* Register rw_ack_intr, scope gio, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_rw_ack_intr; +#define REG_RD_ADDR_gio_rw_ack_intr 20 +#define REG_WR_ADDR_gio_rw_ack_intr 20 + +/* Register r_intr, scope gio, type r */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_r_intr; +#define REG_RD_ADDR_gio_r_intr 24 + +/* Register r_masked_intr, scope gio, type r */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int dummy1 : 24; +} reg_gio_r_masked_intr; +#define REG_RD_ADDR_gio_r_masked_intr 28 + +/* Register rw_pb_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pb_dout; +#define REG_RD_ADDR_gio_rw_pb_dout 32 +#define REG_WR_ADDR_gio_rw_pb_dout 32 + +/* Register r_pb_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pb_din; +#define REG_RD_ADDR_gio_r_pb_din 36 + +/* Register rw_pb_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pb_oe; +#define REG_RD_ADDR_gio_rw_pb_oe 40 +#define REG_WR_ADDR_gio_rw_pb_oe 40 + +/* Register rw_pc_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pc_dout; +#define REG_RD_ADDR_gio_rw_pc_dout 48 +#define REG_WR_ADDR_gio_rw_pc_dout 48 + +/* Register r_pc_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pc_din; +#define REG_RD_ADDR_gio_r_pc_din 52 + +/* Register rw_pc_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pc_oe; +#define REG_RD_ADDR_gio_rw_pc_oe 56 +#define REG_WR_ADDR_gio_rw_pc_oe 56 + +/* Register rw_pd_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pd_dout; +#define REG_RD_ADDR_gio_rw_pd_dout 64 +#define REG_WR_ADDR_gio_rw_pd_dout 64 + +/* Register r_pd_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pd_din; +#define REG_RD_ADDR_gio_r_pd_din 68 + +/* Register rw_pd_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pd_oe; +#define REG_RD_ADDR_gio_rw_pd_oe 72 +#define REG_WR_ADDR_gio_rw_pd_oe 72 + +/* Register rw_pe_dout, scope gio, type rw */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pe_dout; +#define REG_RD_ADDR_gio_rw_pe_dout 80 +#define REG_WR_ADDR_gio_rw_pe_dout 80 + +/* Register r_pe_din, scope gio, type r */ +typedef struct { + unsigned int data : 18; + unsigned int dummy1 : 14; +} reg_gio_r_pe_din; +#define REG_RD_ADDR_gio_r_pe_din 84 + +/* Register rw_pe_oe, scope gio, type rw */ +typedef struct { + unsigned int oe : 18; + unsigned int dummy1 : 14; +} reg_gio_rw_pe_oe; +#define REG_RD_ADDR_gio_rw_pe_oe 88 +#define REG_WR_ADDR_gio_rw_pe_oe 88 + + +/* Constants */ +enum { + regk_gio_anyedge = 0x00000007, + regk_gio_hi = 0x00000001, + regk_gio_lo = 0x00000002, + regk_gio_negedge = 0x00000006, + regk_gio_no = 0x00000000, + regk_gio_off = 0x00000000, + regk_gio_posedge = 0x00000005, + regk_gio_rw_intr_cfg_default = 0x00000000, + regk_gio_rw_intr_mask_default = 0x00000000, + regk_gio_rw_pa_oe_default = 0x00000000, + regk_gio_rw_pb_oe_default = 0x00000000, + regk_gio_rw_pc_oe_default = 0x00000000, + regk_gio_rw_pd_oe_default = 0x00000000, + regk_gio_rw_pe_oe_default = 0x00000000, + regk_gio_set = 0x00000003, + regk_gio_yes = 0x00000001 +}; +#endif /* __gio_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h new file mode 100644 index 000000000..bacc2a895 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h @@ -0,0 +1,41 @@ +/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version + from ../../inst/intr_vect/rtl/guinness/ivmask.config.r +version . */ + +#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R +#define MEMARB_INTR_VECT 0x31 +#define GEN_IO_INTR_VECT 0x32 +#define GIO_INTR_VECT GEN_IO_INTR_VECT +#define IOP0_INTR_VECT 0x33 +#define IOP1_INTR_VECT 0x34 +#define IOP2_INTR_VECT 0x35 +#define IOP3_INTR_VECT 0x36 +#define DMA0_INTR_VECT 0x37 +#define DMA1_INTR_VECT 0x38 +#define DMA2_INTR_VECT 0x39 +#define DMA3_INTR_VECT 0x3a +#define DMA4_INTR_VECT 0x3b +#define DMA5_INTR_VECT 0x3c +#define DMA6_INTR_VECT 0x3d +#define DMA7_INTR_VECT 0x3e +#define DMA8_INTR_VECT 0x3f +#define DMA9_INTR_VECT 0x40 +#define ATA_INTR_VECT 0x41 +#define SSER0_INTR_VECT 0x42 +#define SSER1_INTR_VECT 0x43 +#define SER0_INTR_VECT 0x44 +#define SER1_INTR_VECT 0x45 +#define SER2_INTR_VECT 0x46 +#define SER3_INTR_VECT 0x47 +#define P21_INTR_VECT 0x48 +#define ETH0_INTR_VECT 0x49 +#define ETH1_INTR_VECT 0x4a +#define TIMER_INTR_VECT 0x4b +#define TIMER0_INTR_VECT TIMER_INTR_VECT +#define BIF_ARB_INTR_VECT 0x4c +#define BIF_DMA_INTR_VECT 0x4d +#define EXT_INTR_VECT 0x4e +#define IPI_INTR_VECT 0x4f +#define NBR_INTR_VECT 0x50 +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h new file mode 100644 index 000000000..aa65128ae --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h @@ -0,0 +1,228 @@ +#ifndef __intr_vect_defs_h +#define __intr_vect_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp + * last modfied: Mon Apr 11 16:08:03 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r + * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope intr_vect */ + +#define STRIDE_intr_vect_rw_mask 0 +/* Register rw_mask, scope intr_vect, type rw */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer0 : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_rw_mask; +#define REG_RD_ADDR_intr_vect_rw_mask 0 +#define REG_WR_ADDR_intr_vect_rw_mask 0 + +#define STRIDE_intr_vect_r_vect 0 +/* Register r_vect, scope intr_vect, type r */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_r_vect; +#define REG_RD_ADDR_intr_vect_r_vect 4 + +#define STRIDE_intr_vect_r_masked_vect 0 +/* Register r_masked_vect, scope intr_vect, type r */ +typedef struct { + unsigned int memarb : 1; + unsigned int gen_io : 1; + unsigned int iop0 : 1; + unsigned int iop1 : 1; + unsigned int iop2 : 1; + unsigned int iop3 : 1; + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int ata : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ser0 : 1; + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int p21 : 1; + unsigned int eth0 : 1; + unsigned int eth1 : 1; + unsigned int timer : 1; + unsigned int bif_arb : 1; + unsigned int bif_dma : 1; + unsigned int ext : 1; + unsigned int dummy1 : 2; +} reg_intr_vect_r_masked_vect; +#define REG_RD_ADDR_intr_vect_r_masked_vect 8 + +/* Register r_nmi, scope intr_vect, type r */ +typedef struct { + unsigned int ext : 1; + unsigned int watchdog : 1; + unsigned int dummy1 : 30; +} reg_intr_vect_r_nmi; +#define REG_RD_ADDR_intr_vect_r_nmi 12 + +/* Register r_guru, scope intr_vect, type r */ +typedef struct { + unsigned int jtag : 1; + unsigned int dummy1 : 31; +} reg_intr_vect_r_guru; +#define REG_RD_ADDR_intr_vect_r_guru 16 + +/* Register rw_ipi, scope intr_vect, type rw */ +typedef struct +{ + unsigned int vector; +} reg_intr_vect_rw_ipi; +#define REG_RD_ADDR_intr_vect_rw_ipi 20 +#define REG_WR_ADDR_intr_vect_rw_ipi 20 + +/* Constants */ +enum { + regk_intr_vect_off = 0x00000000, + regk_intr_vect_on = 0x00000001, + regk_intr_vect_rw_mask_default = 0x00000000 +}; +#endif /* __intr_vect_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h new file mode 100644 index 000000000..dcaaec462 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h @@ -0,0 +1,205 @@ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Fri Nov 7 15:36:04 2003 + * + * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_break_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_addr; +#define REG_RD_ADDR_marb_bp_r_break_addr 20 + +/* Register r_break_op, scope marb_bp, type r */ +typedef struct { + unsigned int read : 1; + unsigned int write : 1; + unsigned int read_excl : 1; + unsigned int pri_write : 1; + unsigned int us_read : 1; + unsigned int us_write : 1; + unsigned int us_read_excl : 1; + unsigned int us_pri_write : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_break_op; +#define REG_RD_ADDR_marb_bp_r_break_op 24 + +/* Register r_break_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_clients; +#define REG_RD_ADDR_marb_bp_r_break_clients 28 + +/* Register r_break_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_break_first_client; +#define REG_RD_ADDR_marb_bp_r_break_first_client 32 + +/* Register r_break_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_break_size; +#define REG_RD_ADDR_marb_bp_r_break_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h new file mode 100644 index 000000000..254da0854 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h @@ -0,0 +1,475 @@ +#ifndef __marb_defs_h +#define __marb_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb */ + +#define STRIDE_marb_rw_int_slots 4 +/* Register rw_int_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_int_slots; +#define REG_RD_ADDR_marb_rw_int_slots 0 +#define REG_WR_ADDR_marb_rw_int_slots 0 + +#define STRIDE_marb_rw_ext_slots 4 +/* Register rw_ext_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_ext_slots; +#define REG_RD_ADDR_marb_rw_ext_slots 256 +#define REG_WR_ADDR_marb_rw_ext_slots 256 + +#define STRIDE_marb_rw_regs_slots 4 +/* Register rw_regs_slots, scope marb, type rw */ +typedef struct { + unsigned int owner : 4; + unsigned int dummy1 : 28; +} reg_marb_rw_regs_slots; +#define REG_RD_ADDR_marb_rw_regs_slots 512 +#define REG_WR_ADDR_marb_rw_regs_slots 512 + +/* Register rw_intr_mask, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_intr_mask; +#define REG_RD_ADDR_marb_rw_intr_mask 528 +#define REG_WR_ADDR_marb_rw_intr_mask 528 + +/* Register rw_ack_intr, scope marb, type rw */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_rw_ack_intr; +#define REG_RD_ADDR_marb_rw_ack_intr 532 +#define REG_WR_ADDR_marb_rw_ack_intr 532 + +/* Register r_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_intr; +#define REG_RD_ADDR_marb_r_intr 536 + +/* Register r_masked_intr, scope marb, type r */ +typedef struct { + unsigned int bp0 : 1; + unsigned int bp1 : 1; + unsigned int bp2 : 1; + unsigned int bp3 : 1; + unsigned int dummy1 : 28; +} reg_marb_r_masked_intr; +#define REG_RD_ADDR_marb_r_masked_intr 540 + +/* Register rw_stop_mask, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_stop_mask; +#define REG_RD_ADDR_marb_rw_stop_mask 544 +#define REG_WR_ADDR_marb_rw_stop_mask 544 + +/* Register r_stopped, scope marb, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_r_stopped; +#define REG_RD_ADDR_marb_r_stopped 548 + +/* Register rw_no_snoop, scope marb, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_rw_no_snoop; +#define REG_RD_ADDR_marb_rw_no_snoop 832 +#define REG_WR_ADDR_marb_rw_no_snoop 832 + +/* Register rw_no_snoop_rq, scope marb, type rw */ +typedef struct { + unsigned int dummy1 : 10; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int dummy2 : 20; +} reg_marb_rw_no_snoop_rq; +#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 +#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 + + +/* Constants */ +enum { + regk_marb_cpud = 0x0000000b, + regk_marb_cpui = 0x0000000a, + regk_marb_dma0 = 0x00000000, + regk_marb_dma1 = 0x00000001, + regk_marb_dma2 = 0x00000002, + regk_marb_dma3 = 0x00000003, + regk_marb_dma4 = 0x00000004, + regk_marb_dma5 = 0x00000005, + regk_marb_dma6 = 0x00000006, + regk_marb_dma7 = 0x00000007, + regk_marb_dma8 = 0x00000008, + regk_marb_dma9 = 0x00000009, + regk_marb_iop = 0x0000000c, + regk_marb_no = 0x00000000, + regk_marb_r_stopped_default = 0x00000000, + regk_marb_rw_ext_slots_default = 0x00000000, + regk_marb_rw_ext_slots_size = 0x00000040, + regk_marb_rw_int_slots_default = 0x00000000, + regk_marb_rw_int_slots_size = 0x00000040, + regk_marb_rw_intr_mask_default = 0x00000000, + regk_marb_rw_no_snoop_default = 0x00000000, + regk_marb_rw_no_snoop_rq_default = 0x00000000, + regk_marb_rw_regs_slots_default = 0x00000000, + regk_marb_rw_regs_slots_size = 0x00000004, + regk_marb_rw_stop_mask_default = 0x00000000, + regk_marb_slave = 0x0000000d, + regk_marb_yes = 0x00000001 +}; +#endif /* __marb_defs_h */ +#ifndef __marb_bp_defs_h +#define __marb_bp_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/memarb/rtl/guinness/marb_top.r + * id: + * last modfied: Mon Apr 11 16:12:16 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r + * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope marb_bp */ + +/* Register rw_first_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_first_addr; +#define REG_RD_ADDR_marb_bp_rw_first_addr 0 +#define REG_WR_ADDR_marb_bp_rw_first_addr 0 + +/* Register rw_last_addr, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_last_addr; +#define REG_RD_ADDR_marb_bp_rw_last_addr 4 +#define REG_WR_ADDR_marb_bp_rw_last_addr 4 + +/* Register rw_op, scope marb_bp, type rw */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_rw_op; +#define REG_RD_ADDR_marb_bp_rw_op 8 +#define REG_WR_ADDR_marb_bp_rw_op 8 + +/* Register rw_clients, scope marb_bp, type rw */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_rw_clients; +#define REG_RD_ADDR_marb_bp_rw_clients 12 +#define REG_WR_ADDR_marb_bp_rw_clients 12 + +/* Register rw_options, scope marb_bp, type rw */ +typedef struct { + unsigned int wrap : 1; + unsigned int dummy1 : 31; +} reg_marb_bp_rw_options; +#define REG_RD_ADDR_marb_bp_rw_options 16 +#define REG_WR_ADDR_marb_bp_rw_options 16 + +/* Register r_brk_addr, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_addr; +#define REG_RD_ADDR_marb_bp_r_brk_addr 20 + +/* Register r_brk_op, scope marb_bp, type r */ +typedef struct { + unsigned int rd : 1; + unsigned int wr : 1; + unsigned int rd_excl : 1; + unsigned int pri_wr : 1; + unsigned int us_rd : 1; + unsigned int us_wr : 1; + unsigned int us_rd_excl : 1; + unsigned int us_pri_wr : 1; + unsigned int dummy1 : 24; +} reg_marb_bp_r_brk_op; +#define REG_RD_ADDR_marb_bp_r_brk_op 24 + +/* Register r_brk_clients, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_clients; +#define REG_RD_ADDR_marb_bp_r_brk_clients 28 + +/* Register r_brk_first_client, scope marb_bp, type r */ +typedef struct { + unsigned int dma0 : 1; + unsigned int dma1 : 1; + unsigned int dma2 : 1; + unsigned int dma3 : 1; + unsigned int dma4 : 1; + unsigned int dma5 : 1; + unsigned int dma6 : 1; + unsigned int dma7 : 1; + unsigned int dma8 : 1; + unsigned int dma9 : 1; + unsigned int cpui : 1; + unsigned int cpud : 1; + unsigned int iop : 1; + unsigned int slave : 1; + unsigned int dummy1 : 18; +} reg_marb_bp_r_brk_first_client; +#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 + +/* Register r_brk_size, scope marb_bp, type r */ +typedef unsigned int reg_marb_bp_r_brk_size; +#define REG_RD_ADDR_marb_bp_r_brk_size 36 + +/* Register rw_ack, scope marb_bp, type rw */ +typedef unsigned int reg_marb_bp_rw_ack; +#define REG_RD_ADDR_marb_bp_rw_ack 40 +#define REG_WR_ADDR_marb_bp_rw_ack 40 + + +/* Constants */ +enum { + regk_marb_bp_no = 0x00000000, + regk_marb_bp_rw_op_default = 0x00000000, + regk_marb_bp_rw_options_default = 0x00000000, + regk_marb_bp_yes = 0x00000001 +}; +#endif /* __marb_bp_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h new file mode 100644 index 000000000..751eab5f1 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h @@ -0,0 +1,357 @@ +#ifndef __pinmux_defs_h +#define __pinmux_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp + * last modfied: Mon Apr 11 16:09:11 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r + * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope pinmux */ + +/* Register rw_pa, scope pinmux, type rw */ +typedef struct { + unsigned int pa0 : 1; + unsigned int pa1 : 1; + unsigned int pa2 : 1; + unsigned int pa3 : 1; + unsigned int pa4 : 1; + unsigned int pa5 : 1; + unsigned int pa6 : 1; + unsigned int pa7 : 1; + unsigned int csp2_n : 1; + unsigned int csp3_n : 1; + unsigned int csp5_n : 1; + unsigned int csp6_n : 1; + unsigned int hsh4 : 1; + unsigned int hsh5 : 1; + unsigned int hsh6 : 1; + unsigned int hsh7 : 1; + unsigned int dummy1 : 16; +} reg_pinmux_rw_pa; +#define REG_RD_ADDR_pinmux_rw_pa 0 +#define REG_WR_ADDR_pinmux_rw_pa 0 + +/* Register rw_hwprot, scope pinmux, type rw */ +typedef struct { + unsigned int ser1 : 1; + unsigned int ser2 : 1; + unsigned int ser3 : 1; + unsigned int sser0 : 1; + unsigned int sser1 : 1; + unsigned int ata0 : 1; + unsigned int ata1 : 1; + unsigned int ata2 : 1; + unsigned int ata3 : 1; + unsigned int ata : 1; + unsigned int eth1 : 1; + unsigned int eth1_mgm : 1; + unsigned int timer : 1; + unsigned int p21 : 1; + unsigned int dummy1 : 18; +} reg_pinmux_rw_hwprot; +#define REG_RD_ADDR_pinmux_rw_hwprot 4 +#define REG_WR_ADDR_pinmux_rw_hwprot 4 + +/* Register rw_pb_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pb_gio; +#define REG_RD_ADDR_pinmux_rw_pb_gio 8 +#define REG_WR_ADDR_pinmux_rw_pb_gio 8 + +/* Register rw_pb_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pb0 : 1; + unsigned int pb1 : 1; + unsigned int pb2 : 1; + unsigned int pb3 : 1; + unsigned int pb4 : 1; + unsigned int pb5 : 1; + unsigned int pb6 : 1; + unsigned int pb7 : 1; + unsigned int pb8 : 1; + unsigned int pb9 : 1; + unsigned int pb10 : 1; + unsigned int pb11 : 1; + unsigned int pb12 : 1; + unsigned int pb13 : 1; + unsigned int pb14 : 1; + unsigned int pb15 : 1; + unsigned int pb16 : 1; + unsigned int pb17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pb_iop; +#define REG_RD_ADDR_pinmux_rw_pb_iop 12 +#define REG_WR_ADDR_pinmux_rw_pb_iop 12 + +/* Register rw_pc_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int pc16 : 1; + unsigned int pc17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pc_gio; +#define REG_RD_ADDR_pinmux_rw_pc_gio 16 +#define REG_WR_ADDR_pinmux_rw_pc_gio 16 + +/* Register rw_pc_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pc0 : 1; + unsigned int pc1 : 1; + unsigned int pc2 : 1; + unsigned int pc3 : 1; + unsigned int pc4 : 1; + unsigned int pc5 : 1; + unsigned int pc6 : 1; + unsigned int pc7 : 1; + unsigned int pc8 : 1; + unsigned int pc9 : 1; + unsigned int pc10 : 1; + unsigned int pc11 : 1; + unsigned int pc12 : 1; + unsigned int pc13 : 1; + unsigned int pc14 : 1; + unsigned int pc15 : 1; + unsigned int pc16 : 1; + unsigned int pc17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pc_iop; +#define REG_RD_ADDR_pinmux_rw_pc_iop 20 +#define REG_WR_ADDR_pinmux_rw_pc_iop 20 + +/* Register rw_pd_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pd0 : 1; + unsigned int pd1 : 1; + unsigned int pd2 : 1; + unsigned int pd3 : 1; + unsigned int pd4 : 1; + unsigned int pd5 : 1; + unsigned int pd6 : 1; + unsigned int pd7 : 1; + unsigned int pd8 : 1; + unsigned int pd9 : 1; + unsigned int pd10 : 1; + unsigned int pd11 : 1; + unsigned int pd12 : 1; + unsigned int pd13 : 1; + unsigned int pd14 : 1; + unsigned int pd15 : 1; + unsigned int pd16 : 1; + unsigned int pd17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pd_gio; +#define REG_RD_ADDR_pinmux_rw_pd_gio 24 +#define REG_WR_ADDR_pinmux_rw_pd_gio 24 + +/* Register rw_pd_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pd0 : 1; + unsigned int pd1 : 1; + unsigned int pd2 : 1; + unsigned int pd3 : 1; + unsigned int pd4 : 1; + unsigned int pd5 : 1; + unsigned int pd6 : 1; + unsigned int pd7 : 1; + unsigned int pd8 : 1; + unsigned int pd9 : 1; + unsigned int pd10 : 1; + unsigned int pd11 : 1; + unsigned int pd12 : 1; + unsigned int pd13 : 1; + unsigned int pd14 : 1; + unsigned int pd15 : 1; + unsigned int pd16 : 1; + unsigned int pd17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pd_iop; +#define REG_RD_ADDR_pinmux_rw_pd_iop 28 +#define REG_WR_ADDR_pinmux_rw_pd_iop 28 + +/* Register rw_pe_gio, scope pinmux, type rw */ +typedef struct { + unsigned int pe0 : 1; + unsigned int pe1 : 1; + unsigned int pe2 : 1; + unsigned int pe3 : 1; + unsigned int pe4 : 1; + unsigned int pe5 : 1; + unsigned int pe6 : 1; + unsigned int pe7 : 1; + unsigned int pe8 : 1; + unsigned int pe9 : 1; + unsigned int pe10 : 1; + unsigned int pe11 : 1; + unsigned int pe12 : 1; + unsigned int pe13 : 1; + unsigned int pe14 : 1; + unsigned int pe15 : 1; + unsigned int pe16 : 1; + unsigned int pe17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pe_gio; +#define REG_RD_ADDR_pinmux_rw_pe_gio 32 +#define REG_WR_ADDR_pinmux_rw_pe_gio 32 + +/* Register rw_pe_iop, scope pinmux, type rw */ +typedef struct { + unsigned int pe0 : 1; + unsigned int pe1 : 1; + unsigned int pe2 : 1; + unsigned int pe3 : 1; + unsigned int pe4 : 1; + unsigned int pe5 : 1; + unsigned int pe6 : 1; + unsigned int pe7 : 1; + unsigned int pe8 : 1; + unsigned int pe9 : 1; + unsigned int pe10 : 1; + unsigned int pe11 : 1; + unsigned int pe12 : 1; + unsigned int pe13 : 1; + unsigned int pe14 : 1; + unsigned int pe15 : 1; + unsigned int pe16 : 1; + unsigned int pe17 : 1; + unsigned int dummy1 : 14; +} reg_pinmux_rw_pe_iop; +#define REG_RD_ADDR_pinmux_rw_pe_iop 36 +#define REG_WR_ADDR_pinmux_rw_pe_iop 36 + +/* Register rw_usb_phy, scope pinmux, type rw */ +typedef struct { + unsigned int en_usb0 : 1; + unsigned int en_usb1 : 1; + unsigned int dummy1 : 30; +} reg_pinmux_rw_usb_phy; +#define REG_RD_ADDR_pinmux_rw_usb_phy 40 +#define REG_WR_ADDR_pinmux_rw_usb_phy 40 + + +/* Constants */ +enum { + regk_pinmux_no = 0x00000000, + regk_pinmux_rw_hwprot_default = 0x00000000, + regk_pinmux_rw_pa_default = 0x00000000, + regk_pinmux_rw_pb_gio_default = 0x00000000, + regk_pinmux_rw_pb_iop_default = 0x00000000, + regk_pinmux_rw_pc_gio_default = 0x00000000, + regk_pinmux_rw_pc_iop_default = 0x00000000, + regk_pinmux_rw_pd_gio_default = 0x00000000, + regk_pinmux_rw_pd_iop_default = 0x00000000, + regk_pinmux_rw_pe_gio_default = 0x00000000, + regk_pinmux_rw_pe_iop_default = 0x00000000, + regk_pinmux_rw_usb_phy_default = 0x00000000, + regk_pinmux_yes = 0x00000001 +}; +#endif /* __pinmux_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h new file mode 100644 index 000000000..4146973a5 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h @@ -0,0 +1,104 @@ +#ifndef __reg_map_h +#define __reg_map_h + +/* + * This file is autogenerated from + * file: ../../mod/fakereg.rmap + * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp + * last modified: Wed Feb 11 20:53:25 2004 + * file: ../../rtl/global.rmap + * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp + * last modified: Mon Aug 18 17:08:23 2003 + * file: ../../mod/modreg.rmap + * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp + * last modified: Fri Feb 20 16:40:04 2004 + * + * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap + * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +typedef enum { + regi_ata = 0xb0032000, + regi_bif_core = 0xb0014000, + regi_bif_dma = 0xb0016000, + regi_bif_slave = 0xb0018000, + regi_config = 0xb003c000, + regi_dma0 = 0xb0000000, + regi_dma1 = 0xb0002000, + regi_dma2 = 0xb0004000, + regi_dma3 = 0xb0006000, + regi_dma4 = 0xb0008000, + regi_dma5 = 0xb000a000, + regi_dma6 = 0xb000c000, + regi_dma7 = 0xb000e000, + regi_dma8 = 0xb0010000, + regi_dma9 = 0xb0012000, + regi_eth0 = 0xb0034000, + regi_eth1 = 0xb0036000, + regi_gio = 0xb001a000, + regi_iop = 0xb0020000, + regi_iop_version = 0xb0020000, + regi_iop_fifo_in0_extra = 0xb0020040, + regi_iop_fifo_in1_extra = 0xb0020080, + regi_iop_fifo_out0_extra = 0xb00200c0, + regi_iop_fifo_out1_extra = 0xb0020100, + regi_iop_trigger_grp0 = 0xb0020140, + regi_iop_trigger_grp1 = 0xb0020180, + regi_iop_trigger_grp2 = 0xb00201c0, + regi_iop_trigger_grp3 = 0xb0020200, + regi_iop_trigger_grp4 = 0xb0020240, + regi_iop_trigger_grp5 = 0xb0020280, + regi_iop_trigger_grp6 = 0xb00202c0, + regi_iop_trigger_grp7 = 0xb0020300, + regi_iop_crc_par0 = 0xb0020380, + regi_iop_crc_par1 = 0xb0020400, + regi_iop_dmc_in0 = 0xb0020480, + regi_iop_dmc_in1 = 0xb0020500, + regi_iop_dmc_out0 = 0xb0020580, + regi_iop_dmc_out1 = 0xb0020600, + regi_iop_fifo_in0 = 0xb0020680, + regi_iop_fifo_in1 = 0xb0020700, + regi_iop_fifo_out0 = 0xb0020780, + regi_iop_fifo_out1 = 0xb0020800, + regi_iop_scrc_in0 = 0xb0020880, + regi_iop_scrc_in1 = 0xb0020900, + regi_iop_scrc_out0 = 0xb0020980, + regi_iop_scrc_out1 = 0xb0020a00, + regi_iop_timer_grp0 = 0xb0020a80, + regi_iop_timer_grp1 = 0xb0020b00, + regi_iop_timer_grp2 = 0xb0020b80, + regi_iop_timer_grp3 = 0xb0020c00, + regi_iop_sap_in = 0xb0020d00, + regi_iop_sap_out = 0xb0020e00, + regi_iop_spu0 = 0xb0020f00, + regi_iop_spu1 = 0xb0021000, + regi_iop_sw_cfg = 0xb0021100, + regi_iop_sw_cpu = 0xb0021200, + regi_iop_sw_mpu = 0xb0021300, + regi_iop_sw_spu0 = 0xb0021400, + regi_iop_sw_spu1 = 0xb0021500, + regi_iop_mpu = 0xb0021600, + regi_irq = 0xb001c000, + regi_irq2 = 0xb005c000, + regi_marb = 0xb003e000, + regi_marb_bp0 = 0xb003e240, + regi_marb_bp1 = 0xb003e280, + regi_marb_bp2 = 0xb003e2c0, + regi_marb_bp3 = 0xb003e300, + regi_pinmux = 0xb0038000, + regi_ser0 = 0xb0026000, + regi_ser1 = 0xb0028000, + regi_ser2 = 0xb002a000, + regi_ser3 = 0xb002c000, + regi_sser0 = 0xb0022000, + regi_sser1 = 0xb0024000, + regi_strcop = 0xb0030000, + regi_strmux = 0xb003a000, + regi_timer = 0xb001e000, + regi_timer0 = 0xb001e000, + regi_timer2 = 0xb005e000, + regi_trace = 0xb0040000, +} reg_scope_instances; +#endif /* __reg_map_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h new file mode 100644 index 000000000..cbfaa8678 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h @@ -0,0 +1,127 @@ +#ifndef __strmux_defs_h +#define __strmux_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp + * last modfied: Mon Apr 11 16:09:43 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r + * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope strmux */ + +/* Register rw_cfg, scope strmux, type rw */ +typedef struct { + unsigned int dma0 : 3; + unsigned int dma1 : 3; + unsigned int dma2 : 3; + unsigned int dma3 : 3; + unsigned int dma4 : 3; + unsigned int dma5 : 3; + unsigned int dma6 : 3; + unsigned int dma7 : 3; + unsigned int dma8 : 3; + unsigned int dma9 : 3; + unsigned int dummy1 : 2; +} reg_strmux_rw_cfg; +#define REG_RD_ADDR_strmux_rw_cfg 0 +#define REG_WR_ADDR_strmux_rw_cfg 0 + + +/* Constants */ +enum { + regk_strmux_ata = 0x00000003, + regk_strmux_eth0 = 0x00000001, + regk_strmux_eth1 = 0x00000004, + regk_strmux_ext0 = 0x00000001, + regk_strmux_ext1 = 0x00000001, + regk_strmux_ext2 = 0x00000001, + regk_strmux_ext3 = 0x00000001, + regk_strmux_iop0 = 0x00000002, + regk_strmux_iop1 = 0x00000001, + regk_strmux_off = 0x00000000, + regk_strmux_p21 = 0x00000004, + regk_strmux_rw_cfg_default = 0x00000000, + regk_strmux_ser0 = 0x00000002, + regk_strmux_ser1 = 0x00000002, + regk_strmux_ser2 = 0x00000004, + regk_strmux_ser3 = 0x00000003, + regk_strmux_sser0 = 0x00000003, + regk_strmux_sser1 = 0x00000003, + regk_strmux_strcop = 0x00000002 +}; +#endif /* __strmux_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h new file mode 100644 index 000000000..76bcc5919 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h @@ -0,0 +1,266 @@ +#ifndef __timer_defs_h +#define __timer_defs_h + +/* + * This file is autogenerated from + * file: ../../inst/timer/rtl/timer_regs.r + * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp + * last modfied: Mon Apr 11 16:09:53 2005 + * + * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r + * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ + * Any changes here will be lost. + * + * -*- buffer-read-only: t -*- + */ +/* Main access macros */ +#ifndef REG_RD +#define REG_RD( scope, inst, reg ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR +#define REG_WR( scope, inst, reg, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_VECT +#define REG_RD_VECT( scope, inst, reg, index ) \ + REG_READ( reg_##scope##_##reg, \ + (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_VECT +#define REG_WR_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( reg_##scope##_##reg, \ + (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT +#define REG_RD_INT( scope, inst, reg ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT +#define REG_WR_INT( scope, inst, reg, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) +#endif + +#ifndef REG_RD_INT_VECT +#define REG_RD_INT_VECT( scope, inst, reg, index ) \ + REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +#ifndef REG_WR_INT_VECT +#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ + REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg, (val) ) +#endif + +#ifndef REG_TYPE_CONV +#define REG_TYPE_CONV( type, orgtype, val ) \ + ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) +#endif + +#ifndef reg_page_size +#define reg_page_size 8192 +#endif + +#ifndef REG_ADDR +#define REG_ADDR( scope, inst, reg ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg ) +#endif + +#ifndef REG_ADDR_VECT +#define REG_ADDR_VECT( scope, inst, reg, index ) \ + ( (inst) + REG_RD_ADDR_##scope##_##reg + \ + (index) * STRIDE_##scope##_##reg ) +#endif + +/* C-code for register scope timer */ + +/* Register rw_tmr0_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr0_div; +#define REG_RD_ADDR_timer_rw_tmr0_div 0 +#define REG_WR_ADDR_timer_rw_tmr0_div 0 + +/* Register r_tmr0_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr0_data; +#define REG_RD_ADDR_timer_r_tmr0_data 4 + +/* Register rw_tmr0_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr0_ctrl; +#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 +#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 + +/* Register rw_tmr1_div, scope timer, type rw */ +typedef unsigned int reg_timer_rw_tmr1_div; +#define REG_RD_ADDR_timer_rw_tmr1_div 16 +#define REG_WR_ADDR_timer_rw_tmr1_div 16 + +/* Register r_tmr1_data, scope timer, type r */ +typedef unsigned int reg_timer_r_tmr1_data; +#define REG_RD_ADDR_timer_r_tmr1_data 20 + +/* Register rw_tmr1_ctrl, scope timer, type rw */ +typedef struct { + unsigned int op : 2; + unsigned int freq : 3; + unsigned int dummy1 : 27; +} reg_timer_rw_tmr1_ctrl; +#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 +#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 + +/* Register rs_cnt_data, scope timer, type rs */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_rs_cnt_data; +#define REG_RD_ADDR_timer_rs_cnt_data 32 + +/* Register r_cnt_data, scope timer, type r */ +typedef struct { + unsigned int tmr : 24; + unsigned int cnt : 8; +} reg_timer_r_cnt_data; +#define REG_RD_ADDR_timer_r_cnt_data 36 + +/* Register rw_cnt_cfg, scope timer, type rw */ +typedef struct { + unsigned int clk : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_cnt_cfg; +#define REG_RD_ADDR_timer_rw_cnt_cfg 40 +#define REG_WR_ADDR_timer_rw_cnt_cfg 40 + +/* Register rw_trig, scope timer, type rw */ +typedef unsigned int reg_timer_rw_trig; +#define REG_RD_ADDR_timer_rw_trig 48 +#define REG_WR_ADDR_timer_rw_trig 48 + +/* Register rw_trig_cfg, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_trig_cfg; +#define REG_RD_ADDR_timer_rw_trig_cfg 52 +#define REG_WR_ADDR_timer_rw_trig_cfg 52 + +/* Register r_time, scope timer, type r */ +typedef unsigned int reg_timer_r_time; +#define REG_RD_ADDR_timer_r_time 56 + +/* Register rw_out, scope timer, type rw */ +typedef struct { + unsigned int tmr : 2; + unsigned int dummy1 : 30; +} reg_timer_rw_out; +#define REG_RD_ADDR_timer_rw_out 60 +#define REG_WR_ADDR_timer_rw_out 60 + +/* Register rw_wd_ctrl, scope timer, type rw */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int key : 7; + unsigned int dummy1 : 16; +} reg_timer_rw_wd_ctrl; +#define REG_RD_ADDR_timer_rw_wd_ctrl 64 +#define REG_WR_ADDR_timer_rw_wd_ctrl 64 + +/* Register r_wd_stat, scope timer, type r */ +typedef struct { + unsigned int cnt : 8; + unsigned int cmd : 1; + unsigned int dummy1 : 23; +} reg_timer_r_wd_stat; +#define REG_RD_ADDR_timer_r_wd_stat 68 + +/* Register rw_intr_mask, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_intr_mask; +#define REG_RD_ADDR_timer_rw_intr_mask 72 +#define REG_WR_ADDR_timer_rw_intr_mask 72 + +/* Register rw_ack_intr, scope timer, type rw */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_rw_ack_intr; +#define REG_RD_ADDR_timer_rw_ack_intr 76 +#define REG_WR_ADDR_timer_rw_ack_intr 76 + +/* Register r_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_intr; +#define REG_RD_ADDR_timer_r_intr 80 + +/* Register r_masked_intr, scope timer, type r */ +typedef struct { + unsigned int tmr0 : 1; + unsigned int tmr1 : 1; + unsigned int cnt : 1; + unsigned int trig : 1; + unsigned int dummy1 : 28; +} reg_timer_r_masked_intr; +#define REG_RD_ADDR_timer_r_masked_intr 84 + +/* Register rw_test, scope timer, type rw */ +typedef struct { + unsigned int dis : 1; + unsigned int en : 1; + unsigned int dummy1 : 30; +} reg_timer_rw_test; +#define REG_RD_ADDR_timer_rw_test 88 +#define REG_WR_ADDR_timer_rw_test 88 + + +/* Constants */ +enum { + regk_timer_ext = 0x00000001, + regk_timer_f100 = 0x00000007, + regk_timer_f29_493 = 0x00000004, + regk_timer_f32 = 0x00000005, + regk_timer_f32_768 = 0x00000006, + regk_timer_hold = 0x00000001, + regk_timer_ld = 0x00000000, + regk_timer_no = 0x00000000, + regk_timer_off = 0x00000000, + regk_timer_run = 0x00000002, + regk_timer_rw_cnt_cfg_default = 0x00000000, + regk_timer_rw_intr_mask_default = 0x00000000, + regk_timer_rw_out_default = 0x00000000, + regk_timer_rw_test_default = 0x00000000, + regk_timer_rw_tmr0_ctrl_default = 0x00000000, + regk_timer_rw_tmr1_ctrl_default = 0x00000000, + regk_timer_rw_trig_cfg_default = 0x00000000, + regk_timer_start = 0x00000001, + regk_timer_stop = 0x00000000, + regk_timer_time = 0x00000001, + regk_timer_tmr0 = 0x00000002, + regk_timer_tmr1 = 0x00000003, + regk_timer_yes = 0x00000001 +}; +#endif /* __timer_defs_h */ diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/memmap.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/memmap.h new file mode 100644 index 000000000..d29df5644 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/memmap.h @@ -0,0 +1,24 @@ +#ifndef _ASM_ARCH_MEMMAP_H +#define _ASM_ARCH_MEMMAP_H + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_INTMEM_START (0x38000000) +#define MEM_INTMEM_SIZE (0x00020000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h b/kernel/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h new file mode 100644 index 000000000..09bf0c90d --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h @@ -0,0 +1,36 @@ +#ifndef _ASM_CRIS_ARCH_PINMUX_H +#define _ASM_CRIS_ARCH_PINMUX_H + +#define PORT_B 0 +#define PORT_C 1 +#define PORT_D 2 +#define PORT_E 3 + +enum pin_mode { + pinmux_none = 0, + pinmux_fixed, + pinmux_gpio, + pinmux_iop +}; + +enum fixed_function { + pinmux_ser1, + pinmux_ser2, + pinmux_ser3, + pinmux_sser0, + pinmux_sser1, + pinmux_ata0, + pinmux_ata1, + pinmux_ata2, + pinmux_ata3, + pinmux_ata, + pinmux_eth1, + pinmux_timer +}; + +int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); +int crisv32_pinmux_alloc_fixed(enum fixed_function function); +int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); +int crisv32_pinmux_dealloc_fixed(enum fixed_function function); + +#endif diff --git a/kernel/arch/cris/include/arch-v32/mach-fs/mach/startup.inc b/kernel/arch/cris/include/arch-v32/mach-fs/mach/startup.inc new file mode 100644 index 000000000..96c3b0fb6 --- /dev/null +++ b/kernel/arch/cris/include/arch-v32/mach-fs/mach/startup.inc @@ -0,0 +1,76 @@ +#ifndef STARTUP_INC_INCLUDED +#define STARTUP_INC_INCLUDED + +#include +#include +#include +#include + + .macro GIO_INIT + move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 + move.d $r0, [$r1] + .endm + + .macro START_CLOCKS + move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 + move.d [$r1], $r0 + or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ + REG_STATE(config, rw_clk_ctrl, bif, yes) | \ + REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 + move.d $r0, [$r1] + .endm + + .macro SETUP_WAIT_STATES + ;; Set up waitstates etc + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 + move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 + move.d $r1, [$r0] + .endm + +#endif diff --git a/kernel/arch/cris/include/asm/Kbuild b/kernel/arch/cris/include/asm/Kbuild new file mode 100644 index 000000000..057e51859 --- /dev/null +++ b/kernel/arch/cris/include/asm/Kbuild @@ -0,0 +1,29 @@ +generic-y += atomic.h +generic-y += barrier.h +generic-y += clkdev.h +generic-y += cmpxchg.h +generic-y += cputime.h +generic-y += device.h +generic-y += div64.h +generic-y += exec.h +generic-y += emergency-restart.h +generic-y += futex.h +generic-y += hardirq.h +generic-y += irq_regs.h +generic-y += irq_work.h +generic-y += kdebug.h +generic-y += kmap_types.h +generic-y += kvm_para.h +generic-y += linkage.h +generic-y += local.h +generic-y += local64.h +generic-y += mcs_spinlock.h +generic-y += module.h +generic-y += percpu.h +generic-y += preempt.h +generic-y += scatterlist.h +generic-y += sections.h +generic-y += topology.h +generic-y += trace_clock.h +generic-y += vga.h +generic-y += xor.h diff --git a/kernel/arch/cris/include/asm/asm-offsets.h b/kernel/arch/cris/include/asm/asm-offsets.h new file mode 100644 index 000000000..d370ee36a --- /dev/null +++ b/kernel/arch/cris/include/asm/asm-offsets.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/asm/axisflashmap.h b/kernel/arch/cris/include/asm/axisflashmap.h new file mode 100644 index 000000000..015ca5445 --- /dev/null +++ b/kernel/arch/cris/include/asm/axisflashmap.h @@ -0,0 +1,61 @@ +#ifndef __ASM_AXISFLASHMAP_H +#define __ASM_AXISFLASHMAP_H + +/* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC + * as start, it ends with 0xFFFFFFFF */ +#define FLASH_BOOT_MAGIC 0xbeefcace +#define BOOTPARAM_OFFSET 0xc000 +/* apps/bootblocktool is used to read and write the parameters, + * and it has nothing to do with the partition table. + */ + +#define PARTITION_TABLE_OFFSET 10 +#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ + +/* The partitiontable_head is located at offset +10: */ +struct partitiontable_head { + __u16 magic; /* PARTITION_TABLE_MAGIC */ + __u16 size; /* Length of ptable block (entries + end marker) */ + __u32 checksum; /* simple longword sum, over entries + end marker */ +}; + +/* And followed by partition table entries */ +struct partitiontable_entry { + __u32 offset; /* relative to the sector the ptable is in */ + __u32 size; /* in bytes */ + __u32 checksum; /* simple longword sum */ + __u16 type; /* see type codes below */ + __u16 flags; /* bit 0: ro/rw = 1/0 */ + __u32 future0; /* 16 bytes reserved for future use */ + __u32 future1; + __u32 future2; + __u32 future3; +}; +/* ended by an end marker: */ +#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF +#define PARTITIONTABLE_END_MARKER_SIZE 4 + +#define PARTITIONTABLE_END_PAD 10 + +/* Complete structure for whole partition table */ +/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting + * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER. + */ +struct partitiontable { + __u8 skip[PARTITION_TABLE_OFFSET]; + struct partitiontable_head head; + struct partitiontable_entry entries[]; +}; + +#define PARTITION_TYPE_PARAM 0x0001 +#define PARTITION_TYPE_KERNEL 0x0002 +#define PARTITION_TYPE_JFFS 0x0003 +#define PARTITION_TYPE_JFFS2 0x0000 + +#define PARTITION_FLAGS_READONLY_MASK 0x0001 +#define PARTITION_FLAGS_READONLY 0x0001 + +/* The master mtd for the entire flash. */ +extern struct mtd_info *axisflash_mtd; + +#endif diff --git a/kernel/arch/cris/include/asm/bitops.h b/kernel/arch/cris/include/asm/bitops.h new file mode 100644 index 000000000..8062cb52d --- /dev/null +++ b/kernel/arch/cris/include/asm/bitops.h @@ -0,0 +1,50 @@ +/* asm/bitops.h for Linux/CRIS + * + * TODO: asm versions if speed is needed + * + * All bit operations return 0 if the bit was cleared before the + * operation and != 0 if it was not. + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + */ + +#ifndef _CRIS_BITOPS_H +#define _CRIS_BITOPS_H + +/* Currently this is unsuitable for consumption outside the kernel. */ +#ifdef __KERNEL__ + +#ifndef _LINUX_BITOPS_H +#error only can be included directly +#endif + +#include +#include +#include + +#include +#include + +/* + * Since we define it "external", it collides with the built-in + * definition, which doesn't have the same semantics. We don't want to + * use -fno-builtin, so just hide the name ffs. + */ +#define ffs(x) kernel_ffs(x) + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#endif /* __KERNEL__ */ + +#endif /* _CRIS_BITOPS_H */ diff --git a/kernel/arch/cris/include/asm/bug.h b/kernel/arch/cris/include/asm/bug.h new file mode 100644 index 000000000..3b3958963 --- /dev/null +++ b/kernel/arch/cris/include/asm/bug.h @@ -0,0 +1,4 @@ +#ifndef _CRIS_BUG_H +#define _CRIS_BUG_H +#include +#endif diff --git a/kernel/arch/cris/include/asm/bugs.h b/kernel/arch/cris/include/asm/bugs.h new file mode 100644 index 000000000..c5907aac1 --- /dev/null +++ b/kernel/arch/cris/include/asm/bugs.h @@ -0,0 +1,21 @@ +/* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $ + * + * include/asm-cris/bugs.h + * + * Copyright (C) 2001 Axis Communications AB + */ + +/* + * This is included by init/main.c to check for architecture-dependent bugs. + * + * Needs: + * void check_bugs(void); + */ + +static void check_bugs(void) +{ +} + + + + diff --git a/kernel/arch/cris/include/asm/cache.h b/kernel/arch/cris/include/asm/cache.h new file mode 100644 index 000000000..a692b9fba --- /dev/null +++ b/kernel/arch/cris/include/asm/cache.h @@ -0,0 +1,6 @@ +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +#include + +#endif /* _ASM_CACHE_H */ diff --git a/kernel/arch/cris/include/asm/cacheflush.h b/kernel/arch/cris/include/asm/cacheflush.h new file mode 100644 index 000000000..36795bca6 --- /dev/null +++ b/kernel/arch/cris/include/asm/cacheflush.h @@ -0,0 +1,32 @@ +#ifndef _CRIS_CACHEFLUSH_H +#define _CRIS_CACHEFLUSH_H + +/* Keep includes the same across arches. */ +#include + +/* The cache doesn't need to be flushed when TLB entries change because + * the cache is mapped to physical memory, not virtual memory + */ +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_dup_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) +#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 +#define flush_dcache_page(page) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_icache_range(start, end) do { } while (0) +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) +#define flush_cache_vmap(start, end) do { } while (0) +#define flush_cache_vunmap(start, end) do { } while (0) + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) + +int change_page_attr(struct page *page, int numpages, pgprot_t prot); + +#endif /* _CRIS_CACHEFLUSH_H */ diff --git a/kernel/arch/cris/include/asm/checksum.h b/kernel/arch/cris/include/asm/checksum.h new file mode 100644 index 000000000..75dcb77d6 --- /dev/null +++ b/kernel/arch/cris/include/asm/checksum.h @@ -0,0 +1,83 @@ +/* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */ + +#ifndef _CRIS_CHECKSUM_H +#define _CRIS_CHECKSUM_H + +#include + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +__wsum csum_partial(const void *buff, int len, __wsum sum); + +/* + * the same as csum_partial, but copies from src while it + * checksums + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +__wsum csum_partial_copy_nocheck(const void *src, void *dst, + int len, __wsum sum); + +/* + * Fold a partial checksum into a word + */ + +static inline __sum16 csum_fold(__wsum csum) +{ + u32 sum = (__force u32)csum; + sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ + sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ + return (__force __sum16)~sum; +} + +extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, + int *errptr); + +/* + * This is a version of ip_compute_csum() optimized for IP headers, + * which always checksum on 4 octet boundaries. + * + */ + +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + return csum_fold(csum_partial(iph, ihl * 4, 0)); +} + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ + +static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, + unsigned short len, + unsigned short proto, + __wsum sum) +{ + return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); +} + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ + +static inline __sum16 ip_compute_csum(const void *buff, int len) +{ + return csum_fold (csum_partial(buff, len, 0)); +} + +#endif diff --git a/kernel/arch/cris/include/asm/current.h b/kernel/arch/cris/include/asm/current.h new file mode 100644 index 000000000..5f5c0efd0 --- /dev/null +++ b/kernel/arch/cris/include/asm/current.h @@ -0,0 +1,15 @@ +#ifndef _CRIS_CURRENT_H +#define _CRIS_CURRENT_H + +#include + +struct task_struct; + +static inline struct task_struct * get_current(void) +{ + return current_thread_info()->task; +} + +#define current get_current() + +#endif /* !(_CRIS_CURRENT_H) */ diff --git a/kernel/arch/cris/include/asm/delay.h b/kernel/arch/cris/include/asm/delay.h new file mode 100644 index 000000000..75ec581bf --- /dev/null +++ b/kernel/arch/cris/include/asm/delay.h @@ -0,0 +1,27 @@ +#ifndef _CRIS_DELAY_H +#define _CRIS_DELAY_H + +/* + * Copyright (C) 1998-2002 Axis Communications AB + * + * Delay routines, using a pre-computed "loops_per_second" value. + */ + +#include + +/* Use only for very small delays ( < 1 msec). */ + +extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ + +/* May be defined by arch/delay.h. */ +#ifndef udelay +static inline void udelay(unsigned long usecs) +{ + __delay(usecs * loops_per_usec); +} +#endif + +#endif /* defined(_CRIS_DELAY_H) */ + + + diff --git a/kernel/arch/cris/include/asm/dma-mapping.h b/kernel/arch/cris/include/asm/dma-mapping.h new file mode 100644 index 000000000..2f0f654f1 --- /dev/null +++ b/kernel/arch/cris/include/asm/dma-mapping.h @@ -0,0 +1,172 @@ +/* DMA mapping. Nothing tricky here, just virt_to_phys */ + +#ifndef _ASM_CRIS_DMA_MAPPING_H +#define _ASM_CRIS_DMA_MAPPING_H + +#include +#include + +#include +#include +#include + +#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) + +#ifdef CONFIG_PCI +#include + +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag); + +void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle); +#else +static inline void * +dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, + gfp_t flag) +{ + BUG(); + return NULL; +} + +static inline void +dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle) +{ + BUG(); +} +#endif +static inline dma_addr_t +dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); + return virt_to_phys(ptr); +} + +static inline void +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + +static inline int +dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) +{ + printk("Map sg\n"); + return nents; +} + +static inline dma_addr_t +dma_map_page(struct device *dev, struct page *page, unsigned long offset, + size_t size, enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); + return page_to_phys(page) + offset; +} + +static inline void +dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + + +static inline void +dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + +static inline void +dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) +{ +} + +static inline void +dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) +{ +} + +static inline int +dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + return 0; +} + +static inline int +dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if(mask < 0x00ffffff) + return 0; + + return 1; +} + +static inline int +dma_set_mask(struct device *dev, u64 mask) +{ + if(!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + + *dev->dma_mask = mask; + + return 0; +} + +static inline void +dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) +{ +} + +/* drivers/base/dma-mapping.c */ +extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, + void *cpu_addr, dma_addr_t dma_addr, size_t size); +extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, + void *cpu_addr, dma_addr_t dma_addr, + size_t size); + +#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s) +#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s) + + +#endif diff --git a/kernel/arch/cris/include/asm/dma.h b/kernel/arch/cris/include/asm/dma.h new file mode 100644 index 000000000..30fd715fa --- /dev/null +++ b/kernel/arch/cris/include/asm/dma.h @@ -0,0 +1,21 @@ +/* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */ + +#ifndef _ASM_DMA_H +#define _ASM_DMA_H + +#include + +/* it's useless on the Etrax, but unfortunately needed by the new + bootmem allocator (but this should do it for this) */ + +#define MAX_DMA_ADDRESS PAGE_OFFSET + +/* From PCI */ + +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) +#endif + +#endif /* _ASM_DMA_H */ diff --git a/kernel/arch/cris/include/asm/elf.h b/kernel/arch/cris/include/asm/elf.h new file mode 100644 index 000000000..c2a394ff5 --- /dev/null +++ b/kernel/arch/cris/include/asm/elf.h @@ -0,0 +1,89 @@ +#ifndef __ASMCRIS_ELF_H +#define __ASMCRIS_ELF_H + +/* + * ELF register definitions.. + */ + +#include + +#define R_CRIS_NONE 0 +#define R_CRIS_8 1 +#define R_CRIS_16 2 +#define R_CRIS_32 3 +#define R_CRIS_8_PCREL 4 +#define R_CRIS_16_PCREL 5 +#define R_CRIS_32_PCREL 6 +#define R_CRIS_GNU_VTINHERIT 7 +#define R_CRIS_GNU_VTENTRY 8 +#define R_CRIS_COPY 9 +#define R_CRIS_GLOB_DAT 10 +#define R_CRIS_JUMP_SLOT 11 +#define R_CRIS_RELATIVE 12 +#define R_CRIS_16_GOT 13 +#define R_CRIS_32_GOT 14 +#define R_CRIS_16_GOTPLT 15 +#define R_CRIS_32_GOTPLT 16 +#define R_CRIS_32_GOTREL 17 +#define R_CRIS_32_PLT_GOTREL 18 +#define R_CRIS_32_PLT_PCREL 19 + +typedef unsigned long elf_greg_t; + +/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is + thus exposed to user-space. */ +#define ELF_NGREG (sizeof (struct user_regs_struct) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +/* A placeholder; CRIS does not have any fp regs. */ +typedef unsigned long elf_fpregset_t; + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_CRIS + +#include + +/* The master for these definitions is {binutils}/include/elf/cris.h: */ +/* User symbols in this file have a leading underscore. */ +#define EF_CRIS_UNDERSCORE 0x00000001 + +/* This is a mask for different incompatible machine variants. */ +#define EF_CRIS_VARIANT_MASK 0x0000000e + +/* Variant 0; may contain v0..10 object. */ +#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 + +/* Variant 1; contains v32 object. */ +#define EF_CRIS_VARIANT_V32 0x00000002 + +/* Variant 2; contains object compatible with v32 and v10. */ +#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 +/* End of excerpt from {binutils}/include/elf/cris.h. */ + +#define ELF_EXEC_PAGESIZE 8192 + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) + +/* This yields a mask that user programs can use to figure out what + instruction set this CPU supports. This could be done in user space, + but it's not easy, and we've already done it here. */ + +#define ELF_HWCAP (0) + +/* This yields a string that ld.so will use to load implementation + specific libraries for optimization. This is more specific in + intent than poking at uname or /proc/cpuinfo. +*/ + +#define ELF_PLATFORM (NULL) + +#endif diff --git a/kernel/arch/cris/include/asm/eshlibld.h b/kernel/arch/cris/include/asm/eshlibld.h new file mode 100644 index 000000000..10ce36cf7 --- /dev/null +++ b/kernel/arch/cris/include/asm/eshlibld.h @@ -0,0 +1,113 @@ +/*!************************************************************************** +*! +*! FILE NAME : eshlibld.h +*! +*! DESCRIPTION: Prototypes for exported shared library functions +*! +*! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit +*! (EXPORTED) +*! +*!--------------------------------------------------------------------------- +*! +*! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN +*! +*!**************************************************************************/ +/* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */ + +#ifndef _cris_relocate_h +#define _cris_relocate_h + +/* Please note that this file is also compiled into the xsim simulator. + Try to avoid breaking its double use (only works on a little-endian + 32-bit machine such as the i386 anyway). + + Use __KERNEL__ when you're about to use kernel functions, + (which you should not do here anyway, since this file is + used by glibc). + Use defined(__KERNEL__) || defined(__elinux__) when doing + things that only makes sense on an elinux system. + Use __CRIS__ when you're about to do (really) CRIS-specific code. +*/ + +/* We have dependencies all over the place for the host system + for xsim being a linux system, so let's not pretend anything + else with #ifdef:s here until fixed. */ +#include + +/* Maybe do sanity checking if file input. */ +#undef SANITYCHECK_RELOC + +/* Maybe output debug messages. */ +#undef RELOC_DEBUG + +/* Maybe we want to share core as well as disk space. + Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is + assumed that we want to share code when debugging (exposes more + trouble). */ +#ifndef SHARE_LIB_CORE +# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \ + && !defined(CONFIG_SHARE_SHLIB_CORE) +# define SHARE_LIB_CORE 0 +# else +# define SHARE_LIB_CORE 1 +# endif /* __KERNEL__ etc */ +#endif /* SHARE_LIB_CORE */ + + +/* Main exported function; supposed to be called when the program a.out + has been read in. */ +extern int +perform_cris_aout_relocations(unsigned long text, unsigned long tlength, + unsigned long data, unsigned long dlength, + unsigned long baddr, unsigned long blength, + + /* These may be zero when there's "perfect" + position-independent code. */ + unsigned char *trel, unsigned long tsrel, + unsigned long dsrel, + + /* These will be zero at a first try, to see + if code is statically linked. Else a + second try, with the symbol table and + string table nonzero should be done. */ + unsigned char *symbols, unsigned long symlength, + unsigned char *strings, unsigned long stringlength, + + /* These will only be used when symbol table + information is present. */ + char **env, int envc, + int euid, int is_suid); + + +#ifdef RELOC_DEBUG +/* Task-specific debug stuff. */ +struct task_reloc_debug { + struct memdebug *alloclast; + unsigned long alloc_total; + unsigned long export_total; +}; +#endif /* RELOC_DEBUG */ + +#if SHARE_LIB_CORE + +/* When code (and some very specific data) is shared and not just + dynamically linked, we need to export hooks for exec beginning and + end. */ + +struct shlibdep; + +extern void +shlibmod_exit(struct shlibdep **deps); + +/* Returns 0 if failure, nonzero for ok. */ +extern int +shlibmod_fork(struct shlibdep **deps); + +#else /* ! SHARE_LIB_CORE */ +# define shlibmod_exit(x) +# define shlibmod_fork(x) 1 +#endif /* ! SHARE_LIB_CORE */ + +#endif _cris_relocate_h +/********************** END OF FILE eshlibld.h *****************************/ + diff --git a/kernel/arch/cris/include/asm/etraxi2c.h b/kernel/arch/cris/include/asm/etraxi2c.h new file mode 100644 index 000000000..e369a7620 --- /dev/null +++ b/kernel/arch/cris/include/asm/etraxi2c.h @@ -0,0 +1,36 @@ +/* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */ + +#ifndef _LINUX_ETRAXI2C_H +#define _LINUX_ETRAXI2C_H + +/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */ + +#define ETRAXI2C_IOCTYPE 44 + +/* supported ioctl _IOC_NR's */ + +/* in write operations, the argument contains both i2c + * slave, register and value. + */ + +#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value)) +#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8)) + +#define I2C_ARGSLAVE(arg) ((arg) >> 16) +#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff) +#define I2C_ARGVALUE(arg) ((arg) & 0xff) + +#define I2C_WRITEREG 0x1 /* write to an i2c register */ +#define I2C_READREG 0x2 /* read from an i2c register */ + +/* +EXAMPLE usage: + + i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); + ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); + + i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); + val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); + +*/ +#endif diff --git a/kernel/arch/cris/include/asm/fasttimer.h b/kernel/arch/cris/include/asm/fasttimer.h new file mode 100644 index 000000000..8f8a8d6c9 --- /dev/null +++ b/kernel/arch/cris/include/asm/fasttimer.h @@ -0,0 +1,47 @@ +/* + * linux/include/asm-cris/fasttimer.h + * + * Fast timers for ETRAX100LX + * Copyright (C) 2000-2007 Axis Communications AB + */ +#include /* struct timeval */ +#include + +#ifdef CONFIG_ETRAX_FAST_TIMER + +typedef void fast_timer_function_type(unsigned long); + +struct fasttime_t { + unsigned long tv_jiff; /* jiffies */ + unsigned long tv_usec; /* microseconds */ +}; + +struct fast_timer{ /* Close to timer_list */ + struct fast_timer *next; + struct fast_timer *prev; + struct fasttime_t tv_set; + struct fasttime_t tv_expires; + unsigned long delay_us; + fast_timer_function_type *function; + unsigned long data; + const char *name; +}; + +extern struct fast_timer *fast_timer_list; + +void start_one_shot_timer(struct fast_timer *t, + fast_timer_function_type *function, + unsigned long data, + unsigned long delay_us, + const char *name); + +int del_fast_timer(struct fast_timer * t); +/* return 1 if deleted */ + + +void schedule_usleep(unsigned long us); + + +int fast_timer_init(void); + +#endif diff --git a/kernel/arch/cris/include/asm/fb.h b/kernel/arch/cris/include/asm/fb.h new file mode 100644 index 000000000..c7df38030 --- /dev/null +++ b/kernel/arch/cris/include/asm/fb.h @@ -0,0 +1,12 @@ +#ifndef _ASM_FB_H_ +#define _ASM_FB_H_ +#include + +#define fb_pgprotect(...) do {} while (0) + +static inline int fb_is_primary_device(struct fb_info *info) +{ + return 0; +} + +#endif /* _ASM_FB_H_ */ diff --git a/kernel/arch/cris/include/asm/ftrace.h b/kernel/arch/cris/include/asm/ftrace.h new file mode 100644 index 000000000..40a8c178f --- /dev/null +++ b/kernel/arch/cris/include/asm/ftrace.h @@ -0,0 +1 @@ +/* empty */ diff --git a/kernel/arch/cris/include/asm/hw_irq.h b/kernel/arch/cris/include/asm/hw_irq.h new file mode 100644 index 000000000..298066020 --- /dev/null +++ b/kernel/arch/cris/include/asm/hw_irq.h @@ -0,0 +1,5 @@ +#ifndef _ASM_HW_IRQ_H +#define _ASM_HW_IRQ_H + +#endif + diff --git a/kernel/arch/cris/include/asm/io.h b/kernel/arch/cris/include/asm/io.h new file mode 100644 index 000000000..752a3f45d --- /dev/null +++ b/kernel/arch/cris/include/asm/io.h @@ -0,0 +1,192 @@ +#ifndef _ASM_CRIS_IO_H +#define _ASM_CRIS_IO_H + +#include /* for __va, __pa */ +#include +#include +#include + +struct cris_io_operations +{ + u32 (*read_mem)(void *addr, int size); + void (*write_mem)(u32 val, int size, void *addr); + u32 (*read_io)(u32 port, void *addr, int size, int count); + void (*write_io)(u32 port, void *addr, int size, int count); +}; + +#ifdef CONFIG_PCI +extern struct cris_io_operations *cris_iops; +#else +#define cris_iops ((struct cris_io_operations*)NULL) +#endif + +/* + * Change virtual addresses to physical addresses and vv. + */ + +static inline unsigned long virt_to_phys(volatile void * address) +{ + return __pa(address); +} + +static inline void * phys_to_virt(unsigned long address) +{ + return __va(address); +} + +extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); +extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot); + +static inline void __iomem * ioremap (unsigned long offset, unsigned long size) +{ + return __ioremap(offset, size, 0); +} + +extern void iounmap(volatile void * __iomem addr); + +extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); + +/* + * IO bus memory addresses are also 1:1 with the physical address + */ +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +/* + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the CRIS architecture, we just read/write the + * memory location directly. + */ +#ifdef CONFIG_PCI +#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000) +#else +#define PCI_SPACE(x) 0 +#endif +static inline unsigned char readb(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 1); + else + return *(volatile unsigned char __force *) addr; +} +static inline unsigned short readw(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 2); + else + return *(volatile unsigned short __force *) addr; +} +static inline unsigned int readl(const volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + return cris_iops->read_mem((void*)addr, 4); + else + return *(volatile unsigned int __force *) addr; +} +#define readb_relaxed(addr) readb(addr) +#define readw_relaxed(addr) readw(addr) +#define readl_relaxed(addr) readl(addr) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl + +static inline void writeb(unsigned char b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 1, (void*)addr); + else + *(volatile unsigned char __force *) addr = b; +} +static inline void writew(unsigned short b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 2, (void*)addr); + else + *(volatile unsigned short __force *) addr = b; +} +static inline void writel(unsigned int b, volatile void __iomem *addr) +{ + if (PCI_SPACE(addr) && cris_iops) + cris_iops->write_mem(b, 4, (void*)addr); + else + *(volatile unsigned int __force *) addr = b; +} +#define writeb_relaxed(b, addr) writeb(b, addr) +#define writew_relaxed(b, addr) writew(b, addr) +#define writel_relaxed(b, addr) writel(b, addr) +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +#define mmiowb() + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + + +/* I/O port access. Normally there is no I/O space on CRIS but when + * Cardbus/PCI is enabled the request is passed through the bridge. + */ + +#define IO_SPACE_LIMIT 0xffff +#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0) +#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0) +#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0) +#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0) +#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0) +#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0) +static inline void outb(unsigned char data, unsigned int port) +{ + if (cris_iops) + cris_iops->write_io(port, (void *) &data, 1, 1); +} +static inline void outw(unsigned short data, unsigned int port) +{ + if (cris_iops) + cris_iops->write_io(port, (void *) &data, 2, 1); +} +static inline void outl(unsigned int data, unsigned int port) +{ + if (cris_iops) + cris_iops->write_io(port, (void *) &data, 4, 1); +} +static inline void outsb(unsigned int port, const void *addr, + unsigned long count) +{ + if (cris_iops) + cris_iops->write_io(port, (void *)addr, 1, count); +} +static inline void outsw(unsigned int port, const void *addr, + unsigned long count) +{ + if (cris_iops) + cris_iops->write_io(port, (void *)addr, 2, count); +} +static inline void outsl(unsigned int port, const void *addr, + unsigned long count) +{ + if (cris_iops) + cris_iops->write_io(port, (void *)addr, 4, count); +} + +#define inb_p(port) inb(port) +#define inw_p(port) inw(port) +#define inl_p(port) inl(port) +#define outb_p(val, port) outb((val), (port)) +#define outw_p(val, port) outw((val), (port)) +#define outl_p(val, port) outl((val), (port)) + +/* + * Convert a physical pointer to a virtual kernel pointer for /dev/mem + * access + */ +#define xlate_dev_mem_ptr(p) __va(p) + +/* + * Convert a virtual cached pointer to an uncached pointer + */ +#define xlate_dev_kmem_ptr(p) p + +#endif diff --git a/kernel/arch/cris/include/asm/irq.h b/kernel/arch/cris/include/asm/irq.h new file mode 100644 index 000000000..ce0fcf540 --- /dev/null +++ b/kernel/arch/cris/include/asm/irq.h @@ -0,0 +1,13 @@ +#ifndef _ASM_IRQ_H +#define _ASM_IRQ_H + +#include + +static inline int irq_canonicalize(int irq) +{ + return irq; +} + +#endif /* _ASM_IRQ_H */ + + diff --git a/kernel/arch/cris/include/asm/irqflags.h b/kernel/arch/cris/include/asm/irqflags.h new file mode 100644 index 000000000..943ba5ca6 --- /dev/null +++ b/kernel/arch/cris/include/asm/irqflags.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/asm/mmu.h b/kernel/arch/cris/include/asm/mmu.h new file mode 100644 index 000000000..e06ea94ec --- /dev/null +++ b/kernel/arch/cris/include/asm/mmu.h @@ -0,0 +1,10 @@ +/* + * CRIS MMU constants and PTE layout + */ + +#ifndef _CRIS_MMU_H +#define _CRIS_MMU_H + +#include + +#endif diff --git a/kernel/arch/cris/include/asm/mmu_context.h b/kernel/arch/cris/include/asm/mmu_context.h new file mode 100644 index 000000000..1d45fd636 --- /dev/null +++ b/kernel/arch/cris/include/asm/mmu_context.h @@ -0,0 +1,27 @@ +#ifndef __CRIS_MMU_CONTEXT_H +#define __CRIS_MMU_CONTEXT_H + +#include + +extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); +extern void get_mmu_context(struct mm_struct *mm); +extern void destroy_context(struct mm_struct *mm); +extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk); + +#define deactivate_mm(tsk,mm) do { } while (0) + +#define activate_mm(prev,next) switch_mm((prev),(next),NULL) + +/* current active pgd - this is similar to other processors pgd + * registers like cr3 on the i386 + */ + +/* defined in arch/cris/mm/fault.c */ +DECLARE_PER_CPU(pgd_t *, current_pgd); + +static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ +} + +#endif diff --git a/kernel/arch/cris/include/asm/mutex.h b/kernel/arch/cris/include/asm/mutex.h new file mode 100644 index 000000000..458c1f7fb --- /dev/null +++ b/kernel/arch/cris/include/asm/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include diff --git a/kernel/arch/cris/include/asm/page.h b/kernel/arch/cris/include/asm/page.h new file mode 100644 index 000000000..dfc53f9b8 --- /dev/null +++ b/kernel/arch/cris/include/asm/page.h @@ -0,0 +1,73 @@ +#ifndef _CRIS_PAGE_H +#define _CRIS_PAGE_H + +#include +#include + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT 13 +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) + +#define clear_user_page(page, vaddr, pg) clear_page(page) +#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) + +#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ + alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) +#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE + +/* + * These are used to make use of C type-checking.. + */ +#ifndef __ASSEMBLY__ +typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pgd; } pgd_t; +typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; +#endif + +#define pte_val(x) ((x).pte) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +/* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */ +/* for that before indexing into the page table starting at mem_map */ +#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) +#define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr) + +/* to index into the page map. our pages all start at physical addr PAGE_OFFSET so + * we can let the map start there. notice that we subtract PAGE_OFFSET because + * we start our mem_map there - in other ports they map mem_map physically and + * use __pa instead. in our system both the physical and virtual address of DRAM + * is too high to let mem_map start at 0, so we do it this way instead (similar + * to arm and m68k I think) + */ + +#define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT)) +#define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT) + +/* convert a page (based on mem_map and forward) to a physical address + * do this by figuring out the virtual address and then use __pa + */ + +#define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) + +#ifndef __ASSEMBLY__ + +#endif /* __ASSEMBLY__ */ + +#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#include +#include + +#endif /* _CRIS_PAGE_H */ + diff --git a/kernel/arch/cris/include/asm/pci.h b/kernel/arch/cris/include/asm/pci.h new file mode 100644 index 000000000..cc2399c17 --- /dev/null +++ b/kernel/arch/cris/include/asm/pci.h @@ -0,0 +1,57 @@ +#ifndef __ASM_CRIS_PCI_H +#define __ASM_CRIS_PCI_H + + +#ifdef __KERNEL__ +#include /* for struct page */ + +/* Can be used to override the logic in pci_scan_bus for skipping + already-configured bus numbers - to be used for buggy BIOSes + or architectures with incomplete PCI setup by the loader */ + +#define pcibios_assign_all_busses(void) 1 + +#define PCIBIOS_MIN_IO 0x1000 +#define PCIBIOS_MIN_MEM 0x10000000 + +#define PCIBIOS_MIN_CARDBUS_IO 0x4000 + +void pcibios_config_init(void); +struct pci_bus * pcibios_scan_root(int bus); + +void pcibios_set_master(struct pci_dev *dev); +struct irq_routing_table *pcibios_get_irq_routing_table(void); +int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); + +/* Dynamic DMA mapping stuff. + * i386 has everything mapped statically. + */ + +#include +#include +#include +#include +#include + +struct pci_dev; + +/* The PCI address space does equal the physical memory + * address space. The networking and block device layers use + * this boolean for bounce buffer decisions. + */ +#define PCI_DMA_BUS_IS_PHYS (1) + +#define HAVE_PCI_MMAP +extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine); + + +#endif /* __KERNEL__ */ + +/* implement the pci_ DMA API in terms of the generic device dma_ one */ +#include + +/* generic pci stuff */ +#include + +#endif /* __ASM_CRIS_PCI_H */ diff --git a/kernel/arch/cris/include/asm/pgalloc.h b/kernel/arch/cris/include/asm/pgalloc.h new file mode 100644 index 000000000..235ece437 --- /dev/null +++ b/kernel/arch/cris/include/asm/pgalloc.h @@ -0,0 +1,63 @@ +#ifndef _CRIS_PGALLOC_H +#define _CRIS_PGALLOC_H + +#include +#include + +#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) +#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) +#define pmd_pgtable(pmd) pmd_page(pmd) + +/* + * Allocate and free page tables. + */ + +static inline pgd_t *pgd_alloc (struct mm_struct *mm) +{ + return (pgd_t *)get_zeroed_page(GFP_KERNEL); +} + +static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) +{ + free_page((unsigned long)pgd); +} + +static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) +{ + pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); + return pte; +} + +static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) +{ + struct page *pte; + pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); + if (!pte) + return NULL; + if (!pgtable_page_ctor(pte)) { + __free_page(pte); + return NULL; + } + return pte; +} + +static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) +{ + free_page((unsigned long)pte); +} + +static inline void pte_free(struct mm_struct *mm, pgtable_t pte) +{ + pgtable_page_dtor(pte); + __free_page(pte); +} + +#define __pte_free_tlb(tlb,pte,address) \ +do { \ + pgtable_page_dtor(pte); \ + tlb_remove_page((tlb), pte); \ +} while (0) + +#define check_pgt_cache() do { } while (0) + +#endif diff --git a/kernel/arch/cris/include/asm/pgtable.h b/kernel/arch/cris/include/asm/pgtable.h new file mode 100644 index 000000000..ceefc314d --- /dev/null +++ b/kernel/arch/cris/include/asm/pgtable.h @@ -0,0 +1,295 @@ +/* + * CRIS pgtable.h - macros and functions to manipulate page tables. + */ + +#ifndef _CRIS_PGTABLE_H +#define _CRIS_PGTABLE_H + +#include +#include + +#ifndef __ASSEMBLY__ +#include +#include +#endif +#include + +/* + * The Linux memory management assumes a three-level page table setup. On + * CRIS, we use that, but "fold" the mid level into the top-level page + * table. Since the MMU TLB is software loaded through an interrupt, it + * supports any page table structure, so we could have used a three-level + * setup, but for the amounts of memory we normally use, a two-level is + * probably more efficient. + * + * This file contains the functions and defines necessary to modify and use + * the CRIS page table tree. + */ +#ifndef __ASSEMBLY__ +extern void paging_init(void); +#endif + +/* Certain architectures need to do special things when pte's + * within a page table are directly modified. Thus, the following + * hook is made available. + */ +#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) +#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) + +/* + * (pmds are folded into pgds so this doesn't get actually called, + * but the define is needed for a generic inline function.) + */ +#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) +#define set_pgu(pudptr, pudval) (*(pudptr) = pudval) + +/* PGDIR_SHIFT determines the size of the area a second-level page table can + * map. It is equal to the page size times the number of PTE's that fit in + * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. + */ + +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * entries per page directory level: we use a two-level, so + * we don't really have any PMD directory physically. + * pointers are 4 bytes so we can use the page size and + * divide it by 4 (shift by 2). + */ +#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) +#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) + +/* calculate how many PGD entries a user-level program can use + * the first mappable virtual address is 0 + * (TASK_SIZE is the maximum virtual address space) + */ + +#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) +#define FIRST_USER_ADDRESS 0UL + +/* zero page used for uninitialized stuff */ +#ifndef __ASSEMBLY__ +extern unsigned long empty_zero_page; +#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) +#endif + +/* number of bits that fit into a memory pointer */ +#define BITS_PER_PTR (8*sizeof(unsigned long)) + +/* to align the pointer to a pointer address */ +#define PTR_MASK (~(sizeof(void*)-1)) + +/* sizeof(void*)==1<>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) + +/* to set the page-dir */ +#define SET_PAGE_DIR(tsk,pgdir) + +#define pte_none(x) (!pte_val(x)) +#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) +#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) + +#define pmd_none(x) (!pmd_val(x)) +/* by removing the _PAGE_KERNEL bit from the comparison, the same pmd_bad + * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. + */ +#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) +#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) +#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) + +#ifndef __ASSEMBLY__ + +/* + * The following only work if pte_present() is true. + * Undefined behaviour if not.. + */ + +static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } +static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } +static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } +static inline int pte_special(pte_t pte) { return 0; } + +static inline pte_t pte_wrprotect(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); + return pte; +} + +static inline pte_t pte_mkclean(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); + return pte; +} + +static inline pte_t pte_mkold(pte_t pte) +{ + pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); + return pte; +} + +static inline pte_t pte_mkwrite(pte_t pte) +{ + pte_val(pte) |= _PAGE_WRITE; + if (pte_val(pte) & _PAGE_MODIFIED) + pte_val(pte) |= _PAGE_SILENT_WRITE; + return pte; +} + +static inline pte_t pte_mkdirty(pte_t pte) +{ + pte_val(pte) |= _PAGE_MODIFIED; + if (pte_val(pte) & _PAGE_WRITE) + pte_val(pte) |= _PAGE_SILENT_WRITE; + return pte; +} + +static inline pte_t pte_mkyoung(pte_t pte) +{ + pte_val(pte) |= _PAGE_ACCESSED; + if (pte_val(pte) & _PAGE_READ) + { + pte_val(pte) |= _PAGE_SILENT_READ; + if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) == + (_PAGE_WRITE | _PAGE_MODIFIED)) + pte_val(pte) |= _PAGE_SILENT_WRITE; + } + return pte; +} +static inline pte_t pte_mkspecial(pte_t pte) { return pte; } + +/* + * Conversion functions: convert a page and protection to a page entry, + * and a page entry and page directory to the page they refer to. + */ + +/* What actually goes as arguments to the various functions is less than + * obvious, but a rule of thumb is that struct page's goes as struct page *, + * really physical DRAM addresses are unsigned long's, and DRAM "virtual" + * addresses (the 0xc0xxxxxx's) goes as void *'s. + */ + +static inline pte_t __mk_pte(void * page, pgprot_t pgprot) +{ + pte_t pte; + /* the PTE needs a physical address */ + pte_val(pte) = __pa(page) | pgprot_val(pgprot); + return pte; +} + +#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot)) + +#define mk_pte_phys(physpage, pgprot) \ +({ \ + pte_t __pte; \ + \ + pte_val(__pte) = (physpage) + pgprot_val(pgprot); \ + __pte; \ +}) + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } + +#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE)) + + +/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval + * __pte_page(pte_val) refers to the "virtual" DRAM interval + * pte_pagenr refers to the page-number counted starting from the virtual DRAM start + */ + +static inline unsigned long __pte_page(pte_t pte) +{ + /* the PTE contains a physical address */ + return (unsigned long)__va(pte_val(pte) & PAGE_MASK); +} + +#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) + +/* permanent address of a page */ + +#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) +#define pte_page(pte) (mem_map+pte_pagenr(pte)) + +/* only the pte's themselves need to point to physical DRAM (see above) + * the pagetable links are purely handled within the kernel SW and thus + * don't need the __pa and __va transformations. + */ + +static inline void pmd_set(pmd_t * pmdp, pte_t * ptep) +{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; } + +#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) +#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) + +/* to find an entry in a page-table-directory. */ +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) + +/* to find an entry in a page-table-directory */ +static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address) +{ + return mm->pgd + pgd_index(address); +} + +/* to find an entry in a kernel page-table-directory */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) + +/* Find an entry in the third-level page table.. */ +#define __pte_offset(address) \ + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset_kernel(dir, address) \ + ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) +#define pte_offset_map(dir, address) \ + ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) + +#define pte_unmap(pte) do { } while (0) +#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) + +#define pte_ERROR(e) \ + printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) +#define pgd_ERROR(e) \ + printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) + + +extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ + +/* + * CRIS doesn't have any external MMU info: the kernel page + * tables contain all the necessary information. + * + * Actually I am not sure on what this could be used for. + */ +static inline void update_mmu_cache(struct vm_area_struct * vma, + unsigned long address, pte_t *ptep) +{ +} + +/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ +/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */ + +#define __swp_type(x) (((x).val >> 5) & 0x7f) +#define __swp_offset(x) ((x).val >> 12) +#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) + +#define kern_addr_valid(addr) (1) + +#include + +/* + * No page table caches to initialise + */ +#define pgtable_cache_init() do { } while (0) + +typedef pte_t *pte_addr_t; + +#endif /* __ASSEMBLY__ */ +#endif /* _CRIS_PGTABLE_H */ diff --git a/kernel/arch/cris/include/asm/processor.h b/kernel/arch/cris/include/asm/processor.h new file mode 100644 index 000000000..862126b58 --- /dev/null +++ b/kernel/arch/cris/include/asm/processor.h @@ -0,0 +1,70 @@ +/* + * include/asm-cris/processor.h + * + * Copyright (C) 2000, 2001 Axis Communications AB + * + * Authors: Bjorn Wesen Initial version + * + */ + +#ifndef __ASM_CRIS_PROCESSOR_H +#define __ASM_CRIS_PROCESSOR_H + +#include +#include +#include +#include + +struct task_struct; + +#define STACK_TOP TASK_SIZE +#define STACK_TOP_MAX STACK_TOP + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) + +/* THREAD_SIZE is the size of the thread_info/kernel_stack combo. + * normally, the stack is found by doing something like p + THREAD_SIZE + * in CRIS, a page is 8192 bytes, which seems like a sane size + */ +#define THREAD_SIZE PAGE_SIZE +#define THREAD_SIZE_ORDER (0) + +/* + * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack. + * This macro allows us to find those regs for a task. + * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while + * we're in the kernel, won't affect this - only the first user->kernel transition + * registers are reached by this. + */ + +#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1) + +/* + * Dito but for the currently running task + */ + +#define task_pt_regs(task) user_regs(task_thread_info(task)) + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) + +extern unsigned long thread_saved_pc(struct task_struct *tsk); + +/* Free all resources held by a thread. */ +static inline void release_thread(struct task_struct *dead_task) +{ + /* Nothing needs to be done. */ +} + +#define init_stack (init_thread_union.stack) + +#define cpu_relax() barrier() +#define cpu_relax_lowlatency() cpu_relax() + +void default_idle(void); + +#endif /* __ASM_CRIS_PROCESSOR_H */ diff --git a/kernel/arch/cris/include/asm/ptrace.h b/kernel/arch/cris/include/asm/ptrace.h new file mode 100644 index 000000000..9e788d04a --- /dev/null +++ b/kernel/arch/cris/include/asm/ptrace.h @@ -0,0 +1,14 @@ +#ifndef _CRIS_PTRACE_H +#define _CRIS_PTRACE_H + +#include + + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 + +#define profile_pc(regs) instruction_pointer(regs) +#define current_user_stack_pointer() rdusp() + +#endif /* _CRIS_PTRACE_H */ diff --git a/kernel/arch/cris/include/asm/segment.h b/kernel/arch/cris/include/asm/segment.h new file mode 100644 index 000000000..c067513be --- /dev/null +++ b/kernel/arch/cris/include/asm/segment.h @@ -0,0 +1,8 @@ +#ifndef _ASM_SEGMENT_H +#define _ASM_SEGMENT_H + +typedef struct { + unsigned long seg; +} mm_segment_t; + +#endif diff --git a/kernel/arch/cris/include/asm/serial.h b/kernel/arch/cris/include/asm/serial.h new file mode 100644 index 000000000..af7535a95 --- /dev/null +++ b/kernel/arch/cris/include/asm/serial.h @@ -0,0 +1,9 @@ +#ifndef _ASM_SERIAL_H +#define _ASM_SERIAL_H + +/* + * This assumes you have a 1.8432 MHz clock for your UART. + */ +#define BASE_BAUD (1843200 / 16) + +#endif /* _ASM_SERIAL_H */ diff --git a/kernel/arch/cris/include/asm/shmparam.h b/kernel/arch/cris/include/asm/shmparam.h new file mode 100644 index 000000000..d29d12270 --- /dev/null +++ b/kernel/arch/cris/include/asm/shmparam.h @@ -0,0 +1,8 @@ +#ifndef _ASM_CRIS_SHMPARAM_H +#define _ASM_CRIS_SHMPARAM_H + +/* same as asm-i386/ version.. */ + +#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ + +#endif /* _ASM_CRIS_SHMPARAM_H */ diff --git a/kernel/arch/cris/include/asm/signal.h b/kernel/arch/cris/include/asm/signal.h new file mode 100644 index 000000000..c11b8745c --- /dev/null +++ b/kernel/arch/cris/include/asm/signal.h @@ -0,0 +1,23 @@ +#ifndef _ASM_CRIS_SIGNAL_H +#define _ASM_CRIS_SIGNAL_H + +#include + +/* Most things should be clean enough to redefine this at will, if care + is taken to make libc match. */ + +#define _NSIG 64 +#define _NSIG_BPW 32 +#define _NSIG_WORDS (_NSIG / _NSIG_BPW) + +typedef unsigned long old_sigset_t; /* at least 32 bits */ + +typedef struct { + unsigned long sig[_NSIG_WORDS]; +} sigset_t; + +#define __ARCH_HAS_SA_RESTORER + +#include + +#endif diff --git a/kernel/arch/cris/include/asm/string.h b/kernel/arch/cris/include/asm/string.h new file mode 100644 index 000000000..d5db39f9e --- /dev/null +++ b/kernel/arch/cris/include/asm/string.h @@ -0,0 +1,20 @@ +#ifndef _ASM_CRIS_STRING_H +#define _ASM_CRIS_STRING_H + +/* the optimized memcpy is in arch/cris/lib/string.c */ + +#define __HAVE_ARCH_MEMCPY +extern void *memcpy(void *, const void *, size_t); + +/* New and improved. In arch/cris/lib/memset.c */ + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *, int, size_t); + +#ifdef CONFIG_ETRAX_ARCH_V32 +/* For v32 we provide strcmp. */ +#define __HAVE_ARCH_STRCMP +extern int strcmp(const char *s1, const char *s2); +#endif + +#endif diff --git a/kernel/arch/cris/include/asm/swab.h b/kernel/arch/cris/include/asm/swab.h new file mode 100644 index 000000000..991b6ace1 --- /dev/null +++ b/kernel/arch/cris/include/asm/swab.h @@ -0,0 +1,7 @@ +#ifndef _CRIS_SWAB_H +#define _CRIS_SWAB_H + +#include +#include + +#endif /* _CRIS_SWAB_H */ diff --git a/kernel/arch/cris/include/asm/switch_to.h b/kernel/arch/cris/include/asm/switch_to.h new file mode 100644 index 000000000..d842e1163 --- /dev/null +++ b/kernel/arch/cris/include/asm/switch_to.h @@ -0,0 +1,12 @@ +#ifndef __ASM_CRIS_SWITCH_TO_H +#define __ASM_CRIS_SWITCH_TO_H + +/* the switch_to macro calls resume, an asm function in entry.S which does the actual + * task switching. + */ + +extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int); +#define switch_to(prev,next,last) last = resume(prev,next, \ + (int)&((struct task_struct *)0)->thread) + +#endif /* __ASM_CRIS_SWITCH_TO_H */ diff --git a/kernel/arch/cris/include/asm/termios.h b/kernel/arch/cris/include/asm/termios.h new file mode 100644 index 000000000..1991cd9e4 --- /dev/null +++ b/kernel/arch/cris/include/asm/termios.h @@ -0,0 +1,51 @@ +#ifndef _CRIS_TERMIOS_H +#define _CRIS_TERMIOS_H + +#include + + +/* intr=^C quit=^\ erase=del kill=^U + eof=^D vtime=\0 vmin=\1 sxtc=\0 + start=^Q stop=^S susp=^Z eol=\0 + reprint=^R discard=^U werase=^W lnext=^V + eol2=\0 +*/ +#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" + +/* + * Translate a "termio" structure into a "termios". Ugh. + */ +#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ + unsigned short __tmp; \ + get_user(__tmp,&(termio)->x); \ + *(unsigned short *) &(termios)->x = __tmp; \ +} + +#define user_termio_to_kernel_termios(termios, termio) \ +({ \ + SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ + copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ +}) + +/* + * Translate a "termios" structure into a "termio". Ugh. + */ +#define kernel_termios_to_user_termio(termio, termios) \ +({ \ + put_user((termios)->c_iflag, &(termio)->c_iflag); \ + put_user((termios)->c_oflag, &(termio)->c_oflag); \ + put_user((termios)->c_cflag, &(termio)->c_cflag); \ + put_user((termios)->c_lflag, &(termio)->c_lflag); \ + put_user((termios)->c_line, &(termio)->c_line); \ + copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ +}) + +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) +#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) + +#endif /* _CRIS_TERMIOS_H */ diff --git a/kernel/arch/cris/include/asm/thread_info.h b/kernel/arch/cris/include/asm/thread_info.h new file mode 100644 index 000000000..4ead1b40d --- /dev/null +++ b/kernel/arch/cris/include/asm/thread_info.h @@ -0,0 +1,85 @@ +/* thread_info.h: CRIS low-level thread information + * + * Copyright (C) 2002 David Howells (dhowells@redhat.com) + * - Incorporating suggestions made by Linus Torvalds and Dave Miller + * + * CRIS port by Axis Communications + */ + +#ifndef _ASM_THREAD_INFO_H +#define _ASM_THREAD_INFO_H + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ +#include +#include +#include +#include +#endif + + +/* + * low level task data that entry.S needs immediate access to + * - this struct should fit entirely inside of one cache line + * - this struct shares the supervisor stack pages + * - if the contents of this structure are changed, the assembly constants must also be changed + */ +#ifndef __ASSEMBLY__ +struct thread_info { + struct task_struct *task; /* main task structure */ + unsigned long flags; /* low level flags */ + __u32 cpu; /* current CPU */ + int preempt_count; /* 0 => preemptable, <0 => BUG */ + __u32 tls; /* TLS for this thread */ + + mm_segment_t addr_limit; /* thread address space: + 0-0xBFFFFFFF for user-thead + 0-0xFFFFFFFF for kernel-thread + */ + __u8 supervisor_stack[0]; +}; + +#endif + +/* + * macros/functions for gaining access to the thread information structure + */ +#ifndef __ASSEMBLY__ +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .flags = 0, \ + .cpu = 0, \ + .preempt_count = INIT_PREEMPT_COUNT, \ + .addr_limit = KERNEL_DS, \ +} + +#define init_thread_info (init_thread_union.thread_info) + +#endif /* !__ASSEMBLY__ */ + +/* + * thread information flags + * - these are process state flags that various assembly files may need to access + * - pending work-to-be-done flags are in LSW + * - other flags in MSW + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ +#define TIF_SIGPENDING 2 /* signal pending */ +#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ +#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ +#define TIF_MEMDIE 17 /* is terminating due to OOM killer */ + +#define _TIF_SYSCALL_TRACE (1< + +/* + * We don't have a cycle-counter.. but we do not support SMP anyway where this is + * used so it does not matter. + */ + +typedef unsigned long long cycles_t; + +static inline cycles_t get_cycles(void) +{ + return 0; +} + +#endif diff --git a/kernel/arch/cris/include/asm/tlb.h b/kernel/arch/cris/include/asm/tlb.h new file mode 100644 index 000000000..77384ea2f --- /dev/null +++ b/kernel/arch/cris/include/asm/tlb.h @@ -0,0 +1,19 @@ +#ifndef _CRIS_TLB_H +#define _CRIS_TLB_H + +#include + +#include + +/* + * cris doesn't need any special per-pte or + * per-vma handling.. + */ +#define tlb_start_vma(tlb, vma) do { } while (0) +#define tlb_end_vma(tlb, vma) do { } while (0) +#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) + +#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) +#include + +#endif diff --git a/kernel/arch/cris/include/asm/tlbflush.h b/kernel/arch/cris/include/asm/tlbflush.h new file mode 100644 index 000000000..b424f43a9 --- /dev/null +++ b/kernel/arch/cris/include/asm/tlbflush.h @@ -0,0 +1,41 @@ +#ifndef _CRIS_TLBFLUSH_H +#define _CRIS_TLBFLUSH_H + +#include +#include +#include +#include + +/* + * TLB flushing (implemented in arch/cris/mm/tlb.c): + * + * - flush_tlb() flushes the current mm struct TLBs + * - flush_tlb_all() flushes all processes TLBs + * - flush_tlb_mm(mm) flushes the specified mm context TLB's + * - flush_tlb_page(vma, vmaddr) flushes one page + * - flush_tlb_range(mm, start, end) flushes a range of pages + * + */ + +extern void __flush_tlb_all(void); +extern void __flush_tlb_mm(struct mm_struct *mm); +extern void __flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr); + +#define flush_tlb_all __flush_tlb_all +#define flush_tlb_mm __flush_tlb_mm +#define flush_tlb_page __flush_tlb_page + +static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) +{ + flush_tlb_mm(vma->vm_mm); +} + +static inline void flush_tlb(void) +{ + flush_tlb_mm(current->mm); +} + +#define flush_tlb_kernel_range(start, end) flush_tlb_all() + +#endif /* _CRIS_TLBFLUSH_H */ diff --git a/kernel/arch/cris/include/asm/types.h b/kernel/arch/cris/include/asm/types.h new file mode 100644 index 000000000..a3cac7757 --- /dev/null +++ b/kernel/arch/cris/include/asm/types.h @@ -0,0 +1,12 @@ +#ifndef _ETRAX_TYPES_H +#define _ETRAX_TYPES_H + +#include + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ + +#define BITS_PER_LONG 32 + +#endif diff --git a/kernel/arch/cris/include/asm/uaccess.h b/kernel/arch/cris/include/asm/uaccess.h new file mode 100644 index 000000000..e3530d0f1 --- /dev/null +++ b/kernel/arch/cris/include/asm/uaccess.h @@ -0,0 +1,428 @@ +/* + * Authors: Bjorn Wesen (bjornw@axis.com) + * Hans-Peter Nilsson (hp@axis.com) + */ + +/* Asm:s have been tweaked (within the domain of correctness) to give + satisfactory results for "gcc version 2.96 20000427 (experimental)". + + Check regularly... + + Register $r9 is chosen for temporaries, being a call-clobbered register + first in line to be used (notably for local blocks), not colliding with + parameter registers. */ + +#ifndef _CRIS_UACCESS_H +#define _CRIS_UACCESS_H + +#ifndef __ASSEMBLY__ +#include +#include +#include +#include + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +/* + * The fs value determines whether argument validity checking should be + * performed or not. If get_fs() == USER_DS, checking is performed, with + * get_fs() == KERNEL_DS, checking is bypassed. + * + * For historical reasons, these macros are grossly misnamed. + */ + +#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) + +/* addr_limit is the maximum accessible address for the task. we misuse + * the KERNEL_DS and USER_DS values to both assign and compare the + * addr_limit values through the equally misnamed get/set_fs macros. + * (see above) + */ + +#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) +#define USER_DS MAKE_MM_SEG(TASK_SIZE) + +#define get_ds() (KERNEL_DS) +#define get_fs() (current_thread_info()->addr_limit) +#define set_fs(x) (current_thread_info()->addr_limit = (x)) + +#define segment_eq(a, b) ((a).seg == (b).seg) + +#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS)) +#define __user_ok(addr, size) \ + (((size) <= TASK_SIZE) && ((addr) <= TASK_SIZE-(size))) +#define __access_ok(addr, size) (__kernel_ok || __user_ok((addr), (size))) +#define access_ok(type, addr, size) __access_ok((unsigned long)(addr), (size)) + +#include + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry { + unsigned long insn, fixup; +}; + +/* + * These are the main single-value transfer routines. They automatically + * use the right size if we just have the right pointer type. + * + * This gets kind of ugly. We want to return _two_ values in "get_user()" + * and yet we don't want to do any pointers, because that is too much + * of a performance impact. Thus we have a few rather ugly macros here, + * and hide all the ugliness from the user. + * + * The "__xxx" versions of the user access functions are versions that + * do not verify the address space, that must have been done previously + * with a separate "access_ok()" call (this is used when we do multiple + * accesses to the same area of user memory). + * + * As we use the same address space for kernel and user data on + * CRIS, we can just do these as direct assignments. (Of course, the + * exception handling means that it's no longer "just"...) + */ +#define get_user(x, ptr) \ + __get_user_check((x), (ptr), sizeof(*(ptr))) +#define put_user(x, ptr) \ + __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr))) + +#define __get_user(x, ptr) \ + __get_user_nocheck((x), (ptr), sizeof(*(ptr))) +#define __put_user(x, ptr) \ + __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr))) + +extern long __put_user_bad(void); + +#define __put_user_size(x, ptr, size, retval) \ +do { \ + retval = 0; \ + switch (size) { \ + case 1: \ + __put_user_asm(x, ptr, retval, "move.b"); \ + break; \ + case 2: \ + __put_user_asm(x, ptr, retval, "move.w"); \ + break; \ + case 4: \ + __put_user_asm(x, ptr, retval, "move.d"); \ + break; \ + case 8: \ + __put_user_asm_64(x, ptr, retval); \ + break; \ + default: \ + __put_user_bad(); \ + } \ +} while (0) + +#define __get_user_size(x, ptr, size, retval) \ +do { \ + retval = 0; \ + switch (size) { \ + case 1: \ + __get_user_asm(x, ptr, retval, "move.b"); \ + break; \ + case 2: \ + __get_user_asm(x, ptr, retval, "move.w"); \ + break; \ + case 4: \ + __get_user_asm(x, ptr, retval, "move.d"); \ + break; \ + case 8: \ + __get_user_asm_64(x, ptr, retval); \ + break; \ + default: \ + (x) = __get_user_bad(); \ + } \ +} while (0) + +#define __put_user_nocheck(x, ptr, size) \ +({ \ + long __pu_err; \ + __put_user_size((x), (ptr), (size), __pu_err); \ + __pu_err; \ +}) + +#define __put_user_check(x, ptr, size) \ +({ \ + long __pu_err = -EFAULT; \ + __typeof__(*(ptr)) *__pu_addr = (ptr); \ + if (access_ok(VERIFY_WRITE, __pu_addr, size)) \ + __put_user_size((x), __pu_addr, (size), __pu_err); \ + __pu_err; \ +}) + +struct __large_struct { unsigned long buf[100]; }; +#define __m(x) (*(struct __large_struct *)(x)) + + + +#define __get_user_nocheck(x, ptr, size) \ +({ \ + long __gu_err, __gu_val; \ + __get_user_size(__gu_val, (ptr), (size), __gu_err); \ + (x) = (__force __typeof__(*(ptr)))__gu_val; \ + __gu_err; \ +}) + +#define __get_user_check(x, ptr, size) \ +({ \ + long __gu_err = -EFAULT, __gu_val = 0; \ + const __typeof__(*(ptr)) *__gu_addr = (ptr); \ + if (access_ok(VERIFY_READ, __gu_addr, size)) \ + __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ + (x) = (__force __typeof__(*(ptr)))__gu_val; \ + __gu_err; \ +}) + +extern long __get_user_bad(void); + +/* More complex functions. Most are inline, but some call functions that + live in lib/usercopy.c */ + +extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n); +extern unsigned long __copy_user_zeroing(void *to, const void __user *from, unsigned long n); +extern unsigned long __do_clear_user(void __user *to, unsigned long n); + +static inline unsigned long +__generic_copy_to_user(void __user *to, const void *from, unsigned long n) +{ + if (access_ok(VERIFY_WRITE, to, n)) + return __copy_user(to, from, n); + return n; +} + +static inline unsigned long +__generic_copy_from_user(void *to, const void __user *from, unsigned long n) +{ + if (access_ok(VERIFY_READ, from, n)) + return __copy_user_zeroing(to, from, n); + return n; +} + +static inline unsigned long +__generic_clear_user(void __user *to, unsigned long n) +{ + if (access_ok(VERIFY_WRITE, to, n)) + return __do_clear_user(to, n); + return n; +} + +static inline long +__strncpy_from_user(char *dst, const char __user *src, long count) +{ + return __do_strncpy_from_user(dst, src, count); +} + +static inline long +strncpy_from_user(char *dst, const char __user *src, long count) +{ + long res = -EFAULT; + + if (access_ok(VERIFY_READ, src, 1)) + res = __do_strncpy_from_user(dst, src, count); + return res; +} + + +/* Note that these expand awfully if made into switch constructs, so + don't do that. */ + +static inline unsigned long +__constant_copy_from_user(void *to, const void __user *from, unsigned long n) +{ + unsigned long ret = 0; + + if (n == 0) + ; + else if (n == 1) + __asm_copy_from_user_1(to, from, ret); + else if (n == 2) + __asm_copy_from_user_2(to, from, ret); + else if (n == 3) + __asm_copy_from_user_3(to, from, ret); + else if (n == 4) + __asm_copy_from_user_4(to, from, ret); + else if (n == 5) + __asm_copy_from_user_5(to, from, ret); + else if (n == 6) + __asm_copy_from_user_6(to, from, ret); + else if (n == 7) + __asm_copy_from_user_7(to, from, ret); + else if (n == 8) + __asm_copy_from_user_8(to, from, ret); + else if (n == 9) + __asm_copy_from_user_9(to, from, ret); + else if (n == 10) + __asm_copy_from_user_10(to, from, ret); + else if (n == 11) + __asm_copy_from_user_11(to, from, ret); + else if (n == 12) + __asm_copy_from_user_12(to, from, ret); + else if (n == 13) + __asm_copy_from_user_13(to, from, ret); + else if (n == 14) + __asm_copy_from_user_14(to, from, ret); + else if (n == 15) + __asm_copy_from_user_15(to, from, ret); + else if (n == 16) + __asm_copy_from_user_16(to, from, ret); + else if (n == 20) + __asm_copy_from_user_20(to, from, ret); + else if (n == 24) + __asm_copy_from_user_24(to, from, ret); + else + ret = __generic_copy_from_user(to, from, n); + + return ret; +} + +/* Ditto, don't make a switch out of this. */ + +static inline unsigned long +__constant_copy_to_user(void __user *to, const void *from, unsigned long n) +{ + unsigned long ret = 0; + + if (n == 0) + ; + else if (n == 1) + __asm_copy_to_user_1(to, from, ret); + else if (n == 2) + __asm_copy_to_user_2(to, from, ret); + else if (n == 3) + __asm_copy_to_user_3(to, from, ret); + else if (n == 4) + __asm_copy_to_user_4(to, from, ret); + else if (n == 5) + __asm_copy_to_user_5(to, from, ret); + else if (n == 6) + __asm_copy_to_user_6(to, from, ret); + else if (n == 7) + __asm_copy_to_user_7(to, from, ret); + else if (n == 8) + __asm_copy_to_user_8(to, from, ret); + else if (n == 9) + __asm_copy_to_user_9(to, from, ret); + else if (n == 10) + __asm_copy_to_user_10(to, from, ret); + else if (n == 11) + __asm_copy_to_user_11(to, from, ret); + else if (n == 12) + __asm_copy_to_user_12(to, from, ret); + else if (n == 13) + __asm_copy_to_user_13(to, from, ret); + else if (n == 14) + __asm_copy_to_user_14(to, from, ret); + else if (n == 15) + __asm_copy_to_user_15(to, from, ret); + else if (n == 16) + __asm_copy_to_user_16(to, from, ret); + else if (n == 20) + __asm_copy_to_user_20(to, from, ret); + else if (n == 24) + __asm_copy_to_user_24(to, from, ret); + else + ret = __generic_copy_to_user(to, from, n); + + return ret; +} + +/* No switch, please. */ + +static inline unsigned long +__constant_clear_user(void __user *to, unsigned long n) +{ + unsigned long ret = 0; + + if (n == 0) + ; + else if (n == 1) + __asm_clear_1(to, ret); + else if (n == 2) + __asm_clear_2(to, ret); + else if (n == 3) + __asm_clear_3(to, ret); + else if (n == 4) + __asm_clear_4(to, ret); + else if (n == 8) + __asm_clear_8(to, ret); + else if (n == 12) + __asm_clear_12(to, ret); + else if (n == 16) + __asm_clear_16(to, ret); + else if (n == 20) + __asm_clear_20(to, ret); + else if (n == 24) + __asm_clear_24(to, ret); + else + ret = __generic_clear_user(to, n); + + return ret; +} + + +#define clear_user(to, n) \ + (__builtin_constant_p(n) ? \ + __constant_clear_user(to, n) : \ + __generic_clear_user(to, n)) + +#define copy_from_user(to, from, n) \ + (__builtin_constant_p(n) ? \ + __constant_copy_from_user(to, from, n) : \ + __generic_copy_from_user(to, from, n)) + +#define copy_to_user(to, from, n) \ + (__builtin_constant_p(n) ? \ + __constant_copy_to_user(to, from, n) : \ + __generic_copy_to_user(to, from, n)) + +/* We let the __ versions of copy_from/to_user inline, because they're often + * used in fast paths and have only a small space overhead. + */ + +static inline unsigned long +__generic_copy_from_user_nocheck(void *to, const void __user *from, + unsigned long n) +{ + return __copy_user_zeroing(to, from, n); +} + +static inline unsigned long +__generic_copy_to_user_nocheck(void __user *to, const void *from, + unsigned long n) +{ + return __copy_user(to, from, n); +} + +static inline unsigned long +__generic_clear_user_nocheck(void __user *to, unsigned long n) +{ + return __do_clear_user(to, n); +} + +/* without checking */ + +#define __copy_to_user(to, from, n) \ + __generic_copy_to_user_nocheck((to), (from), (n)) +#define __copy_from_user(to, from, n) \ + __generic_copy_from_user_nocheck((to), (from), (n)) +#define __copy_to_user_inatomic __copy_to_user +#define __copy_from_user_inatomic __copy_from_user +#define __clear_user(to, n) __generic_clear_user_nocheck((to), (n)) + +#define strlen_user(str) strnlen_user((str), 0x7ffffffe) + +#endif /* __ASSEMBLY__ */ + +#endif /* _CRIS_UACCESS_H */ diff --git a/kernel/arch/cris/include/asm/ucontext.h b/kernel/arch/cris/include/asm/ucontext.h new file mode 100644 index 000000000..eed6ad5eb --- /dev/null +++ b/kernel/arch/cris/include/asm/ucontext.h @@ -0,0 +1,12 @@ +#ifndef _ASM_CRIS_UCONTEXT_H +#define _ASM_CRIS_UCONTEXT_H + +struct ucontext { + unsigned long uc_flags; + struct ucontext *uc_link; + stack_t uc_stack; + struct sigcontext uc_mcontext; + sigset_t uc_sigmask; /* mask last for extensibility */ +}; + +#endif /* !_ASM_CRIS_UCONTEXT_H */ diff --git a/kernel/arch/cris/include/asm/unaligned.h b/kernel/arch/cris/include/asm/unaligned.h new file mode 100644 index 000000000..7b3f3fec5 --- /dev/null +++ b/kernel/arch/cris/include/asm/unaligned.h @@ -0,0 +1,13 @@ +#ifndef _ASM_CRIS_UNALIGNED_H +#define _ASM_CRIS_UNALIGNED_H + +/* + * CRIS can do unaligned accesses itself. + */ +#include +#include + +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le + +#endif /* _ASM_CRIS_UNALIGNED_H */ diff --git a/kernel/arch/cris/include/asm/unistd.h b/kernel/arch/cris/include/asm/unistd.h new file mode 100644 index 000000000..0f40fed1b --- /dev/null +++ b/kernel/arch/cris/include/asm/unistd.h @@ -0,0 +1,36 @@ +#ifndef _ASM_CRIS_UNISTD_H_ +#define _ASM_CRIS_UNISTD_H_ + +#include + + +#define NR_syscalls 360 + +#include + +#define __ARCH_WANT_OLD_READDIR +#define __ARCH_WANT_OLD_STAT +#define __ARCH_WANT_STAT64 +#define __ARCH_WANT_SYS_ALARM +#define __ARCH_WANT_SYS_GETHOSTNAME +#define __ARCH_WANT_SYS_IPC +#define __ARCH_WANT_SYS_PAUSE +#define __ARCH_WANT_SYS_SIGNAL +#define __ARCH_WANT_SYS_TIME +#define __ARCH_WANT_SYS_UTIME +#define __ARCH_WANT_SYS_WAITPID +#define __ARCH_WANT_SYS_SOCKETCALL +#define __ARCH_WANT_SYS_FADVISE64 +#define __ARCH_WANT_SYS_GETPGRP +#define __ARCH_WANT_SYS_LLSEEK +#define __ARCH_WANT_SYS_NICE +#define __ARCH_WANT_SYS_OLD_GETRLIMIT +#define __ARCH_WANT_SYS_OLD_MMAP +#define __ARCH_WANT_SYS_OLDUMOUNT +#define __ARCH_WANT_SYS_SIGPENDING +#define __ARCH_WANT_SYS_SIGPROCMASK +#define __ARCH_WANT_SYS_FORK +#define __ARCH_WANT_SYS_VFORK +#define __ARCH_WANT_SYS_CLONE + +#endif /* _ASM_CRIS_UNISTD_H_ */ diff --git a/kernel/arch/cris/include/asm/user.h b/kernel/arch/cris/include/asm/user.h new file mode 100644 index 000000000..59147cf43 --- /dev/null +++ b/kernel/arch/cris/include/asm/user.h @@ -0,0 +1,52 @@ +#ifndef __ASM_CRIS_USER_H +#define __ASM_CRIS_USER_H + +#include +#include +#include +#include + +/* + * Core file format: The core file is written in such a way that gdb + * can understand it and provide useful information to the user (under + * linux we use the `trad-core' bfd). The file contents are as follows: + * + * upage: 1 page consisting of a user struct that tells gdb + * what is present in the file. Directly after this is a + * copy of the task_struct, which is currently not used by gdb, + * but it may come in handy at some point. All of the registers + * are stored as part of the upage. The upage should always be + * only one page long. + * data: The data segment follows next. We use current->end_text to + * current->brk to pick up all of the user variables, plus any memory + * that may have been sbrk'ed. No attempt is made to determine if a + * page is demand-zero or if a page is totally unused, we just cover + * the entire range. All of the addresses are rounded in such a way + * that an integral number of pages is written. + * stack: We need the stack information in order to get a meaningful + * backtrace. We need to write the data from usp to + * current->start_stack, so we round each of these in order to be able + * to write an integer number of pages. + */ + +struct user { + struct user_regs_struct regs; /* entire machine state */ + size_t u_tsize; /* text size (pages) */ + size_t u_dsize; /* data size (pages) */ + size_t u_ssize; /* stack size (pages) */ + unsigned long start_code; /* text starting address */ + unsigned long start_data; /* data starting address */ + unsigned long start_stack; /* stack starting address */ + long int signal; /* signal causing core dump */ + unsigned long u_ar0; /* help gdb find registers */ + unsigned long magic; /* identifies a core file */ + char u_comm[32]; /* user command name */ +}; + +#define NBPG PAGE_SIZE +#define UPAGES 1 +#define HOST_TEXT_START_ADDR (u.start_code) +#define HOST_DATA_START_ADDR (u.start_data) +#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) + +#endif /* __ASM_CRIS_USER_H */ diff --git a/kernel/arch/cris/include/uapi/arch-v10/arch/Kbuild b/kernel/arch/cris/include/uapi/arch-v10/arch/Kbuild new file mode 100644 index 000000000..9048c87a7 --- /dev/null +++ b/kernel/arch/cris/include/uapi/arch-v10/arch/Kbuild @@ -0,0 +1,5 @@ +# UAPI Header export list +header-y += sv_addr.agh +header-y += sv_addr_ag.h +header-y += svinto.h +header-y += user.h diff --git a/kernel/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh b/kernel/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh new file mode 100644 index 000000000..6ac3a7bc9 --- /dev/null +++ b/kernel/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh @@ -0,0 +1,7306 @@ +/* +!* This file was automatically generated by /n/asic/bin/reg_macro_gen +!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. +!* Editing within this file is thus not recommended, +!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. +!*/ + + +/* +!* Bus interface configuration registers +!*/ + +#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) +#define R_WAITSTATES__pcs4_7_zw__BITNR 30 +#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 +#define R_WAITSTATES__pcs4_7_ew__BITNR 28 +#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 +#define R_WAITSTATES__pcs4_7_lw__BITNR 24 +#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 +#define R_WAITSTATES__pcs0_3_zw__BITNR 22 +#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 +#define R_WAITSTATES__pcs0_3_ew__BITNR 20 +#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 +#define R_WAITSTATES__pcs0_3_lw__BITNR 16 +#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 +#define R_WAITSTATES__sram_zw__BITNR 14 +#define R_WAITSTATES__sram_zw__WIDTH 2 +#define R_WAITSTATES__sram_ew__BITNR 12 +#define R_WAITSTATES__sram_ew__WIDTH 2 +#define R_WAITSTATES__sram_lw__BITNR 8 +#define R_WAITSTATES__sram_lw__WIDTH 4 +#define R_WAITSTATES__flash_zw__BITNR 6 +#define R_WAITSTATES__flash_zw__WIDTH 2 +#define R_WAITSTATES__flash_ew__BITNR 4 +#define R_WAITSTATES__flash_ew__WIDTH 2 +#define R_WAITSTATES__flash_lw__BITNR 0 +#define R_WAITSTATES__flash_lw__WIDTH 4 + +#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) +#define R_BUS_CONFIG__sram_type__BITNR 9 +#define R_BUS_CONFIG__sram_type__WIDTH 1 +#define R_BUS_CONFIG__sram_type__cwe 1 +#define R_BUS_CONFIG__sram_type__bwe 0 +#define R_BUS_CONFIG__dma_burst__BITNR 8 +#define R_BUS_CONFIG__dma_burst__WIDTH 1 +#define R_BUS_CONFIG__dma_burst__burst16 1 +#define R_BUS_CONFIG__dma_burst__burst32 0 +#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 +#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 +#define R_BUS_CONFIG__pcs4_7_wr__ext 1 +#define R_BUS_CONFIG__pcs4_7_wr__norm 0 +#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 +#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 +#define R_BUS_CONFIG__pcs0_3_wr__ext 1 +#define R_BUS_CONFIG__pcs0_3_wr__norm 0 +#define R_BUS_CONFIG__sram_wr__BITNR 5 +#define R_BUS_CONFIG__sram_wr__WIDTH 1 +#define R_BUS_CONFIG__sram_wr__ext 1 +#define R_BUS_CONFIG__sram_wr__norm 0 +#define R_BUS_CONFIG__flash_wr__BITNR 4 +#define R_BUS_CONFIG__flash_wr__WIDTH 1 +#define R_BUS_CONFIG__flash_wr__ext 1 +#define R_BUS_CONFIG__flash_wr__norm 0 +#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 +#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 +#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 +#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 +#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 +#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 +#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 +#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 +#define R_BUS_CONFIG__sram_bw__BITNR 1 +#define R_BUS_CONFIG__sram_bw__WIDTH 1 +#define R_BUS_CONFIG__sram_bw__bw32 1 +#define R_BUS_CONFIG__sram_bw__bw16 0 +#define R_BUS_CONFIG__flash_bw__BITNR 0 +#define R_BUS_CONFIG__flash_bw__WIDTH 1 +#define R_BUS_CONFIG__flash_bw__bw32 1 +#define R_BUS_CONFIG__flash_bw__bw16 0 + +#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) +#define R_BUS_STATUS__pll_lock_tm__BITNR 5 +#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 +#define R_BUS_STATUS__pll_lock_tm__expired 0 +#define R_BUS_STATUS__pll_lock_tm__counting 1 +#define R_BUS_STATUS__both_faults__BITNR 4 +#define R_BUS_STATUS__both_faults__WIDTH 1 +#define R_BUS_STATUS__both_faults__no 0 +#define R_BUS_STATUS__both_faults__yes 1 +#define R_BUS_STATUS__bsen___BITNR 3 +#define R_BUS_STATUS__bsen___WIDTH 1 +#define R_BUS_STATUS__bsen___enable 0 +#define R_BUS_STATUS__bsen___disable 1 +#define R_BUS_STATUS__boot__BITNR 1 +#define R_BUS_STATUS__boot__WIDTH 2 +#define R_BUS_STATUS__boot__uncached 0 +#define R_BUS_STATUS__boot__serial 1 +#define R_BUS_STATUS__boot__network 2 +#define R_BUS_STATUS__boot__parallel 3 +#define R_BUS_STATUS__flashw__BITNR 0 +#define R_BUS_STATUS__flashw__WIDTH 1 +#define R_BUS_STATUS__flashw__bw32 1 +#define R_BUS_STATUS__flashw__bw16 0 + +#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) +#define R_DRAM_TIMING__sdram__BITNR 31 +#define R_DRAM_TIMING__sdram__WIDTH 1 +#define R_DRAM_TIMING__sdram__enable 1 +#define R_DRAM_TIMING__sdram__disable 0 +#define R_DRAM_TIMING__ref__BITNR 14 +#define R_DRAM_TIMING__ref__WIDTH 2 +#define R_DRAM_TIMING__ref__e52us 0 +#define R_DRAM_TIMING__ref__e13us 1 +#define R_DRAM_TIMING__ref__e8700ns 2 +#define R_DRAM_TIMING__ref__disable 3 +#define R_DRAM_TIMING__rp__BITNR 12 +#define R_DRAM_TIMING__rp__WIDTH 2 +#define R_DRAM_TIMING__rs__BITNR 10 +#define R_DRAM_TIMING__rs__WIDTH 2 +#define R_DRAM_TIMING__rh__BITNR 8 +#define R_DRAM_TIMING__rh__WIDTH 2 +#define R_DRAM_TIMING__w__BITNR 7 +#define R_DRAM_TIMING__w__WIDTH 1 +#define R_DRAM_TIMING__w__norm 0 +#define R_DRAM_TIMING__w__ext 1 +#define R_DRAM_TIMING__c__BITNR 6 +#define R_DRAM_TIMING__c__WIDTH 1 +#define R_DRAM_TIMING__c__norm 0 +#define R_DRAM_TIMING__c__ext 1 +#define R_DRAM_TIMING__cz__BITNR 4 +#define R_DRAM_TIMING__cz__WIDTH 2 +#define R_DRAM_TIMING__cp__BITNR 2 +#define R_DRAM_TIMING__cp__WIDTH 2 +#define R_DRAM_TIMING__cw__BITNR 0 +#define R_DRAM_TIMING__cw__WIDTH 2 + +#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) +#define R_SDRAM_TIMING__sdram__BITNR 31 +#define R_SDRAM_TIMING__sdram__WIDTH 1 +#define R_SDRAM_TIMING__sdram__enable 1 +#define R_SDRAM_TIMING__sdram__disable 0 +#define R_SDRAM_TIMING__mrs_data__BITNR 16 +#define R_SDRAM_TIMING__mrs_data__WIDTH 15 +#define R_SDRAM_TIMING__ref__BITNR 14 +#define R_SDRAM_TIMING__ref__WIDTH 2 +#define R_SDRAM_TIMING__ref__e52us 0 +#define R_SDRAM_TIMING__ref__e13us 1 +#define R_SDRAM_TIMING__ref__e6500ns 2 +#define R_SDRAM_TIMING__ref__disable 3 +#define R_SDRAM_TIMING__ddr__BITNR 13 +#define R_SDRAM_TIMING__ddr__WIDTH 1 +#define R_SDRAM_TIMING__ddr__on 1 +#define R_SDRAM_TIMING__ddr__off 0 +#define R_SDRAM_TIMING__clk100__BITNR 12 +#define R_SDRAM_TIMING__clk100__WIDTH 1 +#define R_SDRAM_TIMING__clk100__on 1 +#define R_SDRAM_TIMING__clk100__off 0 +#define R_SDRAM_TIMING__ps__BITNR 11 +#define R_SDRAM_TIMING__ps__WIDTH 1 +#define R_SDRAM_TIMING__ps__on 1 +#define R_SDRAM_TIMING__ps__off 0 +#define R_SDRAM_TIMING__cmd__BITNR 9 +#define R_SDRAM_TIMING__cmd__WIDTH 2 +#define R_SDRAM_TIMING__cmd__pre 3 +#define R_SDRAM_TIMING__cmd__ref 2 +#define R_SDRAM_TIMING__cmd__mrs 1 +#define R_SDRAM_TIMING__cmd__nop 0 +#define R_SDRAM_TIMING__pde__BITNR 8 +#define R_SDRAM_TIMING__pde__WIDTH 1 +#define R_SDRAM_TIMING__rc__BITNR 6 +#define R_SDRAM_TIMING__rc__WIDTH 2 +#define R_SDRAM_TIMING__rp__BITNR 4 +#define R_SDRAM_TIMING__rp__WIDTH 2 +#define R_SDRAM_TIMING__rcd__BITNR 2 +#define R_SDRAM_TIMING__rcd__WIDTH 2 +#define R_SDRAM_TIMING__cl__BITNR 0 +#define R_SDRAM_TIMING__cl__WIDTH 2 + +#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) +#define R_DRAM_CONFIG__wmm1__BITNR 31 +#define R_DRAM_CONFIG__wmm1__WIDTH 1 +#define R_DRAM_CONFIG__wmm1__wmm 1 +#define R_DRAM_CONFIG__wmm1__norm 0 +#define R_DRAM_CONFIG__wmm0__BITNR 30 +#define R_DRAM_CONFIG__wmm0__WIDTH 1 +#define R_DRAM_CONFIG__wmm0__wmm 1 +#define R_DRAM_CONFIG__wmm0__norm 0 +#define R_DRAM_CONFIG__sh1__BITNR 27 +#define R_DRAM_CONFIG__sh1__WIDTH 3 +#define R_DRAM_CONFIG__sh0__BITNR 24 +#define R_DRAM_CONFIG__sh0__WIDTH 3 +#define R_DRAM_CONFIG__w__BITNR 23 +#define R_DRAM_CONFIG__w__WIDTH 1 +#define R_DRAM_CONFIG__w__bw16 0 +#define R_DRAM_CONFIG__w__bw32 1 +#define R_DRAM_CONFIG__c__BITNR 22 +#define R_DRAM_CONFIG__c__WIDTH 1 +#define R_DRAM_CONFIG__c__byte 0 +#define R_DRAM_CONFIG__c__bank 1 +#define R_DRAM_CONFIG__e__BITNR 21 +#define R_DRAM_CONFIG__e__WIDTH 1 +#define R_DRAM_CONFIG__e__fast 0 +#define R_DRAM_CONFIG__e__edo 1 +#define R_DRAM_CONFIG__group_sel__BITNR 16 +#define R_DRAM_CONFIG__group_sel__WIDTH 5 +#define R_DRAM_CONFIG__group_sel__grp0 0 +#define R_DRAM_CONFIG__group_sel__grp1 1 +#define R_DRAM_CONFIG__group_sel__bit9 9 +#define R_DRAM_CONFIG__group_sel__bit10 10 +#define R_DRAM_CONFIG__group_sel__bit11 11 +#define R_DRAM_CONFIG__group_sel__bit12 12 +#define R_DRAM_CONFIG__group_sel__bit13 13 +#define R_DRAM_CONFIG__group_sel__bit14 14 +#define R_DRAM_CONFIG__group_sel__bit15 15 +#define R_DRAM_CONFIG__group_sel__bit16 16 +#define R_DRAM_CONFIG__group_sel__bit17 17 +#define R_DRAM_CONFIG__group_sel__bit18 18 +#define R_DRAM_CONFIG__group_sel__bit19 19 +#define R_DRAM_CONFIG__group_sel__bit20 20 +#define R_DRAM_CONFIG__group_sel__bit21 21 +#define R_DRAM_CONFIG__group_sel__bit22 22 +#define R_DRAM_CONFIG__group_sel__bit23 23 +#define R_DRAM_CONFIG__group_sel__bit24 24 +#define R_DRAM_CONFIG__group_sel__bit25 25 +#define R_DRAM_CONFIG__group_sel__bit26 26 +#define R_DRAM_CONFIG__group_sel__bit27 27 +#define R_DRAM_CONFIG__group_sel__bit28 28 +#define R_DRAM_CONFIG__group_sel__bit29 29 +#define R_DRAM_CONFIG__ca1__BITNR 13 +#define R_DRAM_CONFIG__ca1__WIDTH 3 +#define R_DRAM_CONFIG__bank23sel__BITNR 8 +#define R_DRAM_CONFIG__bank23sel__WIDTH 5 +#define R_DRAM_CONFIG__bank23sel__bank0 0 +#define R_DRAM_CONFIG__bank23sel__bank1 1 +#define R_DRAM_CONFIG__bank23sel__bit9 9 +#define R_DRAM_CONFIG__bank23sel__bit10 10 +#define R_DRAM_CONFIG__bank23sel__bit11 11 +#define R_DRAM_CONFIG__bank23sel__bit12 12 +#define R_DRAM_CONFIG__bank23sel__bit13 13 +#define R_DRAM_CONFIG__bank23sel__bit14 14 +#define R_DRAM_CONFIG__bank23sel__bit15 15 +#define R_DRAM_CONFIG__bank23sel__bit16 16 +#define R_DRAM_CONFIG__bank23sel__bit17 17 +#define R_DRAM_CONFIG__bank23sel__bit18 18 +#define R_DRAM_CONFIG__bank23sel__bit19 19 +#define R_DRAM_CONFIG__bank23sel__bit20 20 +#define R_DRAM_CONFIG__bank23sel__bit21 21 +#define R_DRAM_CONFIG__bank23sel__bit22 22 +#define R_DRAM_CONFIG__bank23sel__bit23 23 +#define R_DRAM_CONFIG__bank23sel__bit24 24 +#define R_DRAM_CONFIG__bank23sel__bit25 25 +#define R_DRAM_CONFIG__bank23sel__bit26 26 +#define R_DRAM_CONFIG__bank23sel__bit27 27 +#define R_DRAM_CONFIG__bank23sel__bit28 28 +#define R_DRAM_CONFIG__bank23sel__bit29 29 +#define R_DRAM_CONFIG__ca0__BITNR 5 +#define R_DRAM_CONFIG__ca0__WIDTH 3 +#define R_DRAM_CONFIG__bank01sel__BITNR 0 +#define R_DRAM_CONFIG__bank01sel__WIDTH 5 +#define R_DRAM_CONFIG__bank01sel__bank0 0 +#define R_DRAM_CONFIG__bank01sel__bank1 1 +#define R_DRAM_CONFIG__bank01sel__bit9 9 +#define R_DRAM_CONFIG__bank01sel__bit10 10 +#define R_DRAM_CONFIG__bank01sel__bit11 11 +#define R_DRAM_CONFIG__bank01sel__bit12 12 +#define R_DRAM_CONFIG__bank01sel__bit13 13 +#define R_DRAM_CONFIG__bank01sel__bit14 14 +#define R_DRAM_CONFIG__bank01sel__bit15 15 +#define R_DRAM_CONFIG__bank01sel__bit16 16 +#define R_DRAM_CONFIG__bank01sel__bit17 17 +#define R_DRAM_CONFIG__bank01sel__bit18 18 +#define R_DRAM_CONFIG__bank01sel__bit19 19 +#define R_DRAM_CONFIG__bank01sel__bit20 20 +#define R_DRAM_CONFIG__bank01sel__bit21 21 +#define R_DRAM_CONFIG__bank01sel__bit22 22 +#define R_DRAM_CONFIG__bank01sel__bit23 23 +#define R_DRAM_CONFIG__bank01sel__bit24 24 +#define R_DRAM_CONFIG__bank01sel__bit25 25 +#define R_DRAM_CONFIG__bank01sel__bit26 26 +#define R_DRAM_CONFIG__bank01sel__bit27 27 +#define R_DRAM_CONFIG__bank01sel__bit28 28 +#define R_DRAM_CONFIG__bank01sel__bit29 29 + +#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) +#define R_SDRAM_CONFIG__wmm1__BITNR 31 +#define R_SDRAM_CONFIG__wmm1__WIDTH 1 +#define R_SDRAM_CONFIG__wmm1__wmm 1 +#define R_SDRAM_CONFIG__wmm1__norm 0 +#define R_SDRAM_CONFIG__wmm0__BITNR 30 +#define R_SDRAM_CONFIG__wmm0__WIDTH 1 +#define R_SDRAM_CONFIG__wmm0__wmm 1 +#define R_SDRAM_CONFIG__wmm0__norm 0 +#define R_SDRAM_CONFIG__sh1__BITNR 27 +#define R_SDRAM_CONFIG__sh1__WIDTH 3 +#define R_SDRAM_CONFIG__sh0__BITNR 24 +#define R_SDRAM_CONFIG__sh0__WIDTH 3 +#define R_SDRAM_CONFIG__w__BITNR 23 +#define R_SDRAM_CONFIG__w__WIDTH 1 +#define R_SDRAM_CONFIG__w__bw16 0 +#define R_SDRAM_CONFIG__w__bw32 1 +#define R_SDRAM_CONFIG__type1__BITNR 22 +#define R_SDRAM_CONFIG__type1__WIDTH 1 +#define R_SDRAM_CONFIG__type1__bank2 0 +#define R_SDRAM_CONFIG__type1__bank4 1 +#define R_SDRAM_CONFIG__type0__BITNR 21 +#define R_SDRAM_CONFIG__type0__WIDTH 1 +#define R_SDRAM_CONFIG__type0__bank2 0 +#define R_SDRAM_CONFIG__type0__bank4 1 +#define R_SDRAM_CONFIG__group_sel__BITNR 16 +#define R_SDRAM_CONFIG__group_sel__WIDTH 5 +#define R_SDRAM_CONFIG__group_sel__grp0 0 +#define R_SDRAM_CONFIG__group_sel__grp1 1 +#define R_SDRAM_CONFIG__group_sel__bit9 9 +#define R_SDRAM_CONFIG__group_sel__bit10 10 +#define R_SDRAM_CONFIG__group_sel__bit11 11 +#define R_SDRAM_CONFIG__group_sel__bit12 12 +#define R_SDRAM_CONFIG__group_sel__bit13 13 +#define R_SDRAM_CONFIG__group_sel__bit14 14 +#define R_SDRAM_CONFIG__group_sel__bit15 15 +#define R_SDRAM_CONFIG__group_sel__bit16 16 +#define R_SDRAM_CONFIG__group_sel__bit17 17 +#define R_SDRAM_CONFIG__group_sel__bit18 18 +#define R_SDRAM_CONFIG__group_sel__bit19 19 +#define R_SDRAM_CONFIG__group_sel__bit20 20 +#define R_SDRAM_CONFIG__group_sel__bit21 21 +#define R_SDRAM_CONFIG__group_sel__bit22 22 +#define R_SDRAM_CONFIG__group_sel__bit23 23 +#define R_SDRAM_CONFIG__group_sel__bit24 24 +#define R_SDRAM_CONFIG__group_sel__bit25 25 +#define R_SDRAM_CONFIG__group_sel__bit26 26 +#define R_SDRAM_CONFIG__group_sel__bit27 27 +#define R_SDRAM_CONFIG__group_sel__bit28 28 +#define R_SDRAM_CONFIG__group_sel__bit29 29 +#define R_SDRAM_CONFIG__ca1__BITNR 13 +#define R_SDRAM_CONFIG__ca1__WIDTH 3 +#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 +#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 +#define R_SDRAM_CONFIG__bank_sel1__bit9 9 +#define R_SDRAM_CONFIG__bank_sel1__bit10 10 +#define R_SDRAM_CONFIG__bank_sel1__bit11 11 +#define R_SDRAM_CONFIG__bank_sel1__bit12 12 +#define R_SDRAM_CONFIG__bank_sel1__bit13 13 +#define R_SDRAM_CONFIG__bank_sel1__bit14 14 +#define R_SDRAM_CONFIG__bank_sel1__bit15 15 +#define R_SDRAM_CONFIG__bank_sel1__bit16 16 +#define R_SDRAM_CONFIG__bank_sel1__bit17 17 +#define R_SDRAM_CONFIG__bank_sel1__bit18 18 +#define R_SDRAM_CONFIG__bank_sel1__bit19 19 +#define R_SDRAM_CONFIG__bank_sel1__bit20 20 +#define R_SDRAM_CONFIG__bank_sel1__bit21 21 +#define R_SDRAM_CONFIG__bank_sel1__bit22 22 +#define R_SDRAM_CONFIG__bank_sel1__bit23 23 +#define R_SDRAM_CONFIG__bank_sel1__bit24 24 +#define R_SDRAM_CONFIG__bank_sel1__bit25 25 +#define R_SDRAM_CONFIG__bank_sel1__bit26 26 +#define R_SDRAM_CONFIG__bank_sel1__bit27 27 +#define R_SDRAM_CONFIG__bank_sel1__bit28 28 +#define R_SDRAM_CONFIG__bank_sel1__bit29 29 +#define R_SDRAM_CONFIG__ca0__BITNR 5 +#define R_SDRAM_CONFIG__ca0__WIDTH 3 +#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 +#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 +#define R_SDRAM_CONFIG__bank_sel0__bit9 9 +#define R_SDRAM_CONFIG__bank_sel0__bit10 10 +#define R_SDRAM_CONFIG__bank_sel0__bit11 11 +#define R_SDRAM_CONFIG__bank_sel0__bit12 12 +#define R_SDRAM_CONFIG__bank_sel0__bit13 13 +#define R_SDRAM_CONFIG__bank_sel0__bit14 14 +#define R_SDRAM_CONFIG__bank_sel0__bit15 15 +#define R_SDRAM_CONFIG__bank_sel0__bit16 16 +#define R_SDRAM_CONFIG__bank_sel0__bit17 17 +#define R_SDRAM_CONFIG__bank_sel0__bit18 18 +#define R_SDRAM_CONFIG__bank_sel0__bit19 19 +#define R_SDRAM_CONFIG__bank_sel0__bit20 20 +#define R_SDRAM_CONFIG__bank_sel0__bit21 21 +#define R_SDRAM_CONFIG__bank_sel0__bit22 22 +#define R_SDRAM_CONFIG__bank_sel0__bit23 23 +#define R_SDRAM_CONFIG__bank_sel0__bit24 24 +#define R_SDRAM_CONFIG__bank_sel0__bit25 25 +#define R_SDRAM_CONFIG__bank_sel0__bit26 26 +#define R_SDRAM_CONFIG__bank_sel0__bit27 27 +#define R_SDRAM_CONFIG__bank_sel0__bit28 28 +#define R_SDRAM_CONFIG__bank_sel0__bit29 29 + +/* +!* External DMA registers +!*/ + +#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) +#define R_EXT_DMA_0_CMD__cnt__BITNR 23 +#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 +#define R_EXT_DMA_0_CMD__cnt__enable 1 +#define R_EXT_DMA_0_CMD__cnt__disable 0 +#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 +#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 +#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 +#define R_EXT_DMA_0_CMD__rqpol__alow 1 +#define R_EXT_DMA_0_CMD__apol__BITNR 21 +#define R_EXT_DMA_0_CMD__apol__WIDTH 1 +#define R_EXT_DMA_0_CMD__apol__ahigh 0 +#define R_EXT_DMA_0_CMD__apol__alow 1 +#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 +#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 +#define R_EXT_DMA_0_CMD__rq_ack__burst 0 +#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 +#define R_EXT_DMA_0_CMD__wid__BITNR 18 +#define R_EXT_DMA_0_CMD__wid__WIDTH 2 +#define R_EXT_DMA_0_CMD__wid__byte 0 +#define R_EXT_DMA_0_CMD__wid__word 1 +#define R_EXT_DMA_0_CMD__wid__dword 2 +#define R_EXT_DMA_0_CMD__dir__BITNR 17 +#define R_EXT_DMA_0_CMD__dir__WIDTH 1 +#define R_EXT_DMA_0_CMD__dir__input 0 +#define R_EXT_DMA_0_CMD__dir__output 1 +#define R_EXT_DMA_0_CMD__run__BITNR 16 +#define R_EXT_DMA_0_CMD__run__WIDTH 1 +#define R_EXT_DMA_0_CMD__run__start 1 +#define R_EXT_DMA_0_CMD__run__stop 0 +#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 +#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 + +#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) +#define R_EXT_DMA_0_STAT__run__BITNR 16 +#define R_EXT_DMA_0_STAT__run__WIDTH 1 +#define R_EXT_DMA_0_STAT__run__start 1 +#define R_EXT_DMA_0_STAT__run__stop 0 +#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 +#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 + +#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) +#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 +#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 + +#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) +#define R_EXT_DMA_1_CMD__cnt__BITNR 23 +#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 +#define R_EXT_DMA_1_CMD__cnt__enable 1 +#define R_EXT_DMA_1_CMD__cnt__disable 0 +#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 +#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 +#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 +#define R_EXT_DMA_1_CMD__rqpol__alow 1 +#define R_EXT_DMA_1_CMD__apol__BITNR 21 +#define R_EXT_DMA_1_CMD__apol__WIDTH 1 +#define R_EXT_DMA_1_CMD__apol__ahigh 0 +#define R_EXT_DMA_1_CMD__apol__alow 1 +#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 +#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 +#define R_EXT_DMA_1_CMD__rq_ack__burst 0 +#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 +#define R_EXT_DMA_1_CMD__wid__BITNR 18 +#define R_EXT_DMA_1_CMD__wid__WIDTH 2 +#define R_EXT_DMA_1_CMD__wid__byte 0 +#define R_EXT_DMA_1_CMD__wid__word 1 +#define R_EXT_DMA_1_CMD__wid__dword 2 +#define R_EXT_DMA_1_CMD__dir__BITNR 17 +#define R_EXT_DMA_1_CMD__dir__WIDTH 1 +#define R_EXT_DMA_1_CMD__dir__input 0 +#define R_EXT_DMA_1_CMD__dir__output 1 +#define R_EXT_DMA_1_CMD__run__BITNR 16 +#define R_EXT_DMA_1_CMD__run__WIDTH 1 +#define R_EXT_DMA_1_CMD__run__start 1 +#define R_EXT_DMA_1_CMD__run__stop 0 +#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 +#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 + +#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) +#define R_EXT_DMA_1_STAT__run__BITNR 16 +#define R_EXT_DMA_1_STAT__run__WIDTH 1 +#define R_EXT_DMA_1_STAT__run__start 1 +#define R_EXT_DMA_1_STAT__run__stop 0 +#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 +#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 + +#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) +#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 +#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 + +/* +!* Timer registers +!*/ + +#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) +#define R_TIMER_CTRL__timerdiv1__BITNR 24 +#define R_TIMER_CTRL__timerdiv1__WIDTH 8 +#define R_TIMER_CTRL__timerdiv0__BITNR 16 +#define R_TIMER_CTRL__timerdiv0__WIDTH 8 +#define R_TIMER_CTRL__presc_timer1__BITNR 15 +#define R_TIMER_CTRL__presc_timer1__WIDTH 1 +#define R_TIMER_CTRL__presc_timer1__normal 0 +#define R_TIMER_CTRL__presc_timer1__prescale 1 +#define R_TIMER_CTRL__i1__BITNR 14 +#define R_TIMER_CTRL__i1__WIDTH 1 +#define R_TIMER_CTRL__i1__clr 1 +#define R_TIMER_CTRL__i1__nop 0 +#define R_TIMER_CTRL__tm1__BITNR 12 +#define R_TIMER_CTRL__tm1__WIDTH 2 +#define R_TIMER_CTRL__tm1__stop_ld 0 +#define R_TIMER_CTRL__tm1__freeze 1 +#define R_TIMER_CTRL__tm1__run 2 +#define R_TIMER_CTRL__tm1__reserved 3 +#define R_TIMER_CTRL__clksel1__BITNR 8 +#define R_TIMER_CTRL__clksel1__WIDTH 4 +#define R_TIMER_CTRL__clksel1__c300Hz 0 +#define R_TIMER_CTRL__clksel1__c600Hz 1 +#define R_TIMER_CTRL__clksel1__c1200Hz 2 +#define R_TIMER_CTRL__clksel1__c2400Hz 3 +#define R_TIMER_CTRL__clksel1__c4800Hz 4 +#define R_TIMER_CTRL__clksel1__c9600Hz 5 +#define R_TIMER_CTRL__clksel1__c19k2Hz 6 +#define R_TIMER_CTRL__clksel1__c38k4Hz 7 +#define R_TIMER_CTRL__clksel1__c57k6Hz 8 +#define R_TIMER_CTRL__clksel1__c115k2Hz 9 +#define R_TIMER_CTRL__clksel1__c230k4Hz 10 +#define R_TIMER_CTRL__clksel1__c460k8Hz 11 +#define R_TIMER_CTRL__clksel1__c921k6Hz 12 +#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 +#define R_TIMER_CTRL__clksel1__c6250kHz 14 +#define R_TIMER_CTRL__clksel1__cascade0 15 +#define R_TIMER_CTRL__presc_ext__BITNR 7 +#define R_TIMER_CTRL__presc_ext__WIDTH 1 +#define R_TIMER_CTRL__presc_ext__prescale 0 +#define R_TIMER_CTRL__presc_ext__external 1 +#define R_TIMER_CTRL__i0__BITNR 6 +#define R_TIMER_CTRL__i0__WIDTH 1 +#define R_TIMER_CTRL__i0__clr 1 +#define R_TIMER_CTRL__i0__nop 0 +#define R_TIMER_CTRL__tm0__BITNR 4 +#define R_TIMER_CTRL__tm0__WIDTH 2 +#define R_TIMER_CTRL__tm0__stop_ld 0 +#define R_TIMER_CTRL__tm0__freeze 1 +#define R_TIMER_CTRL__tm0__run 2 +#define R_TIMER_CTRL__tm0__reserved 3 +#define R_TIMER_CTRL__clksel0__BITNR 0 +#define R_TIMER_CTRL__clksel0__WIDTH 4 +#define R_TIMER_CTRL__clksel0__c300Hz 0 +#define R_TIMER_CTRL__clksel0__c600Hz 1 +#define R_TIMER_CTRL__clksel0__c1200Hz 2 +#define R_TIMER_CTRL__clksel0__c2400Hz 3 +#define R_TIMER_CTRL__clksel0__c4800Hz 4 +#define R_TIMER_CTRL__clksel0__c9600Hz 5 +#define R_TIMER_CTRL__clksel0__c19k2Hz 6 +#define R_TIMER_CTRL__clksel0__c38k4Hz 7 +#define R_TIMER_CTRL__clksel0__c57k6Hz 8 +#define R_TIMER_CTRL__clksel0__c115k2Hz 9 +#define R_TIMER_CTRL__clksel0__c230k4Hz 10 +#define R_TIMER_CTRL__clksel0__c460k8Hz 11 +#define R_TIMER_CTRL__clksel0__c921k6Hz 12 +#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 +#define R_TIMER_CTRL__clksel0__c6250kHz 14 +#define R_TIMER_CTRL__clksel0__flexible 15 + +#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) +#define R_TIMER_DATA__timer1__BITNR 24 +#define R_TIMER_DATA__timer1__WIDTH 8 +#define R_TIMER_DATA__timer0__BITNR 16 +#define R_TIMER_DATA__timer0__WIDTH 8 +#define R_TIMER_DATA__clkdiv_high__BITNR 8 +#define R_TIMER_DATA__clkdiv_high__WIDTH 8 +#define R_TIMER_DATA__clkdiv_low__BITNR 0 +#define R_TIMER_DATA__clkdiv_low__WIDTH 8 + +#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) +#define R_TIMER01_DATA__count__BITNR 0 +#define R_TIMER01_DATA__count__WIDTH 16 + +#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) +#define R_TIMER0_DATA__count__BITNR 0 +#define R_TIMER0_DATA__count__WIDTH 8 + +#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) +#define R_TIMER1_DATA__count__BITNR 0 +#define R_TIMER1_DATA__count__WIDTH 8 + +#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) +#define R_WATCHDOG__key__BITNR 1 +#define R_WATCHDOG__key__WIDTH 3 +#define R_WATCHDOG__enable__BITNR 0 +#define R_WATCHDOG__enable__WIDTH 1 +#define R_WATCHDOG__enable__stop 0 +#define R_WATCHDOG__enable__start 1 + +#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) +#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 +#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 +#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 +#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 + +#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) +#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 +#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 + +#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) +#define R_TIMER_PRESCALE__tim_presc__BITNR 0 +#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 + +#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) +#define R_PRESCALE_STATUS__ser_status__BITNR 16 +#define R_PRESCALE_STATUS__ser_status__WIDTH 16 +#define R_PRESCALE_STATUS__tim_status__BITNR 0 +#define R_PRESCALE_STATUS__tim_status__WIDTH 16 + +#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) +#define R_SER_PRESC_STATUS__ser_status__BITNR 0 +#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 + +#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) +#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 +#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 + +#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 +#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 +#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 +#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 +#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 +#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 +#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 + +/* +!* Shared RAM interface registers +!*/ + +#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) +#define R_SHARED_RAM_CONFIG__width__BITNR 3 +#define R_SHARED_RAM_CONFIG__width__WIDTH 1 +#define R_SHARED_RAM_CONFIG__width__byte 0 +#define R_SHARED_RAM_CONFIG__width__word 1 +#define R_SHARED_RAM_CONFIG__enable__BITNR 2 +#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 +#define R_SHARED_RAM_CONFIG__enable__yes 1 +#define R_SHARED_RAM_CONFIG__enable__no 0 +#define R_SHARED_RAM_CONFIG__pint__BITNR 1 +#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 +#define R_SHARED_RAM_CONFIG__pint__int 1 +#define R_SHARED_RAM_CONFIG__pint__nop 0 +#define R_SHARED_RAM_CONFIG__clri__BITNR 0 +#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 +#define R_SHARED_RAM_CONFIG__clri__clr 1 +#define R_SHARED_RAM_CONFIG__clri__nop 0 + +#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) +#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 +#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 + +/* +!* General config registers +!*/ + +#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) +#define R_GEN_CONFIG__par_w__BITNR 31 +#define R_GEN_CONFIG__par_w__WIDTH 1 +#define R_GEN_CONFIG__par_w__select 1 +#define R_GEN_CONFIG__par_w__disable 0 +#define R_GEN_CONFIG__usb2__BITNR 30 +#define R_GEN_CONFIG__usb2__WIDTH 1 +#define R_GEN_CONFIG__usb2__select 1 +#define R_GEN_CONFIG__usb2__disable 0 +#define R_GEN_CONFIG__usb1__BITNR 29 +#define R_GEN_CONFIG__usb1__WIDTH 1 +#define R_GEN_CONFIG__usb1__select 1 +#define R_GEN_CONFIG__usb1__disable 0 +#define R_GEN_CONFIG__g24dir__BITNR 27 +#define R_GEN_CONFIG__g24dir__WIDTH 1 +#define R_GEN_CONFIG__g24dir__in 0 +#define R_GEN_CONFIG__g24dir__out 1 +#define R_GEN_CONFIG__g16_23dir__BITNR 26 +#define R_GEN_CONFIG__g16_23dir__WIDTH 1 +#define R_GEN_CONFIG__g16_23dir__in 0 +#define R_GEN_CONFIG__g16_23dir__out 1 +#define R_GEN_CONFIG__g8_15dir__BITNR 25 +#define R_GEN_CONFIG__g8_15dir__WIDTH 1 +#define R_GEN_CONFIG__g8_15dir__in 0 +#define R_GEN_CONFIG__g8_15dir__out 1 +#define R_GEN_CONFIG__g0dir__BITNR 24 +#define R_GEN_CONFIG__g0dir__WIDTH 1 +#define R_GEN_CONFIG__g0dir__in 0 +#define R_GEN_CONFIG__g0dir__out 1 +#define R_GEN_CONFIG__dma9__BITNR 23 +#define R_GEN_CONFIG__dma9__WIDTH 1 +#define R_GEN_CONFIG__dma9__usb 0 +#define R_GEN_CONFIG__dma9__serial1 1 +#define R_GEN_CONFIG__dma8__BITNR 22 +#define R_GEN_CONFIG__dma8__WIDTH 1 +#define R_GEN_CONFIG__dma8__usb 0 +#define R_GEN_CONFIG__dma8__serial1 1 +#define R_GEN_CONFIG__dma7__BITNR 20 +#define R_GEN_CONFIG__dma7__WIDTH 2 +#define R_GEN_CONFIG__dma7__unused 0 +#define R_GEN_CONFIG__dma7__serial0 1 +#define R_GEN_CONFIG__dma7__extdma1 2 +#define R_GEN_CONFIG__dma7__intdma6 3 +#define R_GEN_CONFIG__dma6__BITNR 18 +#define R_GEN_CONFIG__dma6__WIDTH 2 +#define R_GEN_CONFIG__dma6__unused 0 +#define R_GEN_CONFIG__dma6__serial0 1 +#define R_GEN_CONFIG__dma6__extdma1 2 +#define R_GEN_CONFIG__dma6__intdma7 3 +#define R_GEN_CONFIG__dma5__BITNR 16 +#define R_GEN_CONFIG__dma5__WIDTH 2 +#define R_GEN_CONFIG__dma5__par1 0 +#define R_GEN_CONFIG__dma5__scsi1 1 +#define R_GEN_CONFIG__dma5__serial3 2 +#define R_GEN_CONFIG__dma5__extdma0 3 +#define R_GEN_CONFIG__dma4__BITNR 14 +#define R_GEN_CONFIG__dma4__WIDTH 2 +#define R_GEN_CONFIG__dma4__par1 0 +#define R_GEN_CONFIG__dma4__scsi1 1 +#define R_GEN_CONFIG__dma4__serial3 2 +#define R_GEN_CONFIG__dma4__extdma0 3 +#define R_GEN_CONFIG__dma3__BITNR 12 +#define R_GEN_CONFIG__dma3__WIDTH 2 +#define R_GEN_CONFIG__dma3__par0 0 +#define R_GEN_CONFIG__dma3__scsi0 1 +#define R_GEN_CONFIG__dma3__serial2 2 +#define R_GEN_CONFIG__dma3__ata 3 +#define R_GEN_CONFIG__dma2__BITNR 10 +#define R_GEN_CONFIG__dma2__WIDTH 2 +#define R_GEN_CONFIG__dma2__par0 0 +#define R_GEN_CONFIG__dma2__scsi0 1 +#define R_GEN_CONFIG__dma2__serial2 2 +#define R_GEN_CONFIG__dma2__ata 3 +#define R_GEN_CONFIG__mio_w__BITNR 9 +#define R_GEN_CONFIG__mio_w__WIDTH 1 +#define R_GEN_CONFIG__mio_w__select 1 +#define R_GEN_CONFIG__mio_w__disable 0 +#define R_GEN_CONFIG__ser3__BITNR 8 +#define R_GEN_CONFIG__ser3__WIDTH 1 +#define R_GEN_CONFIG__ser3__select 1 +#define R_GEN_CONFIG__ser3__disable 0 +#define R_GEN_CONFIG__par1__BITNR 7 +#define R_GEN_CONFIG__par1__WIDTH 1 +#define R_GEN_CONFIG__par1__select 1 +#define R_GEN_CONFIG__par1__disable 0 +#define R_GEN_CONFIG__scsi0w__BITNR 6 +#define R_GEN_CONFIG__scsi0w__WIDTH 1 +#define R_GEN_CONFIG__scsi0w__select 1 +#define R_GEN_CONFIG__scsi0w__disable 0 +#define R_GEN_CONFIG__scsi1__BITNR 5 +#define R_GEN_CONFIG__scsi1__WIDTH 1 +#define R_GEN_CONFIG__scsi1__select 1 +#define R_GEN_CONFIG__scsi1__disable 0 +#define R_GEN_CONFIG__mio__BITNR 4 +#define R_GEN_CONFIG__mio__WIDTH 1 +#define R_GEN_CONFIG__mio__select 1 +#define R_GEN_CONFIG__mio__disable 0 +#define R_GEN_CONFIG__ser2__BITNR 3 +#define R_GEN_CONFIG__ser2__WIDTH 1 +#define R_GEN_CONFIG__ser2__select 1 +#define R_GEN_CONFIG__ser2__disable 0 +#define R_GEN_CONFIG__par0__BITNR 2 +#define R_GEN_CONFIG__par0__WIDTH 1 +#define R_GEN_CONFIG__par0__select 1 +#define R_GEN_CONFIG__par0__disable 0 +#define R_GEN_CONFIG__ata__BITNR 1 +#define R_GEN_CONFIG__ata__WIDTH 1 +#define R_GEN_CONFIG__ata__select 1 +#define R_GEN_CONFIG__ata__disable 0 +#define R_GEN_CONFIG__scsi0__BITNR 0 +#define R_GEN_CONFIG__scsi0__WIDTH 1 +#define R_GEN_CONFIG__scsi0__select 1 +#define R_GEN_CONFIG__scsi0__disable 0 + +#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) +#define R_GEN_CONFIG_II__sermode3__BITNR 6 +#define R_GEN_CONFIG_II__sermode3__WIDTH 1 +#define R_GEN_CONFIG_II__sermode3__async 0 +#define R_GEN_CONFIG_II__sermode3__sync 1 +#define R_GEN_CONFIG_II__sermode1__BITNR 4 +#define R_GEN_CONFIG_II__sermode1__WIDTH 1 +#define R_GEN_CONFIG_II__sermode1__async 0 +#define R_GEN_CONFIG_II__sermode1__sync 1 +#define R_GEN_CONFIG_II__ext_clk__BITNR 2 +#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 +#define R_GEN_CONFIG_II__ext_clk__select 1 +#define R_GEN_CONFIG_II__ext_clk__disable 0 +#define R_GEN_CONFIG_II__ser2__BITNR 1 +#define R_GEN_CONFIG_II__ser2__WIDTH 1 +#define R_GEN_CONFIG_II__ser2__select 1 +#define R_GEN_CONFIG_II__ser2__disable 0 +#define R_GEN_CONFIG_II__ser3__BITNR 0 +#define R_GEN_CONFIG_II__ser3__WIDTH 1 +#define R_GEN_CONFIG_II__ser3__select 1 +#define R_GEN_CONFIG_II__ser3__disable 0 + +#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) +#define R_PORT_G_DATA__data__BITNR 0 +#define R_PORT_G_DATA__data__WIDTH 32 + +/* +!* General port configuration registers +!*/ + +#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) +#define R_PORT_PA_SET__dir7__BITNR 15 +#define R_PORT_PA_SET__dir7__WIDTH 1 +#define R_PORT_PA_SET__dir7__input 0 +#define R_PORT_PA_SET__dir7__output 1 +#define R_PORT_PA_SET__dir6__BITNR 14 +#define R_PORT_PA_SET__dir6__WIDTH 1 +#define R_PORT_PA_SET__dir6__input 0 +#define R_PORT_PA_SET__dir6__output 1 +#define R_PORT_PA_SET__dir5__BITNR 13 +#define R_PORT_PA_SET__dir5__WIDTH 1 +#define R_PORT_PA_SET__dir5__input 0 +#define R_PORT_PA_SET__dir5__output 1 +#define R_PORT_PA_SET__dir4__BITNR 12 +#define R_PORT_PA_SET__dir4__WIDTH 1 +#define R_PORT_PA_SET__dir4__input 0 +#define R_PORT_PA_SET__dir4__output 1 +#define R_PORT_PA_SET__dir3__BITNR 11 +#define R_PORT_PA_SET__dir3__WIDTH 1 +#define R_PORT_PA_SET__dir3__input 0 +#define R_PORT_PA_SET__dir3__output 1 +#define R_PORT_PA_SET__dir2__BITNR 10 +#define R_PORT_PA_SET__dir2__WIDTH 1 +#define R_PORT_PA_SET__dir2__input 0 +#define R_PORT_PA_SET__dir2__output 1 +#define R_PORT_PA_SET__dir1__BITNR 9 +#define R_PORT_PA_SET__dir1__WIDTH 1 +#define R_PORT_PA_SET__dir1__input 0 +#define R_PORT_PA_SET__dir1__output 1 +#define R_PORT_PA_SET__dir0__BITNR 8 +#define R_PORT_PA_SET__dir0__WIDTH 1 +#define R_PORT_PA_SET__dir0__input 0 +#define R_PORT_PA_SET__dir0__output 1 +#define R_PORT_PA_SET__data_out__BITNR 0 +#define R_PORT_PA_SET__data_out__WIDTH 8 + +#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) +#define R_PORT_PA_DATA__data_out__BITNR 0 +#define R_PORT_PA_DATA__data_out__WIDTH 8 + +#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) +#define R_PORT_PA_DIR__dir7__BITNR 7 +#define R_PORT_PA_DIR__dir7__WIDTH 1 +#define R_PORT_PA_DIR__dir7__input 0 +#define R_PORT_PA_DIR__dir7__output 1 +#define R_PORT_PA_DIR__dir6__BITNR 6 +#define R_PORT_PA_DIR__dir6__WIDTH 1 +#define R_PORT_PA_DIR__dir6__input 0 +#define R_PORT_PA_DIR__dir6__output 1 +#define R_PORT_PA_DIR__dir5__BITNR 5 +#define R_PORT_PA_DIR__dir5__WIDTH 1 +#define R_PORT_PA_DIR__dir5__input 0 +#define R_PORT_PA_DIR__dir5__output 1 +#define R_PORT_PA_DIR__dir4__BITNR 4 +#define R_PORT_PA_DIR__dir4__WIDTH 1 +#define R_PORT_PA_DIR__dir4__input 0 +#define R_PORT_PA_DIR__dir4__output 1 +#define R_PORT_PA_DIR__dir3__BITNR 3 +#define R_PORT_PA_DIR__dir3__WIDTH 1 +#define R_PORT_PA_DIR__dir3__input 0 +#define R_PORT_PA_DIR__dir3__output 1 +#define R_PORT_PA_DIR__dir2__BITNR 2 +#define R_PORT_PA_DIR__dir2__WIDTH 1 +#define R_PORT_PA_DIR__dir2__input 0 +#define R_PORT_PA_DIR__dir2__output 1 +#define R_PORT_PA_DIR__dir1__BITNR 1 +#define R_PORT_PA_DIR__dir1__WIDTH 1 +#define R_PORT_PA_DIR__dir1__input 0 +#define R_PORT_PA_DIR__dir1__output 1 +#define R_PORT_PA_DIR__dir0__BITNR 0 +#define R_PORT_PA_DIR__dir0__WIDTH 1 +#define R_PORT_PA_DIR__dir0__input 0 +#define R_PORT_PA_DIR__dir0__output 1 + +#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) +#define R_PORT_PA_READ__data_in__BITNR 0 +#define R_PORT_PA_READ__data_in__WIDTH 8 + +#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) +#define R_PORT_PB_SET__syncser3__BITNR 29 +#define R_PORT_PB_SET__syncser3__WIDTH 1 +#define R_PORT_PB_SET__syncser3__port_cs 0 +#define R_PORT_PB_SET__syncser3__ss3extra 1 +#define R_PORT_PB_SET__syncser1__BITNR 28 +#define R_PORT_PB_SET__syncser1__WIDTH 1 +#define R_PORT_PB_SET__syncser1__port_cs 0 +#define R_PORT_PB_SET__syncser1__ss1extra 1 +#define R_PORT_PB_SET__i2c_en__BITNR 27 +#define R_PORT_PB_SET__i2c_en__WIDTH 1 +#define R_PORT_PB_SET__i2c_en__off 0 +#define R_PORT_PB_SET__i2c_en__on 1 +#define R_PORT_PB_SET__i2c_d__BITNR 26 +#define R_PORT_PB_SET__i2c_d__WIDTH 1 +#define R_PORT_PB_SET__i2c_clk__BITNR 25 +#define R_PORT_PB_SET__i2c_clk__WIDTH 1 +#define R_PORT_PB_SET__i2c_oe___BITNR 24 +#define R_PORT_PB_SET__i2c_oe___WIDTH 1 +#define R_PORT_PB_SET__i2c_oe___enable 0 +#define R_PORT_PB_SET__i2c_oe___disable 1 +#define R_PORT_PB_SET__cs7__BITNR 23 +#define R_PORT_PB_SET__cs7__WIDTH 1 +#define R_PORT_PB_SET__cs7__port 0 +#define R_PORT_PB_SET__cs7__cs 1 +#define R_PORT_PB_SET__cs6__BITNR 22 +#define R_PORT_PB_SET__cs6__WIDTH 1 +#define R_PORT_PB_SET__cs6__port 0 +#define R_PORT_PB_SET__cs6__cs 1 +#define R_PORT_PB_SET__cs5__BITNR 21 +#define R_PORT_PB_SET__cs5__WIDTH 1 +#define R_PORT_PB_SET__cs5__port 0 +#define R_PORT_PB_SET__cs5__cs 1 +#define R_PORT_PB_SET__cs4__BITNR 20 +#define R_PORT_PB_SET__cs4__WIDTH 1 +#define R_PORT_PB_SET__cs4__port 0 +#define R_PORT_PB_SET__cs4__cs 1 +#define R_PORT_PB_SET__cs3__BITNR 19 +#define R_PORT_PB_SET__cs3__WIDTH 1 +#define R_PORT_PB_SET__cs3__port 0 +#define R_PORT_PB_SET__cs3__cs 1 +#define R_PORT_PB_SET__cs2__BITNR 18 +#define R_PORT_PB_SET__cs2__WIDTH 1 +#define R_PORT_PB_SET__cs2__port 0 +#define R_PORT_PB_SET__cs2__cs 1 +#define R_PORT_PB_SET__scsi1__BITNR 17 +#define R_PORT_PB_SET__scsi1__WIDTH 1 +#define R_PORT_PB_SET__scsi1__port_cs 0 +#define R_PORT_PB_SET__scsi1__enph 1 +#define R_PORT_PB_SET__scsi0__BITNR 16 +#define R_PORT_PB_SET__scsi0__WIDTH 1 +#define R_PORT_PB_SET__scsi0__port_cs 0 +#define R_PORT_PB_SET__scsi0__enph 1 +#define R_PORT_PB_SET__dir7__BITNR 15 +#define R_PORT_PB_SET__dir7__WIDTH 1 +#define R_PORT_PB_SET__dir7__input 0 +#define R_PORT_PB_SET__dir7__output 1 +#define R_PORT_PB_SET__dir6__BITNR 14 +#define R_PORT_PB_SET__dir6__WIDTH 1 +#define R_PORT_PB_SET__dir6__input 0 +#define R_PORT_PB_SET__dir6__output 1 +#define R_PORT_PB_SET__dir5__BITNR 13 +#define R_PORT_PB_SET__dir5__WIDTH 1 +#define R_PORT_PB_SET__dir5__input 0 +#define R_PORT_PB_SET__dir5__output 1 +#define R_PORT_PB_SET__dir4__BITNR 12 +#define R_PORT_PB_SET__dir4__WIDTH 1 +#define R_PORT_PB_SET__dir4__input 0 +#define R_PORT_PB_SET__dir4__output 1 +#define R_PORT_PB_SET__dir3__BITNR 11 +#define R_PORT_PB_SET__dir3__WIDTH 1 +#define R_PORT_PB_SET__dir3__input 0 +#define R_PORT_PB_SET__dir3__output 1 +#define R_PORT_PB_SET__dir2__BITNR 10 +#define R_PORT_PB_SET__dir2__WIDTH 1 +#define R_PORT_PB_SET__dir2__input 0 +#define R_PORT_PB_SET__dir2__output 1 +#define R_PORT_PB_SET__dir1__BITNR 9 +#define R_PORT_PB_SET__dir1__WIDTH 1 +#define R_PORT_PB_SET__dir1__input 0 +#define R_PORT_PB_SET__dir1__output 1 +#define R_PORT_PB_SET__dir0__BITNR 8 +#define R_PORT_PB_SET__dir0__WIDTH 1 +#define R_PORT_PB_SET__dir0__input 0 +#define R_PORT_PB_SET__dir0__output 1 +#define R_PORT_PB_SET__data_out__BITNR 0 +#define R_PORT_PB_SET__data_out__WIDTH 8 + +#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) +#define R_PORT_PB_DATA__data_out__BITNR 0 +#define R_PORT_PB_DATA__data_out__WIDTH 8 + +#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) +#define R_PORT_PB_DIR__dir7__BITNR 7 +#define R_PORT_PB_DIR__dir7__WIDTH 1 +#define R_PORT_PB_DIR__dir7__input 0 +#define R_PORT_PB_DIR__dir7__output 1 +#define R_PORT_PB_DIR__dir6__BITNR 6 +#define R_PORT_PB_DIR__dir6__WIDTH 1 +#define R_PORT_PB_DIR__dir6__input 0 +#define R_PORT_PB_DIR__dir6__output 1 +#define R_PORT_PB_DIR__dir5__BITNR 5 +#define R_PORT_PB_DIR__dir5__WIDTH 1 +#define R_PORT_PB_DIR__dir5__input 0 +#define R_PORT_PB_DIR__dir5__output 1 +#define R_PORT_PB_DIR__dir4__BITNR 4 +#define R_PORT_PB_DIR__dir4__WIDTH 1 +#define R_PORT_PB_DIR__dir4__input 0 +#define R_PORT_PB_DIR__dir4__output 1 +#define R_PORT_PB_DIR__dir3__BITNR 3 +#define R_PORT_PB_DIR__dir3__WIDTH 1 +#define R_PORT_PB_DIR__dir3__input 0 +#define R_PORT_PB_DIR__dir3__output 1 +#define R_PORT_PB_DIR__dir2__BITNR 2 +#define R_PORT_PB_DIR__dir2__WIDTH 1 +#define R_PORT_PB_DIR__dir2__input 0 +#define R_PORT_PB_DIR__dir2__output 1 +#define R_PORT_PB_DIR__dir1__BITNR 1 +#define R_PORT_PB_DIR__dir1__WIDTH 1 +#define R_PORT_PB_DIR__dir1__input 0 +#define R_PORT_PB_DIR__dir1__output 1 +#define R_PORT_PB_DIR__dir0__BITNR 0 +#define R_PORT_PB_DIR__dir0__WIDTH 1 +#define R_PORT_PB_DIR__dir0__input 0 +#define R_PORT_PB_DIR__dir0__output 1 + +#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) +#define R_PORT_PB_CONFIG__cs7__BITNR 7 +#define R_PORT_PB_CONFIG__cs7__WIDTH 1 +#define R_PORT_PB_CONFIG__cs7__port 0 +#define R_PORT_PB_CONFIG__cs7__cs 1 +#define R_PORT_PB_CONFIG__cs6__BITNR 6 +#define R_PORT_PB_CONFIG__cs6__WIDTH 1 +#define R_PORT_PB_CONFIG__cs6__port 0 +#define R_PORT_PB_CONFIG__cs6__cs 1 +#define R_PORT_PB_CONFIG__cs5__BITNR 5 +#define R_PORT_PB_CONFIG__cs5__WIDTH 1 +#define R_PORT_PB_CONFIG__cs5__port 0 +#define R_PORT_PB_CONFIG__cs5__cs 1 +#define R_PORT_PB_CONFIG__cs4__BITNR 4 +#define R_PORT_PB_CONFIG__cs4__WIDTH 1 +#define R_PORT_PB_CONFIG__cs4__port 0 +#define R_PORT_PB_CONFIG__cs4__cs 1 +#define R_PORT_PB_CONFIG__cs3__BITNR 3 +#define R_PORT_PB_CONFIG__cs3__WIDTH 1 +#define R_PORT_PB_CONFIG__cs3__port 0 +#define R_PORT_PB_CONFIG__cs3__cs 1 +#define R_PORT_PB_CONFIG__cs2__BITNR 2 +#define R_PORT_PB_CONFIG__cs2__WIDTH 1 +#define R_PORT_PB_CONFIG__cs2__port 0 +#define R_PORT_PB_CONFIG__cs2__cs 1 +#define R_PORT_PB_CONFIG__scsi1__BITNR 1 +#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 +#define R_PORT_PB_CONFIG__scsi1__port_cs 0 +#define R_PORT_PB_CONFIG__scsi1__enph 1 +#define R_PORT_PB_CONFIG__scsi0__BITNR 0 +#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 +#define R_PORT_PB_CONFIG__scsi0__port_cs 0 +#define R_PORT_PB_CONFIG__scsi0__enph 1 + +#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) +#define R_PORT_PB_I2C__syncser3__BITNR 5 +#define R_PORT_PB_I2C__syncser3__WIDTH 1 +#define R_PORT_PB_I2C__syncser3__port_cs 0 +#define R_PORT_PB_I2C__syncser3__ss3extra 1 +#define R_PORT_PB_I2C__syncser1__BITNR 4 +#define R_PORT_PB_I2C__syncser1__WIDTH 1 +#define R_PORT_PB_I2C__syncser1__port_cs 0 +#define R_PORT_PB_I2C__syncser1__ss1extra 1 +#define R_PORT_PB_I2C__i2c_en__BITNR 3 +#define R_PORT_PB_I2C__i2c_en__WIDTH 1 +#define R_PORT_PB_I2C__i2c_en__off 0 +#define R_PORT_PB_I2C__i2c_en__on 1 +#define R_PORT_PB_I2C__i2c_d__BITNR 2 +#define R_PORT_PB_I2C__i2c_d__WIDTH 1 +#define R_PORT_PB_I2C__i2c_clk__BITNR 1 +#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 +#define R_PORT_PB_I2C__i2c_oe___BITNR 0 +#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 +#define R_PORT_PB_I2C__i2c_oe___enable 0 +#define R_PORT_PB_I2C__i2c_oe___disable 1 + +#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) +#define R_PORT_PB_READ__data_in__BITNR 0 +#define R_PORT_PB_READ__data_in__WIDTH 8 + +/* +!* Serial port registers +!*/ + +#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) +#define R_SERIAL0_CTRL__tr_baud__BITNR 28 +#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL0_CTRL__tr_baud__reserved 15 +#define R_SERIAL0_CTRL__rec_baud__BITNR 24 +#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL0_CTRL__rec_baud__reserved 15 +#define R_SERIAL0_CTRL__dma_err__BITNR 23 +#define R_SERIAL0_CTRL__dma_err__WIDTH 1 +#define R_SERIAL0_CTRL__dma_err__stop 0 +#define R_SERIAL0_CTRL__dma_err__ignore 1 +#define R_SERIAL0_CTRL__rec_enable__BITNR 22 +#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL0_CTRL__rec_enable__disable 0 +#define R_SERIAL0_CTRL__rec_enable__enable 1 +#define R_SERIAL0_CTRL__rts___BITNR 21 +#define R_SERIAL0_CTRL__rts___WIDTH 1 +#define R_SERIAL0_CTRL__rts___active 0 +#define R_SERIAL0_CTRL__rts___inactive 1 +#define R_SERIAL0_CTRL__sampling__BITNR 20 +#define R_SERIAL0_CTRL__sampling__WIDTH 1 +#define R_SERIAL0_CTRL__sampling__middle 0 +#define R_SERIAL0_CTRL__sampling__majority 1 +#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL0_CTRL__rec_stick_par__normal 0 +#define R_SERIAL0_CTRL__rec_stick_par__stick 1 +#define R_SERIAL0_CTRL__rec_par__BITNR 18 +#define R_SERIAL0_CTRL__rec_par__WIDTH 1 +#define R_SERIAL0_CTRL__rec_par__even 0 +#define R_SERIAL0_CTRL__rec_par__odd 1 +#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL0_CTRL__rec_par_en__disable 0 +#define R_SERIAL0_CTRL__rec_par_en__enable 1 +#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL0_CTRL__txd__BITNR 15 +#define R_SERIAL0_CTRL__txd__WIDTH 1 +#define R_SERIAL0_CTRL__tr_enable__BITNR 14 +#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL0_CTRL__tr_enable__disable 0 +#define R_SERIAL0_CTRL__tr_enable__enable 1 +#define R_SERIAL0_CTRL__auto_cts__BITNR 13 +#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL0_CTRL__auto_cts__disabled 0 +#define R_SERIAL0_CTRL__auto_cts__active 1 +#define R_SERIAL0_CTRL__stop_bits__BITNR 12 +#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL0_CTRL__stop_bits__one_bit 0 +#define R_SERIAL0_CTRL__stop_bits__two_bits 1 +#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL0_CTRL__tr_stick_par__normal 0 +#define R_SERIAL0_CTRL__tr_stick_par__stick 1 +#define R_SERIAL0_CTRL__tr_par__BITNR 10 +#define R_SERIAL0_CTRL__tr_par__WIDTH 1 +#define R_SERIAL0_CTRL__tr_par__even 0 +#define R_SERIAL0_CTRL__tr_par__odd 1 +#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL0_CTRL__tr_par_en__disable 0 +#define R_SERIAL0_CTRL__tr_par_en__enable 1 +#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL0_CTRL__data_out__BITNR 0 +#define R_SERIAL0_CTRL__data_out__WIDTH 8 + +#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) +#define R_SERIAL0_BAUD__tr_baud__BITNR 4 +#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL0_BAUD__tr_baud__reserved 15 +#define R_SERIAL0_BAUD__rec_baud__BITNR 0 +#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL0_BAUD__rec_baud__reserved 15 + +#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) +#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL0_REC_CTRL__dma_err__stop 0 +#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL0_REC_CTRL__rts___BITNR 5 +#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL0_REC_CTRL__rts___active 0 +#define R_SERIAL0_REC_CTRL__rts___inactive 1 +#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL0_REC_CTRL__sampling__middle 0 +#define R_SERIAL0_REC_CTRL__sampling__majority 1 +#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_par__even 0 +#define R_SERIAL0_REC_CTRL__rec_par__odd 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) +#define R_SERIAL0_TR_CTRL__txd__BITNR 7 +#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL0_TR_CTRL__auto_cts__active 1 +#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_par__even 0 +#define R_SERIAL0_TR_CTRL__tr_par__odd 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) +#define R_SERIAL0_TR_DATA__data_out__BITNR 0 +#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) +#define R_SERIAL0_READ__xoff_detect__BITNR 15 +#define R_SERIAL0_READ__xoff_detect__WIDTH 1 +#define R_SERIAL0_READ__xoff_detect__no_xoff 0 +#define R_SERIAL0_READ__xoff_detect__xoff 1 +#define R_SERIAL0_READ__cts___BITNR 14 +#define R_SERIAL0_READ__cts___WIDTH 1 +#define R_SERIAL0_READ__cts___active 0 +#define R_SERIAL0_READ__cts___inactive 1 +#define R_SERIAL0_READ__tr_ready__BITNR 13 +#define R_SERIAL0_READ__tr_ready__WIDTH 1 +#define R_SERIAL0_READ__tr_ready__full 0 +#define R_SERIAL0_READ__tr_ready__ready 1 +#define R_SERIAL0_READ__rxd__BITNR 12 +#define R_SERIAL0_READ__rxd__WIDTH 1 +#define R_SERIAL0_READ__overrun__BITNR 11 +#define R_SERIAL0_READ__overrun__WIDTH 1 +#define R_SERIAL0_READ__overrun__no 0 +#define R_SERIAL0_READ__overrun__yes 1 +#define R_SERIAL0_READ__par_err__BITNR 10 +#define R_SERIAL0_READ__par_err__WIDTH 1 +#define R_SERIAL0_READ__par_err__no 0 +#define R_SERIAL0_READ__par_err__yes 1 +#define R_SERIAL0_READ__framing_err__BITNR 9 +#define R_SERIAL0_READ__framing_err__WIDTH 1 +#define R_SERIAL0_READ__framing_err__no 0 +#define R_SERIAL0_READ__framing_err__yes 1 +#define R_SERIAL0_READ__data_avail__BITNR 8 +#define R_SERIAL0_READ__data_avail__WIDTH 1 +#define R_SERIAL0_READ__data_avail__no 0 +#define R_SERIAL0_READ__data_avail__yes 1 +#define R_SERIAL0_READ__data_in__BITNR 0 +#define R_SERIAL0_READ__data_in__WIDTH 8 + +#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) +#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL0_STATUS__xoff_detect__xoff 1 +#define R_SERIAL0_STATUS__cts___BITNR 6 +#define R_SERIAL0_STATUS__cts___WIDTH 1 +#define R_SERIAL0_STATUS__cts___active 0 +#define R_SERIAL0_STATUS__cts___inactive 1 +#define R_SERIAL0_STATUS__tr_ready__BITNR 5 +#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL0_STATUS__tr_ready__full 0 +#define R_SERIAL0_STATUS__tr_ready__ready 1 +#define R_SERIAL0_STATUS__rxd__BITNR 4 +#define R_SERIAL0_STATUS__rxd__WIDTH 1 +#define R_SERIAL0_STATUS__overrun__BITNR 3 +#define R_SERIAL0_STATUS__overrun__WIDTH 1 +#define R_SERIAL0_STATUS__overrun__no 0 +#define R_SERIAL0_STATUS__overrun__yes 1 +#define R_SERIAL0_STATUS__par_err__BITNR 2 +#define R_SERIAL0_STATUS__par_err__WIDTH 1 +#define R_SERIAL0_STATUS__par_err__no 0 +#define R_SERIAL0_STATUS__par_err__yes 1 +#define R_SERIAL0_STATUS__framing_err__BITNR 1 +#define R_SERIAL0_STATUS__framing_err__WIDTH 1 +#define R_SERIAL0_STATUS__framing_err__no 0 +#define R_SERIAL0_STATUS__framing_err__yes 1 +#define R_SERIAL0_STATUS__data_avail__BITNR 0 +#define R_SERIAL0_STATUS__data_avail__WIDTH 1 +#define R_SERIAL0_STATUS__data_avail__no 0 +#define R_SERIAL0_STATUS__data_avail__yes 1 + +#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) +#define R_SERIAL0_REC_DATA__data_in__BITNR 0 +#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) +#define R_SERIAL0_XOFF__tx_stop__BITNR 9 +#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL0_XOFF__tx_stop__enable 0 +#define R_SERIAL0_XOFF__tx_stop__stop 1 +#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL0_XOFF__auto_xoff__disable 0 +#define R_SERIAL0_XOFF__auto_xoff__enable 1 +#define R_SERIAL0_XOFF__xoff_char__BITNR 0 +#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) +#define R_SERIAL1_CTRL__tr_baud__BITNR 28 +#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL1_CTRL__tr_baud__reserved 15 +#define R_SERIAL1_CTRL__rec_baud__BITNR 24 +#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL1_CTRL__rec_baud__reserved 15 +#define R_SERIAL1_CTRL__dma_err__BITNR 23 +#define R_SERIAL1_CTRL__dma_err__WIDTH 1 +#define R_SERIAL1_CTRL__dma_err__stop 0 +#define R_SERIAL1_CTRL__dma_err__ignore 1 +#define R_SERIAL1_CTRL__rec_enable__BITNR 22 +#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL1_CTRL__rec_enable__disable 0 +#define R_SERIAL1_CTRL__rec_enable__enable 1 +#define R_SERIAL1_CTRL__rts___BITNR 21 +#define R_SERIAL1_CTRL__rts___WIDTH 1 +#define R_SERIAL1_CTRL__rts___active 0 +#define R_SERIAL1_CTRL__rts___inactive 1 +#define R_SERIAL1_CTRL__sampling__BITNR 20 +#define R_SERIAL1_CTRL__sampling__WIDTH 1 +#define R_SERIAL1_CTRL__sampling__middle 0 +#define R_SERIAL1_CTRL__sampling__majority 1 +#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL1_CTRL__rec_stick_par__normal 0 +#define R_SERIAL1_CTRL__rec_stick_par__stick 1 +#define R_SERIAL1_CTRL__rec_par__BITNR 18 +#define R_SERIAL1_CTRL__rec_par__WIDTH 1 +#define R_SERIAL1_CTRL__rec_par__even 0 +#define R_SERIAL1_CTRL__rec_par__odd 1 +#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL1_CTRL__rec_par_en__disable 0 +#define R_SERIAL1_CTRL__rec_par_en__enable 1 +#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL1_CTRL__txd__BITNR 15 +#define R_SERIAL1_CTRL__txd__WIDTH 1 +#define R_SERIAL1_CTRL__tr_enable__BITNR 14 +#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL1_CTRL__tr_enable__disable 0 +#define R_SERIAL1_CTRL__tr_enable__enable 1 +#define R_SERIAL1_CTRL__auto_cts__BITNR 13 +#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL1_CTRL__auto_cts__disabled 0 +#define R_SERIAL1_CTRL__auto_cts__active 1 +#define R_SERIAL1_CTRL__stop_bits__BITNR 12 +#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL1_CTRL__stop_bits__one_bit 0 +#define R_SERIAL1_CTRL__stop_bits__two_bits 1 +#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL1_CTRL__tr_stick_par__normal 0 +#define R_SERIAL1_CTRL__tr_stick_par__stick 1 +#define R_SERIAL1_CTRL__tr_par__BITNR 10 +#define R_SERIAL1_CTRL__tr_par__WIDTH 1 +#define R_SERIAL1_CTRL__tr_par__even 0 +#define R_SERIAL1_CTRL__tr_par__odd 1 +#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL1_CTRL__tr_par_en__disable 0 +#define R_SERIAL1_CTRL__tr_par_en__enable 1 +#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL1_CTRL__data_out__BITNR 0 +#define R_SERIAL1_CTRL__data_out__WIDTH 8 + +#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) +#define R_SERIAL1_BAUD__tr_baud__BITNR 4 +#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL1_BAUD__tr_baud__reserved 15 +#define R_SERIAL1_BAUD__rec_baud__BITNR 0 +#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL1_BAUD__rec_baud__reserved 15 + +#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) +#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL1_REC_CTRL__dma_err__stop 0 +#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL1_REC_CTRL__rts___BITNR 5 +#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL1_REC_CTRL__rts___active 0 +#define R_SERIAL1_REC_CTRL__rts___inactive 1 +#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL1_REC_CTRL__sampling__middle 0 +#define R_SERIAL1_REC_CTRL__sampling__majority 1 +#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_par__even 0 +#define R_SERIAL1_REC_CTRL__rec_par__odd 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) +#define R_SERIAL1_TR_CTRL__txd__BITNR 7 +#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL1_TR_CTRL__auto_cts__active 1 +#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_par__even 0 +#define R_SERIAL1_TR_CTRL__tr_par__odd 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) +#define R_SERIAL1_TR_DATA__data_out__BITNR 0 +#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) +#define R_SERIAL1_READ__xoff_detect__BITNR 15 +#define R_SERIAL1_READ__xoff_detect__WIDTH 1 +#define R_SERIAL1_READ__xoff_detect__no_xoff 0 +#define R_SERIAL1_READ__xoff_detect__xoff 1 +#define R_SERIAL1_READ__cts___BITNR 14 +#define R_SERIAL1_READ__cts___WIDTH 1 +#define R_SERIAL1_READ__cts___active 0 +#define R_SERIAL1_READ__cts___inactive 1 +#define R_SERIAL1_READ__tr_ready__BITNR 13 +#define R_SERIAL1_READ__tr_ready__WIDTH 1 +#define R_SERIAL1_READ__tr_ready__full 0 +#define R_SERIAL1_READ__tr_ready__ready 1 +#define R_SERIAL1_READ__rxd__BITNR 12 +#define R_SERIAL1_READ__rxd__WIDTH 1 +#define R_SERIAL1_READ__overrun__BITNR 11 +#define R_SERIAL1_READ__overrun__WIDTH 1 +#define R_SERIAL1_READ__overrun__no 0 +#define R_SERIAL1_READ__overrun__yes 1 +#define R_SERIAL1_READ__par_err__BITNR 10 +#define R_SERIAL1_READ__par_err__WIDTH 1 +#define R_SERIAL1_READ__par_err__no 0 +#define R_SERIAL1_READ__par_err__yes 1 +#define R_SERIAL1_READ__framing_err__BITNR 9 +#define R_SERIAL1_READ__framing_err__WIDTH 1 +#define R_SERIAL1_READ__framing_err__no 0 +#define R_SERIAL1_READ__framing_err__yes 1 +#define R_SERIAL1_READ__data_avail__BITNR 8 +#define R_SERIAL1_READ__data_avail__WIDTH 1 +#define R_SERIAL1_READ__data_avail__no 0 +#define R_SERIAL1_READ__data_avail__yes 1 +#define R_SERIAL1_READ__data_in__BITNR 0 +#define R_SERIAL1_READ__data_in__WIDTH 8 + +#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) +#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL1_STATUS__xoff_detect__xoff 1 +#define R_SERIAL1_STATUS__cts___BITNR 6 +#define R_SERIAL1_STATUS__cts___WIDTH 1 +#define R_SERIAL1_STATUS__cts___active 0 +#define R_SERIAL1_STATUS__cts___inactive 1 +#define R_SERIAL1_STATUS__tr_ready__BITNR 5 +#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL1_STATUS__tr_ready__full 0 +#define R_SERIAL1_STATUS__tr_ready__ready 1 +#define R_SERIAL1_STATUS__rxd__BITNR 4 +#define R_SERIAL1_STATUS__rxd__WIDTH 1 +#define R_SERIAL1_STATUS__overrun__BITNR 3 +#define R_SERIAL1_STATUS__overrun__WIDTH 1 +#define R_SERIAL1_STATUS__overrun__no 0 +#define R_SERIAL1_STATUS__overrun__yes 1 +#define R_SERIAL1_STATUS__par_err__BITNR 2 +#define R_SERIAL1_STATUS__par_err__WIDTH 1 +#define R_SERIAL1_STATUS__par_err__no 0 +#define R_SERIAL1_STATUS__par_err__yes 1 +#define R_SERIAL1_STATUS__framing_err__BITNR 1 +#define R_SERIAL1_STATUS__framing_err__WIDTH 1 +#define R_SERIAL1_STATUS__framing_err__no 0 +#define R_SERIAL1_STATUS__framing_err__yes 1 +#define R_SERIAL1_STATUS__data_avail__BITNR 0 +#define R_SERIAL1_STATUS__data_avail__WIDTH 1 +#define R_SERIAL1_STATUS__data_avail__no 0 +#define R_SERIAL1_STATUS__data_avail__yes 1 + +#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) +#define R_SERIAL1_REC_DATA__data_in__BITNR 0 +#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) +#define R_SERIAL1_XOFF__tx_stop__BITNR 9 +#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL1_XOFF__tx_stop__enable 0 +#define R_SERIAL1_XOFF__tx_stop__stop 1 +#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL1_XOFF__auto_xoff__disable 0 +#define R_SERIAL1_XOFF__auto_xoff__enable 1 +#define R_SERIAL1_XOFF__xoff_char__BITNR 0 +#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) +#define R_SERIAL2_CTRL__tr_baud__BITNR 28 +#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL2_CTRL__tr_baud__reserved 15 +#define R_SERIAL2_CTRL__rec_baud__BITNR 24 +#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL2_CTRL__rec_baud__reserved 15 +#define R_SERIAL2_CTRL__dma_err__BITNR 23 +#define R_SERIAL2_CTRL__dma_err__WIDTH 1 +#define R_SERIAL2_CTRL__dma_err__stop 0 +#define R_SERIAL2_CTRL__dma_err__ignore 1 +#define R_SERIAL2_CTRL__rec_enable__BITNR 22 +#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL2_CTRL__rec_enable__disable 0 +#define R_SERIAL2_CTRL__rec_enable__enable 1 +#define R_SERIAL2_CTRL__rts___BITNR 21 +#define R_SERIAL2_CTRL__rts___WIDTH 1 +#define R_SERIAL2_CTRL__rts___active 0 +#define R_SERIAL2_CTRL__rts___inactive 1 +#define R_SERIAL2_CTRL__sampling__BITNR 20 +#define R_SERIAL2_CTRL__sampling__WIDTH 1 +#define R_SERIAL2_CTRL__sampling__middle 0 +#define R_SERIAL2_CTRL__sampling__majority 1 +#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL2_CTRL__rec_stick_par__normal 0 +#define R_SERIAL2_CTRL__rec_stick_par__stick 1 +#define R_SERIAL2_CTRL__rec_par__BITNR 18 +#define R_SERIAL2_CTRL__rec_par__WIDTH 1 +#define R_SERIAL2_CTRL__rec_par__even 0 +#define R_SERIAL2_CTRL__rec_par__odd 1 +#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL2_CTRL__rec_par_en__disable 0 +#define R_SERIAL2_CTRL__rec_par_en__enable 1 +#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL2_CTRL__txd__BITNR 15 +#define R_SERIAL2_CTRL__txd__WIDTH 1 +#define R_SERIAL2_CTRL__tr_enable__BITNR 14 +#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL2_CTRL__tr_enable__disable 0 +#define R_SERIAL2_CTRL__tr_enable__enable 1 +#define R_SERIAL2_CTRL__auto_cts__BITNR 13 +#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL2_CTRL__auto_cts__disabled 0 +#define R_SERIAL2_CTRL__auto_cts__active 1 +#define R_SERIAL2_CTRL__stop_bits__BITNR 12 +#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL2_CTRL__stop_bits__one_bit 0 +#define R_SERIAL2_CTRL__stop_bits__two_bits 1 +#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL2_CTRL__tr_stick_par__normal 0 +#define R_SERIAL2_CTRL__tr_stick_par__stick 1 +#define R_SERIAL2_CTRL__tr_par__BITNR 10 +#define R_SERIAL2_CTRL__tr_par__WIDTH 1 +#define R_SERIAL2_CTRL__tr_par__even 0 +#define R_SERIAL2_CTRL__tr_par__odd 1 +#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL2_CTRL__tr_par_en__disable 0 +#define R_SERIAL2_CTRL__tr_par_en__enable 1 +#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL2_CTRL__data_out__BITNR 0 +#define R_SERIAL2_CTRL__data_out__WIDTH 8 + +#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) +#define R_SERIAL2_BAUD__tr_baud__BITNR 4 +#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL2_BAUD__tr_baud__reserved 15 +#define R_SERIAL2_BAUD__rec_baud__BITNR 0 +#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL2_BAUD__rec_baud__reserved 15 + +#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) +#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL2_REC_CTRL__dma_err__stop 0 +#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL2_REC_CTRL__rts___BITNR 5 +#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL2_REC_CTRL__rts___active 0 +#define R_SERIAL2_REC_CTRL__rts___inactive 1 +#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL2_REC_CTRL__sampling__middle 0 +#define R_SERIAL2_REC_CTRL__sampling__majority 1 +#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_par__even 0 +#define R_SERIAL2_REC_CTRL__rec_par__odd 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) +#define R_SERIAL2_TR_CTRL__txd__BITNR 7 +#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL2_TR_CTRL__auto_cts__active 1 +#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_par__even 0 +#define R_SERIAL2_TR_CTRL__tr_par__odd 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) +#define R_SERIAL2_TR_DATA__data_out__BITNR 0 +#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) +#define R_SERIAL2_READ__xoff_detect__BITNR 15 +#define R_SERIAL2_READ__xoff_detect__WIDTH 1 +#define R_SERIAL2_READ__xoff_detect__no_xoff 0 +#define R_SERIAL2_READ__xoff_detect__xoff 1 +#define R_SERIAL2_READ__cts___BITNR 14 +#define R_SERIAL2_READ__cts___WIDTH 1 +#define R_SERIAL2_READ__cts___active 0 +#define R_SERIAL2_READ__cts___inactive 1 +#define R_SERIAL2_READ__tr_ready__BITNR 13 +#define R_SERIAL2_READ__tr_ready__WIDTH 1 +#define R_SERIAL2_READ__tr_ready__full 0 +#define R_SERIAL2_READ__tr_ready__ready 1 +#define R_SERIAL2_READ__rxd__BITNR 12 +#define R_SERIAL2_READ__rxd__WIDTH 1 +#define R_SERIAL2_READ__overrun__BITNR 11 +#define R_SERIAL2_READ__overrun__WIDTH 1 +#define R_SERIAL2_READ__overrun__no 0 +#define R_SERIAL2_READ__overrun__yes 1 +#define R_SERIAL2_READ__par_err__BITNR 10 +#define R_SERIAL2_READ__par_err__WIDTH 1 +#define R_SERIAL2_READ__par_err__no 0 +#define R_SERIAL2_READ__par_err__yes 1 +#define R_SERIAL2_READ__framing_err__BITNR 9 +#define R_SERIAL2_READ__framing_err__WIDTH 1 +#define R_SERIAL2_READ__framing_err__no 0 +#define R_SERIAL2_READ__framing_err__yes 1 +#define R_SERIAL2_READ__data_avail__BITNR 8 +#define R_SERIAL2_READ__data_avail__WIDTH 1 +#define R_SERIAL2_READ__data_avail__no 0 +#define R_SERIAL2_READ__data_avail__yes 1 +#define R_SERIAL2_READ__data_in__BITNR 0 +#define R_SERIAL2_READ__data_in__WIDTH 8 + +#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) +#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL2_STATUS__xoff_detect__xoff 1 +#define R_SERIAL2_STATUS__cts___BITNR 6 +#define R_SERIAL2_STATUS__cts___WIDTH 1 +#define R_SERIAL2_STATUS__cts___active 0 +#define R_SERIAL2_STATUS__cts___inactive 1 +#define R_SERIAL2_STATUS__tr_ready__BITNR 5 +#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL2_STATUS__tr_ready__full 0 +#define R_SERIAL2_STATUS__tr_ready__ready 1 +#define R_SERIAL2_STATUS__rxd__BITNR 4 +#define R_SERIAL2_STATUS__rxd__WIDTH 1 +#define R_SERIAL2_STATUS__overrun__BITNR 3 +#define R_SERIAL2_STATUS__overrun__WIDTH 1 +#define R_SERIAL2_STATUS__overrun__no 0 +#define R_SERIAL2_STATUS__overrun__yes 1 +#define R_SERIAL2_STATUS__par_err__BITNR 2 +#define R_SERIAL2_STATUS__par_err__WIDTH 1 +#define R_SERIAL2_STATUS__par_err__no 0 +#define R_SERIAL2_STATUS__par_err__yes 1 +#define R_SERIAL2_STATUS__framing_err__BITNR 1 +#define R_SERIAL2_STATUS__framing_err__WIDTH 1 +#define R_SERIAL2_STATUS__framing_err__no 0 +#define R_SERIAL2_STATUS__framing_err__yes 1 +#define R_SERIAL2_STATUS__data_avail__BITNR 0 +#define R_SERIAL2_STATUS__data_avail__WIDTH 1 +#define R_SERIAL2_STATUS__data_avail__no 0 +#define R_SERIAL2_STATUS__data_avail__yes 1 + +#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) +#define R_SERIAL2_REC_DATA__data_in__BITNR 0 +#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) +#define R_SERIAL2_XOFF__tx_stop__BITNR 9 +#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL2_XOFF__tx_stop__enable 0 +#define R_SERIAL2_XOFF__tx_stop__stop 1 +#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL2_XOFF__auto_xoff__disable 0 +#define R_SERIAL2_XOFF__auto_xoff__enable 1 +#define R_SERIAL2_XOFF__xoff_char__BITNR 0 +#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) +#define R_SERIAL3_CTRL__tr_baud__BITNR 28 +#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL3_CTRL__tr_baud__reserved 15 +#define R_SERIAL3_CTRL__rec_baud__BITNR 24 +#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL3_CTRL__rec_baud__reserved 15 +#define R_SERIAL3_CTRL__dma_err__BITNR 23 +#define R_SERIAL3_CTRL__dma_err__WIDTH 1 +#define R_SERIAL3_CTRL__dma_err__stop 0 +#define R_SERIAL3_CTRL__dma_err__ignore 1 +#define R_SERIAL3_CTRL__rec_enable__BITNR 22 +#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL3_CTRL__rec_enable__disable 0 +#define R_SERIAL3_CTRL__rec_enable__enable 1 +#define R_SERIAL3_CTRL__rts___BITNR 21 +#define R_SERIAL3_CTRL__rts___WIDTH 1 +#define R_SERIAL3_CTRL__rts___active 0 +#define R_SERIAL3_CTRL__rts___inactive 1 +#define R_SERIAL3_CTRL__sampling__BITNR 20 +#define R_SERIAL3_CTRL__sampling__WIDTH 1 +#define R_SERIAL3_CTRL__sampling__middle 0 +#define R_SERIAL3_CTRL__sampling__majority 1 +#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL3_CTRL__rec_stick_par__normal 0 +#define R_SERIAL3_CTRL__rec_stick_par__stick 1 +#define R_SERIAL3_CTRL__rec_par__BITNR 18 +#define R_SERIAL3_CTRL__rec_par__WIDTH 1 +#define R_SERIAL3_CTRL__rec_par__even 0 +#define R_SERIAL3_CTRL__rec_par__odd 1 +#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL3_CTRL__rec_par_en__disable 0 +#define R_SERIAL3_CTRL__rec_par_en__enable 1 +#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL3_CTRL__txd__BITNR 15 +#define R_SERIAL3_CTRL__txd__WIDTH 1 +#define R_SERIAL3_CTRL__tr_enable__BITNR 14 +#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL3_CTRL__tr_enable__disable 0 +#define R_SERIAL3_CTRL__tr_enable__enable 1 +#define R_SERIAL3_CTRL__auto_cts__BITNR 13 +#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL3_CTRL__auto_cts__disabled 0 +#define R_SERIAL3_CTRL__auto_cts__active 1 +#define R_SERIAL3_CTRL__stop_bits__BITNR 12 +#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL3_CTRL__stop_bits__one_bit 0 +#define R_SERIAL3_CTRL__stop_bits__two_bits 1 +#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL3_CTRL__tr_stick_par__normal 0 +#define R_SERIAL3_CTRL__tr_stick_par__stick 1 +#define R_SERIAL3_CTRL__tr_par__BITNR 10 +#define R_SERIAL3_CTRL__tr_par__WIDTH 1 +#define R_SERIAL3_CTRL__tr_par__even 0 +#define R_SERIAL3_CTRL__tr_par__odd 1 +#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL3_CTRL__tr_par_en__disable 0 +#define R_SERIAL3_CTRL__tr_par_en__enable 1 +#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL3_CTRL__data_out__BITNR 0 +#define R_SERIAL3_CTRL__data_out__WIDTH 8 + +#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) +#define R_SERIAL3_BAUD__tr_baud__BITNR 4 +#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL3_BAUD__tr_baud__reserved 15 +#define R_SERIAL3_BAUD__rec_baud__BITNR 0 +#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL3_BAUD__rec_baud__reserved 15 + +#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) +#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL3_REC_CTRL__dma_err__stop 0 +#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL3_REC_CTRL__rts___BITNR 5 +#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL3_REC_CTRL__rts___active 0 +#define R_SERIAL3_REC_CTRL__rts___inactive 1 +#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL3_REC_CTRL__sampling__middle 0 +#define R_SERIAL3_REC_CTRL__sampling__majority 1 +#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_par__even 0 +#define R_SERIAL3_REC_CTRL__rec_par__odd 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) +#define R_SERIAL3_TR_CTRL__txd__BITNR 7 +#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL3_TR_CTRL__auto_cts__active 1 +#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_par__even 0 +#define R_SERIAL3_TR_CTRL__tr_par__odd 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) +#define R_SERIAL3_TR_DATA__data_out__BITNR 0 +#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) +#define R_SERIAL3_READ__xoff_detect__BITNR 15 +#define R_SERIAL3_READ__xoff_detect__WIDTH 1 +#define R_SERIAL3_READ__xoff_detect__no_xoff 0 +#define R_SERIAL3_READ__xoff_detect__xoff 1 +#define R_SERIAL3_READ__cts___BITNR 14 +#define R_SERIAL3_READ__cts___WIDTH 1 +#define R_SERIAL3_READ__cts___active 0 +#define R_SERIAL3_READ__cts___inactive 1 +#define R_SERIAL3_READ__tr_ready__BITNR 13 +#define R_SERIAL3_READ__tr_ready__WIDTH 1 +#define R_SERIAL3_READ__tr_ready__full 0 +#define R_SERIAL3_READ__tr_ready__ready 1 +#define R_SERIAL3_READ__rxd__BITNR 12 +#define R_SERIAL3_READ__rxd__WIDTH 1 +#define R_SERIAL3_READ__overrun__BITNR 11 +#define R_SERIAL3_READ__overrun__WIDTH 1 +#define R_SERIAL3_READ__overrun__no 0 +#define R_SERIAL3_READ__overrun__yes 1 +#define R_SERIAL3_READ__par_err__BITNR 10 +#define R_SERIAL3_READ__par_err__WIDTH 1 +#define R_SERIAL3_READ__par_err__no 0 +#define R_SERIAL3_READ__par_err__yes 1 +#define R_SERIAL3_READ__framing_err__BITNR 9 +#define R_SERIAL3_READ__framing_err__WIDTH 1 +#define R_SERIAL3_READ__framing_err__no 0 +#define R_SERIAL3_READ__framing_err__yes 1 +#define R_SERIAL3_READ__data_avail__BITNR 8 +#define R_SERIAL3_READ__data_avail__WIDTH 1 +#define R_SERIAL3_READ__data_avail__no 0 +#define R_SERIAL3_READ__data_avail__yes 1 +#define R_SERIAL3_READ__data_in__BITNR 0 +#define R_SERIAL3_READ__data_in__WIDTH 8 + +#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) +#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL3_STATUS__xoff_detect__xoff 1 +#define R_SERIAL3_STATUS__cts___BITNR 6 +#define R_SERIAL3_STATUS__cts___WIDTH 1 +#define R_SERIAL3_STATUS__cts___active 0 +#define R_SERIAL3_STATUS__cts___inactive 1 +#define R_SERIAL3_STATUS__tr_ready__BITNR 5 +#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL3_STATUS__tr_ready__full 0 +#define R_SERIAL3_STATUS__tr_ready__ready 1 +#define R_SERIAL3_STATUS__rxd__BITNR 4 +#define R_SERIAL3_STATUS__rxd__WIDTH 1 +#define R_SERIAL3_STATUS__overrun__BITNR 3 +#define R_SERIAL3_STATUS__overrun__WIDTH 1 +#define R_SERIAL3_STATUS__overrun__no 0 +#define R_SERIAL3_STATUS__overrun__yes 1 +#define R_SERIAL3_STATUS__par_err__BITNR 2 +#define R_SERIAL3_STATUS__par_err__WIDTH 1 +#define R_SERIAL3_STATUS__par_err__no 0 +#define R_SERIAL3_STATUS__par_err__yes 1 +#define R_SERIAL3_STATUS__framing_err__BITNR 1 +#define R_SERIAL3_STATUS__framing_err__WIDTH 1 +#define R_SERIAL3_STATUS__framing_err__no 0 +#define R_SERIAL3_STATUS__framing_err__yes 1 +#define R_SERIAL3_STATUS__data_avail__BITNR 0 +#define R_SERIAL3_STATUS__data_avail__WIDTH 1 +#define R_SERIAL3_STATUS__data_avail__no 0 +#define R_SERIAL3_STATUS__data_avail__yes 1 + +#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) +#define R_SERIAL3_REC_DATA__data_in__BITNR 0 +#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) +#define R_SERIAL3_XOFF__tx_stop__BITNR 9 +#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL3_XOFF__tx_stop__enable 0 +#define R_SERIAL3_XOFF__tx_stop__stop 1 +#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL3_XOFF__auto_xoff__disable 0 +#define R_SERIAL3_XOFF__auto_xoff__enable 1 +#define R_SERIAL3_XOFF__xoff_char__BITNR 0 +#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 + +#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) +#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 +#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 +#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 +#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 +#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 +#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 +#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 +#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 +#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 + +/* +!* Network interface registers +!*/ + +#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) +#define R_NETWORK_SA_0__ma0_low__BITNR 0 +#define R_NETWORK_SA_0__ma0_low__WIDTH 32 + +#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) +#define R_NETWORK_SA_1__ma1_low__BITNR 16 +#define R_NETWORK_SA_1__ma1_low__WIDTH 16 +#define R_NETWORK_SA_1__ma0_high__BITNR 0 +#define R_NETWORK_SA_1__ma0_high__WIDTH 16 + +#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) +#define R_NETWORK_SA_2__ma1_high__BITNR 0 +#define R_NETWORK_SA_2__ma1_high__WIDTH 32 + +#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) +#define R_NETWORK_GA_0__ga_low__BITNR 0 +#define R_NETWORK_GA_0__ga_low__WIDTH 32 + +#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) +#define R_NETWORK_GA_1__ga_high__BITNR 0 +#define R_NETWORK_GA_1__ga_high__WIDTH 32 + +#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) +#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 +#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 +#define R_NETWORK_REC_CONFIG__max_size__size1518 0 +#define R_NETWORK_REC_CONFIG__max_size__size1522 1 +#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 +#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 +#define R_NETWORK_REC_CONFIG__duplex__full 1 +#define R_NETWORK_REC_CONFIG__duplex__half 0 +#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 +#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 +#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 +#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 +#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 +#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 +#define R_NETWORK_REC_CONFIG__oversize__receive 1 +#define R_NETWORK_REC_CONFIG__oversize__discard 0 +#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 +#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 +#define R_NETWORK_REC_CONFIG__undersize__receive 1 +#define R_NETWORK_REC_CONFIG__undersize__discard 0 +#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 +#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 +#define R_NETWORK_REC_CONFIG__all_roots__receive 1 +#define R_NETWORK_REC_CONFIG__all_roots__discard 0 +#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 +#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 +#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 +#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 +#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 +#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 +#define R_NETWORK_REC_CONFIG__broadcast__receive 1 +#define R_NETWORK_REC_CONFIG__broadcast__discard 0 +#define R_NETWORK_REC_CONFIG__individual__BITNR 2 +#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 +#define R_NETWORK_REC_CONFIG__individual__receive 1 +#define R_NETWORK_REC_CONFIG__individual__discard 0 +#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 +#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 +#define R_NETWORK_REC_CONFIG__ma1__enable 1 +#define R_NETWORK_REC_CONFIG__ma1__disable 0 +#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 +#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 +#define R_NETWORK_REC_CONFIG__ma0__enable 1 +#define R_NETWORK_REC_CONFIG__ma0__disable 0 + +#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) +#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 +#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__loopback__on 1 +#define R_NETWORK_GEN_CONFIG__loopback__off 0 +#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 +#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 +#define R_NETWORK_GEN_CONFIG__frame__ether 0 +#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 +#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__vg__on 1 +#define R_NETWORK_GEN_CONFIG__vg__off 0 +#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 +#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 +#define R_NETWORK_GEN_CONFIG__phy__sni 0 +#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 +#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 +#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 +#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 +#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__enable__on 1 +#define R_NETWORK_GEN_CONFIG__enable__off 0 + +#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) +#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 +#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 +#define R_NETWORK_TR_CTRL__clr_error__clr 1 +#define R_NETWORK_TR_CTRL__clr_error__nop 0 +#define R_NETWORK_TR_CTRL__delay__BITNR 5 +#define R_NETWORK_TR_CTRL__delay__WIDTH 1 +#define R_NETWORK_TR_CTRL__delay__d2us 1 +#define R_NETWORK_TR_CTRL__delay__none 0 +#define R_NETWORK_TR_CTRL__cancel__BITNR 4 +#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 +#define R_NETWORK_TR_CTRL__cancel__do 1 +#define R_NETWORK_TR_CTRL__cancel__dont 0 +#define R_NETWORK_TR_CTRL__cd__BITNR 3 +#define R_NETWORK_TR_CTRL__cd__WIDTH 1 +#define R_NETWORK_TR_CTRL__cd__enable 0 +#define R_NETWORK_TR_CTRL__cd__disable 1 +#define R_NETWORK_TR_CTRL__cd__ack_col 0 +#define R_NETWORK_TR_CTRL__cd__ack_crs 1 +#define R_NETWORK_TR_CTRL__retry__BITNR 2 +#define R_NETWORK_TR_CTRL__retry__WIDTH 1 +#define R_NETWORK_TR_CTRL__retry__enable 0 +#define R_NETWORK_TR_CTRL__retry__disable 1 +#define R_NETWORK_TR_CTRL__pad__BITNR 1 +#define R_NETWORK_TR_CTRL__pad__WIDTH 1 +#define R_NETWORK_TR_CTRL__pad__enable 1 +#define R_NETWORK_TR_CTRL__pad__disable 0 +#define R_NETWORK_TR_CTRL__crc__BITNR 0 +#define R_NETWORK_TR_CTRL__crc__WIDTH 1 +#define R_NETWORK_TR_CTRL__crc__enable 0 +#define R_NETWORK_TR_CTRL__crc__disable 1 + +#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) +#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 +#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 +#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 +#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 +#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 +#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdoe__enable 1 +#define R_NETWORK_MGM_CTRL__mdoe__disable 0 +#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 +#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 + +#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) +#define R_NETWORK_STAT__rxd_pins__BITNR 4 +#define R_NETWORK_STAT__rxd_pins__WIDTH 4 +#define R_NETWORK_STAT__rxer__BITNR 3 +#define R_NETWORK_STAT__rxer__WIDTH 1 +#define R_NETWORK_STAT__underrun__BITNR 2 +#define R_NETWORK_STAT__underrun__WIDTH 1 +#define R_NETWORK_STAT__underrun__yes 1 +#define R_NETWORK_STAT__underrun__no 0 +#define R_NETWORK_STAT__exc_col__BITNR 1 +#define R_NETWORK_STAT__exc_col__WIDTH 1 +#define R_NETWORK_STAT__exc_col__yes 1 +#define R_NETWORK_STAT__exc_col__no 0 +#define R_NETWORK_STAT__mdio__BITNR 0 +#define R_NETWORK_STAT__mdio__WIDTH 1 + +#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) +#define R_REC_COUNTERS__congestion__BITNR 24 +#define R_REC_COUNTERS__congestion__WIDTH 8 +#define R_REC_COUNTERS__oversize__BITNR 16 +#define R_REC_COUNTERS__oversize__WIDTH 8 +#define R_REC_COUNTERS__alignment_error__BITNR 8 +#define R_REC_COUNTERS__alignment_error__WIDTH 8 +#define R_REC_COUNTERS__crc_error__BITNR 0 +#define R_REC_COUNTERS__crc_error__WIDTH 8 + +#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) +#define R_TR_COUNTERS__deferred__BITNR 24 +#define R_TR_COUNTERS__deferred__WIDTH 8 +#define R_TR_COUNTERS__late_col__BITNR 16 +#define R_TR_COUNTERS__late_col__WIDTH 8 +#define R_TR_COUNTERS__multiple_col__BITNR 8 +#define R_TR_COUNTERS__multiple_col__WIDTH 8 +#define R_TR_COUNTERS__single_col__BITNR 0 +#define R_TR_COUNTERS__single_col__WIDTH 8 + +#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) +#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 +#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 +#define R_PHY_COUNTERS__carrier_loss__BITNR 0 +#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 + +/* +!* Parallel printer port registers +!*/ + +#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 +#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 +#define R_PAR0_CTRL_DATA__peri_int__ack 1 +#define R_PAR0_CTRL_DATA__peri_int__nop 0 +#define R_PAR0_CTRL_DATA__oe__BITNR 20 +#define R_PAR0_CTRL_DATA__oe__WIDTH 1 +#define R_PAR0_CTRL_DATA__oe__enable 1 +#define R_PAR0_CTRL_DATA__oe__disable 0 +#define R_PAR0_CTRL_DATA__seli__BITNR 19 +#define R_PAR0_CTRL_DATA__seli__WIDTH 1 +#define R_PAR0_CTRL_DATA__seli__active 1 +#define R_PAR0_CTRL_DATA__seli__inactive 0 +#define R_PAR0_CTRL_DATA__autofd__BITNR 18 +#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 +#define R_PAR0_CTRL_DATA__autofd__active 1 +#define R_PAR0_CTRL_DATA__autofd__inactive 0 +#define R_PAR0_CTRL_DATA__strb__BITNR 17 +#define R_PAR0_CTRL_DATA__strb__WIDTH 1 +#define R_PAR0_CTRL_DATA__strb__active 1 +#define R_PAR0_CTRL_DATA__strb__inactive 0 +#define R_PAR0_CTRL_DATA__init__BITNR 16 +#define R_PAR0_CTRL_DATA__init__WIDTH 1 +#define R_PAR0_CTRL_DATA__init__active 1 +#define R_PAR0_CTRL_DATA__init__inactive 0 +#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 +#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 +#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 +#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 +#define R_PAR0_CTRL_DATA__data__BITNR 0 +#define R_PAR0_CTRL_DATA__data__WIDTH 8 + +#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) +#define R_PAR0_CTRL__ctrl__BITNR 0 +#define R_PAR0_CTRL__ctrl__WIDTH 5 + +#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) +#define R_PAR0_STATUS_DATA__mode__BITNR 29 +#define R_PAR0_STATUS_DATA__mode__WIDTH 3 +#define R_PAR0_STATUS_DATA__mode__manual 0 +#define R_PAR0_STATUS_DATA__mode__centronics 1 +#define R_PAR0_STATUS_DATA__mode__fastbyte 2 +#define R_PAR0_STATUS_DATA__mode__nibble 3 +#define R_PAR0_STATUS_DATA__mode__byte 4 +#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 +#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 +#define R_PAR0_STATUS_DATA__mode__off 7 +#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 +#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 +#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 +#define R_PAR0_STATUS_DATA__mode__epp_rd 0 +#define R_PAR0_STATUS_DATA__perr__BITNR 28 +#define R_PAR0_STATUS_DATA__perr__WIDTH 1 +#define R_PAR0_STATUS_DATA__perr__active 1 +#define R_PAR0_STATUS_DATA__perr__inactive 0 +#define R_PAR0_STATUS_DATA__ack__BITNR 27 +#define R_PAR0_STATUS_DATA__ack__WIDTH 1 +#define R_PAR0_STATUS_DATA__ack__active 0 +#define R_PAR0_STATUS_DATA__ack__inactive 1 +#define R_PAR0_STATUS_DATA__busy__BITNR 26 +#define R_PAR0_STATUS_DATA__busy__WIDTH 1 +#define R_PAR0_STATUS_DATA__busy__active 1 +#define R_PAR0_STATUS_DATA__busy__inactive 0 +#define R_PAR0_STATUS_DATA__fault__BITNR 25 +#define R_PAR0_STATUS_DATA__fault__WIDTH 1 +#define R_PAR0_STATUS_DATA__fault__active 0 +#define R_PAR0_STATUS_DATA__fault__inactive 1 +#define R_PAR0_STATUS_DATA__sel__BITNR 24 +#define R_PAR0_STATUS_DATA__sel__WIDTH 1 +#define R_PAR0_STATUS_DATA__sel__active 1 +#define R_PAR0_STATUS_DATA__sel__inactive 0 +#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 +#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 +#define R_PAR0_STATUS_DATA__ext_mode__enable 1 +#define R_PAR0_STATUS_DATA__ext_mode__disable 0 +#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 +#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 +#define R_PAR0_STATUS_DATA__ecp_16__active 1 +#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 +#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 +#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 +#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 +#define R_PAR0_STATUS_DATA__dav__BITNR 16 +#define R_PAR0_STATUS_DATA__dav__WIDTH 1 +#define R_PAR0_STATUS_DATA__dav__data 1 +#define R_PAR0_STATUS_DATA__dav__nodata 0 +#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 +#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 +#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 +#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 +#define R_PAR0_STATUS_DATA__data__BITNR 0 +#define R_PAR0_STATUS_DATA__data__WIDTH 8 + +#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) +#define R_PAR0_STATUS__mode__BITNR 13 +#define R_PAR0_STATUS__mode__WIDTH 3 +#define R_PAR0_STATUS__mode__manual 0 +#define R_PAR0_STATUS__mode__centronics 1 +#define R_PAR0_STATUS__mode__fastbyte 2 +#define R_PAR0_STATUS__mode__nibble 3 +#define R_PAR0_STATUS__mode__byte 4 +#define R_PAR0_STATUS__mode__ecp_fwd 5 +#define R_PAR0_STATUS__mode__ecp_rev 6 +#define R_PAR0_STATUS__mode__off 7 +#define R_PAR0_STATUS__mode__epp_wr1 5 +#define R_PAR0_STATUS__mode__epp_wr2 6 +#define R_PAR0_STATUS__mode__epp_wr3 7 +#define R_PAR0_STATUS__mode__epp_rd 0 +#define R_PAR0_STATUS__perr__BITNR 12 +#define R_PAR0_STATUS__perr__WIDTH 1 +#define R_PAR0_STATUS__perr__active 1 +#define R_PAR0_STATUS__perr__inactive 0 +#define R_PAR0_STATUS__ack__BITNR 11 +#define R_PAR0_STATUS__ack__WIDTH 1 +#define R_PAR0_STATUS__ack__active 0 +#define R_PAR0_STATUS__ack__inactive 1 +#define R_PAR0_STATUS__busy__BITNR 10 +#define R_PAR0_STATUS__busy__WIDTH 1 +#define R_PAR0_STATUS__busy__active 1 +#define R_PAR0_STATUS__busy__inactive 0 +#define R_PAR0_STATUS__fault__BITNR 9 +#define R_PAR0_STATUS__fault__WIDTH 1 +#define R_PAR0_STATUS__fault__active 0 +#define R_PAR0_STATUS__fault__inactive 1 +#define R_PAR0_STATUS__sel__BITNR 8 +#define R_PAR0_STATUS__sel__WIDTH 1 +#define R_PAR0_STATUS__sel__active 1 +#define R_PAR0_STATUS__sel__inactive 0 +#define R_PAR0_STATUS__ext_mode__BITNR 7 +#define R_PAR0_STATUS__ext_mode__WIDTH 1 +#define R_PAR0_STATUS__ext_mode__enable 1 +#define R_PAR0_STATUS__ext_mode__disable 0 +#define R_PAR0_STATUS__ecp_16__BITNR 6 +#define R_PAR0_STATUS__ecp_16__WIDTH 1 +#define R_PAR0_STATUS__ecp_16__active 1 +#define R_PAR0_STATUS__ecp_16__inactive 0 +#define R_PAR0_STATUS__tr_rdy__BITNR 1 +#define R_PAR0_STATUS__tr_rdy__WIDTH 1 +#define R_PAR0_STATUS__tr_rdy__ready 1 +#define R_PAR0_STATUS__tr_rdy__busy 0 +#define R_PAR0_STATUS__dav__BITNR 0 +#define R_PAR0_STATUS__dav__WIDTH 1 +#define R_PAR0_STATUS__dav__data 1 +#define R_PAR0_STATUS__dav__nodata 0 + +#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) +#define R_PAR_ECP16_DATA__data__BITNR 0 +#define R_PAR_ECP16_DATA__data__WIDTH 16 + +#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) +#define R_PAR0_CONFIG__ioe__BITNR 25 +#define R_PAR0_CONFIG__ioe__WIDTH 1 +#define R_PAR0_CONFIG__ioe__inv 1 +#define R_PAR0_CONFIG__ioe__noninv 0 +#define R_PAR0_CONFIG__iseli__BITNR 24 +#define R_PAR0_CONFIG__iseli__WIDTH 1 +#define R_PAR0_CONFIG__iseli__inv 1 +#define R_PAR0_CONFIG__iseli__noninv 0 +#define R_PAR0_CONFIG__iautofd__BITNR 23 +#define R_PAR0_CONFIG__iautofd__WIDTH 1 +#define R_PAR0_CONFIG__iautofd__inv 1 +#define R_PAR0_CONFIG__iautofd__noninv 0 +#define R_PAR0_CONFIG__istrb__BITNR 22 +#define R_PAR0_CONFIG__istrb__WIDTH 1 +#define R_PAR0_CONFIG__istrb__inv 1 +#define R_PAR0_CONFIG__istrb__noninv 0 +#define R_PAR0_CONFIG__iinit__BITNR 21 +#define R_PAR0_CONFIG__iinit__WIDTH 1 +#define R_PAR0_CONFIG__iinit__inv 1 +#define R_PAR0_CONFIG__iinit__noninv 0 +#define R_PAR0_CONFIG__iperr__BITNR 20 +#define R_PAR0_CONFIG__iperr__WIDTH 1 +#define R_PAR0_CONFIG__iperr__inv 1 +#define R_PAR0_CONFIG__iperr__noninv 0 +#define R_PAR0_CONFIG__iack__BITNR 19 +#define R_PAR0_CONFIG__iack__WIDTH 1 +#define R_PAR0_CONFIG__iack__inv 1 +#define R_PAR0_CONFIG__iack__noninv 0 +#define R_PAR0_CONFIG__ibusy__BITNR 18 +#define R_PAR0_CONFIG__ibusy__WIDTH 1 +#define R_PAR0_CONFIG__ibusy__inv 1 +#define R_PAR0_CONFIG__ibusy__noninv 0 +#define R_PAR0_CONFIG__ifault__BITNR 17 +#define R_PAR0_CONFIG__ifault__WIDTH 1 +#define R_PAR0_CONFIG__ifault__inv 1 +#define R_PAR0_CONFIG__ifault__noninv 0 +#define R_PAR0_CONFIG__isel__BITNR 16 +#define R_PAR0_CONFIG__isel__WIDTH 1 +#define R_PAR0_CONFIG__isel__inv 1 +#define R_PAR0_CONFIG__isel__noninv 0 +#define R_PAR0_CONFIG__ext_mode__BITNR 11 +#define R_PAR0_CONFIG__ext_mode__WIDTH 1 +#define R_PAR0_CONFIG__ext_mode__enable 1 +#define R_PAR0_CONFIG__ext_mode__disable 0 +#define R_PAR0_CONFIG__wide__BITNR 10 +#define R_PAR0_CONFIG__wide__WIDTH 1 +#define R_PAR0_CONFIG__wide__enable 1 +#define R_PAR0_CONFIG__wide__disable 0 +#define R_PAR0_CONFIG__dma__BITNR 9 +#define R_PAR0_CONFIG__dma__WIDTH 1 +#define R_PAR0_CONFIG__dma__enable 1 +#define R_PAR0_CONFIG__dma__disable 0 +#define R_PAR0_CONFIG__rle_in__BITNR 8 +#define R_PAR0_CONFIG__rle_in__WIDTH 1 +#define R_PAR0_CONFIG__rle_in__enable 1 +#define R_PAR0_CONFIG__rle_in__disable 0 +#define R_PAR0_CONFIG__rle_out__BITNR 7 +#define R_PAR0_CONFIG__rle_out__WIDTH 1 +#define R_PAR0_CONFIG__rle_out__enable 1 +#define R_PAR0_CONFIG__rle_out__disable 0 +#define R_PAR0_CONFIG__enable__BITNR 6 +#define R_PAR0_CONFIG__enable__WIDTH 1 +#define R_PAR0_CONFIG__enable__on 1 +#define R_PAR0_CONFIG__enable__reset 0 +#define R_PAR0_CONFIG__force__BITNR 5 +#define R_PAR0_CONFIG__force__WIDTH 1 +#define R_PAR0_CONFIG__force__on 1 +#define R_PAR0_CONFIG__force__off 0 +#define R_PAR0_CONFIG__ign_ack__BITNR 4 +#define R_PAR0_CONFIG__ign_ack__WIDTH 1 +#define R_PAR0_CONFIG__ign_ack__ignore 1 +#define R_PAR0_CONFIG__ign_ack__wait 0 +#define R_PAR0_CONFIG__oe_ack__BITNR 3 +#define R_PAR0_CONFIG__oe_ack__WIDTH 1 +#define R_PAR0_CONFIG__oe_ack__wait_oe 1 +#define R_PAR0_CONFIG__oe_ack__dont_wait 0 +#define R_PAR0_CONFIG__oe_ack__epp_addr 1 +#define R_PAR0_CONFIG__oe_ack__epp_data 0 +#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 +#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 +#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 +#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 +#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 +#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 +#define R_PAR0_CONFIG__mode__BITNR 0 +#define R_PAR0_CONFIG__mode__WIDTH 3 +#define R_PAR0_CONFIG__mode__manual 0 +#define R_PAR0_CONFIG__mode__centronics 1 +#define R_PAR0_CONFIG__mode__fastbyte 2 +#define R_PAR0_CONFIG__mode__nibble 3 +#define R_PAR0_CONFIG__mode__byte 4 +#define R_PAR0_CONFIG__mode__ecp_fwd 5 +#define R_PAR0_CONFIG__mode__ecp_rev 6 +#define R_PAR0_CONFIG__mode__off 7 +#define R_PAR0_CONFIG__mode__epp_wr1 5 +#define R_PAR0_CONFIG__mode__epp_wr2 6 +#define R_PAR0_CONFIG__mode__epp_wr3 7 +#define R_PAR0_CONFIG__mode__epp_rd 0 + +#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) +#define R_PAR0_DELAY__fine_hold__BITNR 21 +#define R_PAR0_DELAY__fine_hold__WIDTH 3 +#define R_PAR0_DELAY__hold__BITNR 16 +#define R_PAR0_DELAY__hold__WIDTH 5 +#define R_PAR0_DELAY__fine_strb__BITNR 13 +#define R_PAR0_DELAY__fine_strb__WIDTH 3 +#define R_PAR0_DELAY__strobe__BITNR 8 +#define R_PAR0_DELAY__strobe__WIDTH 5 +#define R_PAR0_DELAY__fine_setup__BITNR 5 +#define R_PAR0_DELAY__fine_setup__WIDTH 3 +#define R_PAR0_DELAY__setup__BITNR 0 +#define R_PAR0_DELAY__setup__WIDTH 5 + +#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) +#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 +#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 +#define R_PAR1_CTRL_DATA__peri_int__ack 1 +#define R_PAR1_CTRL_DATA__peri_int__nop 0 +#define R_PAR1_CTRL_DATA__oe__BITNR 20 +#define R_PAR1_CTRL_DATA__oe__WIDTH 1 +#define R_PAR1_CTRL_DATA__oe__enable 1 +#define R_PAR1_CTRL_DATA__oe__disable 0 +#define R_PAR1_CTRL_DATA__seli__BITNR 19 +#define R_PAR1_CTRL_DATA__seli__WIDTH 1 +#define R_PAR1_CTRL_DATA__seli__active 1 +#define R_PAR1_CTRL_DATA__seli__inactive 0 +#define R_PAR1_CTRL_DATA__autofd__BITNR 18 +#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 +#define R_PAR1_CTRL_DATA__autofd__active 1 +#define R_PAR1_CTRL_DATA__autofd__inactive 0 +#define R_PAR1_CTRL_DATA__strb__BITNR 17 +#define R_PAR1_CTRL_DATA__strb__WIDTH 1 +#define R_PAR1_CTRL_DATA__strb__active 1 +#define R_PAR1_CTRL_DATA__strb__inactive 0 +#define R_PAR1_CTRL_DATA__init__BITNR 16 +#define R_PAR1_CTRL_DATA__init__WIDTH 1 +#define R_PAR1_CTRL_DATA__init__active 1 +#define R_PAR1_CTRL_DATA__init__inactive 0 +#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 +#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 +#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 +#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 +#define R_PAR1_CTRL_DATA__data__BITNR 0 +#define R_PAR1_CTRL_DATA__data__WIDTH 8 + +#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) +#define R_PAR1_CTRL__ctrl__BITNR 0 +#define R_PAR1_CTRL__ctrl__WIDTH 5 + +#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) +#define R_PAR1_STATUS_DATA__mode__BITNR 29 +#define R_PAR1_STATUS_DATA__mode__WIDTH 3 +#define R_PAR1_STATUS_DATA__mode__manual 0 +#define R_PAR1_STATUS_DATA__mode__centronics 1 +#define R_PAR1_STATUS_DATA__mode__fastbyte 2 +#define R_PAR1_STATUS_DATA__mode__nibble 3 +#define R_PAR1_STATUS_DATA__mode__byte 4 +#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 +#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 +#define R_PAR1_STATUS_DATA__mode__off 7 +#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 +#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 +#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 +#define R_PAR1_STATUS_DATA__mode__epp_rd 0 +#define R_PAR1_STATUS_DATA__perr__BITNR 28 +#define R_PAR1_STATUS_DATA__perr__WIDTH 1 +#define R_PAR1_STATUS_DATA__perr__active 1 +#define R_PAR1_STATUS_DATA__perr__inactive 0 +#define R_PAR1_STATUS_DATA__ack__BITNR 27 +#define R_PAR1_STATUS_DATA__ack__WIDTH 1 +#define R_PAR1_STATUS_DATA__ack__active 0 +#define R_PAR1_STATUS_DATA__ack__inactive 1 +#define R_PAR1_STATUS_DATA__busy__BITNR 26 +#define R_PAR1_STATUS_DATA__busy__WIDTH 1 +#define R_PAR1_STATUS_DATA__busy__active 1 +#define R_PAR1_STATUS_DATA__busy__inactive 0 +#define R_PAR1_STATUS_DATA__fault__BITNR 25 +#define R_PAR1_STATUS_DATA__fault__WIDTH 1 +#define R_PAR1_STATUS_DATA__fault__active 0 +#define R_PAR1_STATUS_DATA__fault__inactive 1 +#define R_PAR1_STATUS_DATA__sel__BITNR 24 +#define R_PAR1_STATUS_DATA__sel__WIDTH 1 +#define R_PAR1_STATUS_DATA__sel__active 1 +#define R_PAR1_STATUS_DATA__sel__inactive 0 +#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 +#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 +#define R_PAR1_STATUS_DATA__ext_mode__enable 1 +#define R_PAR1_STATUS_DATA__ext_mode__disable 0 +#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 +#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 +#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 +#define R_PAR1_STATUS_DATA__dav__BITNR 16 +#define R_PAR1_STATUS_DATA__dav__WIDTH 1 +#define R_PAR1_STATUS_DATA__dav__data 1 +#define R_PAR1_STATUS_DATA__dav__nodata 0 +#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 +#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 +#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 +#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 +#define R_PAR1_STATUS_DATA__data__BITNR 0 +#define R_PAR1_STATUS_DATA__data__WIDTH 8 + +#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) +#define R_PAR1_STATUS__mode__BITNR 13 +#define R_PAR1_STATUS__mode__WIDTH 3 +#define R_PAR1_STATUS__mode__manual 0 +#define R_PAR1_STATUS__mode__centronics 1 +#define R_PAR1_STATUS__mode__fastbyte 2 +#define R_PAR1_STATUS__mode__nibble 3 +#define R_PAR1_STATUS__mode__byte 4 +#define R_PAR1_STATUS__mode__ecp_fwd 5 +#define R_PAR1_STATUS__mode__ecp_rev 6 +#define R_PAR1_STATUS__mode__off 7 +#define R_PAR1_STATUS__mode__epp_wr1 5 +#define R_PAR1_STATUS__mode__epp_wr2 6 +#define R_PAR1_STATUS__mode__epp_wr3 7 +#define R_PAR1_STATUS__mode__epp_rd 0 +#define R_PAR1_STATUS__perr__BITNR 12 +#define R_PAR1_STATUS__perr__WIDTH 1 +#define R_PAR1_STATUS__perr__active 1 +#define R_PAR1_STATUS__perr__inactive 0 +#define R_PAR1_STATUS__ack__BITNR 11 +#define R_PAR1_STATUS__ack__WIDTH 1 +#define R_PAR1_STATUS__ack__active 0 +#define R_PAR1_STATUS__ack__inactive 1 +#define R_PAR1_STATUS__busy__BITNR 10 +#define R_PAR1_STATUS__busy__WIDTH 1 +#define R_PAR1_STATUS__busy__active 1 +#define R_PAR1_STATUS__busy__inactive 0 +#define R_PAR1_STATUS__fault__BITNR 9 +#define R_PAR1_STATUS__fault__WIDTH 1 +#define R_PAR1_STATUS__fault__active 0 +#define R_PAR1_STATUS__fault__inactive 1 +#define R_PAR1_STATUS__sel__BITNR 8 +#define R_PAR1_STATUS__sel__WIDTH 1 +#define R_PAR1_STATUS__sel__active 1 +#define R_PAR1_STATUS__sel__inactive 0 +#define R_PAR1_STATUS__ext_mode__BITNR 7 +#define R_PAR1_STATUS__ext_mode__WIDTH 1 +#define R_PAR1_STATUS__ext_mode__enable 1 +#define R_PAR1_STATUS__ext_mode__disable 0 +#define R_PAR1_STATUS__tr_rdy__BITNR 1 +#define R_PAR1_STATUS__tr_rdy__WIDTH 1 +#define R_PAR1_STATUS__tr_rdy__ready 1 +#define R_PAR1_STATUS__tr_rdy__busy 0 +#define R_PAR1_STATUS__dav__BITNR 0 +#define R_PAR1_STATUS__dav__WIDTH 1 +#define R_PAR1_STATUS__dav__data 1 +#define R_PAR1_STATUS__dav__nodata 0 + +#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) +#define R_PAR1_CONFIG__ioe__BITNR 25 +#define R_PAR1_CONFIG__ioe__WIDTH 1 +#define R_PAR1_CONFIG__ioe__inv 1 +#define R_PAR1_CONFIG__ioe__noninv 0 +#define R_PAR1_CONFIG__iseli__BITNR 24 +#define R_PAR1_CONFIG__iseli__WIDTH 1 +#define R_PAR1_CONFIG__iseli__inv 1 +#define R_PAR1_CONFIG__iseli__noninv 0 +#define R_PAR1_CONFIG__iautofd__BITNR 23 +#define R_PAR1_CONFIG__iautofd__WIDTH 1 +#define R_PAR1_CONFIG__iautofd__inv 1 +#define R_PAR1_CONFIG__iautofd__noninv 0 +#define R_PAR1_CONFIG__istrb__BITNR 22 +#define R_PAR1_CONFIG__istrb__WIDTH 1 +#define R_PAR1_CONFIG__istrb__inv 1 +#define R_PAR1_CONFIG__istrb__noninv 0 +#define R_PAR1_CONFIG__iinit__BITNR 21 +#define R_PAR1_CONFIG__iinit__WIDTH 1 +#define R_PAR1_CONFIG__iinit__inv 1 +#define R_PAR1_CONFIG__iinit__noninv 0 +#define R_PAR1_CONFIG__iperr__BITNR 20 +#define R_PAR1_CONFIG__iperr__WIDTH 1 +#define R_PAR1_CONFIG__iperr__inv 1 +#define R_PAR1_CONFIG__iperr__noninv 0 +#define R_PAR1_CONFIG__iack__BITNR 19 +#define R_PAR1_CONFIG__iack__WIDTH 1 +#define R_PAR1_CONFIG__iack__inv 1 +#define R_PAR1_CONFIG__iack__noninv 0 +#define R_PAR1_CONFIG__ibusy__BITNR 18 +#define R_PAR1_CONFIG__ibusy__WIDTH 1 +#define R_PAR1_CONFIG__ibusy__inv 1 +#define R_PAR1_CONFIG__ibusy__noninv 0 +#define R_PAR1_CONFIG__ifault__BITNR 17 +#define R_PAR1_CONFIG__ifault__WIDTH 1 +#define R_PAR1_CONFIG__ifault__inv 1 +#define R_PAR1_CONFIG__ifault__noninv 0 +#define R_PAR1_CONFIG__isel__BITNR 16 +#define R_PAR1_CONFIG__isel__WIDTH 1 +#define R_PAR1_CONFIG__isel__inv 1 +#define R_PAR1_CONFIG__isel__noninv 0 +#define R_PAR1_CONFIG__ext_mode__BITNR 11 +#define R_PAR1_CONFIG__ext_mode__WIDTH 1 +#define R_PAR1_CONFIG__ext_mode__enable 1 +#define R_PAR1_CONFIG__ext_mode__disable 0 +#define R_PAR1_CONFIG__dma__BITNR 9 +#define R_PAR1_CONFIG__dma__WIDTH 1 +#define R_PAR1_CONFIG__dma__enable 1 +#define R_PAR1_CONFIG__dma__disable 0 +#define R_PAR1_CONFIG__rle_in__BITNR 8 +#define R_PAR1_CONFIG__rle_in__WIDTH 1 +#define R_PAR1_CONFIG__rle_in__enable 1 +#define R_PAR1_CONFIG__rle_in__disable 0 +#define R_PAR1_CONFIG__rle_out__BITNR 7 +#define R_PAR1_CONFIG__rle_out__WIDTH 1 +#define R_PAR1_CONFIG__rle_out__enable 1 +#define R_PAR1_CONFIG__rle_out__disable 0 +#define R_PAR1_CONFIG__enable__BITNR 6 +#define R_PAR1_CONFIG__enable__WIDTH 1 +#define R_PAR1_CONFIG__enable__on 1 +#define R_PAR1_CONFIG__enable__reset 0 +#define R_PAR1_CONFIG__force__BITNR 5 +#define R_PAR1_CONFIG__force__WIDTH 1 +#define R_PAR1_CONFIG__force__on 1 +#define R_PAR1_CONFIG__force__off 0 +#define R_PAR1_CONFIG__ign_ack__BITNR 4 +#define R_PAR1_CONFIG__ign_ack__WIDTH 1 +#define R_PAR1_CONFIG__ign_ack__ignore 1 +#define R_PAR1_CONFIG__ign_ack__wait 0 +#define R_PAR1_CONFIG__oe_ack__BITNR 3 +#define R_PAR1_CONFIG__oe_ack__WIDTH 1 +#define R_PAR1_CONFIG__oe_ack__wait_oe 1 +#define R_PAR1_CONFIG__oe_ack__dont_wait 0 +#define R_PAR1_CONFIG__oe_ack__epp_addr 1 +#define R_PAR1_CONFIG__oe_ack__epp_data 0 +#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 +#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 +#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 +#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 +#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 +#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 +#define R_PAR1_CONFIG__mode__BITNR 0 +#define R_PAR1_CONFIG__mode__WIDTH 3 +#define R_PAR1_CONFIG__mode__manual 0 +#define R_PAR1_CONFIG__mode__centronics 1 +#define R_PAR1_CONFIG__mode__fastbyte 2 +#define R_PAR1_CONFIG__mode__nibble 3 +#define R_PAR1_CONFIG__mode__byte 4 +#define R_PAR1_CONFIG__mode__ecp_fwd 5 +#define R_PAR1_CONFIG__mode__ecp_rev 6 +#define R_PAR1_CONFIG__mode__off 7 +#define R_PAR1_CONFIG__mode__epp_wr1 5 +#define R_PAR1_CONFIG__mode__epp_wr2 6 +#define R_PAR1_CONFIG__mode__epp_wr3 7 +#define R_PAR1_CONFIG__mode__epp_rd 0 + +#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) +#define R_PAR1_DELAY__fine_hold__BITNR 21 +#define R_PAR1_DELAY__fine_hold__WIDTH 3 +#define R_PAR1_DELAY__hold__BITNR 16 +#define R_PAR1_DELAY__hold__WIDTH 5 +#define R_PAR1_DELAY__fine_strb__BITNR 13 +#define R_PAR1_DELAY__fine_strb__WIDTH 3 +#define R_PAR1_DELAY__strobe__BITNR 8 +#define R_PAR1_DELAY__strobe__WIDTH 5 +#define R_PAR1_DELAY__fine_setup__BITNR 5 +#define R_PAR1_DELAY__fine_setup__WIDTH 3 +#define R_PAR1_DELAY__setup__BITNR 0 +#define R_PAR1_DELAY__setup__WIDTH 5 + +/* +!* ATA interface registers +!*/ + +#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_ATA_CTRL_DATA__sel__BITNR 30 +#define R_ATA_CTRL_DATA__sel__WIDTH 2 +#define R_ATA_CTRL_DATA__cs1__BITNR 29 +#define R_ATA_CTRL_DATA__cs1__WIDTH 1 +#define R_ATA_CTRL_DATA__cs1__active 1 +#define R_ATA_CTRL_DATA__cs1__inactive 0 +#define R_ATA_CTRL_DATA__cs0__BITNR 28 +#define R_ATA_CTRL_DATA__cs0__WIDTH 1 +#define R_ATA_CTRL_DATA__cs0__active 1 +#define R_ATA_CTRL_DATA__cs0__inactive 0 +#define R_ATA_CTRL_DATA__addr__BITNR 25 +#define R_ATA_CTRL_DATA__addr__WIDTH 3 +#define R_ATA_CTRL_DATA__rw__BITNR 24 +#define R_ATA_CTRL_DATA__rw__WIDTH 1 +#define R_ATA_CTRL_DATA__rw__read 1 +#define R_ATA_CTRL_DATA__rw__write 0 +#define R_ATA_CTRL_DATA__src_dst__BITNR 23 +#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 +#define R_ATA_CTRL_DATA__src_dst__dma 1 +#define R_ATA_CTRL_DATA__src_dst__register 0 +#define R_ATA_CTRL_DATA__handsh__BITNR 22 +#define R_ATA_CTRL_DATA__handsh__WIDTH 1 +#define R_ATA_CTRL_DATA__handsh__dma 1 +#define R_ATA_CTRL_DATA__handsh__pio 0 +#define R_ATA_CTRL_DATA__multi__BITNR 21 +#define R_ATA_CTRL_DATA__multi__WIDTH 1 +#define R_ATA_CTRL_DATA__multi__on 1 +#define R_ATA_CTRL_DATA__multi__off 0 +#define R_ATA_CTRL_DATA__dma_size__BITNR 20 +#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 +#define R_ATA_CTRL_DATA__dma_size__byte 1 +#define R_ATA_CTRL_DATA__dma_size__word 0 +#define R_ATA_CTRL_DATA__data__BITNR 0 +#define R_ATA_CTRL_DATA__data__WIDTH 16 + +#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) +#define R_ATA_STATUS_DATA__busy__BITNR 18 +#define R_ATA_STATUS_DATA__busy__WIDTH 1 +#define R_ATA_STATUS_DATA__busy__yes 1 +#define R_ATA_STATUS_DATA__busy__no 0 +#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 +#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_ATA_STATUS_DATA__tr_rdy__ready 1 +#define R_ATA_STATUS_DATA__tr_rdy__busy 0 +#define R_ATA_STATUS_DATA__dav__BITNR 16 +#define R_ATA_STATUS_DATA__dav__WIDTH 1 +#define R_ATA_STATUS_DATA__dav__data 1 +#define R_ATA_STATUS_DATA__dav__nodata 0 +#define R_ATA_STATUS_DATA__data__BITNR 0 +#define R_ATA_STATUS_DATA__data__WIDTH 16 + +#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) +#define R_ATA_CONFIG__enable__BITNR 25 +#define R_ATA_CONFIG__enable__WIDTH 1 +#define R_ATA_CONFIG__enable__on 1 +#define R_ATA_CONFIG__enable__off 0 +#define R_ATA_CONFIG__dma_strobe__BITNR 20 +#define R_ATA_CONFIG__dma_strobe__WIDTH 5 +#define R_ATA_CONFIG__dma_hold__BITNR 15 +#define R_ATA_CONFIG__dma_hold__WIDTH 5 +#define R_ATA_CONFIG__pio_setup__BITNR 10 +#define R_ATA_CONFIG__pio_setup__WIDTH 5 +#define R_ATA_CONFIG__pio_strobe__BITNR 5 +#define R_ATA_CONFIG__pio_strobe__WIDTH 5 +#define R_ATA_CONFIG__pio_hold__BITNR 0 +#define R_ATA_CONFIG__pio_hold__WIDTH 5 + +#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) +#define R_ATA_TRANSFER_CNT__count__BITNR 0 +#define R_ATA_TRANSFER_CNT__count__WIDTH 17 + +/* +!* SCSI registers +!*/ + +#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) +#define R_SCSI0_CTRL__id_type__BITNR 31 +#define R_SCSI0_CTRL__id_type__WIDTH 1 +#define R_SCSI0_CTRL__id_type__software 1 +#define R_SCSI0_CTRL__id_type__hardware 0 +#define R_SCSI0_CTRL__sel_timeout__BITNR 24 +#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 +#define R_SCSI0_CTRL__synch_per__BITNR 16 +#define R_SCSI0_CTRL__synch_per__WIDTH 8 +#define R_SCSI0_CTRL__rst__BITNR 15 +#define R_SCSI0_CTRL__rst__WIDTH 1 +#define R_SCSI0_CTRL__rst__yes 1 +#define R_SCSI0_CTRL__rst__no 0 +#define R_SCSI0_CTRL__atn__BITNR 14 +#define R_SCSI0_CTRL__atn__WIDTH 1 +#define R_SCSI0_CTRL__atn__yes 1 +#define R_SCSI0_CTRL__atn__no 0 +#define R_SCSI0_CTRL__my_id__BITNR 9 +#define R_SCSI0_CTRL__my_id__WIDTH 4 +#define R_SCSI0_CTRL__target_id__BITNR 4 +#define R_SCSI0_CTRL__target_id__WIDTH 4 +#define R_SCSI0_CTRL__fast_20__BITNR 3 +#define R_SCSI0_CTRL__fast_20__WIDTH 1 +#define R_SCSI0_CTRL__fast_20__yes 1 +#define R_SCSI0_CTRL__fast_20__no 0 +#define R_SCSI0_CTRL__bus_width__BITNR 2 +#define R_SCSI0_CTRL__bus_width__WIDTH 1 +#define R_SCSI0_CTRL__bus_width__wide 1 +#define R_SCSI0_CTRL__bus_width__narrow 0 +#define R_SCSI0_CTRL__synch__BITNR 1 +#define R_SCSI0_CTRL__synch__WIDTH 1 +#define R_SCSI0_CTRL__synch__synch 1 +#define R_SCSI0_CTRL__synch__asynch 0 +#define R_SCSI0_CTRL__enable__BITNR 0 +#define R_SCSI0_CTRL__enable__WIDTH 1 +#define R_SCSI0_CTRL__enable__on 1 +#define R_SCSI0_CTRL__enable__off 0 + +#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 +#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 +#define R_SCSI0_CMD_DATA__parity_in__on 0 +#define R_SCSI0_CMD_DATA__parity_in__off 1 +#define R_SCSI0_CMD_DATA__skip__BITNR 25 +#define R_SCSI0_CMD_DATA__skip__WIDTH 1 +#define R_SCSI0_CMD_DATA__skip__on 1 +#define R_SCSI0_CMD_DATA__skip__off 0 +#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 +#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 +#define R_SCSI0_CMD_DATA__clr_status__yes 1 +#define R_SCSI0_CMD_DATA__clr_status__nop 0 +#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 +#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 +#define R_SCSI0_CMD_DATA__command__BITNR 16 +#define R_SCSI0_CMD_DATA__command__WIDTH 4 +#define R_SCSI0_CMD_DATA__command__full_din_1 0 +#define R_SCSI0_CMD_DATA__command__full_dout_1 1 +#define R_SCSI0_CMD_DATA__command__full_stat_1 2 +#define R_SCSI0_CMD_DATA__command__resel_din 3 +#define R_SCSI0_CMD_DATA__command__resel_dout 4 +#define R_SCSI0_CMD_DATA__command__resel_stat 5 +#define R_SCSI0_CMD_DATA__command__arb_only 6 +#define R_SCSI0_CMD_DATA__command__full_din_3 8 +#define R_SCSI0_CMD_DATA__command__full_dout_3 9 +#define R_SCSI0_CMD_DATA__command__full_stat_3 10 +#define R_SCSI0_CMD_DATA__command__man_data_in 11 +#define R_SCSI0_CMD_DATA__command__man_data_out 12 +#define R_SCSI0_CMD_DATA__command__man_rat 13 +#define R_SCSI0_CMD_DATA__data_out__BITNR 0 +#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 + +#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) +#define R_SCSI0_DATA__data_out__BITNR 0 +#define R_SCSI0_DATA__data_out__WIDTH 16 + +#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) +#define R_SCSI0_CMD__asynch_setup__BITNR 4 +#define R_SCSI0_CMD__asynch_setup__WIDTH 4 +#define R_SCSI0_CMD__command__BITNR 0 +#define R_SCSI0_CMD__command__WIDTH 4 +#define R_SCSI0_CMD__command__full_din_1 0 +#define R_SCSI0_CMD__command__full_dout_1 1 +#define R_SCSI0_CMD__command__full_stat_1 2 +#define R_SCSI0_CMD__command__resel_din 3 +#define R_SCSI0_CMD__command__resel_dout 4 +#define R_SCSI0_CMD__command__resel_stat 5 +#define R_SCSI0_CMD__command__arb_only 6 +#define R_SCSI0_CMD__command__full_din_3 8 +#define R_SCSI0_CMD__command__full_dout_3 9 +#define R_SCSI0_CMD__command__full_stat_3 10 +#define R_SCSI0_CMD__command__man_data_in 11 +#define R_SCSI0_CMD__command__man_data_out 12 +#define R_SCSI0_CMD__command__man_rat 13 + +#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) +#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 +#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__parity_in__on 0 +#define R_SCSI0_STATUS_CTRL__parity_in__off 1 +#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 +#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__skip__on 1 +#define R_SCSI0_STATUS_CTRL__skip__off 0 +#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 +#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 +#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 + +#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) +#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 +#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 +#define R_SCSI0_STATUS__tst_resel__BITNR 22 +#define R_SCSI0_STATUS__tst_resel__WIDTH 1 +#define R_SCSI0_STATUS__parity_error__BITNR 21 +#define R_SCSI0_STATUS__parity_error__WIDTH 1 +#define R_SCSI0_STATUS__bus_reset__BITNR 20 +#define R_SCSI0_STATUS__bus_reset__WIDTH 1 +#define R_SCSI0_STATUS__bus_reset__yes 1 +#define R_SCSI0_STATUS__bus_reset__no 0 +#define R_SCSI0_STATUS__resel_target__BITNR 15 +#define R_SCSI0_STATUS__resel_target__WIDTH 4 +#define R_SCSI0_STATUS__resel__BITNR 14 +#define R_SCSI0_STATUS__resel__WIDTH 1 +#define R_SCSI0_STATUS__resel__yes 1 +#define R_SCSI0_STATUS__resel__no 0 +#define R_SCSI0_STATUS__curr_phase__BITNR 11 +#define R_SCSI0_STATUS__curr_phase__WIDTH 3 +#define R_SCSI0_STATUS__curr_phase__ph_undef 0 +#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 +#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 +#define R_SCSI0_STATUS__curr_phase__ph_status 3 +#define R_SCSI0_STATUS__curr_phase__ph_command 2 +#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 +#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 +#define R_SCSI0_STATUS__curr_phase__ph_resel 1 +#define R_SCSI0_STATUS__last_seq_step__BITNR 6 +#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 +#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 +#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 +#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 +#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 +#define R_SCSI0_STATUS__last_seq_step__st_manual 28 +#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 +#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 +#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 +#define R_SCSI0_STATUS__last_seq_step__st_answer 3 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 +#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 +#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 +#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 +#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 +#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 +#define R_SCSI0_STATUS__last_seq_step__st_cc 31 +#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 +#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 +#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 +#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 +#define R_SCSI0_STATUS__valid_status__BITNR 5 +#define R_SCSI0_STATUS__valid_status__WIDTH 1 +#define R_SCSI0_STATUS__valid_status__yes 1 +#define R_SCSI0_STATUS__valid_status__no 0 +#define R_SCSI0_STATUS__seq_status__BITNR 0 +#define R_SCSI0_STATUS__seq_status__WIDTH 5 +#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 +#define R_SCSI0_STATUS__seq_status__info_parity_error 1 +#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 +#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 +#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 +#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 +#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 +#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 +#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 +#define R_SCSI0_STATUS__seq_status__info_reselected 9 +#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 +#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 +#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 +#define R_SCSI0_STATUS__seq_status__info_bus_free 13 + +#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) +#define R_SCSI0_DATA_IN__data_in__BITNR 0 +#define R_SCSI0_DATA_IN__data_in__WIDTH 16 + +#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) +#define R_SCSI1_CTRL__id_type__BITNR 31 +#define R_SCSI1_CTRL__id_type__WIDTH 1 +#define R_SCSI1_CTRL__id_type__software 1 +#define R_SCSI1_CTRL__id_type__hardware 0 +#define R_SCSI1_CTRL__sel_timeout__BITNR 24 +#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 +#define R_SCSI1_CTRL__synch_per__BITNR 16 +#define R_SCSI1_CTRL__synch_per__WIDTH 8 +#define R_SCSI1_CTRL__rst__BITNR 15 +#define R_SCSI1_CTRL__rst__WIDTH 1 +#define R_SCSI1_CTRL__rst__yes 1 +#define R_SCSI1_CTRL__rst__no 0 +#define R_SCSI1_CTRL__atn__BITNR 14 +#define R_SCSI1_CTRL__atn__WIDTH 1 +#define R_SCSI1_CTRL__atn__yes 1 +#define R_SCSI1_CTRL__atn__no 0 +#define R_SCSI1_CTRL__my_id__BITNR 9 +#define R_SCSI1_CTRL__my_id__WIDTH 4 +#define R_SCSI1_CTRL__target_id__BITNR 4 +#define R_SCSI1_CTRL__target_id__WIDTH 4 +#define R_SCSI1_CTRL__fast_20__BITNR 3 +#define R_SCSI1_CTRL__fast_20__WIDTH 1 +#define R_SCSI1_CTRL__fast_20__yes 1 +#define R_SCSI1_CTRL__fast_20__no 0 +#define R_SCSI1_CTRL__bus_width__BITNR 2 +#define R_SCSI1_CTRL__bus_width__WIDTH 1 +#define R_SCSI1_CTRL__bus_width__wide 1 +#define R_SCSI1_CTRL__bus_width__narrow 0 +#define R_SCSI1_CTRL__synch__BITNR 1 +#define R_SCSI1_CTRL__synch__WIDTH 1 +#define R_SCSI1_CTRL__synch__synch 1 +#define R_SCSI1_CTRL__synch__asynch 0 +#define R_SCSI1_CTRL__enable__BITNR 0 +#define R_SCSI1_CTRL__enable__WIDTH 1 +#define R_SCSI1_CTRL__enable__on 1 +#define R_SCSI1_CTRL__enable__off 0 + +#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) +#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 +#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 +#define R_SCSI1_CMD_DATA__parity_in__on 0 +#define R_SCSI1_CMD_DATA__parity_in__off 1 +#define R_SCSI1_CMD_DATA__skip__BITNR 25 +#define R_SCSI1_CMD_DATA__skip__WIDTH 1 +#define R_SCSI1_CMD_DATA__skip__on 1 +#define R_SCSI1_CMD_DATA__skip__off 0 +#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 +#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 +#define R_SCSI1_CMD_DATA__clr_status__yes 1 +#define R_SCSI1_CMD_DATA__clr_status__nop 0 +#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 +#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 +#define R_SCSI1_CMD_DATA__command__BITNR 16 +#define R_SCSI1_CMD_DATA__command__WIDTH 4 +#define R_SCSI1_CMD_DATA__command__full_din_1 0 +#define R_SCSI1_CMD_DATA__command__full_dout_1 1 +#define R_SCSI1_CMD_DATA__command__full_stat_1 2 +#define R_SCSI1_CMD_DATA__command__resel_din 3 +#define R_SCSI1_CMD_DATA__command__resel_dout 4 +#define R_SCSI1_CMD_DATA__command__resel_stat 5 +#define R_SCSI1_CMD_DATA__command__arb_only 6 +#define R_SCSI1_CMD_DATA__command__full_din_3 8 +#define R_SCSI1_CMD_DATA__command__full_dout_3 9 +#define R_SCSI1_CMD_DATA__command__full_stat_3 10 +#define R_SCSI1_CMD_DATA__command__man_data_in 11 +#define R_SCSI1_CMD_DATA__command__man_data_out 12 +#define R_SCSI1_CMD_DATA__command__man_rat 13 +#define R_SCSI1_CMD_DATA__data_out__BITNR 0 +#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 + +#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) +#define R_SCSI1_DATA__data_out__BITNR 0 +#define R_SCSI1_DATA__data_out__WIDTH 16 + +#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) +#define R_SCSI1_CMD__asynch_setup__BITNR 4 +#define R_SCSI1_CMD__asynch_setup__WIDTH 4 +#define R_SCSI1_CMD__command__BITNR 0 +#define R_SCSI1_CMD__command__WIDTH 4 +#define R_SCSI1_CMD__command__full_din_1 0 +#define R_SCSI1_CMD__command__full_dout_1 1 +#define R_SCSI1_CMD__command__full_stat_1 2 +#define R_SCSI1_CMD__command__resel_din 3 +#define R_SCSI1_CMD__command__resel_dout 4 +#define R_SCSI1_CMD__command__resel_stat 5 +#define R_SCSI1_CMD__command__arb_only 6 +#define R_SCSI1_CMD__command__full_din_3 8 +#define R_SCSI1_CMD__command__full_dout_3 9 +#define R_SCSI1_CMD__command__full_stat_3 10 +#define R_SCSI1_CMD__command__man_data_in 11 +#define R_SCSI1_CMD__command__man_data_out 12 +#define R_SCSI1_CMD__command__man_rat 13 + +#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) +#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 +#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__parity_in__on 0 +#define R_SCSI1_STATUS_CTRL__parity_in__off 1 +#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 +#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__skip__on 1 +#define R_SCSI1_STATUS_CTRL__skip__off 0 +#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 +#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 +#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 + +#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) +#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 +#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 +#define R_SCSI1_STATUS__tst_resel__BITNR 22 +#define R_SCSI1_STATUS__tst_resel__WIDTH 1 +#define R_SCSI1_STATUS__parity_error__BITNR 21 +#define R_SCSI1_STATUS__parity_error__WIDTH 1 +#define R_SCSI1_STATUS__bus_reset__BITNR 20 +#define R_SCSI1_STATUS__bus_reset__WIDTH 1 +#define R_SCSI1_STATUS__bus_reset__yes 1 +#define R_SCSI1_STATUS__bus_reset__no 0 +#define R_SCSI1_STATUS__resel_target__BITNR 15 +#define R_SCSI1_STATUS__resel_target__WIDTH 4 +#define R_SCSI1_STATUS__resel__BITNR 14 +#define R_SCSI1_STATUS__resel__WIDTH 1 +#define R_SCSI1_STATUS__resel__yes 1 +#define R_SCSI1_STATUS__resel__no 0 +#define R_SCSI1_STATUS__curr_phase__BITNR 11 +#define R_SCSI1_STATUS__curr_phase__WIDTH 3 +#define R_SCSI1_STATUS__curr_phase__ph_undef 0 +#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 +#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 +#define R_SCSI1_STATUS__curr_phase__ph_status 3 +#define R_SCSI1_STATUS__curr_phase__ph_command 2 +#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 +#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 +#define R_SCSI1_STATUS__curr_phase__ph_resel 1 +#define R_SCSI1_STATUS__last_seq_step__BITNR 6 +#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 +#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 +#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 +#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 +#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 +#define R_SCSI1_STATUS__last_seq_step__st_manual 28 +#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 +#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 +#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 +#define R_SCSI1_STATUS__last_seq_step__st_answer 3 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 +#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 +#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 +#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 +#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 +#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 +#define R_SCSI1_STATUS__last_seq_step__st_cc 31 +#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 +#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 +#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 +#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 +#define R_SCSI1_STATUS__valid_status__BITNR 5 +#define R_SCSI1_STATUS__valid_status__WIDTH 1 +#define R_SCSI1_STATUS__valid_status__yes 1 +#define R_SCSI1_STATUS__valid_status__no 0 +#define R_SCSI1_STATUS__seq_status__BITNR 0 +#define R_SCSI1_STATUS__seq_status__WIDTH 5 +#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 +#define R_SCSI1_STATUS__seq_status__info_parity_error 1 +#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 +#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 +#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 +#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 +#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 +#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 +#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 +#define R_SCSI1_STATUS__seq_status__info_reselected 9 +#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 +#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 +#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 +#define R_SCSI1_STATUS__seq_status__info_bus_free 13 + +#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) +#define R_SCSI1_DATA_IN__data_in__BITNR 0 +#define R_SCSI1_DATA_IN__data_in__WIDTH 16 + +/* +!* Interrupt mask and status registers +!*/ + +#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) +#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_RD__nmi_pin__active 1 +#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 +#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 +#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 +#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_RD__sqe_test_error__active 1 +#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 +#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_RD__carrier_loss__active 1 +#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 +#define R_IRQ_MASK0_RD__deferred__BITNR 27 +#define R_IRQ_MASK0_RD__deferred__WIDTH 1 +#define R_IRQ_MASK0_RD__deferred__active 1 +#define R_IRQ_MASK0_RD__deferred__inactive 0 +#define R_IRQ_MASK0_RD__late_col__BITNR 26 +#define R_IRQ_MASK0_RD__late_col__WIDTH 1 +#define R_IRQ_MASK0_RD__late_col__active 1 +#define R_IRQ_MASK0_RD__late_col__inactive 0 +#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 +#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_RD__multiple_col__active 1 +#define R_IRQ_MASK0_RD__multiple_col__inactive 0 +#define R_IRQ_MASK0_RD__single_col__BITNR 24 +#define R_IRQ_MASK0_RD__single_col__WIDTH 1 +#define R_IRQ_MASK0_RD__single_col__active 1 +#define R_IRQ_MASK0_RD__single_col__inactive 0 +#define R_IRQ_MASK0_RD__congestion__BITNR 23 +#define R_IRQ_MASK0_RD__congestion__WIDTH 1 +#define R_IRQ_MASK0_RD__congestion__active 1 +#define R_IRQ_MASK0_RD__congestion__inactive 0 +#define R_IRQ_MASK0_RD__oversize__BITNR 22 +#define R_IRQ_MASK0_RD__oversize__WIDTH 1 +#define R_IRQ_MASK0_RD__oversize__active 1 +#define R_IRQ_MASK0_RD__oversize__inactive 0 +#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 +#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_RD__alignment_error__active 1 +#define R_IRQ_MASK0_RD__alignment_error__inactive 0 +#define R_IRQ_MASK0_RD__crc_error__BITNR 20 +#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 +#define R_IRQ_MASK0_RD__crc_error__active 1 +#define R_IRQ_MASK0_RD__crc_error__inactive 0 +#define R_IRQ_MASK0_RD__overrun__BITNR 19 +#define R_IRQ_MASK0_RD__overrun__WIDTH 1 +#define R_IRQ_MASK0_RD__overrun__active 1 +#define R_IRQ_MASK0_RD__overrun__inactive 0 +#define R_IRQ_MASK0_RD__underrun__BITNR 18 +#define R_IRQ_MASK0_RD__underrun__WIDTH 1 +#define R_IRQ_MASK0_RD__underrun__active 1 +#define R_IRQ_MASK0_RD__underrun__inactive 0 +#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 +#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_RD__excessive_col__active 1 +#define R_IRQ_MASK0_RD__excessive_col__inactive 0 +#define R_IRQ_MASK0_RD__mdio__BITNR 16 +#define R_IRQ_MASK0_RD__mdio__WIDTH 1 +#define R_IRQ_MASK0_RD__mdio__active 1 +#define R_IRQ_MASK0_RD__mdio__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq3__active 1 +#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq2__active 1 +#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq1__active 1 +#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq0__active 1 +#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq3__active 1 +#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 +#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 +#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_peri__active 1 +#define R_IRQ_MASK0_RD__par0_peri__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq2__active 1 +#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 +#define R_IRQ_MASK0_RD__par0_data__BITNR 9 +#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_data__active 1 +#define R_IRQ_MASK0_RD__par0_data__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq1__active 1 +#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 +#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 +#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_ready__active 1 +#define R_IRQ_MASK0_RD__par0_ready__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq0__active 1 +#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 +#define R_IRQ_MASK0_RD__mio__BITNR 8 +#define R_IRQ_MASK0_RD__mio__WIDTH 1 +#define R_IRQ_MASK0_RD__mio__active 1 +#define R_IRQ_MASK0_RD__mio__inactive 0 +#define R_IRQ_MASK0_RD__scsi0__BITNR 8 +#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 +#define R_IRQ_MASK0_RD__scsi0__active 1 +#define R_IRQ_MASK0_RD__scsi0__inactive 0 +#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_dmaend__active 1 +#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 +#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_RD__ext_dma1__active 1 +#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 +#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_RD__ext_dma0__active 1 +#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 +#define R_IRQ_MASK0_RD__timer1__BITNR 1 +#define R_IRQ_MASK0_RD__timer1__WIDTH 1 +#define R_IRQ_MASK0_RD__timer1__active 1 +#define R_IRQ_MASK0_RD__timer1__inactive 0 +#define R_IRQ_MASK0_RD__timer0__BITNR 0 +#define R_IRQ_MASK0_RD__timer0__WIDTH 1 +#define R_IRQ_MASK0_RD__timer0__active 1 +#define R_IRQ_MASK0_RD__timer0__inactive 0 + +#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) +#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 +#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 +#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 +#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 +#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 +#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 +#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 +#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 +#define R_IRQ_MASK0_CLR__deferred__BITNR 27 +#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 +#define R_IRQ_MASK0_CLR__deferred__clr 1 +#define R_IRQ_MASK0_CLR__deferred__nop 0 +#define R_IRQ_MASK0_CLR__late_col__BITNR 26 +#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__late_col__clr 1 +#define R_IRQ_MASK0_CLR__late_col__nop 0 +#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 +#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__multiple_col__clr 1 +#define R_IRQ_MASK0_CLR__multiple_col__nop 0 +#define R_IRQ_MASK0_CLR__single_col__BITNR 24 +#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__single_col__clr 1 +#define R_IRQ_MASK0_CLR__single_col__nop 0 +#define R_IRQ_MASK0_CLR__congestion__BITNR 23 +#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 +#define R_IRQ_MASK0_CLR__congestion__clr 1 +#define R_IRQ_MASK0_CLR__congestion__nop 0 +#define R_IRQ_MASK0_CLR__oversize__BITNR 22 +#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 +#define R_IRQ_MASK0_CLR__oversize__clr 1 +#define R_IRQ_MASK0_CLR__oversize__nop 0 +#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 +#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__alignment_error__clr 1 +#define R_IRQ_MASK0_CLR__alignment_error__nop 0 +#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 +#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__crc_error__clr 1 +#define R_IRQ_MASK0_CLR__crc_error__nop 0 +#define R_IRQ_MASK0_CLR__overrun__BITNR 19 +#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 +#define R_IRQ_MASK0_CLR__overrun__clr 1 +#define R_IRQ_MASK0_CLR__overrun__nop 0 +#define R_IRQ_MASK0_CLR__underrun__BITNR 18 +#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 +#define R_IRQ_MASK0_CLR__underrun__clr 1 +#define R_IRQ_MASK0_CLR__underrun__nop 0 +#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 +#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__excessive_col__clr 1 +#define R_IRQ_MASK0_CLR__excessive_col__nop 0 +#define R_IRQ_MASK0_CLR__mdio__BITNR 16 +#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 +#define R_IRQ_MASK0_CLR__mdio__clr 1 +#define R_IRQ_MASK0_CLR__mdio__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 +#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 +#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_peri__clr 1 +#define R_IRQ_MASK0_CLR__par0_peri__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 +#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 +#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_data__clr 1 +#define R_IRQ_MASK0_CLR__par0_data__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 +#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 +#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_ready__clr 1 +#define R_IRQ_MASK0_CLR__par0_ready__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 +#define R_IRQ_MASK0_CLR__mio__BITNR 8 +#define R_IRQ_MASK0_CLR__mio__WIDTH 1 +#define R_IRQ_MASK0_CLR__mio__clr 1 +#define R_IRQ_MASK0_CLR__mio__nop 0 +#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 +#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 +#define R_IRQ_MASK0_CLR__scsi0__clr 1 +#define R_IRQ_MASK0_CLR__scsi0__nop 0 +#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 +#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 +#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 +#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 +#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 +#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 +#define R_IRQ_MASK0_CLR__timer1__BITNR 1 +#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 +#define R_IRQ_MASK0_CLR__timer1__clr 1 +#define R_IRQ_MASK0_CLR__timer1__nop 0 +#define R_IRQ_MASK0_CLR__timer0__BITNR 0 +#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 +#define R_IRQ_MASK0_CLR__timer0__clr 1 +#define R_IRQ_MASK0_CLR__timer0__nop 0 + +#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) +#define R_IRQ_READ0__nmi_pin__BITNR 31 +#define R_IRQ_READ0__nmi_pin__WIDTH 1 +#define R_IRQ_READ0__nmi_pin__active 1 +#define R_IRQ_READ0__nmi_pin__inactive 0 +#define R_IRQ_READ0__watchdog_nmi__BITNR 30 +#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 +#define R_IRQ_READ0__watchdog_nmi__active 1 +#define R_IRQ_READ0__watchdog_nmi__inactive 0 +#define R_IRQ_READ0__sqe_test_error__BITNR 29 +#define R_IRQ_READ0__sqe_test_error__WIDTH 1 +#define R_IRQ_READ0__sqe_test_error__active 1 +#define R_IRQ_READ0__sqe_test_error__inactive 0 +#define R_IRQ_READ0__carrier_loss__BITNR 28 +#define R_IRQ_READ0__carrier_loss__WIDTH 1 +#define R_IRQ_READ0__carrier_loss__active 1 +#define R_IRQ_READ0__carrier_loss__inactive 0 +#define R_IRQ_READ0__deferred__BITNR 27 +#define R_IRQ_READ0__deferred__WIDTH 1 +#define R_IRQ_READ0__deferred__active 1 +#define R_IRQ_READ0__deferred__inactive 0 +#define R_IRQ_READ0__late_col__BITNR 26 +#define R_IRQ_READ0__late_col__WIDTH 1 +#define R_IRQ_READ0__late_col__active 1 +#define R_IRQ_READ0__late_col__inactive 0 +#define R_IRQ_READ0__multiple_col__BITNR 25 +#define R_IRQ_READ0__multiple_col__WIDTH 1 +#define R_IRQ_READ0__multiple_col__active 1 +#define R_IRQ_READ0__multiple_col__inactive 0 +#define R_IRQ_READ0__single_col__BITNR 24 +#define R_IRQ_READ0__single_col__WIDTH 1 +#define R_IRQ_READ0__single_col__active 1 +#define R_IRQ_READ0__single_col__inactive 0 +#define R_IRQ_READ0__congestion__BITNR 23 +#define R_IRQ_READ0__congestion__WIDTH 1 +#define R_IRQ_READ0__congestion__active 1 +#define R_IRQ_READ0__congestion__inactive 0 +#define R_IRQ_READ0__oversize__BITNR 22 +#define R_IRQ_READ0__oversize__WIDTH 1 +#define R_IRQ_READ0__oversize__active 1 +#define R_IRQ_READ0__oversize__inactive 0 +#define R_IRQ_READ0__alignment_error__BITNR 21 +#define R_IRQ_READ0__alignment_error__WIDTH 1 +#define R_IRQ_READ0__alignment_error__active 1 +#define R_IRQ_READ0__alignment_error__inactive 0 +#define R_IRQ_READ0__crc_error__BITNR 20 +#define R_IRQ_READ0__crc_error__WIDTH 1 +#define R_IRQ_READ0__crc_error__active 1 +#define R_IRQ_READ0__crc_error__inactive 0 +#define R_IRQ_READ0__overrun__BITNR 19 +#define R_IRQ_READ0__overrun__WIDTH 1 +#define R_IRQ_READ0__overrun__active 1 +#define R_IRQ_READ0__overrun__inactive 0 +#define R_IRQ_READ0__underrun__BITNR 18 +#define R_IRQ_READ0__underrun__WIDTH 1 +#define R_IRQ_READ0__underrun__active 1 +#define R_IRQ_READ0__underrun__inactive 0 +#define R_IRQ_READ0__excessive_col__BITNR 17 +#define R_IRQ_READ0__excessive_col__WIDTH 1 +#define R_IRQ_READ0__excessive_col__active 1 +#define R_IRQ_READ0__excessive_col__inactive 0 +#define R_IRQ_READ0__mdio__BITNR 16 +#define R_IRQ_READ0__mdio__WIDTH 1 +#define R_IRQ_READ0__mdio__active 1 +#define R_IRQ_READ0__mdio__inactive 0 +#define R_IRQ_READ0__ata_drq3__BITNR 15 +#define R_IRQ_READ0__ata_drq3__WIDTH 1 +#define R_IRQ_READ0__ata_drq3__active 1 +#define R_IRQ_READ0__ata_drq3__inactive 0 +#define R_IRQ_READ0__ata_drq2__BITNR 14 +#define R_IRQ_READ0__ata_drq2__WIDTH 1 +#define R_IRQ_READ0__ata_drq2__active 1 +#define R_IRQ_READ0__ata_drq2__inactive 0 +#define R_IRQ_READ0__ata_drq1__BITNR 13 +#define R_IRQ_READ0__ata_drq1__WIDTH 1 +#define R_IRQ_READ0__ata_drq1__active 1 +#define R_IRQ_READ0__ata_drq1__inactive 0 +#define R_IRQ_READ0__ata_drq0__BITNR 12 +#define R_IRQ_READ0__ata_drq0__WIDTH 1 +#define R_IRQ_READ0__ata_drq0__active 1 +#define R_IRQ_READ0__ata_drq0__inactive 0 +#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 +#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_READ0__par0_ecp_cmd__active 1 +#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 +#define R_IRQ_READ0__ata_irq3__BITNR 11 +#define R_IRQ_READ0__ata_irq3__WIDTH 1 +#define R_IRQ_READ0__ata_irq3__active 1 +#define R_IRQ_READ0__ata_irq3__inactive 0 +#define R_IRQ_READ0__par0_peri__BITNR 10 +#define R_IRQ_READ0__par0_peri__WIDTH 1 +#define R_IRQ_READ0__par0_peri__active 1 +#define R_IRQ_READ0__par0_peri__inactive 0 +#define R_IRQ_READ0__ata_irq2__BITNR 10 +#define R_IRQ_READ0__ata_irq2__WIDTH 1 +#define R_IRQ_READ0__ata_irq2__active 1 +#define R_IRQ_READ0__ata_irq2__inactive 0 +#define R_IRQ_READ0__par0_data__BITNR 9 +#define R_IRQ_READ0__par0_data__WIDTH 1 +#define R_IRQ_READ0__par0_data__active 1 +#define R_IRQ_READ0__par0_data__inactive 0 +#define R_IRQ_READ0__ata_irq1__BITNR 9 +#define R_IRQ_READ0__ata_irq1__WIDTH 1 +#define R_IRQ_READ0__ata_irq1__active 1 +#define R_IRQ_READ0__ata_irq1__inactive 0 +#define R_IRQ_READ0__par0_ready__BITNR 8 +#define R_IRQ_READ0__par0_ready__WIDTH 1 +#define R_IRQ_READ0__par0_ready__active 1 +#define R_IRQ_READ0__par0_ready__inactive 0 +#define R_IRQ_READ0__ata_irq0__BITNR 8 +#define R_IRQ_READ0__ata_irq0__WIDTH 1 +#define R_IRQ_READ0__ata_irq0__active 1 +#define R_IRQ_READ0__ata_irq0__inactive 0 +#define R_IRQ_READ0__mio__BITNR 8 +#define R_IRQ_READ0__mio__WIDTH 1 +#define R_IRQ_READ0__mio__active 1 +#define R_IRQ_READ0__mio__inactive 0 +#define R_IRQ_READ0__scsi0__BITNR 8 +#define R_IRQ_READ0__scsi0__WIDTH 1 +#define R_IRQ_READ0__scsi0__active 1 +#define R_IRQ_READ0__scsi0__inactive 0 +#define R_IRQ_READ0__ata_dmaend__BITNR 7 +#define R_IRQ_READ0__ata_dmaend__WIDTH 1 +#define R_IRQ_READ0__ata_dmaend__active 1 +#define R_IRQ_READ0__ata_dmaend__inactive 0 +#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_READ0__irq_ext_vector_nr__active 1 +#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 +#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 +#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_READ0__irq_int_vector_nr__active 1 +#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 +#define R_IRQ_READ0__ext_dma1__BITNR 3 +#define R_IRQ_READ0__ext_dma1__WIDTH 1 +#define R_IRQ_READ0__ext_dma1__active 1 +#define R_IRQ_READ0__ext_dma1__inactive 0 +#define R_IRQ_READ0__ext_dma0__BITNR 2 +#define R_IRQ_READ0__ext_dma0__WIDTH 1 +#define R_IRQ_READ0__ext_dma0__active 1 +#define R_IRQ_READ0__ext_dma0__inactive 0 +#define R_IRQ_READ0__timer1__BITNR 1 +#define R_IRQ_READ0__timer1__WIDTH 1 +#define R_IRQ_READ0__timer1__active 1 +#define R_IRQ_READ0__timer1__inactive 0 +#define R_IRQ_READ0__timer0__BITNR 0 +#define R_IRQ_READ0__timer0__WIDTH 1 +#define R_IRQ_READ0__timer0__active 1 +#define R_IRQ_READ0__timer0__inactive 0 + +#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) +#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_SET__nmi_pin__set 1 +#define R_IRQ_MASK0_SET__nmi_pin__nop 0 +#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 +#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 +#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_SET__sqe_test_error__set 1 +#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 +#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_SET__carrier_loss__set 1 +#define R_IRQ_MASK0_SET__carrier_loss__nop 0 +#define R_IRQ_MASK0_SET__deferred__BITNR 27 +#define R_IRQ_MASK0_SET__deferred__WIDTH 1 +#define R_IRQ_MASK0_SET__deferred__set 1 +#define R_IRQ_MASK0_SET__deferred__nop 0 +#define R_IRQ_MASK0_SET__late_col__BITNR 26 +#define R_IRQ_MASK0_SET__late_col__WIDTH 1 +#define R_IRQ_MASK0_SET__late_col__set 1 +#define R_IRQ_MASK0_SET__late_col__nop 0 +#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 +#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_SET__multiple_col__set 1 +#define R_IRQ_MASK0_SET__multiple_col__nop 0 +#define R_IRQ_MASK0_SET__single_col__BITNR 24 +#define R_IRQ_MASK0_SET__single_col__WIDTH 1 +#define R_IRQ_MASK0_SET__single_col__set 1 +#define R_IRQ_MASK0_SET__single_col__nop 0 +#define R_IRQ_MASK0_SET__congestion__BITNR 23 +#define R_IRQ_MASK0_SET__congestion__WIDTH 1 +#define R_IRQ_MASK0_SET__congestion__set 1 +#define R_IRQ_MASK0_SET__congestion__nop 0 +#define R_IRQ_MASK0_SET__oversize__BITNR 22 +#define R_IRQ_MASK0_SET__oversize__WIDTH 1 +#define R_IRQ_MASK0_SET__oversize__set 1 +#define R_IRQ_MASK0_SET__oversize__nop 0 +#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 +#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_SET__alignment_error__set 1 +#define R_IRQ_MASK0_SET__alignment_error__nop 0 +#define R_IRQ_MASK0_SET__crc_error__BITNR 20 +#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 +#define R_IRQ_MASK0_SET__crc_error__set 1 +#define R_IRQ_MASK0_SET__crc_error__nop 0 +#define R_IRQ_MASK0_SET__overrun__BITNR 19 +#define R_IRQ_MASK0_SET__overrun__WIDTH 1 +#define R_IRQ_MASK0_SET__overrun__set 1 +#define R_IRQ_MASK0_SET__overrun__nop 0 +#define R_IRQ_MASK0_SET__underrun__BITNR 18 +#define R_IRQ_MASK0_SET__underrun__WIDTH 1 +#define R_IRQ_MASK0_SET__underrun__set 1 +#define R_IRQ_MASK0_SET__underrun__nop 0 +#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 +#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_SET__excessive_col__set 1 +#define R_IRQ_MASK0_SET__excessive_col__nop 0 +#define R_IRQ_MASK0_SET__mdio__BITNR 16 +#define R_IRQ_MASK0_SET__mdio__WIDTH 1 +#define R_IRQ_MASK0_SET__mdio__set 1 +#define R_IRQ_MASK0_SET__mdio__nop 0 +#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq3__set 1 +#define R_IRQ_MASK0_SET__ata_drq3__nop 0 +#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq2__set 1 +#define R_IRQ_MASK0_SET__ata_drq2__nop 0 +#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq1__set 1 +#define R_IRQ_MASK0_SET__ata_drq1__nop 0 +#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq0__set 1 +#define R_IRQ_MASK0_SET__ata_drq0__nop 0 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 +#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq3__set 1 +#define R_IRQ_MASK0_SET__ata_irq3__nop 0 +#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 +#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_peri__set 1 +#define R_IRQ_MASK0_SET__par0_peri__nop 0 +#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq2__set 1 +#define R_IRQ_MASK0_SET__ata_irq2__nop 0 +#define R_IRQ_MASK0_SET__par0_data__BITNR 9 +#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_data__set 1 +#define R_IRQ_MASK0_SET__par0_data__nop 0 +#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq1__set 1 +#define R_IRQ_MASK0_SET__ata_irq1__nop 0 +#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 +#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_ready__set 1 +#define R_IRQ_MASK0_SET__par0_ready__nop 0 +#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq0__set 1 +#define R_IRQ_MASK0_SET__ata_irq0__nop 0 +#define R_IRQ_MASK0_SET__mio__BITNR 8 +#define R_IRQ_MASK0_SET__mio__WIDTH 1 +#define R_IRQ_MASK0_SET__mio__set 1 +#define R_IRQ_MASK0_SET__mio__nop 0 +#define R_IRQ_MASK0_SET__scsi0__BITNR 8 +#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 +#define R_IRQ_MASK0_SET__scsi0__set 1 +#define R_IRQ_MASK0_SET__scsi0__nop 0 +#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_dmaend__set 1 +#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 +#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_SET__ext_dma1__set 1 +#define R_IRQ_MASK0_SET__ext_dma1__nop 0 +#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_SET__ext_dma0__set 1 +#define R_IRQ_MASK0_SET__ext_dma0__nop 0 +#define R_IRQ_MASK0_SET__timer1__BITNR 1 +#define R_IRQ_MASK0_SET__timer1__WIDTH 1 +#define R_IRQ_MASK0_SET__timer1__set 1 +#define R_IRQ_MASK0_SET__timer1__nop 0 +#define R_IRQ_MASK0_SET__timer0__BITNR 0 +#define R_IRQ_MASK0_SET__timer0__WIDTH 1 +#define R_IRQ_MASK0_SET__timer0__set 1 +#define R_IRQ_MASK0_SET__timer0__nop 0 + +#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) +#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 +#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int7__active 1 +#define R_IRQ_MASK1_RD__sw_int7__inactive 0 +#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 +#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int6__active 1 +#define R_IRQ_MASK1_RD__sw_int6__inactive 0 +#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 +#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int5__active 1 +#define R_IRQ_MASK1_RD__sw_int5__inactive 0 +#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 +#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int4__active 1 +#define R_IRQ_MASK1_RD__sw_int4__inactive 0 +#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 +#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int3__active 1 +#define R_IRQ_MASK1_RD__sw_int3__inactive 0 +#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 +#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int2__active 1 +#define R_IRQ_MASK1_RD__sw_int2__inactive 0 +#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 +#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int1__active 1 +#define R_IRQ_MASK1_RD__sw_int1__inactive 0 +#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 +#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int0__active 1 +#define R_IRQ_MASK1_RD__sw_int0__inactive 0 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 +#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 +#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_peri__active 1 +#define R_IRQ_MASK1_RD__par1_peri__inactive 0 +#define R_IRQ_MASK1_RD__par1_data__BITNR 17 +#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_data__active 1 +#define R_IRQ_MASK1_RD__par1_data__inactive 0 +#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 +#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_ready__active 1 +#define R_IRQ_MASK1_RD__par1_ready__inactive 0 +#define R_IRQ_MASK1_RD__scsi1__BITNR 16 +#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 +#define R_IRQ_MASK1_RD__scsi1__active 1 +#define R_IRQ_MASK1_RD__scsi1__inactive 0 +#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser3_ready__active 1 +#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 +#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser3_data__active 1 +#define R_IRQ_MASK1_RD__ser3_data__inactive 0 +#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser2_ready__active 1 +#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 +#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser2_data__active 1 +#define R_IRQ_MASK1_RD__ser2_data__inactive 0 +#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser1_ready__active 1 +#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 +#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser1_data__active 1 +#define R_IRQ_MASK1_RD__ser1_data__inactive 0 +#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser0_ready__active 1 +#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 +#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser0_data__active 1 +#define R_IRQ_MASK1_RD__ser0_data__inactive 0 +#define R_IRQ_MASK1_RD__pa7__BITNR 7 +#define R_IRQ_MASK1_RD__pa7__WIDTH 1 +#define R_IRQ_MASK1_RD__pa7__active 1 +#define R_IRQ_MASK1_RD__pa7__inactive 0 +#define R_IRQ_MASK1_RD__pa6__BITNR 6 +#define R_IRQ_MASK1_RD__pa6__WIDTH 1 +#define R_IRQ_MASK1_RD__pa6__active 1 +#define R_IRQ_MASK1_RD__pa6__inactive 0 +#define R_IRQ_MASK1_RD__pa5__BITNR 5 +#define R_IRQ_MASK1_RD__pa5__WIDTH 1 +#define R_IRQ_MASK1_RD__pa5__active 1 +#define R_IRQ_MASK1_RD__pa5__inactive 0 +#define R_IRQ_MASK1_RD__pa4__BITNR 4 +#define R_IRQ_MASK1_RD__pa4__WIDTH 1 +#define R_IRQ_MASK1_RD__pa4__active 1 +#define R_IRQ_MASK1_RD__pa4__inactive 0 +#define R_IRQ_MASK1_RD__pa3__BITNR 3 +#define R_IRQ_MASK1_RD__pa3__WIDTH 1 +#define R_IRQ_MASK1_RD__pa3__active 1 +#define R_IRQ_MASK1_RD__pa3__inactive 0 +#define R_IRQ_MASK1_RD__pa2__BITNR 2 +#define R_IRQ_MASK1_RD__pa2__WIDTH 1 +#define R_IRQ_MASK1_RD__pa2__active 1 +#define R_IRQ_MASK1_RD__pa2__inactive 0 +#define R_IRQ_MASK1_RD__pa1__BITNR 1 +#define R_IRQ_MASK1_RD__pa1__WIDTH 1 +#define R_IRQ_MASK1_RD__pa1__active 1 +#define R_IRQ_MASK1_RD__pa1__inactive 0 +#define R_IRQ_MASK1_RD__pa0__BITNR 0 +#define R_IRQ_MASK1_RD__pa0__WIDTH 1 +#define R_IRQ_MASK1_RD__pa0__active 1 +#define R_IRQ_MASK1_RD__pa0__inactive 0 + +#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) +#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 +#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int7__clr 1 +#define R_IRQ_MASK1_CLR__sw_int7__nop 0 +#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 +#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int6__clr 1 +#define R_IRQ_MASK1_CLR__sw_int6__nop 0 +#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 +#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int5__clr 1 +#define R_IRQ_MASK1_CLR__sw_int5__nop 0 +#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 +#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int4__clr 1 +#define R_IRQ_MASK1_CLR__sw_int4__nop 0 +#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 +#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int3__clr 1 +#define R_IRQ_MASK1_CLR__sw_int3__nop 0 +#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 +#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int2__clr 1 +#define R_IRQ_MASK1_CLR__sw_int2__nop 0 +#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 +#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int1__clr 1 +#define R_IRQ_MASK1_CLR__sw_int1__nop 0 +#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 +#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int0__clr 1 +#define R_IRQ_MASK1_CLR__sw_int0__nop 0 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 +#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 +#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_peri__clr 1 +#define R_IRQ_MASK1_CLR__par1_peri__nop 0 +#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 +#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_data__clr 1 +#define R_IRQ_MASK1_CLR__par1_data__nop 0 +#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 +#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_ready__clr 1 +#define R_IRQ_MASK1_CLR__par1_ready__nop 0 +#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 +#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 +#define R_IRQ_MASK1_CLR__scsi1__clr 1 +#define R_IRQ_MASK1_CLR__scsi1__nop 0 +#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 +#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser3_data__clr 1 +#define R_IRQ_MASK1_CLR__ser3_data__nop 0 +#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 +#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser2_data__clr 1 +#define R_IRQ_MASK1_CLR__ser2_data__nop 0 +#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 +#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser1_data__clr 1 +#define R_IRQ_MASK1_CLR__ser1_data__nop 0 +#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 +#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser0_data__clr 1 +#define R_IRQ_MASK1_CLR__ser0_data__nop 0 +#define R_IRQ_MASK1_CLR__pa7__BITNR 7 +#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa7__clr 1 +#define R_IRQ_MASK1_CLR__pa7__nop 0 +#define R_IRQ_MASK1_CLR__pa6__BITNR 6 +#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa6__clr 1 +#define R_IRQ_MASK1_CLR__pa6__nop 0 +#define R_IRQ_MASK1_CLR__pa5__BITNR 5 +#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa5__clr 1 +#define R_IRQ_MASK1_CLR__pa5__nop 0 +#define R_IRQ_MASK1_CLR__pa4__BITNR 4 +#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa4__clr 1 +#define R_IRQ_MASK1_CLR__pa4__nop 0 +#define R_IRQ_MASK1_CLR__pa3__BITNR 3 +#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa3__clr 1 +#define R_IRQ_MASK1_CLR__pa3__nop 0 +#define R_IRQ_MASK1_CLR__pa2__BITNR 2 +#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa2__clr 1 +#define R_IRQ_MASK1_CLR__pa2__nop 0 +#define R_IRQ_MASK1_CLR__pa1__BITNR 1 +#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa1__clr 1 +#define R_IRQ_MASK1_CLR__pa1__nop 0 +#define R_IRQ_MASK1_CLR__pa0__BITNR 0 +#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa0__clr 1 +#define R_IRQ_MASK1_CLR__pa0__nop 0 + +#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) +#define R_IRQ_READ1__sw_int7__BITNR 31 +#define R_IRQ_READ1__sw_int7__WIDTH 1 +#define R_IRQ_READ1__sw_int7__active 1 +#define R_IRQ_READ1__sw_int7__inactive 0 +#define R_IRQ_READ1__sw_int6__BITNR 30 +#define R_IRQ_READ1__sw_int6__WIDTH 1 +#define R_IRQ_READ1__sw_int6__active 1 +#define R_IRQ_READ1__sw_int6__inactive 0 +#define R_IRQ_READ1__sw_int5__BITNR 29 +#define R_IRQ_READ1__sw_int5__WIDTH 1 +#define R_IRQ_READ1__sw_int5__active 1 +#define R_IRQ_READ1__sw_int5__inactive 0 +#define R_IRQ_READ1__sw_int4__BITNR 28 +#define R_IRQ_READ1__sw_int4__WIDTH 1 +#define R_IRQ_READ1__sw_int4__active 1 +#define R_IRQ_READ1__sw_int4__inactive 0 +#define R_IRQ_READ1__sw_int3__BITNR 27 +#define R_IRQ_READ1__sw_int3__WIDTH 1 +#define R_IRQ_READ1__sw_int3__active 1 +#define R_IRQ_READ1__sw_int3__inactive 0 +#define R_IRQ_READ1__sw_int2__BITNR 26 +#define R_IRQ_READ1__sw_int2__WIDTH 1 +#define R_IRQ_READ1__sw_int2__active 1 +#define R_IRQ_READ1__sw_int2__inactive 0 +#define R_IRQ_READ1__sw_int1__BITNR 25 +#define R_IRQ_READ1__sw_int1__WIDTH 1 +#define R_IRQ_READ1__sw_int1__active 1 +#define R_IRQ_READ1__sw_int1__inactive 0 +#define R_IRQ_READ1__sw_int0__BITNR 24 +#define R_IRQ_READ1__sw_int0__WIDTH 1 +#define R_IRQ_READ1__sw_int0__active 1 +#define R_IRQ_READ1__sw_int0__inactive 0 +#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 +#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_READ1__par1_ecp_cmd__active 1 +#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 +#define R_IRQ_READ1__par1_peri__BITNR 18 +#define R_IRQ_READ1__par1_peri__WIDTH 1 +#define R_IRQ_READ1__par1_peri__active 1 +#define R_IRQ_READ1__par1_peri__inactive 0 +#define R_IRQ_READ1__par1_data__BITNR 17 +#define R_IRQ_READ1__par1_data__WIDTH 1 +#define R_IRQ_READ1__par1_data__active 1 +#define R_IRQ_READ1__par1_data__inactive 0 +#define R_IRQ_READ1__par1_ready__BITNR 16 +#define R_IRQ_READ1__par1_ready__WIDTH 1 +#define R_IRQ_READ1__par1_ready__active 1 +#define R_IRQ_READ1__par1_ready__inactive 0 +#define R_IRQ_READ1__scsi1__BITNR 16 +#define R_IRQ_READ1__scsi1__WIDTH 1 +#define R_IRQ_READ1__scsi1__active 1 +#define R_IRQ_READ1__scsi1__inactive 0 +#define R_IRQ_READ1__ser3_ready__BITNR 15 +#define R_IRQ_READ1__ser3_ready__WIDTH 1 +#define R_IRQ_READ1__ser3_ready__active 1 +#define R_IRQ_READ1__ser3_ready__inactive 0 +#define R_IRQ_READ1__ser3_data__BITNR 14 +#define R_IRQ_READ1__ser3_data__WIDTH 1 +#define R_IRQ_READ1__ser3_data__active 1 +#define R_IRQ_READ1__ser3_data__inactive 0 +#define R_IRQ_READ1__ser2_ready__BITNR 13 +#define R_IRQ_READ1__ser2_ready__WIDTH 1 +#define R_IRQ_READ1__ser2_ready__active 1 +#define R_IRQ_READ1__ser2_ready__inactive 0 +#define R_IRQ_READ1__ser2_data__BITNR 12 +#define R_IRQ_READ1__ser2_data__WIDTH 1 +#define R_IRQ_READ1__ser2_data__active 1 +#define R_IRQ_READ1__ser2_data__inactive 0 +#define R_IRQ_READ1__ser1_ready__BITNR 11 +#define R_IRQ_READ1__ser1_ready__WIDTH 1 +#define R_IRQ_READ1__ser1_ready__active 1 +#define R_IRQ_READ1__ser1_ready__inactive 0 +#define R_IRQ_READ1__ser1_data__BITNR 10 +#define R_IRQ_READ1__ser1_data__WIDTH 1 +#define R_IRQ_READ1__ser1_data__active 1 +#define R_IRQ_READ1__ser1_data__inactive 0 +#define R_IRQ_READ1__ser0_ready__BITNR 9 +#define R_IRQ_READ1__ser0_ready__WIDTH 1 +#define R_IRQ_READ1__ser0_ready__active 1 +#define R_IRQ_READ1__ser0_ready__inactive 0 +#define R_IRQ_READ1__ser0_data__BITNR 8 +#define R_IRQ_READ1__ser0_data__WIDTH 1 +#define R_IRQ_READ1__ser0_data__active 1 +#define R_IRQ_READ1__ser0_data__inactive 0 +#define R_IRQ_READ1__pa7__BITNR 7 +#define R_IRQ_READ1__pa7__WIDTH 1 +#define R_IRQ_READ1__pa7__active 1 +#define R_IRQ_READ1__pa7__inactive 0 +#define R_IRQ_READ1__pa6__BITNR 6 +#define R_IRQ_READ1__pa6__WIDTH 1 +#define R_IRQ_READ1__pa6__active 1 +#define R_IRQ_READ1__pa6__inactive 0 +#define R_IRQ_READ1__pa5__BITNR 5 +#define R_IRQ_READ1__pa5__WIDTH 1 +#define R_IRQ_READ1__pa5__active 1 +#define R_IRQ_READ1__pa5__inactive 0 +#define R_IRQ_READ1__pa4__BITNR 4 +#define R_IRQ_READ1__pa4__WIDTH 1 +#define R_IRQ_READ1__pa4__active 1 +#define R_IRQ_READ1__pa4__inactive 0 +#define R_IRQ_READ1__pa3__BITNR 3 +#define R_IRQ_READ1__pa3__WIDTH 1 +#define R_IRQ_READ1__pa3__active 1 +#define R_IRQ_READ1__pa3__inactive 0 +#define R_IRQ_READ1__pa2__BITNR 2 +#define R_IRQ_READ1__pa2__WIDTH 1 +#define R_IRQ_READ1__pa2__active 1 +#define R_IRQ_READ1__pa2__inactive 0 +#define R_IRQ_READ1__pa1__BITNR 1 +#define R_IRQ_READ1__pa1__WIDTH 1 +#define R_IRQ_READ1__pa1__active 1 +#define R_IRQ_READ1__pa1__inactive 0 +#define R_IRQ_READ1__pa0__BITNR 0 +#define R_IRQ_READ1__pa0__WIDTH 1 +#define R_IRQ_READ1__pa0__active 1 +#define R_IRQ_READ1__pa0__inactive 0 + +#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) +#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 +#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int7__set 1 +#define R_IRQ_MASK1_SET__sw_int7__nop 0 +#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 +#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int6__set 1 +#define R_IRQ_MASK1_SET__sw_int6__nop 0 +#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 +#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int5__set 1 +#define R_IRQ_MASK1_SET__sw_int5__nop 0 +#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 +#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int4__set 1 +#define R_IRQ_MASK1_SET__sw_int4__nop 0 +#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 +#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int3__set 1 +#define R_IRQ_MASK1_SET__sw_int3__nop 0 +#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 +#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int2__set 1 +#define R_IRQ_MASK1_SET__sw_int2__nop 0 +#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 +#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int1__set 1 +#define R_IRQ_MASK1_SET__sw_int1__nop 0 +#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 +#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int0__set 1 +#define R_IRQ_MASK1_SET__sw_int0__nop 0 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 +#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 +#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_peri__set 1 +#define R_IRQ_MASK1_SET__par1_peri__nop 0 +#define R_IRQ_MASK1_SET__par1_data__BITNR 17 +#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_data__set 1 +#define R_IRQ_MASK1_SET__par1_data__nop 0 +#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 +#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_ready__set 1 +#define R_IRQ_MASK1_SET__par1_ready__nop 0 +#define R_IRQ_MASK1_SET__scsi1__BITNR 16 +#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 +#define R_IRQ_MASK1_SET__scsi1__set 1 +#define R_IRQ_MASK1_SET__scsi1__nop 0 +#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser3_ready__set 1 +#define R_IRQ_MASK1_SET__ser3_ready__nop 0 +#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 +#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser3_data__set 1 +#define R_IRQ_MASK1_SET__ser3_data__nop 0 +#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser2_ready__set 1 +#define R_IRQ_MASK1_SET__ser2_ready__nop 0 +#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 +#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser2_data__set 1 +#define R_IRQ_MASK1_SET__ser2_data__nop 0 +#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser1_ready__set 1 +#define R_IRQ_MASK1_SET__ser1_ready__nop 0 +#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 +#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser1_data__set 1 +#define R_IRQ_MASK1_SET__ser1_data__nop 0 +#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser0_ready__set 1 +#define R_IRQ_MASK1_SET__ser0_ready__nop 0 +#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 +#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser0_data__set 1 +#define R_IRQ_MASK1_SET__ser0_data__nop 0 +#define R_IRQ_MASK1_SET__pa7__BITNR 7 +#define R_IRQ_MASK1_SET__pa7__WIDTH 1 +#define R_IRQ_MASK1_SET__pa7__set 1 +#define R_IRQ_MASK1_SET__pa7__nop 0 +#define R_IRQ_MASK1_SET__pa6__BITNR 6 +#define R_IRQ_MASK1_SET__pa6__WIDTH 1 +#define R_IRQ_MASK1_SET__pa6__set 1 +#define R_IRQ_MASK1_SET__pa6__nop 0 +#define R_IRQ_MASK1_SET__pa5__BITNR 5 +#define R_IRQ_MASK1_SET__pa5__WIDTH 1 +#define R_IRQ_MASK1_SET__pa5__set 1 +#define R_IRQ_MASK1_SET__pa5__nop 0 +#define R_IRQ_MASK1_SET__pa4__BITNR 4 +#define R_IRQ_MASK1_SET__pa4__WIDTH 1 +#define R_IRQ_MASK1_SET__pa4__set 1 +#define R_IRQ_MASK1_SET__pa4__nop 0 +#define R_IRQ_MASK1_SET__pa3__BITNR 3 +#define R_IRQ_MASK1_SET__pa3__WIDTH 1 +#define R_IRQ_MASK1_SET__pa3__set 1 +#define R_IRQ_MASK1_SET__pa3__nop 0 +#define R_IRQ_MASK1_SET__pa2__BITNR 2 +#define R_IRQ_MASK1_SET__pa2__WIDTH 1 +#define R_IRQ_MASK1_SET__pa2__set 1 +#define R_IRQ_MASK1_SET__pa2__nop 0 +#define R_IRQ_MASK1_SET__pa1__BITNR 1 +#define R_IRQ_MASK1_SET__pa1__WIDTH 1 +#define R_IRQ_MASK1_SET__pa1__set 1 +#define R_IRQ_MASK1_SET__pa1__nop 0 +#define R_IRQ_MASK1_SET__pa0__BITNR 0 +#define R_IRQ_MASK1_SET__pa0__WIDTH 1 +#define R_IRQ_MASK1_SET__pa0__set 1 +#define R_IRQ_MASK1_SET__pa0__nop 0 + +#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) +#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma9_eop__active 1 +#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma9_descr__active 1 +#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_eop__active 1 +#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma7_eop__active 1 +#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma7_descr__active 1 +#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma6_eop__active 1 +#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma6_descr__active 1 +#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma5_eop__active 1 +#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma5_descr__active 1 +#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma4_eop__active 1 +#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma4_descr__active 1 +#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma3_eop__active 1 +#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma3_descr__active 1 +#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma2_eop__active 1 +#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma2_descr__active 1 +#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma1_eop__active 1 +#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma1_descr__active 1 +#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma0_eop__active 1 +#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma0_descr__active 1 +#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 + +#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 + +#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) +#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 +#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub3_descr__active 1 +#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 +#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub2_descr__active 1 +#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 +#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub1_descr__active 1 +#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 +#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub0_descr__active 1 +#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 +#define R_IRQ_READ2__dma9_eop__BITNR 19 +#define R_IRQ_READ2__dma9_eop__WIDTH 1 +#define R_IRQ_READ2__dma9_eop__active 1 +#define R_IRQ_READ2__dma9_eop__inactive 0 +#define R_IRQ_READ2__dma9_descr__BITNR 18 +#define R_IRQ_READ2__dma9_descr__WIDTH 1 +#define R_IRQ_READ2__dma9_descr__active 1 +#define R_IRQ_READ2__dma9_descr__inactive 0 +#define R_IRQ_READ2__dma8_eop__BITNR 17 +#define R_IRQ_READ2__dma8_eop__WIDTH 1 +#define R_IRQ_READ2__dma8_eop__active 1 +#define R_IRQ_READ2__dma8_eop__inactive 0 +#define R_IRQ_READ2__dma8_descr__BITNR 16 +#define R_IRQ_READ2__dma8_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_descr__active 1 +#define R_IRQ_READ2__dma8_descr__inactive 0 +#define R_IRQ_READ2__dma7_eop__BITNR 15 +#define R_IRQ_READ2__dma7_eop__WIDTH 1 +#define R_IRQ_READ2__dma7_eop__active 1 +#define R_IRQ_READ2__dma7_eop__inactive 0 +#define R_IRQ_READ2__dma7_descr__BITNR 14 +#define R_IRQ_READ2__dma7_descr__WIDTH 1 +#define R_IRQ_READ2__dma7_descr__active 1 +#define R_IRQ_READ2__dma7_descr__inactive 0 +#define R_IRQ_READ2__dma6_eop__BITNR 13 +#define R_IRQ_READ2__dma6_eop__WIDTH 1 +#define R_IRQ_READ2__dma6_eop__active 1 +#define R_IRQ_READ2__dma6_eop__inactive 0 +#define R_IRQ_READ2__dma6_descr__BITNR 12 +#define R_IRQ_READ2__dma6_descr__WIDTH 1 +#define R_IRQ_READ2__dma6_descr__active 1 +#define R_IRQ_READ2__dma6_descr__inactive 0 +#define R_IRQ_READ2__dma5_eop__BITNR 11 +#define R_IRQ_READ2__dma5_eop__WIDTH 1 +#define R_IRQ_READ2__dma5_eop__active 1 +#define R_IRQ_READ2__dma5_eop__inactive 0 +#define R_IRQ_READ2__dma5_descr__BITNR 10 +#define R_IRQ_READ2__dma5_descr__WIDTH 1 +#define R_IRQ_READ2__dma5_descr__active 1 +#define R_IRQ_READ2__dma5_descr__inactive 0 +#define R_IRQ_READ2__dma4_eop__BITNR 9 +#define R_IRQ_READ2__dma4_eop__WIDTH 1 +#define R_IRQ_READ2__dma4_eop__active 1 +#define R_IRQ_READ2__dma4_eop__inactive 0 +#define R_IRQ_READ2__dma4_descr__BITNR 8 +#define R_IRQ_READ2__dma4_descr__WIDTH 1 +#define R_IRQ_READ2__dma4_descr__active 1 +#define R_IRQ_READ2__dma4_descr__inactive 0 +#define R_IRQ_READ2__dma3_eop__BITNR 7 +#define R_IRQ_READ2__dma3_eop__WIDTH 1 +#define R_IRQ_READ2__dma3_eop__active 1 +#define R_IRQ_READ2__dma3_eop__inactive 0 +#define R_IRQ_READ2__dma3_descr__BITNR 6 +#define R_IRQ_READ2__dma3_descr__WIDTH 1 +#define R_IRQ_READ2__dma3_descr__active 1 +#define R_IRQ_READ2__dma3_descr__inactive 0 +#define R_IRQ_READ2__dma2_eop__BITNR 5 +#define R_IRQ_READ2__dma2_eop__WIDTH 1 +#define R_IRQ_READ2__dma2_eop__active 1 +#define R_IRQ_READ2__dma2_eop__inactive 0 +#define R_IRQ_READ2__dma2_descr__BITNR 4 +#define R_IRQ_READ2__dma2_descr__WIDTH 1 +#define R_IRQ_READ2__dma2_descr__active 1 +#define R_IRQ_READ2__dma2_descr__inactive 0 +#define R_IRQ_READ2__dma1_eop__BITNR 3 +#define R_IRQ_READ2__dma1_eop__WIDTH 1 +#define R_IRQ_READ2__dma1_eop__active 1 +#define R_IRQ_READ2__dma1_eop__inactive 0 +#define R_IRQ_READ2__dma1_descr__BITNR 2 +#define R_IRQ_READ2__dma1_descr__WIDTH 1 +#define R_IRQ_READ2__dma1_descr__active 1 +#define R_IRQ_READ2__dma1_descr__inactive 0 +#define R_IRQ_READ2__dma0_eop__BITNR 1 +#define R_IRQ_READ2__dma0_eop__WIDTH 1 +#define R_IRQ_READ2__dma0_eop__active 1 +#define R_IRQ_READ2__dma0_eop__inactive 0 +#define R_IRQ_READ2__dma0_descr__BITNR 0 +#define R_IRQ_READ2__dma0_descr__WIDTH 1 +#define R_IRQ_READ2__dma0_descr__active 1 +#define R_IRQ_READ2__dma0_descr__inactive 0 + +#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) +#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 +#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma9_eop__set 1 +#define R_IRQ_MASK2_SET__dma9_eop__nop 0 +#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma9_descr__set 1 +#define R_IRQ_MASK2_SET__dma9_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_eop__set 1 +#define R_IRQ_MASK2_SET__dma8_eop__nop 0 +#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_descr__nop 0 +#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma7_eop__set 1 +#define R_IRQ_MASK2_SET__dma7_eop__nop 0 +#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma7_descr__set 1 +#define R_IRQ_MASK2_SET__dma7_descr__nop 0 +#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma6_eop__set 1 +#define R_IRQ_MASK2_SET__dma6_eop__nop 0 +#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma6_descr__set 1 +#define R_IRQ_MASK2_SET__dma6_descr__nop 0 +#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma5_eop__set 1 +#define R_IRQ_MASK2_SET__dma5_eop__nop 0 +#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma5_descr__set 1 +#define R_IRQ_MASK2_SET__dma5_descr__nop 0 +#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma4_eop__set 1 +#define R_IRQ_MASK2_SET__dma4_eop__nop 0 +#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma4_descr__set 1 +#define R_IRQ_MASK2_SET__dma4_descr__nop 0 +#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma3_eop__set 1 +#define R_IRQ_MASK2_SET__dma3_eop__nop 0 +#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma3_descr__set 1 +#define R_IRQ_MASK2_SET__dma3_descr__nop 0 +#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma2_eop__set 1 +#define R_IRQ_MASK2_SET__dma2_eop__nop 0 +#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma2_descr__set 1 +#define R_IRQ_MASK2_SET__dma2_descr__nop 0 +#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma1_eop__set 1 +#define R_IRQ_MASK2_SET__dma1_eop__nop 0 +#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma1_descr__set 1 +#define R_IRQ_MASK2_SET__dma1_descr__nop 0 +#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma0_eop__set 1 +#define R_IRQ_MASK2_SET__dma0_eop__nop 0 +#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma0_descr__set 1 +#define R_IRQ_MASK2_SET__dma0_descr__nop 0 + +#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) +#define R_VECT_MASK_RD__usb__BITNR 31 +#define R_VECT_MASK_RD__usb__WIDTH 1 +#define R_VECT_MASK_RD__usb__active 1 +#define R_VECT_MASK_RD__usb__inactive 0 +#define R_VECT_MASK_RD__dma9__BITNR 25 +#define R_VECT_MASK_RD__dma9__WIDTH 1 +#define R_VECT_MASK_RD__dma9__active 1 +#define R_VECT_MASK_RD__dma9__inactive 0 +#define R_VECT_MASK_RD__dma8__BITNR 24 +#define R_VECT_MASK_RD__dma8__WIDTH 1 +#define R_VECT_MASK_RD__dma8__active 1 +#define R_VECT_MASK_RD__dma8__inactive 0 +#define R_VECT_MASK_RD__dma7__BITNR 23 +#define R_VECT_MASK_RD__dma7__WIDTH 1 +#define R_VECT_MASK_RD__dma7__active 1 +#define R_VECT_MASK_RD__dma7__inactive 0 +#define R_VECT_MASK_RD__dma6__BITNR 22 +#define R_VECT_MASK_RD__dma6__WIDTH 1 +#define R_VECT_MASK_RD__dma6__active 1 +#define R_VECT_MASK_RD__dma6__inactive 0 +#define R_VECT_MASK_RD__dma5__BITNR 21 +#define R_VECT_MASK_RD__dma5__WIDTH 1 +#define R_VECT_MASK_RD__dma5__active 1 +#define R_VECT_MASK_RD__dma5__inactive 0 +#define R_VECT_MASK_RD__dma4__BITNR 20 +#define R_VECT_MASK_RD__dma4__WIDTH 1 +#define R_VECT_MASK_RD__dma4__active 1 +#define R_VECT_MASK_RD__dma4__inactive 0 +#define R_VECT_MASK_RD__dma3__BITNR 19 +#define R_VECT_MASK_RD__dma3__WIDTH 1 +#define R_VECT_MASK_RD__dma3__active 1 +#define R_VECT_MASK_RD__dma3__inactive 0 +#define R_VECT_MASK_RD__dma2__BITNR 18 +#define R_VECT_MASK_RD__dma2__WIDTH 1 +#define R_VECT_MASK_RD__dma2__active 1 +#define R_VECT_MASK_RD__dma2__inactive 0 +#define R_VECT_MASK_RD__dma1__BITNR 17 +#define R_VECT_MASK_RD__dma1__WIDTH 1 +#define R_VECT_MASK_RD__dma1__active 1 +#define R_VECT_MASK_RD__dma1__inactive 0 +#define R_VECT_MASK_RD__dma0__BITNR 16 +#define R_VECT_MASK_RD__dma0__WIDTH 1 +#define R_VECT_MASK_RD__dma0__active 1 +#define R_VECT_MASK_RD__dma0__inactive 0 +#define R_VECT_MASK_RD__ext_dma1__BITNR 13 +#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 +#define R_VECT_MASK_RD__ext_dma1__active 1 +#define R_VECT_MASK_RD__ext_dma1__inactive 0 +#define R_VECT_MASK_RD__ext_dma0__BITNR 12 +#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 +#define R_VECT_MASK_RD__ext_dma0__active 1 +#define R_VECT_MASK_RD__ext_dma0__inactive 0 +#define R_VECT_MASK_RD__pa__BITNR 11 +#define R_VECT_MASK_RD__pa__WIDTH 1 +#define R_VECT_MASK_RD__pa__active 1 +#define R_VECT_MASK_RD__pa__inactive 0 +#define R_VECT_MASK_RD__irq_intnr__BITNR 10 +#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 +#define R_VECT_MASK_RD__irq_intnr__active 1 +#define R_VECT_MASK_RD__irq_intnr__inactive 0 +#define R_VECT_MASK_RD__sw__BITNR 9 +#define R_VECT_MASK_RD__sw__WIDTH 1 +#define R_VECT_MASK_RD__sw__active 1 +#define R_VECT_MASK_RD__sw__inactive 0 +#define R_VECT_MASK_RD__serial__BITNR 8 +#define R_VECT_MASK_RD__serial__WIDTH 1 +#define R_VECT_MASK_RD__serial__active 1 +#define R_VECT_MASK_RD__serial__inactive 0 +#define R_VECT_MASK_RD__snmp__BITNR 7 +#define R_VECT_MASK_RD__snmp__WIDTH 1 +#define R_VECT_MASK_RD__snmp__active 1 +#define R_VECT_MASK_RD__snmp__inactive 0 +#define R_VECT_MASK_RD__network__BITNR 6 +#define R_VECT_MASK_RD__network__WIDTH 1 +#define R_VECT_MASK_RD__network__active 1 +#define R_VECT_MASK_RD__network__inactive 0 +#define R_VECT_MASK_RD__scsi1__BITNR 5 +#define R_VECT_MASK_RD__scsi1__WIDTH 1 +#define R_VECT_MASK_RD__scsi1__active 1 +#define R_VECT_MASK_RD__scsi1__inactive 0 +#define R_VECT_MASK_RD__par1__BITNR 5 +#define R_VECT_MASK_RD__par1__WIDTH 1 +#define R_VECT_MASK_RD__par1__active 1 +#define R_VECT_MASK_RD__par1__inactive 0 +#define R_VECT_MASK_RD__scsi0__BITNR 4 +#define R_VECT_MASK_RD__scsi0__WIDTH 1 +#define R_VECT_MASK_RD__scsi0__active 1 +#define R_VECT_MASK_RD__scsi0__inactive 0 +#define R_VECT_MASK_RD__par0__BITNR 4 +#define R_VECT_MASK_RD__par0__WIDTH 1 +#define R_VECT_MASK_RD__par0__active 1 +#define R_VECT_MASK_RD__par0__inactive 0 +#define R_VECT_MASK_RD__ata__BITNR 4 +#define R_VECT_MASK_RD__ata__WIDTH 1 +#define R_VECT_MASK_RD__ata__active 1 +#define R_VECT_MASK_RD__ata__inactive 0 +#define R_VECT_MASK_RD__mio__BITNR 4 +#define R_VECT_MASK_RD__mio__WIDTH 1 +#define R_VECT_MASK_RD__mio__active 1 +#define R_VECT_MASK_RD__mio__inactive 0 +#define R_VECT_MASK_RD__timer1__BITNR 3 +#define R_VECT_MASK_RD__timer1__WIDTH 1 +#define R_VECT_MASK_RD__timer1__active 1 +#define R_VECT_MASK_RD__timer1__inactive 0 +#define R_VECT_MASK_RD__timer0__BITNR 2 +#define R_VECT_MASK_RD__timer0__WIDTH 1 +#define R_VECT_MASK_RD__timer0__active 1 +#define R_VECT_MASK_RD__timer0__inactive 0 +#define R_VECT_MASK_RD__nmi__BITNR 1 +#define R_VECT_MASK_RD__nmi__WIDTH 1 +#define R_VECT_MASK_RD__nmi__active 1 +#define R_VECT_MASK_RD__nmi__inactive 0 +#define R_VECT_MASK_RD__some__BITNR 0 +#define R_VECT_MASK_RD__some__WIDTH 1 +#define R_VECT_MASK_RD__some__active 1 +#define R_VECT_MASK_RD__some__inactive 0 + +#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) +#define R_VECT_MASK_CLR__usb__BITNR 31 +#define R_VECT_MASK_CLR__usb__WIDTH 1 +#define R_VECT_MASK_CLR__usb__clr 1 +#define R_VECT_MASK_CLR__usb__nop 0 +#define R_VECT_MASK_CLR__dma9__BITNR 25 +#define R_VECT_MASK_CLR__dma9__WIDTH 1 +#define R_VECT_MASK_CLR__dma9__clr 1 +#define R_VECT_MASK_CLR__dma9__nop 0 +#define R_VECT_MASK_CLR__dma8__BITNR 24 +#define R_VECT_MASK_CLR__dma8__WIDTH 1 +#define R_VECT_MASK_CLR__dma8__clr 1 +#define R_VECT_MASK_CLR__dma8__nop 0 +#define R_VECT_MASK_CLR__dma7__BITNR 23 +#define R_VECT_MASK_CLR__dma7__WIDTH 1 +#define R_VECT_MASK_CLR__dma7__clr 1 +#define R_VECT_MASK_CLR__dma7__nop 0 +#define R_VECT_MASK_CLR__dma6__BITNR 22 +#define R_VECT_MASK_CLR__dma6__WIDTH 1 +#define R_VECT_MASK_CLR__dma6__clr 1 +#define R_VECT_MASK_CLR__dma6__nop 0 +#define R_VECT_MASK_CLR__dma5__BITNR 21 +#define R_VECT_MASK_CLR__dma5__WIDTH 1 +#define R_VECT_MASK_CLR__dma5__clr 1 +#define R_VECT_MASK_CLR__dma5__nop 0 +#define R_VECT_MASK_CLR__dma4__BITNR 20 +#define R_VECT_MASK_CLR__dma4__WIDTH 1 +#define R_VECT_MASK_CLR__dma4__clr 1 +#define R_VECT_MASK_CLR__dma4__nop 0 +#define R_VECT_MASK_CLR__dma3__BITNR 19 +#define R_VECT_MASK_CLR__dma3__WIDTH 1 +#define R_VECT_MASK_CLR__dma3__clr 1 +#define R_VECT_MASK_CLR__dma3__nop 0 +#define R_VECT_MASK_CLR__dma2__BITNR 18 +#define R_VECT_MASK_CLR__dma2__WIDTH 1 +#define R_VECT_MASK_CLR__dma2__clr 1 +#define R_VECT_MASK_CLR__dma2__nop 0 +#define R_VECT_MASK_CLR__dma1__BITNR 17 +#define R_VECT_MASK_CLR__dma1__WIDTH 1 +#define R_VECT_MASK_CLR__dma1__clr 1 +#define R_VECT_MASK_CLR__dma1__nop 0 +#define R_VECT_MASK_CLR__dma0__BITNR 16 +#define R_VECT_MASK_CLR__dma0__WIDTH 1 +#define R_VECT_MASK_CLR__dma0__clr 1 +#define R_VECT_MASK_CLR__dma0__nop 0 +#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 +#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 +#define R_VECT_MASK_CLR__ext_dma1__clr 1 +#define R_VECT_MASK_CLR__ext_dma1__nop 0 +#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 +#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 +#define R_VECT_MASK_CLR__ext_dma0__clr 1 +#define R_VECT_MASK_CLR__ext_dma0__nop 0 +#define R_VECT_MASK_CLR__pa__BITNR 11 +#define R_VECT_MASK_CLR__pa__WIDTH 1 +#define R_VECT_MASK_CLR__pa__clr 1 +#define R_VECT_MASK_CLR__pa__nop 0 +#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 +#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 +#define R_VECT_MASK_CLR__irq_intnr__clr 1 +#define R_VECT_MASK_CLR__irq_intnr__nop 0 +#define R_VECT_MASK_CLR__sw__BITNR 9 +#define R_VECT_MASK_CLR__sw__WIDTH 1 +#define R_VECT_MASK_CLR__sw__clr 1 +#define R_VECT_MASK_CLR__sw__nop 0 +#define R_VECT_MASK_CLR__serial__BITNR 8 +#define R_VECT_MASK_CLR__serial__WIDTH 1 +#define R_VECT_MASK_CLR__serial__clr 1 +#define R_VECT_MASK_CLR__serial__nop 0 +#define R_VECT_MASK_CLR__snmp__BITNR 7 +#define R_VECT_MASK_CLR__snmp__WIDTH 1 +#define R_VECT_MASK_CLR__snmp__clr 1 +#define R_VECT_MASK_CLR__snmp__nop 0 +#define R_VECT_MASK_CLR__network__BITNR 6 +#define R_VECT_MASK_CLR__network__WIDTH 1 +#define R_VECT_MASK_CLR__network__clr 1 +#define R_VECT_MASK_CLR__network__nop 0 +#define R_VECT_MASK_CLR__scsi1__BITNR 5 +#define R_VECT_MASK_CLR__scsi1__WIDTH 1 +#define R_VECT_MASK_CLR__scsi1__clr 1 +#define R_VECT_MASK_CLR__scsi1__nop 0 +#define R_VECT_MASK_CLR__par1__BITNR 5 +#define R_VECT_MASK_CLR__par1__WIDTH 1 +#define R_VECT_MASK_CLR__par1__clr 1 +#define R_VECT_MASK_CLR__par1__nop 0 +#define R_VECT_MASK_CLR__scsi0__BITNR 4 +#define R_VECT_MASK_CLR__scsi0__WIDTH 1 +#define R_VECT_MASK_CLR__scsi0__clr 1 +#define R_VECT_MASK_CLR__scsi0__nop 0 +#define R_VECT_MASK_CLR__par0__BITNR 4 +#define R_VECT_MASK_CLR__par0__WIDTH 1 +#define R_VECT_MASK_CLR__par0__clr 1 +#define R_VECT_MASK_CLR__par0__nop 0 +#define R_VECT_MASK_CLR__ata__BITNR 4 +#define R_VECT_MASK_CLR__ata__WIDTH 1 +#define R_VECT_MASK_CLR__ata__clr 1 +#define R_VECT_MASK_CLR__ata__nop 0 +#define R_VECT_MASK_CLR__mio__BITNR 4 +#define R_VECT_MASK_CLR__mio__WIDTH 1 +#define R_VECT_MASK_CLR__mio__clr 1 +#define R_VECT_MASK_CLR__mio__nop 0 +#define R_VECT_MASK_CLR__timer1__BITNR 3 +#define R_VECT_MASK_CLR__timer1__WIDTH 1 +#define R_VECT_MASK_CLR__timer1__clr 1 +#define R_VECT_MASK_CLR__timer1__nop 0 +#define R_VECT_MASK_CLR__timer0__BITNR 2 +#define R_VECT_MASK_CLR__timer0__WIDTH 1 +#define R_VECT_MASK_CLR__timer0__clr 1 +#define R_VECT_MASK_CLR__timer0__nop 0 +#define R_VECT_MASK_CLR__nmi__BITNR 1 +#define R_VECT_MASK_CLR__nmi__WIDTH 1 +#define R_VECT_MASK_CLR__nmi__clr 1 +#define R_VECT_MASK_CLR__nmi__nop 0 +#define R_VECT_MASK_CLR__some__BITNR 0 +#define R_VECT_MASK_CLR__some__WIDTH 1 +#define R_VECT_MASK_CLR__some__clr 1 +#define R_VECT_MASK_CLR__some__nop 0 + +#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) +#define R_VECT_READ__usb__BITNR 31 +#define R_VECT_READ__usb__WIDTH 1 +#define R_VECT_READ__usb__active 1 +#define R_VECT_READ__usb__inactive 0 +#define R_VECT_READ__dma9__BITNR 25 +#define R_VECT_READ__dma9__WIDTH 1 +#define R_VECT_READ__dma9__active 1 +#define R_VECT_READ__dma9__inactive 0 +#define R_VECT_READ__dma8__BITNR 24 +#define R_VECT_READ__dma8__WIDTH 1 +#define R_VECT_READ__dma8__active 1 +#define R_VECT_READ__dma8__inactive 0 +#define R_VECT_READ__dma7__BITNR 23 +#define R_VECT_READ__dma7__WIDTH 1 +#define R_VECT_READ__dma7__active 1 +#define R_VECT_READ__dma7__inactive 0 +#define R_VECT_READ__dma6__BITNR 22 +#define R_VECT_READ__dma6__WIDTH 1 +#define R_VECT_READ__dma6__active 1 +#define R_VECT_READ__dma6__inactive 0 +#define R_VECT_READ__dma5__BITNR 21 +#define R_VECT_READ__dma5__WIDTH 1 +#define R_VECT_READ__dma5__active 1 +#define R_VECT_READ__dma5__inactive 0 +#define R_VECT_READ__dma4__BITNR 20 +#define R_VECT_READ__dma4__WIDTH 1 +#define R_VECT_READ__dma4__active 1 +#define R_VECT_READ__dma4__inactive 0 +#define R_VECT_READ__dma3__BITNR 19 +#define R_VECT_READ__dma3__WIDTH 1 +#define R_VECT_READ__dma3__active 1 +#define R_VECT_READ__dma3__inactive 0 +#define R_VECT_READ__dma2__BITNR 18 +#define R_VECT_READ__dma2__WIDTH 1 +#define R_VECT_READ__dma2__active 1 +#define R_VECT_READ__dma2__inactive 0 +#define R_VECT_READ__dma1__BITNR 17 +#define R_VECT_READ__dma1__WIDTH 1 +#define R_VECT_READ__dma1__active 1 +#define R_VECT_READ__dma1__inactive 0 +#define R_VECT_READ__dma0__BITNR 16 +#define R_VECT_READ__dma0__WIDTH 1 +#define R_VECT_READ__dma0__active 1 +#define R_VECT_READ__dma0__inactive 0 +#define R_VECT_READ__ext_dma1__BITNR 13 +#define R_VECT_READ__ext_dma1__WIDTH 1 +#define R_VECT_READ__ext_dma1__active 1 +#define R_VECT_READ__ext_dma1__inactive 0 +#define R_VECT_READ__ext_dma0__BITNR 12 +#define R_VECT_READ__ext_dma0__WIDTH 1 +#define R_VECT_READ__ext_dma0__active 1 +#define R_VECT_READ__ext_dma0__inactive 0 +#define R_VECT_READ__pa__BITNR 11 +#define R_VECT_READ__pa__WIDTH 1 +#define R_VECT_READ__pa__active 1 +#define R_VECT_READ__pa__inactive 0 +#define R_VECT_READ__irq_intnr__BITNR 10 +#define R_VECT_READ__irq_intnr__WIDTH 1 +#define R_VECT_READ__irq_intnr__active 1 +#define R_VECT_READ__irq_intnr__inactive 0 +#define R_VECT_READ__sw__BITNR 9 +#define R_VECT_READ__sw__WIDTH 1 +#define R_VECT_READ__sw__active 1 +#define R_VECT_READ__sw__inactive 0 +#define R_VECT_READ__serial__BITNR 8 +#define R_VECT_READ__serial__WIDTH 1 +#define R_VECT_READ__serial__active 1 +#define R_VECT_READ__serial__inactive 0 +#define R_VECT_READ__snmp__BITNR 7 +#define R_VECT_READ__snmp__WIDTH 1 +#define R_VECT_READ__snmp__active 1 +#define R_VECT_READ__snmp__inactive 0 +#define R_VECT_READ__network__BITNR 6 +#define R_VECT_READ__network__WIDTH 1 +#define R_VECT_READ__network__active 1 +#define R_VECT_READ__network__inactive 0 +#define R_VECT_READ__scsi1__BITNR 5 +#define R_VECT_READ__scsi1__WIDTH 1 +#define R_VECT_READ__scsi1__active 1 +#define R_VECT_READ__scsi1__inactive 0 +#define R_VECT_READ__par1__BITNR 5 +#define R_VECT_READ__par1__WIDTH 1 +#define R_VECT_READ__par1__active 1 +#define R_VECT_READ__par1__inactive 0 +#define R_VECT_READ__scsi0__BITNR 4 +#define R_VECT_READ__scsi0__WIDTH 1 +#define R_VECT_READ__scsi0__active 1 +#define R_VECT_READ__scsi0__inactive 0 +#define R_VECT_READ__par0__BITNR 4 +#define R_VECT_READ__par0__WIDTH 1 +#define R_VECT_READ__par0__active 1 +#define R_VECT_READ__par0__inactive 0 +#define R_VECT_READ__ata__BITNR 4 +#define R_VECT_READ__ata__WIDTH 1 +#define R_VECT_READ__ata__active 1 +#define R_VECT_READ__ata__inactive 0 +#define R_VECT_READ__mio__BITNR 4 +#define R_VECT_READ__mio__WIDTH 1 +#define R_VECT_READ__mio__active 1 +#define R_VECT_READ__mio__inactive 0 +#define R_VECT_READ__timer1__BITNR 3 +#define R_VECT_READ__timer1__WIDTH 1 +#define R_VECT_READ__timer1__active 1 +#define R_VECT_READ__timer1__inactive 0 +#define R_VECT_READ__timer0__BITNR 2 +#define R_VECT_READ__timer0__WIDTH 1 +#define R_VECT_READ__timer0__active 1 +#define R_VECT_READ__timer0__inactive 0 +#define R_VECT_READ__nmi__BITNR 1 +#define R_VECT_READ__nmi__WIDTH 1 +#define R_VECT_READ__nmi__active 1 +#define R_VECT_READ__nmi__inactive 0 +#define R_VECT_READ__some__BITNR 0 +#define R_VECT_READ__some__WIDTH 1 +#define R_VECT_READ__some__active 1 +#define R_VECT_READ__some__inactive 0 + +#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) +#define R_VECT_MASK_SET__usb__BITNR 31 +#define R_VECT_MASK_SET__usb__WIDTH 1 +#define R_VECT_MASK_SET__usb__set 1 +#define R_VECT_MASK_SET__usb__nop 0 +#define R_VECT_MASK_SET__dma9__BITNR 25 +#define R_VECT_MASK_SET__dma9__WIDTH 1 +#define R_VECT_MASK_SET__dma9__set 1 +#define R_VECT_MASK_SET__dma9__nop 0 +#define R_VECT_MASK_SET__dma8__BITNR 24 +#define R_VECT_MASK_SET__dma8__WIDTH 1 +#define R_VECT_MASK_SET__dma8__set 1 +#define R_VECT_MASK_SET__dma8__nop 0 +#define R_VECT_MASK_SET__dma7__BITNR 23 +#define R_VECT_MASK_SET__dma7__WIDTH 1 +#define R_VECT_MASK_SET__dma7__set 1 +#define R_VECT_MASK_SET__dma7__nop 0 +#define R_VECT_MASK_SET__dma6__BITNR 22 +#define R_VECT_MASK_SET__dma6__WIDTH 1 +#define R_VECT_MASK_SET__dma6__set 1 +#define R_VECT_MASK_SET__dma6__nop 0 +#define R_VECT_MASK_SET__dma5__BITNR 21 +#define R_VECT_MASK_SET__dma5__WIDTH 1 +#define R_VECT_MASK_SET__dma5__set 1 +#define R_VECT_MASK_SET__dma5__nop 0 +#define R_VECT_MASK_SET__dma4__BITNR 20 +#define R_VECT_MASK_SET__dma4__WIDTH 1 +#define R_VECT_MASK_SET__dma4__set 1 +#define R_VECT_MASK_SET__dma4__nop 0 +#define R_VECT_MASK_SET__dma3__BITNR 19 +#define R_VECT_MASK_SET__dma3__WIDTH 1 +#define R_VECT_MASK_SET__dma3__set 1 +#define R_VECT_MASK_SET__dma3__nop 0 +#define R_VECT_MASK_SET__dma2__BITNR 18 +#define R_VECT_MASK_SET__dma2__WIDTH 1 +#define R_VECT_MASK_SET__dma2__set 1 +#define R_VECT_MASK_SET__dma2__nop 0 +#define R_VECT_MASK_SET__dma1__BITNR 17 +#define R_VECT_MASK_SET__dma1__WIDTH 1 +#define R_VECT_MASK_SET__dma1__set 1 +#define R_VECT_MASK_SET__dma1__nop 0 +#define R_VECT_MASK_SET__dma0__BITNR 16 +#define R_VECT_MASK_SET__dma0__WIDTH 1 +#define R_VECT_MASK_SET__dma0__set 1 +#define R_VECT_MASK_SET__dma0__nop 0 +#define R_VECT_MASK_SET__ext_dma1__BITNR 13 +#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 +#define R_VECT_MASK_SET__ext_dma1__set 1 +#define R_VECT_MASK_SET__ext_dma1__nop 0 +#define R_VECT_MASK_SET__ext_dma0__BITNR 12 +#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 +#define R_VECT_MASK_SET__ext_dma0__set 1 +#define R_VECT_MASK_SET__ext_dma0__nop 0 +#define R_VECT_MASK_SET__pa__BITNR 11 +#define R_VECT_MASK_SET__pa__WIDTH 1 +#define R_VECT_MASK_SET__pa__set 1 +#define R_VECT_MASK_SET__pa__nop 0 +#define R_VECT_MASK_SET__irq_intnr__BITNR 10 +#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 +#define R_VECT_MASK_SET__irq_intnr__set 1 +#define R_VECT_MASK_SET__irq_intnr__nop 0 +#define R_VECT_MASK_SET__sw__BITNR 9 +#define R_VECT_MASK_SET__sw__WIDTH 1 +#define R_VECT_MASK_SET__sw__set 1 +#define R_VECT_MASK_SET__sw__nop 0 +#define R_VECT_MASK_SET__serial__BITNR 8 +#define R_VECT_MASK_SET__serial__WIDTH 1 +#define R_VECT_MASK_SET__serial__set 1 +#define R_VECT_MASK_SET__serial__nop 0 +#define R_VECT_MASK_SET__snmp__BITNR 7 +#define R_VECT_MASK_SET__snmp__WIDTH 1 +#define R_VECT_MASK_SET__snmp__set 1 +#define R_VECT_MASK_SET__snmp__nop 0 +#define R_VECT_MASK_SET__network__BITNR 6 +#define R_VECT_MASK_SET__network__WIDTH 1 +#define R_VECT_MASK_SET__network__set 1 +#define R_VECT_MASK_SET__network__nop 0 +#define R_VECT_MASK_SET__scsi1__BITNR 5 +#define R_VECT_MASK_SET__scsi1__WIDTH 1 +#define R_VECT_MASK_SET__scsi1__set 1 +#define R_VECT_MASK_SET__scsi1__nop 0 +#define R_VECT_MASK_SET__par1__BITNR 5 +#define R_VECT_MASK_SET__par1__WIDTH 1 +#define R_VECT_MASK_SET__par1__set 1 +#define R_VECT_MASK_SET__par1__nop 0 +#define R_VECT_MASK_SET__scsi0__BITNR 4 +#define R_VECT_MASK_SET__scsi0__WIDTH 1 +#define R_VECT_MASK_SET__scsi0__set 1 +#define R_VECT_MASK_SET__scsi0__nop 0 +#define R_VECT_MASK_SET__par0__BITNR 4 +#define R_VECT_MASK_SET__par0__WIDTH 1 +#define R_VECT_MASK_SET__par0__set 1 +#define R_VECT_MASK_SET__par0__nop 0 +#define R_VECT_MASK_SET__ata__BITNR 4 +#define R_VECT_MASK_SET__ata__WIDTH 1 +#define R_VECT_MASK_SET__ata__set 1 +#define R_VECT_MASK_SET__ata__nop 0 +#define R_VECT_MASK_SET__mio__BITNR 4 +#define R_VECT_MASK_SET__mio__WIDTH 1 +#define R_VECT_MASK_SET__mio__set 1 +#define R_VECT_MASK_SET__mio__nop 0 +#define R_VECT_MASK_SET__timer1__BITNR 3 +#define R_VECT_MASK_SET__timer1__WIDTH 1 +#define R_VECT_MASK_SET__timer1__set 1 +#define R_VECT_MASK_SET__timer1__nop 0 +#define R_VECT_MASK_SET__timer0__BITNR 2 +#define R_VECT_MASK_SET__timer0__WIDTH 1 +#define R_VECT_MASK_SET__timer0__set 1 +#define R_VECT_MASK_SET__timer0__nop 0 +#define R_VECT_MASK_SET__nmi__BITNR 1 +#define R_VECT_MASK_SET__nmi__WIDTH 1 +#define R_VECT_MASK_SET__nmi__set 1 +#define R_VECT_MASK_SET__nmi__nop 0 +#define R_VECT_MASK_SET__some__BITNR 0 +#define R_VECT_MASK_SET__some__WIDTH 1 +#define R_VECT_MASK_SET__some__set 1 +#define R_VECT_MASK_SET__some__nop 0 + +/* +!* DMA registers +!*/ + +#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) +#define R_SET_EOP__ch9_eop__BITNR 3 +#define R_SET_EOP__ch9_eop__WIDTH 1 +#define R_SET_EOP__ch9_eop__set 1 +#define R_SET_EOP__ch9_eop__nop 0 +#define R_SET_EOP__ch7_eop__BITNR 2 +#define R_SET_EOP__ch7_eop__WIDTH 1 +#define R_SET_EOP__ch7_eop__set 1 +#define R_SET_EOP__ch7_eop__nop 0 +#define R_SET_EOP__ch5_eop__BITNR 1 +#define R_SET_EOP__ch5_eop__WIDTH 1 +#define R_SET_EOP__ch5_eop__set 1 +#define R_SET_EOP__ch5_eop__nop 0 +#define R_SET_EOP__ch3_eop__BITNR 0 +#define R_SET_EOP__ch3_eop__WIDTH 1 +#define R_SET_EOP__ch3_eop__set 1 +#define R_SET_EOP__ch3_eop__nop 0 + +#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) +#define R_DMA_CH0_HWSW__hw__BITNR 16 +#define R_DMA_CH0_HWSW__hw__WIDTH 16 +#define R_DMA_CH0_HWSW__sw__BITNR 0 +#define R_DMA_CH0_HWSW__sw__WIDTH 16 + +#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) +#define R_DMA_CH0_DESCR__descr__BITNR 0 +#define R_DMA_CH0_DESCR__descr__WIDTH 32 + +#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) +#define R_DMA_CH0_NEXT__next__BITNR 0 +#define R_DMA_CH0_NEXT__next__WIDTH 32 + +#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) +#define R_DMA_CH0_BUF__buf__BITNR 0 +#define R_DMA_CH0_BUF__buf__WIDTH 32 + +#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) +#define R_DMA_CH0_FIRST__first__BITNR 0 +#define R_DMA_CH0_FIRST__first__WIDTH 32 + +#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) +#define R_DMA_CH0_CMD__cmd__BITNR 0 +#define R_DMA_CH0_CMD__cmd__WIDTH 3 +#define R_DMA_CH0_CMD__cmd__hold 0 +#define R_DMA_CH0_CMD__cmd__start 1 +#define R_DMA_CH0_CMD__cmd__restart 3 +#define R_DMA_CH0_CMD__cmd__continue 3 +#define R_DMA_CH0_CMD__cmd__reset 4 + +#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) +#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) +#define R_DMA_CH0_STATUS__avail__BITNR 0 +#define R_DMA_CH0_STATUS__avail__WIDTH 7 + +#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) +#define R_DMA_CH1_HWSW__hw__BITNR 16 +#define R_DMA_CH1_HWSW__hw__WIDTH 16 +#define R_DMA_CH1_HWSW__sw__BITNR 0 +#define R_DMA_CH1_HWSW__sw__WIDTH 16 + +#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) +#define R_DMA_CH1_DESCR__descr__BITNR 0 +#define R_DMA_CH1_DESCR__descr__WIDTH 32 + +#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) +#define R_DMA_CH1_NEXT__next__BITNR 0 +#define R_DMA_CH1_NEXT__next__WIDTH 32 + +#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) +#define R_DMA_CH1_BUF__buf__BITNR 0 +#define R_DMA_CH1_BUF__buf__WIDTH 32 + +#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) +#define R_DMA_CH1_FIRST__first__BITNR 0 +#define R_DMA_CH1_FIRST__first__WIDTH 32 + +#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) +#define R_DMA_CH1_CMD__cmd__BITNR 0 +#define R_DMA_CH1_CMD__cmd__WIDTH 3 +#define R_DMA_CH1_CMD__cmd__hold 0 +#define R_DMA_CH1_CMD__cmd__start 1 +#define R_DMA_CH1_CMD__cmd__restart 3 +#define R_DMA_CH1_CMD__cmd__continue 3 +#define R_DMA_CH1_CMD__cmd__reset 4 + +#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) +#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) +#define R_DMA_CH1_STATUS__avail__BITNR 0 +#define R_DMA_CH1_STATUS__avail__WIDTH 7 + +#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) +#define R_DMA_CH2_HWSW__hw__BITNR 16 +#define R_DMA_CH2_HWSW__hw__WIDTH 16 +#define R_DMA_CH2_HWSW__sw__BITNR 0 +#define R_DMA_CH2_HWSW__sw__WIDTH 16 + +#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) +#define R_DMA_CH2_DESCR__descr__BITNR 0 +#define R_DMA_CH2_DESCR__descr__WIDTH 32 + +#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) +#define R_DMA_CH2_NEXT__next__BITNR 0 +#define R_DMA_CH2_NEXT__next__WIDTH 32 + +#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) +#define R_DMA_CH2_BUF__buf__BITNR 0 +#define R_DMA_CH2_BUF__buf__WIDTH 32 + +#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) +#define R_DMA_CH2_FIRST__first__BITNR 0 +#define R_DMA_CH2_FIRST__first__WIDTH 32 + +#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) +#define R_DMA_CH2_CMD__cmd__BITNR 0 +#define R_DMA_CH2_CMD__cmd__WIDTH 3 +#define R_DMA_CH2_CMD__cmd__hold 0 +#define R_DMA_CH2_CMD__cmd__start 1 +#define R_DMA_CH2_CMD__cmd__restart 3 +#define R_DMA_CH2_CMD__cmd__continue 3 +#define R_DMA_CH2_CMD__cmd__reset 4 + +#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) +#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) +#define R_DMA_CH2_STATUS__avail__BITNR 0 +#define R_DMA_CH2_STATUS__avail__WIDTH 7 + +#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) +#define R_DMA_CH3_HWSW__hw__BITNR 16 +#define R_DMA_CH3_HWSW__hw__WIDTH 16 +#define R_DMA_CH3_HWSW__sw__BITNR 0 +#define R_DMA_CH3_HWSW__sw__WIDTH 16 + +#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) +#define R_DMA_CH3_DESCR__descr__BITNR 0 +#define R_DMA_CH3_DESCR__descr__WIDTH 32 + +#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) +#define R_DMA_CH3_NEXT__next__BITNR 0 +#define R_DMA_CH3_NEXT__next__WIDTH 32 + +#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) +#define R_DMA_CH3_BUF__buf__BITNR 0 +#define R_DMA_CH3_BUF__buf__WIDTH 32 + +#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) +#define R_DMA_CH3_FIRST__first__BITNR 0 +#define R_DMA_CH3_FIRST__first__WIDTH 32 + +#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) +#define R_DMA_CH3_CMD__cmd__BITNR 0 +#define R_DMA_CH3_CMD__cmd__WIDTH 3 +#define R_DMA_CH3_CMD__cmd__hold 0 +#define R_DMA_CH3_CMD__cmd__start 1 +#define R_DMA_CH3_CMD__cmd__restart 3 +#define R_DMA_CH3_CMD__cmd__continue 3 +#define R_DMA_CH3_CMD__cmd__reset 4 + +#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) +#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) +#define R_DMA_CH3_STATUS__avail__BITNR 0 +#define R_DMA_CH3_STATUS__avail__WIDTH 7 + +#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) +#define R_DMA_CH4_HWSW__hw__BITNR 16 +#define R_DMA_CH4_HWSW__hw__WIDTH 16 +#define R_DMA_CH4_HWSW__sw__BITNR 0 +#define R_DMA_CH4_HWSW__sw__WIDTH 16 + +#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) +#define R_DMA_CH4_DESCR__descr__BITNR 0 +#define R_DMA_CH4_DESCR__descr__WIDTH 32 + +#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) +#define R_DMA_CH4_NEXT__next__BITNR 0 +#define R_DMA_CH4_NEXT__next__WIDTH 32 + +#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) +#define R_DMA_CH4_BUF__buf__BITNR 0 +#define R_DMA_CH4_BUF__buf__WIDTH 32 + +#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) +#define R_DMA_CH4_FIRST__first__BITNR 0 +#define R_DMA_CH4_FIRST__first__WIDTH 32 + +#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) +#define R_DMA_CH4_CMD__cmd__BITNR 0 +#define R_DMA_CH4_CMD__cmd__WIDTH 3 +#define R_DMA_CH4_CMD__cmd__hold 0 +#define R_DMA_CH4_CMD__cmd__start 1 +#define R_DMA_CH4_CMD__cmd__restart 3 +#define R_DMA_CH4_CMD__cmd__continue 3 +#define R_DMA_CH4_CMD__cmd__reset 4 + +#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) +#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) +#define R_DMA_CH4_STATUS__avail__BITNR 0 +#define R_DMA_CH4_STATUS__avail__WIDTH 7 + +#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) +#define R_DMA_CH5_HWSW__hw__BITNR 16 +#define R_DMA_CH5_HWSW__hw__WIDTH 16 +#define R_DMA_CH5_HWSW__sw__BITNR 0 +#define R_DMA_CH5_HWSW__sw__WIDTH 16 + +#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) +#define R_DMA_CH5_DESCR__descr__BITNR 0 +#define R_DMA_CH5_DESCR__descr__WIDTH 32 + +#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) +#define R_DMA_CH5_NEXT__next__BITNR 0 +#define R_DMA_CH5_NEXT__next__WIDTH 32 + +#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) +#define R_DMA_CH5_BUF__buf__BITNR 0 +#define R_DMA_CH5_BUF__buf__WIDTH 32 + +#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) +#define R_DMA_CH5_FIRST__first__BITNR 0 +#define R_DMA_CH5_FIRST__first__WIDTH 32 + +#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) +#define R_DMA_CH5_CMD__cmd__BITNR 0 +#define R_DMA_CH5_CMD__cmd__WIDTH 3 +#define R_DMA_CH5_CMD__cmd__hold 0 +#define R_DMA_CH5_CMD__cmd__start 1 +#define R_DMA_CH5_CMD__cmd__restart 3 +#define R_DMA_CH5_CMD__cmd__continue 3 +#define R_DMA_CH5_CMD__cmd__reset 4 + +#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) +#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) +#define R_DMA_CH5_STATUS__avail__BITNR 0 +#define R_DMA_CH5_STATUS__avail__WIDTH 7 + +#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) +#define R_DMA_CH6_HWSW__hw__BITNR 16 +#define R_DMA_CH6_HWSW__hw__WIDTH 16 +#define R_DMA_CH6_HWSW__sw__BITNR 0 +#define R_DMA_CH6_HWSW__sw__WIDTH 16 + +#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) +#define R_DMA_CH6_DESCR__descr__BITNR 0 +#define R_DMA_CH6_DESCR__descr__WIDTH 32 + +#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) +#define R_DMA_CH6_NEXT__next__BITNR 0 +#define R_DMA_CH6_NEXT__next__WIDTH 32 + +#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) +#define R_DMA_CH6_BUF__buf__BITNR 0 +#define R_DMA_CH6_BUF__buf__WIDTH 32 + +#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) +#define R_DMA_CH6_FIRST__first__BITNR 0 +#define R_DMA_CH6_FIRST__first__WIDTH 32 + +#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) +#define R_DMA_CH6_CMD__cmd__BITNR 0 +#define R_DMA_CH6_CMD__cmd__WIDTH 3 +#define R_DMA_CH6_CMD__cmd__hold 0 +#define R_DMA_CH6_CMD__cmd__start 1 +#define R_DMA_CH6_CMD__cmd__restart 3 +#define R_DMA_CH6_CMD__cmd__continue 3 +#define R_DMA_CH6_CMD__cmd__reset 4 + +#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) +#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) +#define R_DMA_CH6_STATUS__avail__BITNR 0 +#define R_DMA_CH6_STATUS__avail__WIDTH 7 + +#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) +#define R_DMA_CH7_HWSW__hw__BITNR 16 +#define R_DMA_CH7_HWSW__hw__WIDTH 16 +#define R_DMA_CH7_HWSW__sw__BITNR 0 +#define R_DMA_CH7_HWSW__sw__WIDTH 16 + +#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) +#define R_DMA_CH7_DESCR__descr__BITNR 0 +#define R_DMA_CH7_DESCR__descr__WIDTH 32 + +#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) +#define R_DMA_CH7_NEXT__next__BITNR 0 +#define R_DMA_CH7_NEXT__next__WIDTH 32 + +#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) +#define R_DMA_CH7_BUF__buf__BITNR 0 +#define R_DMA_CH7_BUF__buf__WIDTH 32 + +#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) +#define R_DMA_CH7_FIRST__first__BITNR 0 +#define R_DMA_CH7_FIRST__first__WIDTH 32 + +#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) +#define R_DMA_CH7_CMD__cmd__BITNR 0 +#define R_DMA_CH7_CMD__cmd__WIDTH 3 +#define R_DMA_CH7_CMD__cmd__hold 0 +#define R_DMA_CH7_CMD__cmd__start 1 +#define R_DMA_CH7_CMD__cmd__restart 3 +#define R_DMA_CH7_CMD__cmd__continue 3 +#define R_DMA_CH7_CMD__cmd__reset 4 + +#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) +#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) +#define R_DMA_CH7_STATUS__avail__BITNR 0 +#define R_DMA_CH7_STATUS__avail__WIDTH 7 + +#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) +#define R_DMA_CH8_HWSW__hw__BITNR 16 +#define R_DMA_CH8_HWSW__hw__WIDTH 16 +#define R_DMA_CH8_HWSW__sw__BITNR 0 +#define R_DMA_CH8_HWSW__sw__WIDTH 16 + +#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) +#define R_DMA_CH8_DESCR__descr__BITNR 0 +#define R_DMA_CH8_DESCR__descr__WIDTH 32 + +#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) +#define R_DMA_CH8_NEXT__next__BITNR 0 +#define R_DMA_CH8_NEXT__next__WIDTH 32 + +#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) +#define R_DMA_CH8_BUF__buf__BITNR 0 +#define R_DMA_CH8_BUF__buf__WIDTH 32 + +#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) +#define R_DMA_CH8_FIRST__first__BITNR 0 +#define R_DMA_CH8_FIRST__first__WIDTH 32 + +#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) +#define R_DMA_CH8_CMD__cmd__BITNR 0 +#define R_DMA_CH8_CMD__cmd__WIDTH 3 +#define R_DMA_CH8_CMD__cmd__hold 0 +#define R_DMA_CH8_CMD__cmd__start 1 +#define R_DMA_CH8_CMD__cmd__restart 3 +#define R_DMA_CH8_CMD__cmd__continue 3 +#define R_DMA_CH8_CMD__cmd__reset 4 + +#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) +#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) +#define R_DMA_CH8_STATUS__avail__BITNR 0 +#define R_DMA_CH8_STATUS__avail__WIDTH 7 + +#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) +#define R_DMA_CH8_SUB__sub__BITNR 0 +#define R_DMA_CH8_SUB__sub__WIDTH 32 + +#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) +#define R_DMA_CH8_NEP__nep__BITNR 0 +#define R_DMA_CH8_NEP__nep__WIDTH 32 + +#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) +#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) +#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB0_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) +#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) +#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB1_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) +#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) +#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB2_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) +#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) +#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB3_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) +#define R_DMA_CH9_HWSW__hw__BITNR 16 +#define R_DMA_CH9_HWSW__hw__WIDTH 16 +#define R_DMA_CH9_HWSW__sw__BITNR 0 +#define R_DMA_CH9_HWSW__sw__WIDTH 16 + +#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) +#define R_DMA_CH9_DESCR__descr__BITNR 0 +#define R_DMA_CH9_DESCR__descr__WIDTH 32 + +#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) +#define R_DMA_CH9_NEXT__next__BITNR 0 +#define R_DMA_CH9_NEXT__next__WIDTH 32 + +#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) +#define R_DMA_CH9_BUF__buf__BITNR 0 +#define R_DMA_CH9_BUF__buf__WIDTH 32 + +#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) +#define R_DMA_CH9_FIRST__first__BITNR 0 +#define R_DMA_CH9_FIRST__first__WIDTH 32 + +#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) +#define R_DMA_CH9_CMD__cmd__BITNR 0 +#define R_DMA_CH9_CMD__cmd__WIDTH 3 +#define R_DMA_CH9_CMD__cmd__hold 0 +#define R_DMA_CH9_CMD__cmd__start 1 +#define R_DMA_CH9_CMD__cmd__restart 3 +#define R_DMA_CH9_CMD__cmd__continue 3 +#define R_DMA_CH9_CMD__cmd__reset 4 + +#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) +#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) +#define R_DMA_CH9_STATUS__avail__BITNR 0 +#define R_DMA_CH9_STATUS__avail__WIDTH 7 + +/* +!* Test mode registers +!*/ + +#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) +#define R_TEST_MODE__single_step__BITNR 19 +#define R_TEST_MODE__single_step__WIDTH 1 +#define R_TEST_MODE__single_step__on 1 +#define R_TEST_MODE__single_step__off 0 +#define R_TEST_MODE__step_wr__BITNR 18 +#define R_TEST_MODE__step_wr__WIDTH 1 +#define R_TEST_MODE__step_wr__on 1 +#define R_TEST_MODE__step_wr__off 0 +#define R_TEST_MODE__step_rd__BITNR 17 +#define R_TEST_MODE__step_rd__WIDTH 1 +#define R_TEST_MODE__step_rd__on 1 +#define R_TEST_MODE__step_rd__off 0 +#define R_TEST_MODE__step_fetch__BITNR 16 +#define R_TEST_MODE__step_fetch__WIDTH 1 +#define R_TEST_MODE__step_fetch__on 1 +#define R_TEST_MODE__step_fetch__off 0 +#define R_TEST_MODE__mmu_test__BITNR 12 +#define R_TEST_MODE__mmu_test__WIDTH 1 +#define R_TEST_MODE__mmu_test__on 1 +#define R_TEST_MODE__mmu_test__off 0 +#define R_TEST_MODE__usb_test__BITNR 11 +#define R_TEST_MODE__usb_test__WIDTH 1 +#define R_TEST_MODE__usb_test__on 1 +#define R_TEST_MODE__usb_test__off 0 +#define R_TEST_MODE__scsi_timer_test__BITNR 10 +#define R_TEST_MODE__scsi_timer_test__WIDTH 1 +#define R_TEST_MODE__scsi_timer_test__on 1 +#define R_TEST_MODE__scsi_timer_test__off 0 +#define R_TEST_MODE__backoff__BITNR 9 +#define R_TEST_MODE__backoff__WIDTH 1 +#define R_TEST_MODE__backoff__on 1 +#define R_TEST_MODE__backoff__off 0 +#define R_TEST_MODE__snmp_test__BITNR 8 +#define R_TEST_MODE__snmp_test__WIDTH 1 +#define R_TEST_MODE__snmp_test__on 1 +#define R_TEST_MODE__snmp_test__off 0 +#define R_TEST_MODE__snmp_inc__BITNR 7 +#define R_TEST_MODE__snmp_inc__WIDTH 1 +#define R_TEST_MODE__snmp_inc__do 1 +#define R_TEST_MODE__snmp_inc__dont 0 +#define R_TEST_MODE__ser_loop__BITNR 6 +#define R_TEST_MODE__ser_loop__WIDTH 1 +#define R_TEST_MODE__ser_loop__on 1 +#define R_TEST_MODE__ser_loop__off 0 +#define R_TEST_MODE__baudrate__BITNR 5 +#define R_TEST_MODE__baudrate__WIDTH 1 +#define R_TEST_MODE__baudrate__on 1 +#define R_TEST_MODE__baudrate__off 0 +#define R_TEST_MODE__timer__BITNR 3 +#define R_TEST_MODE__timer__WIDTH 2 +#define R_TEST_MODE__timer__off 0 +#define R_TEST_MODE__timer__even 1 +#define R_TEST_MODE__timer__odd 2 +#define R_TEST_MODE__timer__all 3 +#define R_TEST_MODE__cache_test__BITNR 2 +#define R_TEST_MODE__cache_test__WIDTH 1 +#define R_TEST_MODE__cache_test__normal 0 +#define R_TEST_MODE__cache_test__test 1 +#define R_TEST_MODE__tag_test__BITNR 1 +#define R_TEST_MODE__tag_test__WIDTH 1 +#define R_TEST_MODE__tag_test__normal 0 +#define R_TEST_MODE__tag_test__test 1 +#define R_TEST_MODE__cache_enable__BITNR 0 +#define R_TEST_MODE__cache_enable__WIDTH 1 +#define R_TEST_MODE__cache_enable__enable 1 +#define R_TEST_MODE__cache_enable__disable 0 + +#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) +#define R_SINGLE_STEP__single_step__BITNR 3 +#define R_SINGLE_STEP__single_step__WIDTH 1 +#define R_SINGLE_STEP__single_step__on 1 +#define R_SINGLE_STEP__single_step__off 0 +#define R_SINGLE_STEP__step_wr__BITNR 2 +#define R_SINGLE_STEP__step_wr__WIDTH 1 +#define R_SINGLE_STEP__step_wr__on 1 +#define R_SINGLE_STEP__step_wr__off 0 +#define R_SINGLE_STEP__step_rd__BITNR 1 +#define R_SINGLE_STEP__step_rd__WIDTH 1 +#define R_SINGLE_STEP__step_rd__on 1 +#define R_SINGLE_STEP__step_rd__off 0 +#define R_SINGLE_STEP__step_fetch__BITNR 0 +#define R_SINGLE_STEP__step_fetch__WIDTH 1 +#define R_SINGLE_STEP__step_fetch__on 1 +#define R_SINGLE_STEP__step_fetch__off 0 + +/* +!* USB interface control registers +!*/ + +#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) +#define R_USB_REVISION__major__BITNR 4 +#define R_USB_REVISION__major__WIDTH 4 +#define R_USB_REVISION__minor__BITNR 0 +#define R_USB_REVISION__minor__WIDTH 4 + +#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) +#define R_USB_COMMAND__port_sel__BITNR 6 +#define R_USB_COMMAND__port_sel__WIDTH 2 +#define R_USB_COMMAND__port_sel__nop 0 +#define R_USB_COMMAND__port_sel__port1 1 +#define R_USB_COMMAND__port_sel__port2 2 +#define R_USB_COMMAND__port_sel__both 3 +#define R_USB_COMMAND__port_cmd__BITNR 4 +#define R_USB_COMMAND__port_cmd__WIDTH 2 +#define R_USB_COMMAND__port_cmd__reset 0 +#define R_USB_COMMAND__port_cmd__disable 1 +#define R_USB_COMMAND__port_cmd__suspend 2 +#define R_USB_COMMAND__port_cmd__resume 3 +#define R_USB_COMMAND__busy__BITNR 3 +#define R_USB_COMMAND__busy__WIDTH 1 +#define R_USB_COMMAND__busy__no 0 +#define R_USB_COMMAND__busy__yes 1 +#define R_USB_COMMAND__ctrl_cmd__BITNR 0 +#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 +#define R_USB_COMMAND__ctrl_cmd__nop 0 +#define R_USB_COMMAND__ctrl_cmd__reset 1 +#define R_USB_COMMAND__ctrl_cmd__deconfig 2 +#define R_USB_COMMAND__ctrl_cmd__host_config 3 +#define R_USB_COMMAND__ctrl_cmd__dev_config 4 +#define R_USB_COMMAND__ctrl_cmd__host_nop 5 +#define R_USB_COMMAND__ctrl_cmd__host_run 6 +#define R_USB_COMMAND__ctrl_cmd__host_stop 7 + +#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) +#define R_USB_COMMAND_DEV__port_sel__BITNR 6 +#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 +#define R_USB_COMMAND_DEV__port_sel__nop 0 +#define R_USB_COMMAND_DEV__port_sel__dummy1 1 +#define R_USB_COMMAND_DEV__port_sel__dummy2 2 +#define R_USB_COMMAND_DEV__port_sel__any 3 +#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 +#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 +#define R_USB_COMMAND_DEV__port_cmd__active 0 +#define R_USB_COMMAND_DEV__port_cmd__passive 1 +#define R_USB_COMMAND_DEV__port_cmd__nop 2 +#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 +#define R_USB_COMMAND_DEV__busy__BITNR 3 +#define R_USB_COMMAND_DEV__busy__WIDTH 1 +#define R_USB_COMMAND_DEV__busy__no 0 +#define R_USB_COMMAND_DEV__busy__yes 1 +#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 +#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 +#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 +#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 +#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 +#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 + +#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) +#define R_USB_STATUS__ourun__BITNR 5 +#define R_USB_STATUS__ourun__WIDTH 1 +#define R_USB_STATUS__ourun__no 0 +#define R_USB_STATUS__ourun__yes 1 +#define R_USB_STATUS__perror__BITNR 4 +#define R_USB_STATUS__perror__WIDTH 1 +#define R_USB_STATUS__perror__no 0 +#define R_USB_STATUS__perror__yes 1 +#define R_USB_STATUS__device_mode__BITNR 3 +#define R_USB_STATUS__device_mode__WIDTH 1 +#define R_USB_STATUS__device_mode__no 0 +#define R_USB_STATUS__device_mode__yes 1 +#define R_USB_STATUS__host_mode__BITNR 2 +#define R_USB_STATUS__host_mode__WIDTH 1 +#define R_USB_STATUS__host_mode__no 0 +#define R_USB_STATUS__host_mode__yes 1 +#define R_USB_STATUS__started__BITNR 1 +#define R_USB_STATUS__started__WIDTH 1 +#define R_USB_STATUS__started__no 0 +#define R_USB_STATUS__started__yes 1 +#define R_USB_STATUS__running__BITNR 0 +#define R_USB_STATUS__running__WIDTH 1 +#define R_USB_STATUS__running__no 0 +#define R_USB_STATUS__running__yes 1 + +#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 +#define R_USB_IRQ_MASK_SET__iso_eof__set 1 +#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 +#define R_USB_IRQ_MASK_SET__intr_eof__set 1 +#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 +#define R_USB_IRQ_MASK_SET__iso_eot__set 1 +#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 +#define R_USB_IRQ_MASK_SET__intr_eot__set 1 +#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 +#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 +#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 +#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 +#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 +#define R_USB_IRQ_MASK_SET__epid_attn__set 1 +#define R_USB_IRQ_MASK_SET__sof__BITNR 2 +#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__sof__nop 0 +#define R_USB_IRQ_MASK_SET__sof__set 1 +#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 +#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET__port_status__nop 0 +#define R_USB_IRQ_MASK_SET__port_status__set 1 +#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 +#define R_USB_IRQ_MASK_SET__ctl_status__set 1 + +#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 +#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 +#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 +#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 +#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 +#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 +#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 +#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 +#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 +#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 +#define R_USB_IRQ_MASK_READ__sof__BITNR 2 +#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__sof__no_pend 0 +#define R_USB_IRQ_MASK_READ__sof__pend 1 +#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 +#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 +#define R_USB_IRQ_MASK_READ__port_status__pend 1 +#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 +#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) +#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 +#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 +#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 +#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 +#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 +#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 +#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 +#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__sof__nop 0 +#define R_USB_IRQ_MASK_CLR__sof__clr 1 +#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 +#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__port_status__nop 0 +#define R_USB_IRQ_MASK_CLR__port_status__clr 1 +#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 +#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 + +#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) +#define R_USB_IRQ_READ__iso_eof__BITNR 13 +#define R_USB_IRQ_READ__iso_eof__WIDTH 1 +#define R_USB_IRQ_READ__iso_eof__no_pend 0 +#define R_USB_IRQ_READ__iso_eof__pend 1 +#define R_USB_IRQ_READ__intr_eof__BITNR 12 +#define R_USB_IRQ_READ__intr_eof__WIDTH 1 +#define R_USB_IRQ_READ__intr_eof__no_pend 0 +#define R_USB_IRQ_READ__intr_eof__pend 1 +#define R_USB_IRQ_READ__iso_eot__BITNR 11 +#define R_USB_IRQ_READ__iso_eot__WIDTH 1 +#define R_USB_IRQ_READ__iso_eot__no_pend 0 +#define R_USB_IRQ_READ__iso_eot__pend 1 +#define R_USB_IRQ_READ__intr_eot__BITNR 10 +#define R_USB_IRQ_READ__intr_eot__WIDTH 1 +#define R_USB_IRQ_READ__intr_eot__no_pend 0 +#define R_USB_IRQ_READ__intr_eot__pend 1 +#define R_USB_IRQ_READ__ctl_eot__BITNR 9 +#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 +#define R_USB_IRQ_READ__ctl_eot__no_pend 0 +#define R_USB_IRQ_READ__ctl_eot__pend 1 +#define R_USB_IRQ_READ__bulk_eot__BITNR 8 +#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 +#define R_USB_IRQ_READ__bulk_eot__no_pend 0 +#define R_USB_IRQ_READ__bulk_eot__pend 1 +#define R_USB_IRQ_READ__epid_attn__BITNR 3 +#define R_USB_IRQ_READ__epid_attn__WIDTH 1 +#define R_USB_IRQ_READ__epid_attn__no_pend 0 +#define R_USB_IRQ_READ__epid_attn__pend 1 +#define R_USB_IRQ_READ__sof__BITNR 2 +#define R_USB_IRQ_READ__sof__WIDTH 1 +#define R_USB_IRQ_READ__sof__no_pend 0 +#define R_USB_IRQ_READ__sof__pend 1 +#define R_USB_IRQ_READ__port_status__BITNR 1 +#define R_USB_IRQ_READ__port_status__WIDTH 1 +#define R_USB_IRQ_READ__port_status__no_pend 0 +#define R_USB_IRQ_READ__port_status__pend 1 +#define R_USB_IRQ_READ__ctl_status__BITNR 0 +#define R_USB_IRQ_READ__ctl_status__WIDTH 1 +#define R_USB_IRQ_READ__ctl_status__no_pend 0 +#define R_USB_IRQ_READ__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 +#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 + +#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 + +#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) +#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__out_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 +#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 +#define R_USB_IRQ_READ_DEV__sof__BITNR 2 +#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 +#define R_USB_IRQ_READ_DEV__sof__no_pend 0 +#define R_USB_IRQ_READ_DEV__sof__pend 1 +#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 +#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 +#define R_USB_IRQ_READ_DEV__port_status__pend 1 +#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 +#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 + +#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) +#define R_USB_FM_NUMBER__value__BITNR 0 +#define R_USB_FM_NUMBER__value__WIDTH 32 + +#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) +#define R_USB_FM_INTERVAL__fixed__BITNR 6 +#define R_USB_FM_INTERVAL__fixed__WIDTH 8 +#define R_USB_FM_INTERVAL__adj__BITNR 0 +#define R_USB_FM_INTERVAL__adj__WIDTH 6 + +#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) +#define R_USB_FM_REMAINING__value__BITNR 0 +#define R_USB_FM_REMAINING__value__WIDTH 14 + +#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) +#define R_USB_FM_PSTART__value__BITNR 0 +#define R_USB_FM_PSTART__value__WIDTH 14 + +#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) +#define R_USB_RH_STATUS__babble2__BITNR 7 +#define R_USB_RH_STATUS__babble2__WIDTH 1 +#define R_USB_RH_STATUS__babble2__no 0 +#define R_USB_RH_STATUS__babble2__yes 1 +#define R_USB_RH_STATUS__babble1__BITNR 6 +#define R_USB_RH_STATUS__babble1__WIDTH 1 +#define R_USB_RH_STATUS__babble1__no 0 +#define R_USB_RH_STATUS__babble1__yes 1 +#define R_USB_RH_STATUS__bus1__BITNR 4 +#define R_USB_RH_STATUS__bus1__WIDTH 2 +#define R_USB_RH_STATUS__bus1__SE0 0 +#define R_USB_RH_STATUS__bus1__Diff0 1 +#define R_USB_RH_STATUS__bus1__Diff1 2 +#define R_USB_RH_STATUS__bus1__SE1 3 +#define R_USB_RH_STATUS__bus2__BITNR 2 +#define R_USB_RH_STATUS__bus2__WIDTH 2 +#define R_USB_RH_STATUS__bus2__SE0 0 +#define R_USB_RH_STATUS__bus2__Diff0 1 +#define R_USB_RH_STATUS__bus2__Diff1 2 +#define R_USB_RH_STATUS__bus2__SE1 3 +#define R_USB_RH_STATUS__nports__BITNR 0 +#define R_USB_RH_STATUS__nports__WIDTH 2 + +#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) +#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 +#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__speed__full 0 +#define R_USB_RH_PORT_STATUS_1__speed__low 1 +#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 +#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 +#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__reset__no 0 +#define R_USB_RH_PORT_STATUS_1__reset__yes 1 +#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 +#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 +#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 +#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 +#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__suspended__no 0 +#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 +#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 +#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__enabled__no 0 +#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 +#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 +#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__connected__no 0 +#define R_USB_RH_PORT_STATUS_1__connected__yes 1 + +#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) +#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 +#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__speed__full 0 +#define R_USB_RH_PORT_STATUS_2__speed__low 1 +#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 +#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 +#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__reset__no 0 +#define R_USB_RH_PORT_STATUS_2__reset__yes 1 +#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 +#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 +#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 +#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 +#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__suspended__no 0 +#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 +#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 +#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__enabled__no 0 +#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 +#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 +#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__connected__no 0 +#define R_USB_RH_PORT_STATUS_2__connected__yes 1 + +#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) +#define R_USB_EPT_INDEX__value__BITNR 0 +#define R_USB_EPT_INDEX__value__WIDTH 5 + +#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA__valid__BITNR 31 +#define R_USB_EPT_DATA__valid__WIDTH 1 +#define R_USB_EPT_DATA__valid__no 0 +#define R_USB_EPT_DATA__valid__yes 1 +#define R_USB_EPT_DATA__hold__BITNR 30 +#define R_USB_EPT_DATA__hold__WIDTH 1 +#define R_USB_EPT_DATA__hold__no 0 +#define R_USB_EPT_DATA__hold__yes 1 +#define R_USB_EPT_DATA__error_count_in__BITNR 28 +#define R_USB_EPT_DATA__error_count_in__WIDTH 2 +#define R_USB_EPT_DATA__t_in__BITNR 27 +#define R_USB_EPT_DATA__t_in__WIDTH 1 +#define R_USB_EPT_DATA__low_speed__BITNR 26 +#define R_USB_EPT_DATA__low_speed__WIDTH 1 +#define R_USB_EPT_DATA__low_speed__no 0 +#define R_USB_EPT_DATA__low_speed__yes 1 +#define R_USB_EPT_DATA__port__BITNR 24 +#define R_USB_EPT_DATA__port__WIDTH 2 +#define R_USB_EPT_DATA__port__any 0 +#define R_USB_EPT_DATA__port__p1 1 +#define R_USB_EPT_DATA__port__p2 2 +#define R_USB_EPT_DATA__port__undef 3 +#define R_USB_EPT_DATA__error_code__BITNR 22 +#define R_USB_EPT_DATA__error_code__WIDTH 2 +#define R_USB_EPT_DATA__error_code__no_error 0 +#define R_USB_EPT_DATA__error_code__stall 1 +#define R_USB_EPT_DATA__error_code__bus_error 2 +#define R_USB_EPT_DATA__error_code__buffer_error 3 +#define R_USB_EPT_DATA__t_out__BITNR 21 +#define R_USB_EPT_DATA__t_out__WIDTH 1 +#define R_USB_EPT_DATA__error_count_out__BITNR 19 +#define R_USB_EPT_DATA__error_count_out__WIDTH 2 +#define R_USB_EPT_DATA__max_len__BITNR 11 +#define R_USB_EPT_DATA__max_len__WIDTH 7 +#define R_USB_EPT_DATA__ep__BITNR 7 +#define R_USB_EPT_DATA__ep__WIDTH 4 +#define R_USB_EPT_DATA__dev__BITNR 0 +#define R_USB_EPT_DATA__dev__WIDTH 7 + +#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA_ISO__valid__BITNR 31 +#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 +#define R_USB_EPT_DATA_ISO__valid__no 0 +#define R_USB_EPT_DATA_ISO__valid__yes 1 +#define R_USB_EPT_DATA_ISO__port__BITNR 24 +#define R_USB_EPT_DATA_ISO__port__WIDTH 2 +#define R_USB_EPT_DATA_ISO__port__any 0 +#define R_USB_EPT_DATA_ISO__port__p1 1 +#define R_USB_EPT_DATA_ISO__port__p2 2 +#define R_USB_EPT_DATA_ISO__port__undef 3 +#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 +#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 +#define R_USB_EPT_DATA_ISO__error_code__no_error 0 +#define R_USB_EPT_DATA_ISO__error_code__stall 1 +#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 +#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 +#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 +#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 +#define R_USB_EPT_DATA_ISO__ep__BITNR 7 +#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 +#define R_USB_EPT_DATA_ISO__dev__BITNR 0 +#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 + +#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA_DEV__valid__BITNR 31 +#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 +#define R_USB_EPT_DATA_DEV__valid__no 0 +#define R_USB_EPT_DATA_DEV__valid__yes 1 +#define R_USB_EPT_DATA_DEV__hold__BITNR 30 +#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 +#define R_USB_EPT_DATA_DEV__hold__no 0 +#define R_USB_EPT_DATA_DEV__hold__yes 1 +#define R_USB_EPT_DATA_DEV__stall__BITNR 29 +#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 +#define R_USB_EPT_DATA_DEV__stall__no 0 +#define R_USB_EPT_DATA_DEV__stall__yes 1 +#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 +#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 +#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 +#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 +#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 +#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 +#define R_USB_EPT_DATA_DEV__ctrl__no 0 +#define R_USB_EPT_DATA_DEV__ctrl__yes 1 +#define R_USB_EPT_DATA_DEV__iso__BITNR 26 +#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 +#define R_USB_EPT_DATA_DEV__iso__no 0 +#define R_USB_EPT_DATA_DEV__iso__yes 1 +#define R_USB_EPT_DATA_DEV__port__BITNR 24 +#define R_USB_EPT_DATA_DEV__port__WIDTH 2 +#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 +#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 +#define R_USB_EPT_DATA_DEV__t__BITNR 21 +#define R_USB_EPT_DATA_DEV__t__WIDTH 1 +#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 +#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 +#define R_USB_EPT_DATA_DEV__ep__BITNR 7 +#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 +#define R_USB_EPT_DATA_DEV__dev__BITNR 0 +#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 + +#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) +#define R_USB_SNMP_TERROR__value__BITNR 0 +#define R_USB_SNMP_TERROR__value__WIDTH 32 + +#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) +#define R_USB_EPID_ATTN__value__BITNR 0 +#define R_USB_EPID_ATTN__value__WIDTH 32 + +#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) +#define R_USB_PORT1_DISABLE__disable__BITNR 0 +#define R_USB_PORT1_DISABLE__disable__WIDTH 1 +#define R_USB_PORT1_DISABLE__disable__yes 0 +#define R_USB_PORT1_DISABLE__disable__no 1 + +#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) +#define R_USB_PORT2_DISABLE__disable__BITNR 0 +#define R_USB_PORT2_DISABLE__disable__WIDTH 1 +#define R_USB_PORT2_DISABLE__disable__yes 0 +#define R_USB_PORT2_DISABLE__disable__no 1 + +/* +!* MMU registers +!*/ + +#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) +#define R_MMU_CONFIG__mmu_enable__BITNR 31 +#define R_MMU_CONFIG__mmu_enable__WIDTH 1 +#define R_MMU_CONFIG__mmu_enable__enable 1 +#define R_MMU_CONFIG__mmu_enable__disable 0 +#define R_MMU_CONFIG__inv_excp__BITNR 18 +#define R_MMU_CONFIG__inv_excp__WIDTH 1 +#define R_MMU_CONFIG__inv_excp__enable 1 +#define R_MMU_CONFIG__inv_excp__disable 0 +#define R_MMU_CONFIG__acc_excp__BITNR 17 +#define R_MMU_CONFIG__acc_excp__WIDTH 1 +#define R_MMU_CONFIG__acc_excp__enable 1 +#define R_MMU_CONFIG__acc_excp__disable 0 +#define R_MMU_CONFIG__we_excp__BITNR 16 +#define R_MMU_CONFIG__we_excp__WIDTH 1 +#define R_MMU_CONFIG__we_excp__enable 1 +#define R_MMU_CONFIG__we_excp__disable 0 +#define R_MMU_CONFIG__seg_f__BITNR 15 +#define R_MMU_CONFIG__seg_f__WIDTH 1 +#define R_MMU_CONFIG__seg_f__seg 1 +#define R_MMU_CONFIG__seg_f__page 0 +#define R_MMU_CONFIG__seg_e__BITNR 14 +#define R_MMU_CONFIG__seg_e__WIDTH 1 +#define R_MMU_CONFIG__seg_e__seg 1 +#define R_MMU_CONFIG__seg_e__page 0 +#define R_MMU_CONFIG__seg_d__BITNR 13 +#define R_MMU_CONFIG__seg_d__WIDTH 1 +#define R_MMU_CONFIG__seg_d__seg 1 +#define R_MMU_CONFIG__seg_d__page 0 +#define R_MMU_CONFIG__seg_c__BITNR 12 +#define R_MMU_CONFIG__seg_c__WIDTH 1 +#define R_MMU_CONFIG__seg_c__seg 1 +#define R_MMU_CONFIG__seg_c__page 0 +#define R_MMU_CONFIG__seg_b__BITNR 11 +#define R_MMU_CONFIG__seg_b__WIDTH 1 +#define R_MMU_CONFIG__seg_b__seg 1 +#define R_MMU_CONFIG__seg_b__page 0 +#define R_MMU_CONFIG__seg_a__BITNR 10 +#define R_MMU_CONFIG__seg_a__WIDTH 1 +#define R_MMU_CONFIG__seg_a__seg 1 +#define R_MMU_CONFIG__seg_a__page 0 +#define R_MMU_CONFIG__seg_9__BITNR 9 +#define R_MMU_CONFIG__seg_9__WIDTH 1 +#define R_MMU_CONFIG__seg_9__seg 1 +#define R_MMU_CONFIG__seg_9__page 0 +#define R_MMU_CONFIG__seg_8__BITNR 8 +#define R_MMU_CONFIG__seg_8__WIDTH 1 +#define R_MMU_CONFIG__seg_8__seg 1 +#define R_MMU_CONFIG__seg_8__page 0 +#define R_MMU_CONFIG__seg_7__BITNR 7 +#define R_MMU_CONFIG__seg_7__WIDTH 1 +#define R_MMU_CONFIG__seg_7__seg 1 +#define R_MMU_CONFIG__seg_7__page 0 +#define R_MMU_CONFIG__seg_6__BITNR 6 +#define R_MMU_CONFIG__seg_6__WIDTH 1 +#define R_MMU_CONFIG__seg_6__seg 1 +#define R_MMU_CONFIG__seg_6__page 0 +#define R_MMU_CONFIG__seg_5__BITNR 5 +#define R_MMU_CONFIG__seg_5__WIDTH 1 +#define R_MMU_CONFIG__seg_5__seg 1 +#define R_MMU_CONFIG__seg_5__page 0 +#define R_MMU_CONFIG__seg_4__BITNR 4 +#define R_MMU_CONFIG__seg_4__WIDTH 1 +#define R_MMU_CONFIG__seg_4__seg 1 +#define R_MMU_CONFIG__seg_4__page 0 +#define R_MMU_CONFIG__seg_3__BITNR 3 +#define R_MMU_CONFIG__seg_3__WIDTH 1 +#define R_MMU_CONFIG__seg_3__seg 1 +#define R_MMU_CONFIG__seg_3__page 0 +#define R_MMU_CONFIG__seg_2__BITNR 2 +#define R_MMU_CONFIG__seg_2__WIDTH 1 +#define R_MMU_CONFIG__seg_2__seg 1 +#define R_MMU_CONFIG__seg_2__page 0 +#define R_MMU_CONFIG__seg_1__BITNR 1 +#define R_MMU_CONFIG__seg_1__WIDTH 1 +#define R_MMU_CONFIG__seg_1__seg 1 +#define R_MMU_CONFIG__seg_1__page 0 +#define R_MMU_CONFIG__seg_0__BITNR 0 +#define R_MMU_CONFIG__seg_0__WIDTH 1 +#define R_MMU_CONFIG__seg_0__seg 1 +#define R_MMU_CONFIG__seg_0__page 0 + +#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) +#define R_MMU_KSEG__seg_f__BITNR 15 +#define R_MMU_KSEG__seg_f__WIDTH 1 +#define R_MMU_KSEG__seg_f__seg 1 +#define R_MMU_KSEG__seg_f__page 0 +#define R_MMU_KSEG__seg_e__BITNR 14 +#define R_MMU_KSEG__seg_e__WIDTH 1 +#define R_MMU_KSEG__seg_e__seg 1 +#define R_MMU_KSEG__seg_e__page 0 +#define R_MMU_KSEG__seg_d__BITNR 13 +#define R_MMU_KSEG__seg_d__WIDTH 1 +#define R_MMU_KSEG__seg_d__seg 1 +#define R_MMU_KSEG__seg_d__page 0 +#define R_MMU_KSEG__seg_c__BITNR 12 +#define R_MMU_KSEG__seg_c__WIDTH 1 +#define R_MMU_KSEG__seg_c__seg 1 +#define R_MMU_KSEG__seg_c__page 0 +#define R_MMU_KSEG__seg_b__BITNR 11 +#define R_MMU_KSEG__seg_b__WIDTH 1 +#define R_MMU_KSEG__seg_b__seg 1 +#define R_MMU_KSEG__seg_b__page 0 +#define R_MMU_KSEG__seg_a__BITNR 10 +#define R_MMU_KSEG__seg_a__WIDTH 1 +#define R_MMU_KSEG__seg_a__seg 1 +#define R_MMU_KSEG__seg_a__page 0 +#define R_MMU_KSEG__seg_9__BITNR 9 +#define R_MMU_KSEG__seg_9__WIDTH 1 +#define R_MMU_KSEG__seg_9__seg 1 +#define R_MMU_KSEG__seg_9__page 0 +#define R_MMU_KSEG__seg_8__BITNR 8 +#define R_MMU_KSEG__seg_8__WIDTH 1 +#define R_MMU_KSEG__seg_8__seg 1 +#define R_MMU_KSEG__seg_8__page 0 +#define R_MMU_KSEG__seg_7__BITNR 7 +#define R_MMU_KSEG__seg_7__WIDTH 1 +#define R_MMU_KSEG__seg_7__seg 1 +#define R_MMU_KSEG__seg_7__page 0 +#define R_MMU_KSEG__seg_6__BITNR 6 +#define R_MMU_KSEG__seg_6__WIDTH 1 +#define R_MMU_KSEG__seg_6__seg 1 +#define R_MMU_KSEG__seg_6__page 0 +#define R_MMU_KSEG__seg_5__BITNR 5 +#define R_MMU_KSEG__seg_5__WIDTH 1 +#define R_MMU_KSEG__seg_5__seg 1 +#define R_MMU_KSEG__seg_5__page 0 +#define R_MMU_KSEG__seg_4__BITNR 4 +#define R_MMU_KSEG__seg_4__WIDTH 1 +#define R_MMU_KSEG__seg_4__seg 1 +#define R_MMU_KSEG__seg_4__page 0 +#define R_MMU_KSEG__seg_3__BITNR 3 +#define R_MMU_KSEG__seg_3__WIDTH 1 +#define R_MMU_KSEG__seg_3__seg 1 +#define R_MMU_KSEG__seg_3__page 0 +#define R_MMU_KSEG__seg_2__BITNR 2 +#define R_MMU_KSEG__seg_2__WIDTH 1 +#define R_MMU_KSEG__seg_2__seg 1 +#define R_MMU_KSEG__seg_2__page 0 +#define R_MMU_KSEG__seg_1__BITNR 1 +#define R_MMU_KSEG__seg_1__WIDTH 1 +#define R_MMU_KSEG__seg_1__seg 1 +#define R_MMU_KSEG__seg_1__page 0 +#define R_MMU_KSEG__seg_0__BITNR 0 +#define R_MMU_KSEG__seg_0__WIDTH 1 +#define R_MMU_KSEG__seg_0__seg 1 +#define R_MMU_KSEG__seg_0__page 0 + +#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) +#define R_MMU_CTRL__inv_excp__BITNR 2 +#define R_MMU_CTRL__inv_excp__WIDTH 1 +#define R_MMU_CTRL__inv_excp__enable 1 +#define R_MMU_CTRL__inv_excp__disable 0 +#define R_MMU_CTRL__acc_excp__BITNR 1 +#define R_MMU_CTRL__acc_excp__WIDTH 1 +#define R_MMU_CTRL__acc_excp__enable 1 +#define R_MMU_CTRL__acc_excp__disable 0 +#define R_MMU_CTRL__we_excp__BITNR 0 +#define R_MMU_CTRL__we_excp__WIDTH 1 +#define R_MMU_CTRL__we_excp__enable 1 +#define R_MMU_CTRL__we_excp__disable 0 + +#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) +#define R_MMU_ENABLE__mmu_enable__BITNR 7 +#define R_MMU_ENABLE__mmu_enable__WIDTH 1 +#define R_MMU_ENABLE__mmu_enable__enable 1 +#define R_MMU_ENABLE__mmu_enable__disable 0 + +#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) +#define R_MMU_KBASE_LO__base_7__BITNR 28 +#define R_MMU_KBASE_LO__base_7__WIDTH 4 +#define R_MMU_KBASE_LO__base_6__BITNR 24 +#define R_MMU_KBASE_LO__base_6__WIDTH 4 +#define R_MMU_KBASE_LO__base_5__BITNR 20 +#define R_MMU_KBASE_LO__base_5__WIDTH 4 +#define R_MMU_KBASE_LO__base_4__BITNR 16 +#define R_MMU_KBASE_LO__base_4__WIDTH 4 +#define R_MMU_KBASE_LO__base_3__BITNR 12 +#define R_MMU_KBASE_LO__base_3__WIDTH 4 +#define R_MMU_KBASE_LO__base_2__BITNR 8 +#define R_MMU_KBASE_LO__base_2__WIDTH 4 +#define R_MMU_KBASE_LO__base_1__BITNR 4 +#define R_MMU_KBASE_LO__base_1__WIDTH 4 +#define R_MMU_KBASE_LO__base_0__BITNR 0 +#define R_MMU_KBASE_LO__base_0__WIDTH 4 + +#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) +#define R_MMU_KBASE_HI__base_f__BITNR 28 +#define R_MMU_KBASE_HI__base_f__WIDTH 4 +#define R_MMU_KBASE_HI__base_e__BITNR 24 +#define R_MMU_KBASE_HI__base_e__WIDTH 4 +#define R_MMU_KBASE_HI__base_d__BITNR 20 +#define R_MMU_KBASE_HI__base_d__WIDTH 4 +#define R_MMU_KBASE_HI__base_c__BITNR 16 +#define R_MMU_KBASE_HI__base_c__WIDTH 4 +#define R_MMU_KBASE_HI__base_b__BITNR 12 +#define R_MMU_KBASE_HI__base_b__WIDTH 4 +#define R_MMU_KBASE_HI__base_a__BITNR 8 +#define R_MMU_KBASE_HI__base_a__WIDTH 4 +#define R_MMU_KBASE_HI__base_9__BITNR 4 +#define R_MMU_KBASE_HI__base_9__WIDTH 4 +#define R_MMU_KBASE_HI__base_8__BITNR 0 +#define R_MMU_KBASE_HI__base_8__WIDTH 4 + +#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) +#define R_MMU_CONTEXT__page_id__BITNR 0 +#define R_MMU_CONTEXT__page_id__WIDTH 6 + +#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) +#define R_MMU_CAUSE__vpn__BITNR 13 +#define R_MMU_CAUSE__vpn__WIDTH 19 +#define R_MMU_CAUSE__miss_excp__BITNR 12 +#define R_MMU_CAUSE__miss_excp__WIDTH 1 +#define R_MMU_CAUSE__miss_excp__yes 1 +#define R_MMU_CAUSE__miss_excp__no 0 +#define R_MMU_CAUSE__inv_excp__BITNR 11 +#define R_MMU_CAUSE__inv_excp__WIDTH 1 +#define R_MMU_CAUSE__inv_excp__yes 1 +#define R_MMU_CAUSE__inv_excp__no 0 +#define R_MMU_CAUSE__acc_excp__BITNR 10 +#define R_MMU_CAUSE__acc_excp__WIDTH 1 +#define R_MMU_CAUSE__acc_excp__yes 1 +#define R_MMU_CAUSE__acc_excp__no 0 +#define R_MMU_CAUSE__we_excp__BITNR 9 +#define R_MMU_CAUSE__we_excp__WIDTH 1 +#define R_MMU_CAUSE__we_excp__yes 1 +#define R_MMU_CAUSE__we_excp__no 0 +#define R_MMU_CAUSE__wr_rd__BITNR 8 +#define R_MMU_CAUSE__wr_rd__WIDTH 1 +#define R_MMU_CAUSE__wr_rd__write 1 +#define R_MMU_CAUSE__wr_rd__read 0 +#define R_MMU_CAUSE__page_id__BITNR 0 +#define R_MMU_CAUSE__page_id__WIDTH 6 + +#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) +#define R_TLB_SELECT__index__BITNR 0 +#define R_TLB_SELECT__index__WIDTH 6 + +#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) +#define R_TLB_LO__pfn__BITNR 13 +#define R_TLB_LO__pfn__WIDTH 19 +#define R_TLB_LO__global__BITNR 3 +#define R_TLB_LO__global__WIDTH 1 +#define R_TLB_LO__global__yes 1 +#define R_TLB_LO__global__no 0 +#define R_TLB_LO__valid__BITNR 2 +#define R_TLB_LO__valid__WIDTH 1 +#define R_TLB_LO__valid__yes 1 +#define R_TLB_LO__valid__no 0 +#define R_TLB_LO__kernel__BITNR 1 +#define R_TLB_LO__kernel__WIDTH 1 +#define R_TLB_LO__kernel__yes 1 +#define R_TLB_LO__kernel__no 0 +#define R_TLB_LO__we__BITNR 0 +#define R_TLB_LO__we__WIDTH 1 +#define R_TLB_LO__we__yes 1 +#define R_TLB_LO__we__no 0 + +#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) +#define R_TLB_HI__vpn__BITNR 13 +#define R_TLB_HI__vpn__WIDTH 19 +#define R_TLB_HI__page_id__BITNR 0 +#define R_TLB_HI__page_id__WIDTH 6 + +/* +!* Syncrounous serial port registers +!*/ + +#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) +#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 + +#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) +#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 + +#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) +#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 + +#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) +#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 +#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 +#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 +#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 +#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 +#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 +#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 +#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 +#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 +#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 +#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 +#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 +#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 +#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 +#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__underflow__no 0 +#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 +#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 +#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__overrun__no 0 +#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 +#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 +#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 +#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 +#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 +#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 + +#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) +#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 + +#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) +#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 + +#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) +#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 + +#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) +#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 +#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 +#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 +#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 +#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 +#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 +#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 +#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 +#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 +#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 +#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 +#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 +#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 +#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 +#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 +#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__error__normal 0 +#define R_SYNC_SERIAL1_CTRL__error__ignore 1 +#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 +#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 +#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 +#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 +#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 +#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 +#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 +#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 +#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 +#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 +#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 +#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 +#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 +#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 +#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 +#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 +#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 +#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 +#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 +#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 +#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 +#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 +#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 +#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 +#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 +#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 +#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 +#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 +#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 +#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 +#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 +#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 +#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 +#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 +#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 +#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 +#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 +#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 +#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 +#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 +#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 + +#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) +#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 + +#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) +#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 + +#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) +#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 + +#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) +#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 +#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 +#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 +#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 +#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 +#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 +#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 +#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 +#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 +#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 +#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 +#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 +#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 +#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 +#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__underflow__no 0 +#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 +#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 +#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__overrun__no 0 +#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 +#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 +#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 +#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 +#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 +#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 + +#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) +#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 + +#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) +#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 + +#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) +#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 + +#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) +#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 +#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 +#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 +#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 +#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 +#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 +#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 +#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 +#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 +#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 +#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 +#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 +#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 +#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 +#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 +#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__error__normal 0 +#define R_SYNC_SERIAL3_CTRL__error__ignore 1 +#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 +#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 +#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 +#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 +#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 +#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 +#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 +#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 +#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 +#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 +#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 +#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 +#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 +#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 +#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 +#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 +#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 +#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 +#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 +#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 +#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 +#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 +#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 +#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 +#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 +#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 +#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 +#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 +#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 +#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 +#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 +#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 +#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 +#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 +#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 +#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 +#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 +#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 +#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 +#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 +#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 + diff --git a/kernel/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h b/kernel/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h new file mode 100644 index 000000000..5517f0415 --- /dev/null +++ b/kernel/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h @@ -0,0 +1,139 @@ +/*!************************************************************************** +*! +*! MACROS: +*! IO_MASK(reg,field) +*! IO_STATE(reg,field,state) +*! IO_EXTRACT(reg,field,val) +*! IO_STATE_VALUE(reg,field,state) +*! IO_BITNR(reg,field) +*! IO_WIDTH(reg,field) +*! IO_FIELD(reg,field,val) +*! IO_RD(reg) +*! All moderegister addresses and fields of these. +*! +*!**************************************************************************/ + +#ifndef __sv_addr_ag_h__ +#define __sv_addr_ag_h__ + + +#define __test_sv_addr__ 0 + +/*------------------------------------------------------------ +!* General macros to manipulate moderegisters. +!*-----------------------------------------------------------*/ + +/* IO_MASK returns a mask for a specified bitfield in a register. + Note that this macro doesn't work when field width is 32 bits. */ +#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) +#define IO_MASK_(reg_, field_) \ + ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) + +/* IO_STATE returns a constant corresponding to a one of the symbolic + states that the bitfield can have. (Shifted to correct position) */ +#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) +#define IO_STATE_(reg_, field_, _state) \ + ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) + +/* IO_EXTRACT returns the masked and shifted value corresponding to the + bitfield can have. */ +#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) +#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ + - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) + +/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic + states that the bitfield can have. (Not shifted) */ +#define IO_STATE_VALUE(reg, field, state) \ + IO_STATE_VALUE_ (reg##_, field##_, _##state) +#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) + +/* IO_FIELD shifts the val parameter to be aligned with the bitfield + specified. */ +#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) +#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) + +/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is + LSB and the returned bitnumber is LSB of the field. */ +#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) +#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) + +/* IO_WIDTH returns the width, in bits, of a bitfield. */ +#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) +#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) + +/*--- Obsolete. Kept for backw compatibility. ---*/ +/* Reads (or writes) a byte/uword/udword from the specified mode + register. */ +#define IO_RD(reg) (*(volatile u32*)(reg)) +#define IO_RD_B(reg) (*(volatile u8*)(reg)) +#define IO_RD_W(reg) (*(volatile u16*)(reg)) +#define IO_RD_D(reg) (*(volatile u32*)(reg)) + +/*------------------------------------------------------------ +!* Start addresses of the different memory areas. +!*-----------------------------------------------------------*/ + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +/*------------------------------------------------------------ +!* Type casts used in mode register macros, making pointer +!* dereferencing possible. Empty in assembler. +!*-----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ +# define IO_TYPECAST_UDWORD (volatile u32*) +# define IO_TYPECAST_RO_UDWORD (const volatile u32*) +# define IO_TYPECAST_UWORD (volatile u16*) +# define IO_TYPECAST_RO_UWORD (const volatile u16*) +# define IO_TYPECAST_BYTE (volatile u8*) +# define IO_TYPECAST_RO_BYTE (const volatile u8*) +#else +# define IO_TYPECAST_UDWORD +# define IO_TYPECAST_RO_UDWORD +# define IO_TYPECAST_UWORD +# define IO_TYPECAST_RO_UWORD +# define IO_TYPECAST_BYTE +# define IO_TYPECAST_RO_BYTE +#endif + +/*------------------------------------------------------------*/ + +#include + +#if __test_sv_addr__ +/* IO_MASK( R_BUS_CONFIG , CE ) */ +IO_MASK( R_WAITSTATES , SRAM_WS ) +IO_MASK( R_TEST , W32 ) + +IO_STATE( R_BUS_CONFIG, CE, DISABLE ) +IO_STATE( R_BUS_CONFIG, CE, ENABLE ) + +IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) + +IO_MASK( R_DRAM_TIMING, REF ) + +IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) + +IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) + == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) +#endif + + +#endif /* ifndef __sv_addr_ag_h__ */ + diff --git a/kernel/arch/cris/include/uapi/arch-v10/arch/svinto.h b/kernel/arch/cris/include/uapi/arch-v10/arch/svinto.h new file mode 100644 index 000000000..da5c15272 --- /dev/null +++ b/kernel/arch/cris/include/uapi/arch-v10/arch/svinto.h @@ -0,0 +1,64 @@ +#ifndef _ASM_CRIS_SVINTO_H +#define _ASM_CRIS_SVINTO_H + +#include + +extern unsigned int genconfig_shadow; /* defined and set in head.S */ + +/* dma stuff */ + +enum { /* Available in: */ + d_eol = (1 << 0), /* flags */ + d_eop = (1 << 1), /* flags & status */ + d_wait = (1 << 2), /* flags */ + d_int = (1 << 3), /* flags */ + d_txerr = (1 << 4), /* flags */ + d_stop = (1 << 4), /* status */ + d_ecp = (1 << 4), /* flags & status */ + d_pri = (1 << 5), /* flags & status */ + d_alignerr = (1 << 6), /* status */ + d_crcerr = (1 << 7) /* status */ +}; + +/* Do remember that DMA does not go through the MMU and needs + * a real physical address, not an address virtually mapped or + * paged. Therefore the buf/next ptrs below are unsigned long instead + * of void * to give a warning if you try to put a pointer directly + * to them instead of going through virt_to_phys/phys_to_virt. + */ + +typedef struct etrax_dma_descr { + unsigned short sw_len; /* 0-1 */ + unsigned short ctrl; /* 2-3 */ + unsigned long next; /* 4-7 */ + unsigned long buf; /* 8-11 */ + unsigned short hw_len; /* 12-13 */ + unsigned char status; /* 14 */ + unsigned char fifo_len; /* 15 */ +} etrax_dma_descr; + + +/* Use this for constant numbers only */ +#define RESET_DMA_NUM( n ) \ + *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) + +/* Use this for constant numbers or symbols, + * having two macros makes it possible to use constant expressions. + */ +#define RESET_DMA( n ) RESET_DMA_NUM( n ) + + +/* Use this for constant numbers only */ +#define WAIT_DMA_NUM( n ) \ + while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ + IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) + +/* Use this for constant numbers or symbols + * having two macros makes it possible to use constant expressions. + */ +#define WAIT_DMA( n ) WAIT_DMA_NUM( n ) + +extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); +extern void flush_etrax_cache(void); + +#endif diff --git a/kernel/arch/cris/include/uapi/arch-v10/arch/user.h b/kernel/arch/cris/include/uapi/arch-v10/arch/user.h new file mode 100644 index 000000000..9303ea77c --- /dev/null +++ b/kernel/arch/cris/include/uapi/arch-v10/arch/user.h @@ -0,0 +1,46 @@ +#ifndef __ASM_CRIS_ARCH_USER_H +#define __ASM_CRIS_ARCH_USER_H + +/* User mode registers, used for core dumps. In order to keep ELF_NGREG + sensible we let all registers be 32 bits. The csr registers are included + for future use. */ +struct user_regs_struct { + unsigned long r0; /* General registers. */ + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long sp; /* Stack pointer. */ + unsigned long pc; /* Program counter. */ + unsigned long p0; /* Constant zero (only 8 bits). */ + unsigned long vr; /* Version register (only 8 bits). */ + unsigned long p2; /* Reserved. */ + unsigned long p3; /* Reserved. */ + unsigned long p4; /* Constant zero (only 16 bits). */ + unsigned long ccr; /* Condition code register (only 16 bits). */ + unsigned long p6; /* Reserved. */ + unsigned long mof; /* Multiply overflow register. */ + unsigned long p8; /* Constant zero. */ + unsigned long ibr; /* Not accessible. */ + unsigned long irp; /* Not accessible. */ + unsigned long srp; /* Subroutine return pointer. */ + unsigned long bar; /* Not accessible. */ + unsigned long dccr; /* Dword condition code register. */ + unsigned long brp; /* Not accessible. */ + unsigned long usp; /* User-mode stack pointer. Same as sp when + in user mode. */ + unsigned long csrinstr; /* Internal status registers. */ + unsigned long csraddr; + unsigned long csrdata; +}; + +#endif diff --git a/kernel/arch/cris/include/uapi/arch-v32/arch/Kbuild b/kernel/arch/cris/include/uapi/arch-v32/arch/Kbuild new file mode 100644 index 000000000..59efffd16 --- /dev/null +++ b/kernel/arch/cris/include/uapi/arch-v32/arch/Kbuild @@ -0,0 +1,3 @@ +# UAPI Header export list +header-y += cryptocop.h +header-y += user.h diff --git a/kernel/arch/cris/include/uapi/arch-v32/arch/cryptocop.h b/kernel/arch/cris/include/uapi/arch-v32/arch/cryptocop.h new file mode 100644 index 000000000..694fd13ce --- /dev/null +++ b/kernel/arch/cris/include/uapi/arch-v32/arch/cryptocop.h @@ -0,0 +1,122 @@ +/* + * The device /dev/cryptocop is accessible using this driver using + * CRYPTOCOP_MAJOR (254) and minor number 0. + */ + +#ifndef _UAPICRYPTOCOP_H +#define _UAPICRYPTOCOP_H + +#include + + +#define CRYPTOCOP_SESSION_ID_NONE (0) + +typedef unsigned long long int cryptocop_session_id; + +/* cryptocop ioctls */ +#define ETRAXCRYPTOCOP_IOCTYPE (250) + +#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) +#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) +#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) +#define CRYPTOCOP_IO_MAXNR (3) + +typedef enum { + cryptocop_cipher_des = 0, + cryptocop_cipher_3des = 1, + cryptocop_cipher_aes = 2, + cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ + cryptocop_cipher_none +} cryptocop_cipher_type; + +typedef enum { + cryptocop_digest_sha1 = 0, + cryptocop_digest_md5 = 1, + cryptocop_digest_none +} cryptocop_digest_type; + +typedef enum { + cryptocop_csum_le = 0, + cryptocop_csum_be = 1, + cryptocop_csum_none +} cryptocop_csum_type; + +typedef enum { + cryptocop_cipher_mode_ecb = 0, + cryptocop_cipher_mode_cbc, + cryptocop_cipher_mode_none +} cryptocop_cipher_mode; + +typedef enum { + cryptocop_3des_eee = 0, + cryptocop_3des_eed = 1, + cryptocop_3des_ede = 2, + cryptocop_3des_edd = 3, + cryptocop_3des_dee = 4, + cryptocop_3des_ded = 5, + cryptocop_3des_dde = 6, + cryptocop_3des_ddd = 7 +} cryptocop_3des_mode; + +/* Usermode accessible (ioctl) operations. */ +struct strcop_session_op{ + cryptocop_session_id ses_id; + + cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ + + cryptocop_cipher_mode cmode; /* ECB, CBC, none */ + cryptocop_3des_mode des3_mode; + + cryptocop_digest_type digest; /* MD5, SHA1, none */ + + cryptocop_csum_type csum; /* BE, LE, none */ + + unsigned char *key; + size_t keylen; +}; + +#define CRYPTOCOP_CSUM_LENGTH (2) +#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ +#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ +#define CRYPTOCOP_MAX_KEY_LENGTH (32) + +struct strcop_crypto_op{ + cryptocop_session_id ses_id; + + /* Indata. */ + unsigned char *indata; + size_t inlen; /* Total indata length. */ + + /* Cipher configuration. */ + unsigned char do_cipher:1; + unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ + unsigned char cipher_explicit:1; + size_t cipher_start; + size_t cipher_len; + /* cipher_iv is used if do_cipher and cipher_explicit and the cipher + mode is CBC. The length is controlled by the type of cipher, + e.g. DES/3DES 8 octets and AES 16 octets. */ + unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; + /* Outdata. */ + unsigned char *cipher_outdata; + size_t cipher_outlen; + + /* digest configuration. */ + unsigned char do_digest:1; + size_t digest_start; + size_t digest_len; + /* Outdata. The actual length is determined by the type of the digest. */ + unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; + + /* Checksum configuration. */ + unsigned char do_csum:1; + size_t csum_start; + size_t csum_len; + /* Outdata. */ + unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; +}; + + + + +#endif /* _UAPICRYPTOCOP_H */ diff --git a/kernel/arch/cris/include/uapi/arch-v32/arch/user.h b/kernel/arch/cris/include/uapi/arch-v32/arch/user.h new file mode 100644 index 000000000..03fa1f3c3 --- /dev/null +++ b/kernel/arch/cris/include/uapi/arch-v32/arch/user.h @@ -0,0 +1,41 @@ +#ifndef _ASM_CRIS_ARCH_USER_H +#define _ASM_CRIS_ARCH_USER_H + +/* User-mode register used for core dumps. */ + +struct user_regs_struct { + unsigned long r0; /* General registers. */ + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long sp; /* R14, Stack pointer. */ + unsigned long acr; /* R15, Address calculation register. */ + unsigned long bz; /* P0, Constant zero (8-bits). */ + unsigned long vr; /* P1, Version register (8-bits). */ + unsigned long pid; /* P2, Process ID (8-bits). */ + unsigned long srs; /* P3, Support register select (8-bits). */ + unsigned long wz; /* P4, Constant zero (16-bits). */ + unsigned long exs; /* P5, Exception status. */ + unsigned long eda; /* P6, Exception data address. */ + unsigned long mof; /* P7, Multiply overflow regiter. */ + unsigned long dz; /* P8, Constant zero (32-bits). */ + unsigned long ebp; /* P9, Exception base pointer. */ + unsigned long erp; /* P10, Exception return pointer. */ + unsigned long srp; /* P11, Subroutine return pointer. */ + unsigned long nrp; /* P12, NMI return pointer. */ + unsigned long ccs; /* P13, Condition code stack. */ + unsigned long usp; /* P14, User mode stack pointer. */ + unsigned long spc; /* P15, Single step PC. */ +}; + +#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/kernel/arch/cris/include/uapi/asm/Kbuild b/kernel/arch/cris/include/uapi/asm/Kbuild new file mode 100644 index 000000000..01f66b8f1 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/Kbuild @@ -0,0 +1,39 @@ +# UAPI Header export list +include include/uapi/asm-generic/Kbuild.asm + +header-y += ../arch-v10/arch/ +header-y += ../arch-v32/arch/ +header-y += auxvec.h +header-y += bitsperlong.h +header-y += byteorder.h +header-y += errno.h +header-y += ethernet.h +header-y += etraxgpio.h +header-y += fcntl.h +header-y += ioctl.h +header-y += ioctls.h +header-y += ipcbuf.h +header-y += mman.h +header-y += msgbuf.h +header-y += param.h +header-y += poll.h +header-y += posix_types.h +header-y += ptrace.h +header-y += resource.h +header-y += rs485.h +header-y += sembuf.h +header-y += setup.h +header-y += shmbuf.h +header-y += sigcontext.h +header-y += siginfo.h +header-y += signal.h +header-y += socket.h +header-y += sockios.h +header-y += stat.h +header-y += statfs.h +header-y += swab.h +header-y += sync_serial.h +header-y += termbits.h +header-y += termios.h +header-y += types.h +header-y += unistd.h diff --git a/kernel/arch/cris/include/uapi/asm/auxvec.h b/kernel/arch/cris/include/uapi/asm/auxvec.h new file mode 100644 index 000000000..cb30b01bf --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/auxvec.h @@ -0,0 +1,4 @@ +#ifndef __ASMCRIS_AUXVEC_H +#define __ASMCRIS_AUXVEC_H + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/bitsperlong.h b/kernel/arch/cris/include/uapi/asm/bitsperlong.h new file mode 100644 index 000000000..6dc0bb0c1 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/bitsperlong.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/byteorder.h b/kernel/arch/cris/include/uapi/asm/byteorder.h new file mode 100644 index 000000000..bcd189798 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/byteorder.h @@ -0,0 +1,8 @@ +#ifndef _CRIS_BYTEORDER_H +#define _CRIS_BYTEORDER_H + +#include + +#endif + + diff --git a/kernel/arch/cris/include/uapi/asm/errno.h b/kernel/arch/cris/include/uapi/asm/errno.h new file mode 100644 index 000000000..2bf5eb5fa --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/errno.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_ERRNO_H +#define _CRIS_ERRNO_H + +#include + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/ethernet.h b/kernel/arch/cris/include/uapi/asm/ethernet.h new file mode 100644 index 000000000..4d58652c3 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/ethernet.h @@ -0,0 +1,21 @@ +/* + * ioctl defines for ethernet driver + * + * Copyright (c) 2001 Axis Communications AB + * + * Author: Mikael Starvik + * + */ + +#ifndef _CRIS_ETHERNET_H +#define _CRIS_ETHERNET_H +#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ +#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ +#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ +#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ +#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ +#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ +#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ +#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ +#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 +#endif /* _CRIS_ETHERNET_H */ diff --git a/kernel/arch/cris/include/uapi/asm/etraxgpio.h b/kernel/arch/cris/include/uapi/asm/etraxgpio.h new file mode 100644 index 000000000..461c089db --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/etraxgpio.h @@ -0,0 +1,239 @@ +/* + * The following devices are accessible using this driver using + * GPIO_MAJOR (120) and a couple of minor numbers. + * + * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): + * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig + * /dev/gpiog minor 3 + * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG + * g1-g7 and g25-g31 is both input and outputs but on different pins + * Also note that some bits change pins depending on what interfaces + * are enabled. + * + * For ETRAX FS (CONFIG_ETRAXFS): + * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction + * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction + * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction + * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig + * + * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): + * /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction + * /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction + * /dev/gpiod minor 4, 32 bit GPIO, input only + * /dev/leds minor 2, Access to leds depending on kernelconfig + * /dev/pwm0 minor 16, PWM channel 0 on PA30 + * /dev/pwm1 minor 17, PWM channel 1 on PA31 + * /dev/pwm2 minor 18, PWM channel 2 on PB26 + * /dev/ppwm minor 19, PPWM channel + * + */ +#ifndef _ASM_ETRAXGPIO_H +#define _ASM_ETRAXGPIO_H + +#define GPIO_MINOR_FIRST 0 + +#define ETRAXGPIO_IOCTYPE 43 + +/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ +#ifdef CONFIG_ETRAX_ARCH_V10 +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_G 3 +#define GPIO_MINOR_LAST 3 +#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST +#endif + +#ifdef CONFIG_ETRAXFS +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_C 3 +#define GPIO_MINOR_D 4 +#define GPIO_MINOR_E 5 +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#define GPIO_MINOR_V 6 +#define GPIO_MINOR_LAST 6 +#else +#define GPIO_MINOR_LAST 5 +#endif +#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST +#endif + +#ifdef CONFIG_CRIS_MACH_ARTPEC3 +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_C 3 +#define GPIO_MINOR_D 4 +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#define GPIO_MINOR_V 6 +#define GPIO_MINOR_LAST 6 +#else +#define GPIO_MINOR_LAST 4 +#endif +#define GPIO_MINOR_FIRST_PWM 16 +#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0) +#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1) +#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2) +#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3) +#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM +#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM +#endif + + + +/* supported ioctl _IOC_NR's */ + +#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ +#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ +#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ + +/* the alarm is waited for by select() */ + +#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ +#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ +#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ + +/* LED ioctl */ +#define IO_LEDACTIVE_SET 0x7 /* set active led + * 0=off, 1=green, 2=red, 3=yellow */ + +/* GPIO direction ioctl's */ +#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ +#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, + returns mask with current inputs (obsolete) */ +#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, + returns mask with current outputs (obsolete)*/ + +/* LED ioctl extended */ +#define IO_LED_SETBIT 0xB +#define IO_LED_CLRBIT 0xC + +/* SHUTDOWN ioctl */ +#define IO_SHUTDOWN 0xD +#define IO_GET_PWR_BT 0xE + +/* Bit toggling in driver settings */ +/* bit set in low byte0 is CLK mask (0x00FF), + bit set in byte1 is DATA mask (0xFF00) + msb, data_mask[7:0] , clk_mask[7:0] + */ +#define IO_CFG_WRITE_MODE 0xF +#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ + ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) + +/* The following 4 ioctl's take a pointer as argument and handles + * 32 bit ports (port G) properly. + * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT + */ +#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ +#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ +#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */ + /* *arg updated with current input pins. */ +#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */ + /* *arg updated with current output pins. */ + +/* The following ioctl's are applicable to the PWM channels only */ + +#define IO_PWM_SET_MODE 0x20 + +enum io_pwm_mode { + PWM_OFF = 0, /* disabled, deallocated */ + PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ + PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ + PWM_VARFREQ = 3, /* individually configurable high/low periods */ + PWM_SOFT = 4 /* software generated */ +}; + +struct io_pwm_set_mode { + enum io_pwm_mode mode; +}; + +/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns + * from 10ns (value = 0) to 81920ns (value = 8191) + * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to + * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty + * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) + */ +#define IO_PWM_SET_PERIOD 0x21 + +struct io_pwm_set_period { + unsigned int lo; /* 0..8191 */ + unsigned int hi; /* 0..8191 */ +}; + +/* Only for modes PWM_STANDARD and PWM_FAST. + * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from + * 0 (value = 0) to 255/256 (value = 255). + * For PWM_FAST, set duty cycle of PWM output signal from + * 0% (value = 0) to 100% (value = 255). Output signal in this mode + * is a 10ns pulse surrounded by a high or low level depending on duty + * cycle (except for 0% and 100% which result in a constant output). + * Resulting output frequency varies from 50 MHz at 50% duty cycle, + * down to 390 kHz at min/max duty cycle. + */ +#define IO_PWM_SET_DUTY 0x22 + +struct io_pwm_set_duty { + int duty; /* 0..255 */ +}; + +/* Returns information about the latest PWM pulse. + * lo: Length of the latest low period, in units of 10ns. + * hi: Length of the latest high period, in units of 10ns. + * cnt: Time since last detected edge, in units of 10ns. + * + * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC. + * + * NOTE: All PWM devices is connected to the same input source. + */ +#define IO_PWM_GET_PERIOD 0x23 + +struct io_pwm_get_period { + unsigned int lo; + unsigned int hi; + unsigned int cnt; +}; + +/* Sets the input source for the PWM input. For the src value see the + * register description for gio:rw_pwm_in_cfg. + * + * NOTE: All PWM devices is connected to the same input source. + */ +#define IO_PWM_SET_INPUT_SRC 0x24 +struct io_pwm_set_input_src { + unsigned int src; /* 0..7 */ +}; + +/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */ +#define IO_PPWM_SET_DUTY 0x25 + +struct io_ppwm_set_duty { + int duty; /* 0..255 */ +}; + +/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure + * PWM capable gpio pins: + */ +#define IO_PWMCLK_SETGET_CONFIG 0x26 +struct gpio_pwmclk_conf { + unsigned int gpiopin; /* The pin number based on the opened device */ + unsigned int baseclk; /* The base clock to use, or sw will select one close*/ + unsigned int low; /* The number of low periods of the baseclk */ + unsigned int high; /* The number of high periods of the baseclk */ +}; + +/* Examples: + * To get a symmetric 12 MHz clock without knowing anything about the hardware: + * baseclk = 12000000, low = 0, high = 0 + * To just get info of current setting: + * baseclk = 0, low = 0, high = 0, the values will be updated by driver. + */ + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/fcntl.h b/kernel/arch/cris/include/uapi/asm/fcntl.h new file mode 100644 index 000000000..46ab12db5 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/fcntl.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/ioctl.h b/kernel/arch/cris/include/uapi/asm/ioctl.h new file mode 100644 index 000000000..b279fe06d --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/ioctl.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/ioctls.h b/kernel/arch/cris/include/uapi/asm/ioctls.h new file mode 100644 index 000000000..488fbb3f5 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/ioctls.h @@ -0,0 +1,11 @@ +#ifndef __ARCH_CRIS_IOCTLS_H__ +#define __ARCH_CRIS_IOCTLS_H__ + +#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ +#define TIOCSERSETRS485 0x5461 /* enable rs-485 (deprecated) */ +#define TIOCSERWRRS485 0x5462 /* write rs-485 */ +#define TIOCSRS485 0x5463 /* enable rs-485 */ + +#include + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/ipcbuf.h b/kernel/arch/cris/include/uapi/asm/ipcbuf.h new file mode 100644 index 000000000..84c7e51cb --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/ipcbuf.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/kvm_para.h b/kernel/arch/cris/include/uapi/asm/kvm_para.h new file mode 100644 index 000000000..14fab8f0b --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/kvm_para.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/mman.h b/kernel/arch/cris/include/uapi/asm/mman.h new file mode 100644 index 000000000..8eebf89f5 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/mman.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/msgbuf.h b/kernel/arch/cris/include/uapi/asm/msgbuf.h new file mode 100644 index 000000000..ada63df1d --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/msgbuf.h @@ -0,0 +1,33 @@ +#ifndef _CRIS_MSGBUF_H +#define _CRIS_MSGBUF_H + +/* verbatim copy of asm-i386 version */ + +/* + * The msqid64_ds structure for CRIS architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct msqid64_ds { + struct ipc64_perm msg_perm; + __kernel_time_t msg_stime; /* last msgsnd time */ + unsigned long __unused1; + __kernel_time_t msg_rtime; /* last msgrcv time */ + unsigned long __unused2; + __kernel_time_t msg_ctime; /* last change time */ + unsigned long __unused3; + unsigned long msg_cbytes; /* current number of bytes on queue */ + unsigned long msg_qnum; /* number of messages in queue */ + unsigned long msg_qbytes; /* max number of bytes on queue */ + __kernel_pid_t msg_lspid; /* pid of last msgsnd */ + __kernel_pid_t msg_lrpid; /* last receive pid */ + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* _CRIS_MSGBUF_H */ diff --git a/kernel/arch/cris/include/uapi/asm/param.h b/kernel/arch/cris/include/uapi/asm/param.h new file mode 100644 index 000000000..484fcf866 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/param.h @@ -0,0 +1,10 @@ +#ifndef _ASMCRIS_PARAM_H +#define _ASMCRIS_PARAM_H + +/* Currently we assume that HZ=100 is good for CRIS. */ + +#define EXEC_PAGESIZE 8192 + +#include + +#endif /* _ASMCRIS_PARAM_H */ diff --git a/kernel/arch/cris/include/uapi/asm/poll.h b/kernel/arch/cris/include/uapi/asm/poll.h new file mode 100644 index 000000000..c98509d31 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/poll.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/posix_types.h b/kernel/arch/cris/include/uapi/asm/posix_types.h new file mode 100644 index 000000000..0f22e6a67 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/posix_types.h @@ -0,0 +1,30 @@ +/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ +/* I guess we should write these in assembler because they are used often. */ + +#ifndef __ARCH_CRIS_POSIX_TYPES_H +#define __ARCH_CRIS_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_mode_t; +#define __kernel_mode_t __kernel_mode_t + +typedef unsigned short __kernel_ipc_pid_t; +#define __kernel_ipc_pid_t __kernel_ipc_pid_t + +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +#define __kernel_uid_t __kernel_uid_t + +typedef unsigned short __kernel_old_dev_t; +#define __kernel_old_dev_t __kernel_old_dev_t + +#include + +#endif /* __ARCH_CRIS_POSIX_TYPES_H */ diff --git a/kernel/arch/cris/include/uapi/asm/ptrace.h b/kernel/arch/cris/include/uapi/asm/ptrace.h new file mode 100644 index 000000000..c689c9bbb --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/ptrace.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/resource.h b/kernel/arch/cris/include/uapi/asm/resource.h new file mode 100644 index 000000000..b5d29448d --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/resource.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_RESOURCE_H +#define _CRIS_RESOURCE_H + +#include + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/rs485.h b/kernel/arch/cris/include/uapi/asm/rs485.h new file mode 100644 index 000000000..ad40f9fbc --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/rs485.h @@ -0,0 +1,18 @@ +/* RS-485 structures */ + +/* Used with ioctl() TIOCSERSETRS485 for backward compatibility! + * XXX: Do not use it for new code! + */ +struct rs485_control { + unsigned short rts_on_send; + unsigned short rts_after_sent; + unsigned long delay_rts_before_send; + unsigned short enabled; +}; + +/* Used with ioctl() TIOCSERWRRS485 */ +struct rs485_write { + unsigned short outc_size; + unsigned char *outc; +}; + diff --git a/kernel/arch/cris/include/uapi/asm/sembuf.h b/kernel/arch/cris/include/uapi/asm/sembuf.h new file mode 100644 index 000000000..7fed98437 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/sembuf.h @@ -0,0 +1,25 @@ +#ifndef _CRIS_SEMBUF_H +#define _CRIS_SEMBUF_H + +/* + * The semid64_ds structure for CRIS architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct semid64_ds { + struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ + __kernel_time_t sem_otime; /* last semop time */ + unsigned long __unused1; + __kernel_time_t sem_ctime; /* last change time */ + unsigned long __unused2; + unsigned long sem_nsems; /* no. of semaphores in array */ + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* _CRIS_SEMBUF_H */ diff --git a/kernel/arch/cris/include/uapi/asm/setup.h b/kernel/arch/cris/include/uapi/asm/setup.h new file mode 100644 index 000000000..b90728652 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/setup.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_SETUP_H +#define _CRIS_SETUP_H + +#define COMMAND_LINE_SIZE 256 + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/shmbuf.h b/kernel/arch/cris/include/uapi/asm/shmbuf.h new file mode 100644 index 000000000..3239e3f00 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/shmbuf.h @@ -0,0 +1,42 @@ +#ifndef _CRIS_SHMBUF_H +#define _CRIS_SHMBUF_H + +/* + * The shmid64_ds structure for CRIS architecture (same as for i386) + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct shmid64_ds { + struct ipc64_perm shm_perm; /* operation perms */ + size_t shm_segsz; /* size of segment (bytes) */ + __kernel_time_t shm_atime; /* last attach time */ + unsigned long __unused1; + __kernel_time_t shm_dtime; /* last detach time */ + unsigned long __unused2; + __kernel_time_t shm_ctime; /* last change time */ + unsigned long __unused3; + __kernel_pid_t shm_cpid; /* pid of creator */ + __kernel_pid_t shm_lpid; /* pid of last operator */ + unsigned long shm_nattch; /* no. of current attaches */ + unsigned long __unused4; + unsigned long __unused5; +}; + +struct shminfo64 { + unsigned long shmmax; + unsigned long shmmin; + unsigned long shmmni; + unsigned long shmseg; + unsigned long shmall; + unsigned long __unused1; + unsigned long __unused2; + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* _CRIS_SHMBUF_H */ diff --git a/kernel/arch/cris/include/uapi/asm/sigcontext.h b/kernel/arch/cris/include/uapi/asm/sigcontext.h new file mode 100644 index 000000000..a1d634e12 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/sigcontext.h @@ -0,0 +1,24 @@ +/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +#ifndef _ASM_CRIS_SIGCONTEXT_H +#define _ASM_CRIS_SIGCONTEXT_H + +#include + +/* This struct is saved by setup_frame in signal.c, to keep the current context while + a signal handler is executed. It's restored by sys_sigreturn. + + To keep things simple, we use pt_regs here even though normally you just specify + the list of regs to save. Then we can use copy_from_user on the entire regs instead + of a bunch of get_user's as well... + +*/ + +struct sigcontext { + struct pt_regs regs; /* needs to be first */ + unsigned long oldmask; + unsigned long usp; /* usp before stacking this gunk on it */ +}; + +#endif + diff --git a/kernel/arch/cris/include/uapi/asm/siginfo.h b/kernel/arch/cris/include/uapi/asm/siginfo.h new file mode 100644 index 000000000..c1cd6d169 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/siginfo.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_SIGINFO_H +#define _CRIS_SIGINFO_H + +#include + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/signal.h b/kernel/arch/cris/include/uapi/asm/signal.h new file mode 100644 index 000000000..ce42fa7c3 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/signal.h @@ -0,0 +1,116 @@ +#ifndef _UAPI_ASM_CRIS_SIGNAL_H +#define _UAPI_ASM_CRIS_SIGNAL_H + +#include + +/* Avoid too many header ordering problems. */ +struct siginfo; + +#ifndef __KERNEL__ +/* Here we must cater to libcs that poke about in kernel headers. */ + +#define NSIG 32 +typedef unsigned long sigset_t; + +#endif /* __KERNEL__ */ + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#define SIGRTMAX _NSIG + +/* + * SA_FLAGS values: + * + * SA_ONSTACK indicates that a registered stack_t will be used. + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_RESETHAND clears the handler when the signal is delivered. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_NODEFER prevents the current signal from being masked in the handler. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ + +#define SA_NOCLDSTOP 0x00000001u +#define SA_NOCLDWAIT 0x00000002u +#define SA_SIGINFO 0x00000004u +#define SA_ONSTACK 0x08000000u +#define SA_RESTART 0x10000000u +#define SA_NODEFER 0x40000000u +#define SA_RESETHAND 0x80000000u + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND + +#define SA_RESTORER 0x04000000 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 + +#include + +#ifndef __KERNEL__ +/* Here we must cater to libcs that poke about in kernel headers. */ + +struct sigaction { + union { + __sighandler_t _sa_handler; + void (*_sa_sigaction)(int, struct siginfo *, void *); + } _u; + sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +#define sa_handler _u._sa_handler +#define sa_sigaction _u._sa_sigaction + +#endif /* __KERNEL__ */ + +typedef struct sigaltstack { + void *ss_sp; + int ss_flags; + size_t ss_size; +} stack_t; + + +#endif /* _UAPI_ASM_CRIS_SIGNAL_H */ diff --git a/kernel/arch/cris/include/uapi/asm/socket.h b/kernel/arch/cris/include/uapi/asm/socket.h new file mode 100644 index 000000000..e2503d9f1 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/socket.h @@ -0,0 +1,92 @@ +#ifndef _ASM_SOCKET_H +#define _ASM_SOCKET_H + +/* almost the same as asm-i386/socket.h */ + +#include + +/* For setsockoptions(2) */ +#define SOL_SOCKET 1 + +#define SO_DEBUG 1 +#define SO_REUSEADDR 2 +#define SO_TYPE 3 +#define SO_ERROR 4 +#define SO_DONTROUTE 5 +#define SO_BROADCAST 6 +#define SO_SNDBUF 7 +#define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 +#define SO_KEEPALIVE 9 +#define SO_OOBINLINE 10 +#define SO_NO_CHECK 11 +#define SO_PRIORITY 12 +#define SO_LINGER 13 +#define SO_BSDCOMPAT 14 +#define SO_REUSEPORT 15 +#define SO_PASSCRED 16 +#define SO_PEERCRED 17 +#define SO_RCVLOWAT 18 +#define SO_SNDLOWAT 19 +#define SO_RCVTIMEO 20 +#define SO_SNDTIMEO 21 + +/* Security levels - as per NRL IPv6 - don't actually do anything */ +#define SO_SECURITY_AUTHENTICATION 22 +#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 +#define SO_SECURITY_ENCRYPTION_NETWORK 24 + +#define SO_BINDTODEVICE 25 + +/* Socket filtering */ +#define SO_ATTACH_FILTER 26 +#define SO_DETACH_FILTER 27 +#define SO_GET_FILTER SO_ATTACH_FILTER + +#define SO_PEERNAME 28 +#define SO_TIMESTAMP 29 +#define SCM_TIMESTAMP SO_TIMESTAMP + +#define SO_ACCEPTCONN 30 + +#define SO_PEERSEC 31 +#define SO_PASSSEC 34 +#define SO_TIMESTAMPNS 35 +#define SCM_TIMESTAMPNS SO_TIMESTAMPNS + +#define SO_MARK 36 + +#define SO_TIMESTAMPING 37 +#define SCM_TIMESTAMPING SO_TIMESTAMPING + +#define SO_PROTOCOL 38 +#define SO_DOMAIN 39 + +#define SO_RXQ_OVFL 40 + +#define SO_WIFI_STATUS 41 +#define SCM_WIFI_STATUS SO_WIFI_STATUS +#define SO_PEEK_OFF 42 + +/* Instruct lower device to use last 4-bytes of skb data as FCS */ +#define SO_NOFCS 43 + +#define SO_LOCK_FILTER 44 + +#define SO_SELECT_ERR_QUEUE 45 + +#define SO_BUSY_POLL 46 + +#define SO_MAX_PACING_RATE 47 + +#define SO_BPF_EXTENSIONS 48 + +#define SO_INCOMING_CPU 49 + +#define SO_ATTACH_BPF 50 +#define SO_DETACH_BPF SO_DETACH_FILTER + +#endif /* _ASM_SOCKET_H */ + + diff --git a/kernel/arch/cris/include/uapi/asm/sockios.h b/kernel/arch/cris/include/uapi/asm/sockios.h new file mode 100644 index 000000000..cfe7bfecf --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/sockios.h @@ -0,0 +1,13 @@ +#ifndef __ARCH_CRIS_SOCKIOS__ +#define __ARCH_CRIS_SOCKIOS__ + +/* Socket-level I/O control calls. */ +#define FIOSETOWN 0x8901 +#define SIOCSPGRP 0x8902 +#define FIOGETOWN 0x8903 +#define SIOCGPGRP 0x8904 +#define SIOCATMARK 0x8905 +#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ +#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/stat.h b/kernel/arch/cris/include/uapi/asm/stat.h new file mode 100644 index 000000000..9e558cc3c --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/stat.h @@ -0,0 +1,81 @@ +#ifndef _CRIS_STAT_H +#define _CRIS_STAT_H + +/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in + the kernel if necessary. */ + +struct __old_kernel_stat { + unsigned short st_dev; + unsigned short st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned long st_size; + unsigned long st_atime; + unsigned long st_mtime; + unsigned long st_ctime; +}; + +#define STAT_HAVE_NSEC 1 + +struct stat { + unsigned long st_dev; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned long st_rdev; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long st_atime_nsec; + unsigned long st_mtime; + unsigned long st_mtime_nsec; + unsigned long st_ctime; + unsigned long st_ctime_nsec; + unsigned long __unused4; + unsigned long __unused5; +}; + +/* This matches struct stat64 in glibc2.1, hence the absolutely + * insane amounts of padding around dev_t's. + */ +struct stat64 { + unsigned long long st_dev; + unsigned char __pad0[4]; + +#define STAT64_HAS_BROKEN_ST_INO 1 + unsigned long __st_ino; + + unsigned int st_mode; + unsigned int st_nlink; + + unsigned long st_uid; + unsigned long st_gid; + + unsigned long long st_rdev; + unsigned char __pad3[4]; + + long long st_size; + unsigned long st_blksize; + + unsigned long st_blocks; /* Number 512-byte blocks allocated. */ + unsigned long __pad4; /* future possible st_blocks high bits */ + + unsigned long st_atime; + unsigned long st_atime_nsec; + + unsigned long st_mtime; + unsigned long st_mtime_nsec; + + unsigned long st_ctime; + unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ + + unsigned long long st_ino; +}; + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/statfs.h b/kernel/arch/cris/include/uapi/asm/statfs.h new file mode 100644 index 000000000..fdaf92184 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/statfs.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_STATFS_H +#define _CRIS_STATFS_H + +#include + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/swab.h b/kernel/arch/cris/include/uapi/asm/swab.h new file mode 100644 index 000000000..4adf1e9f0 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/swab.h @@ -0,0 +1,3 @@ +/* + * CRIS byte swapping. + */ diff --git a/kernel/arch/cris/include/uapi/asm/sync_serial.h b/kernel/arch/cris/include/uapi/asm/sync_serial.h new file mode 100644 index 000000000..7f827fea3 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/sync_serial.h @@ -0,0 +1,132 @@ +/* + * ioctl defines for synchronous serial port driver + * + * Copyright (c) 2001-2003 Axis Communications AB + * + * Author: Mikael Starvik + * + */ + +#ifndef SYNC_SERIAL_H +#define SYNC_SERIAL_H + +#include + +#define SSP_SPEED _IOR('S', 0, unsigned int) +#define SSP_MODE _IOR('S', 1, unsigned int) +#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) +#define SSP_IPOLARITY _IOR('S', 3, unsigned int) +#define SSP_OPOLARITY _IOR('S', 4, unsigned int) +#define SSP_SPI _IOR('S', 5, unsigned int) +#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) +#define SSP_INPUT _IOR('S', 7, unsigned int) + +/* Values for SSP_SPEED */ +#define SSP150 0 +#define SSP300 1 +#define SSP600 2 +#define SSP1200 3 +#define SSP2400 4 +#define SSP4800 5 +#define SSP9600 6 +#define SSP19200 7 +#define SSP28800 8 +#define SSP57600 9 +#define SSP115200 10 +#define SSP230400 11 +#define SSP460800 12 +#define SSP921600 13 +#define SSP3125000 14 +#define CODEC 15 +#define CODEC_f32768 16 + +#define FREQ_4MHz 0 +#define FREQ_2MHz 1 +#define FREQ_1MHz 2 +#define FREQ_512kHz 3 +#define FREQ_256kHz 4 +#define FREQ_128kHz 5 +#define FREQ_64kHz 6 +#define FREQ_32kHz 7 +/* FREQ_* with values where bit (value & 0x10) is set are */ +/* used for CODEC_f32768 */ +#define FREQ_4096kHz 16 /* CODEC_f32768 */ + +/* Used by application to set CODEC divider, word rate and frame rate */ +#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \ + ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \ + (clk_per_sync << 16) | (sync_per_frame << 28)) + +/* Used by driver to extract speed */ +#define GET_SPEED(x) (x & 0xff) +#define GET_FREQ(x) ((x & 0xff00) >> 8) +#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) +#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) + +/* Values for SSP_MODE */ +#define MASTER_OUTPUT 0 +#define SLAVE_OUTPUT 1 +#define MASTER_INPUT 2 +#define SLAVE_INPUT 3 +#define MASTER_BIDIR 4 +#define SLAVE_BIDIR 5 + +/* Values for SSP_FRAME_SYNC */ +#define NORMAL_SYNC 1 +#define EARLY_SYNC 2 +#define SECOND_WORD_SYNC 0x40000 +#define LATE_SYNC 0x80000 + +#define BIT_SYNC 4 +#define WORD_SYNC 8 +#define EXTENDED_SYNC 0x10 + +#define SYNC_OFF 0x20 +#define SYNC_ON 0x40 +#define WORD_SIZE_8 0x80 +#define WORD_SIZE_12 0x100 +#define WORD_SIZE_16 0x200 +#define WORD_SIZE_24 0x400 +#define WORD_SIZE_32 0x800 +#define BIT_ORDER_LSB 0x1000 +#define BIT_ORDER_MSB 0x2000 +#define FLOW_CONTROL_ENABLE 0x4000 +#define FLOW_CONTROL_DISABLE 0x8000 +#define CLOCK_GATED 0x10000 +#define CLOCK_NOT_GATED 0x20000 + +/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ +#define CLOCK_NORMAL 1 +#define CLOCK_INVERT 2 +#define CLOCK_INEGEDGE CLOCK_NORMAL +#define CLOCK_IPOSEDGE CLOCK_INVERT +#define FRAME_NORMAL 4 +#define FRAME_INVERT 8 +#define STATUS_NORMAL 0x10 +#define STATUS_INVERT 0x20 + +/* Values for SSP_SPI */ +#define SPI_MASTER 0 +#define SPI_SLAVE 1 + +/* Values for SSP_INBUFCHUNK */ +/* plain integer with the size of DMA chunks */ + +/* To ensure that the timestamps are aligned with the data being read + * the read length MUST be a multiple of the length of the DMA buffers. + * + * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below. + */ +#define SSP_INPUT_CHUNK_SIZE 256 + +/* Request struct to pass through the ioctl interface to read + * data with timestamps. + */ +struct ssp_request { + char __user *buf; /* Where to put the data. */ + size_t len; /* Size of buf. MUST be a multiple of */ + /* SSP_INPUT_CHUNK_SIZE! */ + struct timespec ts; /* The time the data was sampled. */ +}; + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/termbits.h b/kernel/arch/cris/include/uapi/asm/termbits.h new file mode 100644 index 000000000..1c43bc874 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/termbits.h @@ -0,0 +1,235 @@ +/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +#ifndef __ARCH_ETRAX100_TERMBITS_H__ +#define __ARCH_ETRAX100_TERMBITS_H__ + +#include + +typedef unsigned char cc_t; +typedef unsigned int speed_t; +typedef unsigned int tcflag_t; + +#define NCCS 19 +struct termios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ +}; + +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + +struct ktermios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + +/* c_cc characters */ +#define VINTR 0 +#define VQUIT 1 +#define VERASE 2 +#define VKILL 3 +#define VEOF 4 +#define VTIME 5 +#define VMIN 6 +#define VSWTC 7 +#define VSTART 8 +#define VSTOP 9 +#define VSUSP 10 +#define VEOL 11 +#define VREPRINT 12 +#define VDISCARD 13 +#define VWERASE 14 +#define VLNEXT 15 +#define VEOL2 16 + +/* c_iflag bits */ +#define IGNBRK 0000001 +#define BRKINT 0000002 +#define IGNPAR 0000004 +#define PARMRK 0000010 +#define INPCK 0000020 +#define ISTRIP 0000040 +#define INLCR 0000100 +#define IGNCR 0000200 +#define ICRNL 0000400 +#define IUCLC 0001000 +#define IXON 0002000 +#define IXANY 0004000 +#define IXOFF 0010000 +#define IMAXBEL 0020000 +#define IUTF8 0040000 + +/* c_oflag bits */ +#define OPOST 0000001 +#define OLCUC 0000002 +#define ONLCR 0000004 +#define OCRNL 0000010 +#define ONOCR 0000020 +#define ONLRET 0000040 +#define OFILL 0000100 +#define OFDEL 0000200 +#define NLDLY 0000400 +#define NL0 0000000 +#define NL1 0000400 +#define CRDLY 0003000 +#define CR0 0000000 +#define CR1 0001000 +#define CR2 0002000 +#define CR3 0003000 +#define TABDLY 0014000 +#define TAB0 0000000 +#define TAB1 0004000 +#define TAB2 0010000 +#define TAB3 0014000 +#define XTABS 0014000 +#define BSDLY 0020000 +#define BS0 0000000 +#define BS1 0020000 +#define VTDLY 0040000 +#define VT0 0000000 +#define VT1 0040000 +#define FFDLY 0100000 +#define FF0 0000000 +#define FF1 0100000 + +/* c_cflag bit meaning */ +/* + * 3 2 1 + * 10 987 654 321 098 765 432 109 876 543 210 + * | | ||| CBAUD + * obaud + * + * ||CSIZE + * + * |CSTOP + * |CREAD + * |CPARENB + * + * |CPARODD + * |HUPCL + * |CLOCAL + * |CBAUDEX + * 10 987 654 321 098 765 432 109 876 543 210 + * | || || CIBAUD, IBSHIFT=16 + * ibaud + * |CMSPAR + * | CRTSCTS + * x x xxx xxx x x xx Free bits + */ + +#define CBAUD 0010017 +#define B0 0000000 /* hang up */ +#define B50 0000001 +#define B75 0000002 +#define B110 0000003 +#define B134 0000004 +#define B150 0000005 +#define B200 0000006 +#define B300 0000007 +#define B600 0000010 +#define B1200 0000011 +#define B1800 0000012 +#define B2400 0000013 +#define B4800 0000014 +#define B9600 0000015 +#define B19200 0000016 +#define B38400 0000017 +#define EXTA B19200 +#define EXTB B38400 +#define CSIZE 0000060 +#define CS5 0000000 +#define CS6 0000020 +#define CS7 0000040 +#define CS8 0000060 +#define CSTOPB 0000100 +#define CREAD 0000200 +#define PARENB 0000400 +#define PARODD 0001000 +#define HUPCL 0002000 +#define CLOCAL 0004000 +#define CBAUDEX 0010000 +#define BOTHER 0010000 +#define B57600 0010001 +#define B115200 0010002 +#define B230400 0010003 +#define B460800 0010004 + +/* Unsupported rates, but needed to avoid compile error. */ +#define B500000 0010005 +#define B576000 0010006 +#define B1000000 0010010 +#define B1152000 0010011 +#define B1500000 0010012 +#define B2000000 0010013 +#define B2500000 0010014 +#define B3000000 0010015 +#define B3500000 0010016 +#define B4000000 0010017 + +/* etrax supports these additional three baud rates */ +#define B921600 0010005 +#define B1843200 0010006 +#define B6250000 0010007 +/* ETRAX FS supports this as well */ +#define B12500000 0010010 +#define CIBAUD 002003600000 /* input baud rate (used in v32) */ +/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX + * shifted left IBSHIFT bits. + */ +#define IBSHIFT 16 +#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ +#define CRTSCTS 020000000000 /* flow control */ + +/* c_lflag bits */ +#define ISIG 0000001 +#define ICANON 0000002 +#define XCASE 0000004 +#define ECHO 0000010 +#define ECHOE 0000020 +#define ECHOK 0000040 +#define ECHONL 0000100 +#define NOFLSH 0000200 +#define TOSTOP 0000400 +#define ECHOCTL 0001000 +#define ECHOPRT 0002000 +#define ECHOKE 0004000 +#define FLUSHO 0010000 +#define PENDIN 0040000 +#define IEXTEN 0100000 +#define EXTPROC 0200000 + +/* tcflow() and TCXONC use these */ +#define TCOOFF 0 +#define TCOON 1 +#define TCIOFF 2 +#define TCION 3 + +/* tcflush() and TCFLSH use these */ +#define TCIFLUSH 0 +#define TCOFLUSH 1 +#define TCIOFLUSH 2 + +/* tcsetattr uses these */ +#define TCSANOW 0 +#define TCSADRAIN 1 +#define TCSAFLUSH 2 + +#endif diff --git a/kernel/arch/cris/include/uapi/asm/termios.h b/kernel/arch/cris/include/uapi/asm/termios.h new file mode 100644 index 000000000..0a0386a55 --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/termios.h @@ -0,0 +1,45 @@ +#ifndef _UAPI_CRIS_TERMIOS_H +#define _UAPI_CRIS_TERMIOS_H + +#include +#include +#include +#include + +struct winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define NCC 8 +struct termio { + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + unsigned char c_line; /* line discipline */ + unsigned char c_cc[NCC]; /* control characters */ +}; + +/* modem lines */ +#define TIOCM_LE 0x001 +#define TIOCM_DTR 0x002 +#define TIOCM_RTS 0x004 +#define TIOCM_ST 0x008 +#define TIOCM_SR 0x010 +#define TIOCM_CTS 0x020 +#define TIOCM_CAR 0x040 +#define TIOCM_RNG 0x080 +#define TIOCM_DSR 0x100 +#define TIOCM_CD TIOCM_CAR +#define TIOCM_RI TIOCM_RNG +#define TIOCM_OUT1 0x2000 +#define TIOCM_OUT2 0x4000 +#define TIOCM_LOOP 0x8000 + +/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ + + +#endif /* _UAPI_CRIS_TERMIOS_H */ diff --git a/kernel/arch/cris/include/uapi/asm/types.h b/kernel/arch/cris/include/uapi/asm/types.h new file mode 100644 index 000000000..9ec9d4c5a --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/types.h @@ -0,0 +1 @@ +#include diff --git a/kernel/arch/cris/include/uapi/asm/unistd.h b/kernel/arch/cris/include/uapi/asm/unistd.h new file mode 100644 index 000000000..f3287face --- /dev/null +++ b/kernel/arch/cris/include/uapi/asm/unistd.h @@ -0,0 +1,360 @@ +#ifndef _UAPI_ASM_CRIS_UNISTD_H_ +#define _UAPI_ASM_CRIS_UNISTD_H_ + +/* + * This file contains the system call numbers, and stub macros for libc. + */ + +#define __NR_restart_syscall 0 +#define __NR_exit 1 +#define __NR_fork 2 +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 +#define __NR_waitpid 7 +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_lchown 16 +#define __NR_break 17 +#define __NR_oldstat 18 +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 +#define __NR_umount 22 +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 +#define __NR_oldfstat 28 +#define __NR_pause 29 +#define __NR_utime 30 +#define __NR_stty 31 +#define __NR_gtty 32 +#define __NR_access 33 +#define __NR_nice 34 +#define __NR_ftime 35 +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 +#define __NR_prof 44 +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 +#define __NR_signal 48 +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 +#define __NR_lock 53 +#define __NR_ioctl 54 +#define __NR_fcntl 55 +#define __NR_mpx 56 +#define __NR_setpgid 57 +#define __NR_ulimit 58 +#define __NR_oldolduname 59 +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 +#define __NR_sigaction 67 +#define __NR_sgetmask 68 +#define __NR_ssetmask 69 +#define __NR_setreuid 70 +#define __NR_setregid 71 +#define __NR_sigsuspend 72 +#define __NR_sigpending 73 +#define __NR_sethostname 74 +#define __NR_setrlimit 75 +#define __NR_getrlimit 76 +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 +#define __NR_select 82 +#define __NR_symlink 83 +#define __NR_oldlstat 84 +#define __NR_readlink 85 +#define __NR_uselib 86 +#define __NR_swapon 87 +#define __NR_reboot 88 +#define __NR_readdir 89 +#define __NR_mmap 90 +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 +#define __NR_profil 98 +#define __NR_statfs 99 +#define __NR_fstatfs 100 +#define __NR_ioperm 101 +#define __NR_socketcall 102 +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 +#define __NR_olduname 109 +#define __NR_iopl 110 +#define __NR_vhangup 111 +#define __NR_idle 112 +#define __NR_vm86 113 +#define __NR_wait4 114 +#define __NR_swapoff 115 +#define __NR_sysinfo 116 +#define __NR_ipc 117 +#define __NR_fsync 118 +#define __NR_sigreturn 119 +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 +#define __NR_modify_ldt 123 +#define __NR_adjtimex 124 +#define __NR_mprotect 125 +#define __NR_sigprocmask 126 +#define __NR_create_module 127 +#define __NR_init_module 128 +#define __NR_delete_module 129 +#define __NR_get_kernel_syms 130 +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 +#define __NR_sysfs 135 +#define __NR_personality 136 +#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 +#define __NR__newselect 142 +#define __NR_flock 143 +#define __NR_msync 144 +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 +#define __NR_mlock 150 +#define __NR_munlock 151 +#define __NR_mlockall 152 +#define __NR_munlockall 153 +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 + +#define __NR_query_module 167 +#define __NR_poll 168 +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread64 180 +#define __NR_pwrite64 181 +#define __NR_chown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 +#define __NR_getpmsg 188 /* some people actually want streams */ +#define __NR_putpmsg 189 /* some people actually want streams */ +#define __NR_vfork 190 +#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_lchown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_chown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_pivot_root 217 +#define __NR_mincore 218 +#define __NR_madvise 219 +#define __NR_getdents64 220 +#define __NR_fcntl64 221 +/* 223 is unused */ +#define __NR_gettid 224 +#define __NR_readahead 225 +#define __NR_setxattr 226 +#define __NR_lsetxattr 227 +#define __NR_fsetxattr 228 +#define __NR_getxattr 229 +#define __NR_lgetxattr 230 +#define __NR_fgetxattr 231 +#define __NR_listxattr 232 +#define __NR_llistxattr 233 +#define __NR_flistxattr 234 +#define __NR_removexattr 235 +#define __NR_lremovexattr 236 +#define __NR_fremovexattr 237 +#define __NR_tkill 238 +#define __NR_sendfile64 239 +#define __NR_futex 240 +#define __NR_sched_setaffinity 241 +#define __NR_sched_getaffinity 242 +#define __NR_set_thread_area 243 +#define __NR_get_thread_area 244 +#define __NR_io_setup 245 +#define __NR_io_destroy 246 +#define __NR_io_getevents 247 +#define __NR_io_submit 248 +#define __NR_io_cancel 249 +#define __NR_fadvise64 250 +/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ +#define __NR_exit_group 252 +#define __NR_lookup_dcookie 253 +#define __NR_epoll_create 254 +#define __NR_epoll_ctl 255 +#define __NR_epoll_wait 256 +#define __NR_remap_file_pages 257 +#define __NR_set_tid_address 258 +#define __NR_timer_create 259 +#define __NR_timer_settime (__NR_timer_create+1) +#define __NR_timer_gettime (__NR_timer_create+2) +#define __NR_timer_getoverrun (__NR_timer_create+3) +#define __NR_timer_delete (__NR_timer_create+4) +#define __NR_clock_settime (__NR_timer_create+5) +#define __NR_clock_gettime (__NR_timer_create+6) +#define __NR_clock_getres (__NR_timer_create+7) +#define __NR_clock_nanosleep (__NR_timer_create+8) +#define __NR_statfs64 268 +#define __NR_fstatfs64 269 +#define __NR_tgkill 270 +#define __NR_utimes 271 +#define __NR_fadvise64_64 272 +#define __NR_vserver 273 +#define __NR_mbind 274 +#define __NR_get_mempolicy 275 +#define __NR_set_mempolicy 276 +#define __NR_mq_open 277 +#define __NR_mq_unlink (__NR_mq_open+1) +#define __NR_mq_timedsend (__NR_mq_open+2) +#define __NR_mq_timedreceive (__NR_mq_open+3) +#define __NR_mq_notify (__NR_mq_open+4) +#define __NR_mq_getsetattr (__NR_mq_open+5) +#define __NR_kexec_load 283 +#define __NR_waitid 284 +/* #define __NR_sys_setaltroot 285 */ +#define __NR_add_key 286 +#define __NR_request_key 287 +#define __NR_keyctl 288 +#define __NR_ioprio_set 289 +#define __NR_ioprio_get 290 +#define __NR_inotify_init 291 +#define __NR_inotify_add_watch 292 +#define __NR_inotify_rm_watch 293 +#define __NR_migrate_pages 294 +#define __NR_openat 295 +#define __NR_mkdirat 296 +#define __NR_mknodat 297 +#define __NR_fchownat 298 +#define __NR_futimesat 299 +#define __NR_fstatat64 300 +#define __NR_unlinkat 301 +#define __NR_renameat 302 +#define __NR_linkat 303 +#define __NR_symlinkat 304 +#define __NR_readlinkat 305 +#define __NR_fchmodat 306 +#define __NR_faccessat 307 +#define __NR_pselect6 308 +#define __NR_ppoll 309 +#define __NR_unshare 310 +#define __NR_set_robust_list 311 +#define __NR_get_robust_list 312 +#define __NR_splice 313 +#define __NR_sync_file_range 314 +#define __NR_tee 315 +#define __NR_vmsplice 316 +#define __NR_move_pages 317 +#define __NR_getcpu 318 +#define __NR_epoll_pwait 319 +#define __NR_utimensat 320 +#define __NR_signalfd 321 +#define __NR_timerfd_create 322 +#define __NR_eventfd 323 +#define __NR_fallocate 324 +#define __NR_timerfd_settime 325 +#define __NR_timerfd_gettime 326 +#define __NR_signalfd4 327 +#define __NR_eventfd2 328 +#define __NR_epoll_create1 329 +#define __NR_dup3 330 +#define __NR_pipe2 331 +#define __NR_inotify_init1 332 +#define __NR_preadv 333 +#define __NR_pwritev 334 +#define __NR_setns 335 +#define __NR_name_to_handle_at 336 +#define __NR_open_by_handle_at 337 +#define __NR_rt_tgsigqueueinfo 338 +#define __NR_perf_event_open 339 +#define __NR_recvmmsg 340 +#define __NR_accept4 341 +#define __NR_fanotify_init 342 +#define __NR_fanotify_mark 343 +#define __NR_prlimit64 344 +#define __NR_clock_adjtime 345 +#define __NR_syncfs 346 +#define __NR_sendmmsg 347 +#define __NR_process_vm_readv 348 +#define __NR_process_vm_writev 349 +#define __NR_kcmp 350 +#define __NR_finit_module 351 + +#endif /* _UAPI_ASM_CRIS_UNISTD_H_ */ diff --git a/kernel/arch/cris/kernel/Makefile b/kernel/arch/cris/kernel/Makefile new file mode 100644 index 000000000..edef71f12 --- /dev/null +++ b/kernel/arch/cris/kernel/Makefile @@ -0,0 +1,17 @@ +# $Id: Makefile,v 1.12 2004/10/19 13:07:43 starvik Exp $ +# +# Makefile for the linux kernel. +# + +CPPFLAGS_vmlinux.lds := -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE) +extra-y := vmlinux.lds + +obj-y := process.o traps.o irq.o ptrace.o setup.o time.o sys_cris.o +obj-y += devicetree.o + +obj-$(CONFIG_MODULES) += crisksyms.o +obj-$(CONFIG_MODULES) += module.o +obj-$(CONFIG_SYSTEM_PROFILER) += profile.o + +clean: + diff --git a/kernel/arch/cris/kernel/asm-offsets.c b/kernel/arch/cris/kernel/asm-offsets.c new file mode 100644 index 000000000..a5fd88d81 --- /dev/null +++ b/kernel/arch/cris/kernel/asm-offsets.c @@ -0,0 +1,59 @@ +#include +#include +#include + +/* + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + */ + +#if !defined(CONFIG_ETRAX_ARCH_V10) && !defined(CONFIG_ETRAX_ARCH_V32) +#error One of ARCH v10 and ARCH v32 must be true! +#endif + +int main(void) +{ +#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry)) + ENTRY(orig_r10); + ENTRY(r13); + ENTRY(r12); + ENTRY(r11); + ENTRY(r10); + ENTRY(r9); +#ifdef CONFIG_ETRAX_ARCH_V32 + ENTRY(acr); + ENTRY(srs); +#endif + ENTRY(mof); +#ifdef CONFIG_ETRAX_ARCH_V10 + ENTRY(dccr); +#else + ENTRY(ccs); +#endif + ENTRY(srp); + BLANK(); +#undef ENTRY +#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry)) + ENTRY(task); + ENTRY(flags); + ENTRY(preempt_count); + BLANK(); +#undef ENTRY +#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry)) + ENTRY(ksp); + ENTRY(usp); +#ifdef CONFIG_ETRAX_ARCH_V10 + ENTRY(dccr); +#else + ENTRY(ccs); +#endif + BLANK(); +#undef ENTRY +#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry)) + ENTRY(pid); + BLANK(); + DEFINE(LCLONE_VM, CLONE_VM); + DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED); + return 0; +} diff --git a/kernel/arch/cris/kernel/crisksyms.c b/kernel/arch/cris/kernel/crisksyms.c new file mode 100644 index 000000000..e704f81f8 --- /dev/null +++ b/kernel/arch/cris/kernel/crisksyms.c @@ -0,0 +1,70 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +extern unsigned long get_cmos_time(void); +extern void __Udiv(void); +extern void __Umod(void); +extern void __Div(void); +extern void __Mod(void); +extern void __ashldi3(void); +extern void __ashrdi3(void); +extern void __lshrdi3(void); +extern void __negdi2(void); +extern void iounmap(volatile void * __iomem); + +/* Platform dependent support */ +EXPORT_SYMBOL(get_cmos_time); +EXPORT_SYMBOL(loops_per_usec); + +/* Math functions */ +EXPORT_SYMBOL(__Udiv); +EXPORT_SYMBOL(__Umod); +EXPORT_SYMBOL(__Div); +EXPORT_SYMBOL(__Mod); +EXPORT_SYMBOL(__ashldi3); +EXPORT_SYMBOL(__ashrdi3); +EXPORT_SYMBOL(__lshrdi3); +EXPORT_SYMBOL(__negdi2); + +/* Memory functions */ +EXPORT_SYMBOL(__ioremap); +EXPORT_SYMBOL(iounmap); + +#undef memcpy +#undef memset +extern void * memset(void *, int, __kernel_size_t); +extern void * memcpy(void *, const void *, __kernel_size_t); +EXPORT_SYMBOL(memcpy); +EXPORT_SYMBOL(memset); +#ifdef CONFIG_ETRAX_ARCH_V32 +#undef strcmp +EXPORT_SYMBOL(strcmp); +#endif + +#ifdef CONFIG_ETRAX_FAST_TIMER +/* Fast timer functions */ +EXPORT_SYMBOL(fast_timer_list); +EXPORT_SYMBOL(start_one_shot_timer); +EXPORT_SYMBOL(del_fast_timer); +EXPORT_SYMBOL(schedule_usleep); +#endif +EXPORT_SYMBOL(csum_partial); +EXPORT_SYMBOL(csum_partial_copy_from_user); +EXPORT_SYMBOL(csum_partial_copy_nocheck); diff --git a/kernel/arch/cris/kernel/devicetree.c b/kernel/arch/cris/kernel/devicetree.c new file mode 100644 index 000000000..53ff8d73e --- /dev/null +++ b/kernel/arch/cris/kernel/devicetree.c @@ -0,0 +1,14 @@ +#include +#include +#include + +void __init early_init_dt_add_memory_arch(u64 base, u64 size) +{ + pr_err("%s(%llx, %llx)\n", + __func__, base, size); +} + +void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) +{ + return alloc_bootmem_align(size, align); +} diff --git a/kernel/arch/cris/kernel/irq.c b/kernel/arch/cris/kernel/irq.c new file mode 100644 index 000000000..dd0be5de5 --- /dev/null +++ b/kernel/arch/cris/kernel/irq.c @@ -0,0 +1,66 @@ +/* + * + * linux/arch/cris/kernel/irq.c + * + * Copyright (c) 2000,2007 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * + * This file contains the code used by various IRQ handling routines: + * asking for different IRQs should be done through these routines + * instead of just grabbing them. Thus setups with different IRQ numbers + * shouldn't result in any weird surprises, and installing new handlers + * should be easier. + * + */ + +/* + * IRQs are in fact implemented a bit like signal handlers for the kernel. + * Naturally it's not a 1:1 relation, but there are similarities. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* called by the assembler IRQ entry functions defined in irq.h + * to dispatch the interrupts to registered handlers + */ + +asmlinkage void do_IRQ(int irq, struct pt_regs * regs) +{ + unsigned long sp; + struct pt_regs *old_regs = set_irq_regs(regs); + irq_enter(); + sp = rdsp(); + if (unlikely((sp & (PAGE_SIZE - 1)) < (PAGE_SIZE/8))) { + printk("do_IRQ: stack overflow: %lX\n", sp); + show_stack(NULL, (unsigned long *)sp); + } + generic_handle_irq(irq); + irq_exit(); + set_irq_regs(old_regs); +} + +void weird_irq(void) +{ + local_irq_disable(); + printk("weird irq\n"); + while(1); +} + diff --git a/kernel/arch/cris/kernel/module.c b/kernel/arch/cris/kernel/module.c new file mode 100644 index 000000000..af04cb6b6 --- /dev/null +++ b/kernel/arch/cris/kernel/module.c @@ -0,0 +1,82 @@ +/* Kernel module help for i386. + Copyright (C) 2001 Rusty Russell. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ +#include +#include +#include +#include +#include +#include +#include + +#if 0 +#define DEBUGP printk +#else +#define DEBUGP(fmt , ...) +#endif + +#ifdef CONFIG_ETRAX_KMALLOCED_MODULES +void *module_alloc(unsigned long size) +{ + return kmalloc(size, GFP_KERNEL); +} + +/* Free memory returned from module_alloc */ +void module_memfree(void *module_region) +{ + kfree(module_region); +} +#endif + +int apply_relocate_add(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + unsigned int i; + Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr; + + DEBUGP ("Applying add relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + + for (i = 0; i < sechdrs[relsec].sh_size / sizeof (*rela); i++) { + /* This is where to make the change */ + uint32_t *loc + = ((void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + + rela[i].r_offset); + /* This is the symbol it is referring to. Note that all + undefined symbols have been resolved. */ + Elf32_Sym *sym + = ((Elf32_Sym *)sechdrs[symindex].sh_addr + + ELF32_R_SYM (rela[i].r_info)); + switch (ELF32_R_TYPE(rela[i].r_info)) { + case R_CRIS_32: + *loc = sym->st_value + rela[i].r_addend; + break; + case R_CRIS_32_PCREL: + *loc = sym->st_value - (unsigned)loc + rela[i].r_addend - 4; + break; + default: + printk(KERN_ERR "module %s: Unknown relocation: %u\n", + me->name, ELF32_R_TYPE(rela[i].r_info)); + return -ENOEXEC; + } + } + + return 0; +} diff --git a/kernel/arch/cris/kernel/process.c b/kernel/arch/cris/kernel/process.c new file mode 100644 index 000000000..b78498eb0 --- /dev/null +++ b/kernel/arch/cris/kernel/process.c @@ -0,0 +1,79 @@ +/* + * linux/arch/cris/kernel/process.c + * + * Copyright (C) 1995 Linus Torvalds + * Copyright (C) 2000-2002 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * + */ + +/* + * This file handles the architecture-dependent parts of process handling.. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//#define DEBUG + +extern void default_idle(void); + +void (*pm_power_off)(void); +EXPORT_SYMBOL(pm_power_off); + +void arch_cpu_idle(void) +{ + default_idle(); +} + +void hard_reset_now (void); + +void machine_restart(char *cmd) +{ + hard_reset_now(); +} + +/* + * Similar to machine_power_off, but don't shut off power. Add code + * here to freeze the system for e.g. post-mortem debug purpose when + * possible. This halt has nothing to do with the idle halt. + */ + +void machine_halt(void) +{ +} + +/* If or when software power-off is implemented, add code here. */ + +void machine_power_off(void) +{ +} + +/* + * When a process does an "exec", machine state like FPU and debug + * registers need to be reset. This is a hook function for that. + * Currently we don't have any such state to reset, so this is empty. + */ + +void flush_thread(void) +{ +} + +/* Fill in the fpu structure for a core dump. */ +int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu) +{ + return 0; +} diff --git a/kernel/arch/cris/kernel/profile.c b/kernel/arch/cris/kernel/profile.c new file mode 100644 index 000000000..cd9f15b92 --- /dev/null +++ b/kernel/arch/cris/kernel/profile.c @@ -0,0 +1,86 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#define SAMPLE_BUFFER_SIZE 8192 + +static char *sample_buffer; +static char *sample_buffer_pos; +static int prof_running = 0; + +void cris_profile_sample(struct pt_regs *regs) +{ + if (!prof_running) + return; + + if (user_mode(regs)) + *(unsigned int*)sample_buffer_pos = current->pid; + else + *(unsigned int*)sample_buffer_pos = 0; + + *(unsigned int *)(sample_buffer_pos + 4) = instruction_pointer(regs); + sample_buffer_pos += 8; + + if (sample_buffer_pos == sample_buffer + SAMPLE_BUFFER_SIZE) + sample_buffer_pos = sample_buffer; +} + +static ssize_t +read_cris_profile(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + unsigned long p = *ppos; + ssize_t ret; + + ret = simple_read_from_buffer(buf, count, ppos, sample_buffer, + SAMPLE_BUFFER_SIZE); + if (ret < 0) + return ret; + + memset(sample_buffer + p, 0, ret); + + return ret; +} + +static ssize_t +write_cris_profile(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + sample_buffer_pos = sample_buffer; + memset(sample_buffer, 0, SAMPLE_BUFFER_SIZE); + return count < SAMPLE_BUFFER_SIZE ? count : SAMPLE_BUFFER_SIZE; +} + +static const struct file_operations cris_proc_profile_operations = { + .read = read_cris_profile, + .write = write_cris_profile, + .llseek = default_llseek, +}; + +static int __init init_cris_profile(void) +{ + struct proc_dir_entry *entry; + + sample_buffer = kmalloc(SAMPLE_BUFFER_SIZE, GFP_KERNEL); + if (!sample_buffer) { + return -ENOMEM; + } + + sample_buffer_pos = sample_buffer; + + entry = proc_create("system_profile", S_IWUSR | S_IRUGO, NULL, + &cris_proc_profile_operations); + if (entry) { + proc_set_size(entry, SAMPLE_BUFFER_SIZE); + } + prof_running = 1; + + return 0; +} +__initcall(init_cris_profile); + diff --git a/kernel/arch/cris/kernel/ptrace.c b/kernel/arch/cris/kernel/ptrace.c new file mode 100644 index 000000000..fd3427e56 --- /dev/null +++ b/kernel/arch/cris/kernel/ptrace.c @@ -0,0 +1,67 @@ +/* + * linux/arch/cris/kernel/ptrace.c + * + * Parts taken from the m68k port. + * + * Copyright (c) 2000, 2001, 2002 Axis Communications AB + * + * Authors: Bjorn Wesen + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +/* notification of userspace execution resumption + * - triggered by current->work.notify_resume + */ +extern int do_signal(int canrestart, struct pt_regs *regs); + + +void do_notify_resume(int canrestart, struct pt_regs *regs, + __u32 thread_info_flags) +{ + /* deal with pending signal delivery */ + if (thread_info_flags & _TIF_SIGPENDING) + do_signal(canrestart,regs); + + if (thread_info_flags & _TIF_NOTIFY_RESUME) { + clear_thread_flag(TIF_NOTIFY_RESUME); + tracehook_notify_resume(regs); + } +} + +void do_work_pending(int syscall, struct pt_regs *regs, + unsigned int thread_flags) +{ + do { + if (likely(thread_flags & _TIF_NEED_RESCHED)) { + schedule(); + } else { + if (unlikely(!user_mode(regs))) + return; + local_irq_enable(); + if (thread_flags & _TIF_SIGPENDING) { + do_signal(syscall, regs); + syscall = 0; + } else { + clear_thread_flag(TIF_NOTIFY_RESUME); + tracehook_notify_resume(regs); + } + } + local_irq_disable(); + thread_flags = current_thread_info()->flags; + } while (thread_flags & _TIF_WORK_MASK); +} diff --git a/kernel/arch/cris/kernel/setup.c b/kernel/arch/cris/kernel/setup.c new file mode 100644 index 000000000..bb12aa932 --- /dev/null +++ b/kernel/arch/cris/kernel/setup.c @@ -0,0 +1,221 @@ +/* + * + * linux/arch/cris/kernel/setup.c + * + * Copyright (C) 1995 Linus Torvalds + * Copyright (c) 2001 Axis Communications AB + */ + +/* + * This file handles the architecture-dependent parts of initialization + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Setup options + */ +struct screen_info screen_info; + +extern int root_mountflags; +extern char _etext, _edata, _end; + +char __initdata cris_command_line[COMMAND_LINE_SIZE] = { 0, }; + +extern const unsigned long text_start, edata; /* set by the linker script */ +extern unsigned long dram_start, dram_end; + +extern unsigned long romfs_start, romfs_length, romfs_in_flash; /* from head.S */ + +static struct cpu cpu_devices[NR_CPUS]; + +extern void show_etrax_copyright(void); /* arch-vX/kernel/setup.c */ + +/* This mainly sets up the memory area, and can be really confusing. + * + * The physical DRAM is virtually mapped into dram_start to dram_end + * (usually c0000000 to c0000000 + DRAM size). The physical address is + * given by the macro __pa(). + * + * In this DRAM, the kernel code and data is loaded, in the beginning. + * It really starts at c0004000 to make room for some special pages - + * the start address is text_start. The kernel data ends at _end. After + * this the ROM filesystem is appended (if there is any). + * + * Between this address and dram_end, we have RAM pages usable to the + * boot code and the system. + * + */ + +void __init setup_arch(char **cmdline_p) +{ + extern void init_etrax_debug(void); + unsigned long bootmap_size; + unsigned long start_pfn, max_pfn; + unsigned long memory_start; + +#ifdef CONFIG_OF + early_init_dt_scan(__dtb_start); +#endif + + /* register an initial console printing routine for printk's */ + + init_etrax_debug(); + + /* we should really poll for DRAM size! */ + + high_memory = &dram_end; + + if(romfs_in_flash || !romfs_length) { + /* if we have the romfs in flash, or if there is no rom filesystem, + * our free area starts directly after the BSS + */ + memory_start = (unsigned long) &_end; + } else { + /* otherwise the free area starts after the ROM filesystem */ + printk("ROM fs in RAM, size %lu bytes\n", romfs_length); + memory_start = romfs_start + romfs_length; + } + + /* process 1's initial memory region is the kernel code/data */ + + init_mm.start_code = (unsigned long) &text_start; + init_mm.end_code = (unsigned long) &_etext; + init_mm.end_data = (unsigned long) &_edata; + init_mm.brk = (unsigned long) &_end; + + /* min_low_pfn points to the start of DRAM, start_pfn points + * to the first DRAM pages after the kernel, and max_low_pfn + * to the end of DRAM. + */ + + /* + * partially used pages are not usable - thus + * we are rounding upwards: + */ + + start_pfn = PFN_UP(memory_start); /* usually c0000000 + kernel + romfs */ + max_pfn = PFN_DOWN((unsigned long)high_memory); /* usually c0000000 + dram size */ + + /* + * Initialize the boot-time allocator (start, end) + * + * We give it access to all our DRAM, but we could as well just have + * given it a small slice. No point in doing that though, unless we + * have non-contiguous memory and want the boot-stuff to be in, say, + * the smallest area. + * + * It will put a bitmap of the allocated pages in the beginning + * of the range we give it, but it won't mark the bitmaps pages + * as reserved. We have to do that ourselves below. + * + * We need to use init_bootmem_node instead of init_bootmem + * because our map starts at a quite high address (min_low_pfn). + */ + + max_low_pfn = max_pfn; + min_low_pfn = PAGE_OFFSET >> PAGE_SHIFT; + + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn, + min_low_pfn, + max_low_pfn); + + /* And free all memory not belonging to the kernel (addr, size) */ + + free_bootmem(PFN_PHYS(start_pfn), PFN_PHYS(max_pfn - start_pfn)); + + /* + * Reserve the bootmem bitmap itself as well. We do this in two + * steps (first step was init_bootmem()) because this catches + * the (very unlikely) case of us accidentally initializing the + * bootmem allocator with an invalid RAM area. + * + * Arguments are start, size + */ + + reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size, BOOTMEM_DEFAULT); + + unflatten_and_copy_device_tree(); + + /* paging_init() sets up the MMU and marks all pages as reserved */ + + paging_init(); + + *cmdline_p = cris_command_line; + +#ifdef CONFIG_ETRAX_CMDLINE + if (!strcmp(cris_command_line, "")) { + strlcpy(cris_command_line, CONFIG_ETRAX_CMDLINE, COMMAND_LINE_SIZE); + cris_command_line[COMMAND_LINE_SIZE - 1] = '\0'; + } +#endif + + /* Save command line for future references. */ + memcpy(boot_command_line, cris_command_line, COMMAND_LINE_SIZE); + boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; + + /* give credit for the CRIS port */ + show_etrax_copyright(); + + /* Setup utsname */ + strcpy(init_utsname()->machine, cris_machine_name); +} + +#ifdef CONFIG_PROC_FS +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < nr_cpu_ids ? (void *)(int)(*pos + 1) : NULL; +} + +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return c_start(m, pos); +} + +static void c_stop(struct seq_file *m, void *v) +{ +} + +extern int show_cpuinfo(struct seq_file *m, void *v); + +const struct seq_operations cpuinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = show_cpuinfo, +}; +#endif /* CONFIG_PROC_FS */ + +static int __init topology_init(void) +{ + int i; + + for_each_possible_cpu(i) { + return register_cpu(&cpu_devices[i], i); + } + + return 0; +} + +subsys_initcall(topology_init); + +static int __init cris_of_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + return 0; +} +core_initcall(cris_of_init); diff --git a/kernel/arch/cris/kernel/sys_cris.c b/kernel/arch/cris/kernel/sys_cris.c new file mode 100644 index 000000000..7aa036ec7 --- /dev/null +++ b/kernel/arch/cris/kernel/sys_cris.c @@ -0,0 +1,35 @@ +/* $Id: sys_cris.c,v 1.6 2004/03/11 11:38:40 starvik Exp $ + * + * linux/arch/cris/kernel/sys_cris.c + * + * This file contains various random system calls that + * have a non-standard calling sequence on some platforms. + * Since we don't have to do any backwards compatibility, our + * versions are done in the most "normal" way possible. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +asmlinkage long +sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot, + unsigned long flags, unsigned long fd, unsigned long pgoff) +{ + /* bug(?): 8Kb pages here */ + return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff); +} diff --git a/kernel/arch/cris/kernel/time.c b/kernel/arch/cris/kernel/time.c new file mode 100644 index 000000000..7780d3795 --- /dev/null +++ b/kernel/arch/cris/kernel/time.c @@ -0,0 +1,97 @@ +/* + * linux/arch/cris/kernel/time.c + * + * Copyright (C) 1991, 1992, 1995 Linus Torvalds + * Copyright (C) 1999, 2000, 2001 Axis Communications AB + * + * 1994-07-02 Alan Modra + * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime + * 1995-03-26 Markus Kuhn + * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887 + * precision CMOS clock update + * 1996-05-03 Ingo Molnar + * fixed time warps in do_[slow|fast]_gettimeoffset() + * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + * + * Linux/CRIS specific code: + * + * Authors: Bjorn Wesen + * Johan Adolfsson + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include /* just for sched_clock() - funny that */ + + +#define D(x) + +#define TICK_SIZE tick + +extern unsigned long loops_per_jiffy; /* init/main.c */ +unsigned long loops_per_usec; + +int set_rtc_mmss(unsigned long nowtime) +{ + D(printk(KERN_DEBUG "set_rtc_mmss(%lu)\n", nowtime)); + return 0; +} + +/* grab the time from the RTC chip */ +unsigned long get_cmos_time(void) +{ + return 0; +} + + +int update_persistent_clock(struct timespec now) +{ + return set_rtc_mmss(now.tv_sec); +} + +void read_persistent_clock(struct timespec *ts) +{ + ts->tv_sec = 0; + ts->tv_nsec = 0; +} + + +extern void cris_profile_sample(struct pt_regs* regs); + +void +cris_do_profile(struct pt_regs* regs) +{ + +#ifdef CONFIG_SYSTEM_PROFILER + cris_profile_sample(regs); +#endif + +#ifdef CONFIG_PROFILING + profile_tick(CPU_PROFILING); +#endif +} + +#ifndef CONFIG_GENERIC_SCHED_CLOCK +unsigned long long sched_clock(void) +{ + return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ) + + get_ns_in_jiffie(); +} +#endif + +static int +__init init_udelay(void) +{ + loops_per_usec = (loops_per_jiffy * HZ) / 1000000; + return 0; +} + +__initcall(init_udelay); diff --git a/kernel/arch/cris/kernel/traps.c b/kernel/arch/cris/kernel/traps.c new file mode 100644 index 000000000..da4c72401 --- /dev/null +++ b/kernel/arch/cris/kernel/traps.c @@ -0,0 +1,239 @@ +/* + * linux/arch/cris/traps.c + * + * Here we handle the break vectors not used by the system call + * mechanism, as well as some general stack/register dumping + * things. + * + * Copyright (C) 2000-2007 Axis Communications AB + * + * Authors: Bjorn Wesen + * Hans-Peter Nilsson + * + */ + +#include +#include +#include +#ifdef CONFIG_KALLSYMS +#include +#endif + +#include +#include +#include + +extern void arch_enable_nmi(void); +extern void stop_watchdog(void); +extern void reset_watchdog(void); +extern void show_registers(struct pt_regs *regs); + +#ifdef CONFIG_DEBUG_BUGVERBOSE +extern void handle_BUG(struct pt_regs *regs); +#else +#define handle_BUG(regs) +#endif + +static int kstack_depth_to_print = 24; + +void (*nmi_handler)(struct pt_regs *); + +void show_trace(unsigned long *stack) +{ + unsigned long addr, module_start, module_end; + extern char _stext, _etext; + int i; + + pr_err("\nCall Trace: "); + + i = 1; + module_start = VMALLOC_START; + module_end = VMALLOC_END; + + while (((long)stack & (THREAD_SIZE - 1)) != 0) { + if (__get_user(addr, stack)) { + /* This message matches "failing address" marked + s390 in ksymoops, so lines containing it will + not be filtered out by ksymoops. */ + pr_err("Failing address 0x%lx\n", (unsigned long)stack); + break; + } + stack++; + + /* + * If the address is either in the text segment of the + * kernel, or in the region which contains vmalloc'ed + * memory, it *may* be the address of a calling + * routine; if so, print it so that someone tracing + * down the cause of the crash will be able to figure + * out the call path that was taken. + */ + if (((addr >= (unsigned long)&_stext) && + (addr <= (unsigned long)&_etext)) || + ((addr >= module_start) && (addr <= module_end))) { +#ifdef CONFIG_KALLSYMS + print_ip_sym(addr); +#else + if (i && ((i % 8) == 0)) + pr_err("\n "); + pr_err("[<%08lx>] ", addr); + i++; +#endif + } + } +} + +/* + * These constants are for searching for possible module text + * segments. MODULE_RANGE is a guess of how much space is likely + * to be vmalloced. + */ + +#define MODULE_RANGE (8*1024*1024) + +/* + * The output (format, strings and order) is adjusted to be usable with + * ksymoops-2.4.1 with some necessary CRIS-specific patches. Please don't + * change it unless you're serious about adjusting ksymoops and syncing + * with the ksymoops maintainer. + */ + +void +show_stack(struct task_struct *task, unsigned long *sp) +{ + unsigned long *stack, addr; + int i; + + /* + * debugging aid: "show_stack(NULL);" prints a + * back trace. + */ + + if (sp == NULL) { + if (task) + sp = (unsigned long*)task->thread.ksp; + else + sp = (unsigned long*)rdsp(); + } + + stack = sp; + + pr_err("\nStack from %08lx:\n ", (unsigned long)stack); + for (i = 0; i < kstack_depth_to_print; i++) { + if (((long)stack & (THREAD_SIZE-1)) == 0) + break; + if (i && ((i % 8) == 0)) + pr_err("\n "); + if (__get_user(addr, stack)) { + /* This message matches "failing address" marked + s390 in ksymoops, so lines containing it will + not be filtered out by ksymoops. */ + pr_err("Failing address 0x%lx\n", (unsigned long)stack); + break; + } + stack++; + pr_err("%08lx ", addr); + } + show_trace(sp); +} + +#if 0 +/* displays a short stack trace */ + +int +show_stack(void) +{ + unsigned long *sp = (unsigned long *)rdusp(); + int i; + + pr_err("Stack dump [0x%08lx]:\n", (unsigned long)sp); + for (i = 0; i < 16; i++) + pr_err("sp + %d: 0x%08lx\n", i*4, sp[i]); + return 0; +} +#endif + +void set_nmi_handler(void (*handler)(struct pt_regs *)) +{ + nmi_handler = handler; + arch_enable_nmi(); +} + +#ifdef CONFIG_DEBUG_NMI_OOPS +void oops_nmi_handler(struct pt_regs *regs) +{ + stop_watchdog(); + oops_in_progress = 1; + pr_err("NMI!\n"); + show_registers(regs); + oops_in_progress = 0; + oops_exit(); + pr_err("\n"); /* Flush mtdoops. */ +} + +static int __init oops_nmi_register(void) +{ + set_nmi_handler(oops_nmi_handler); + return 0; +} + +__initcall(oops_nmi_register); + +#endif + +/* + * This gets called from entry.S when the watchdog has bitten. Show something + * similar to an Oops dump, and if the kernel is configured to be a nice + * doggy, then halt instead of reboot. + */ +void watchdog_bite_hook(struct pt_regs *regs) +{ +#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY + local_irq_disable(); + stop_watchdog(); + show_registers(regs); + + while (1) + ; /* Do nothing. */ +#else + show_registers(regs); +#endif +} + +/* This is normally the Oops function. */ +void die_if_kernel(const char *str, struct pt_regs *regs, long err) +{ + if (user_mode(regs)) + return; + +#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY + /* + * This printout might take too long and could trigger + * the watchdog normally. If NICE_DOGGY is set, simply + * stop the watchdog during the printout. + */ + stop_watchdog(); +#endif + + oops_enter(); + handle_BUG(regs); + + pr_err("Linux %s %s\n", utsname()->release, utsname()->version); + pr_err("%s: %04lx\n", str, err & 0xffff); + + show_registers(regs); + + oops_exit(); + oops_in_progress = 0; + pr_err("\n"); /* Flush mtdoops. */ + +#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY + reset_watchdog(); +#endif + do_exit(SIGSEGV); +} + +void __init trap_init(void) +{ + /* Nothing needs to be done */ +} diff --git a/kernel/arch/cris/kernel/vmlinux.lds.S b/kernel/arch/cris/kernel/vmlinux.lds.S new file mode 100644 index 000000000..a68b983dc --- /dev/null +++ b/kernel/arch/cris/kernel/vmlinux.lds.S @@ -0,0 +1,132 @@ +/* ld script to make the Linux/CRIS kernel + * Authors: Bjorn Wesen (bjornw@axis.com) + * + * It is VERY DANGEROUS to fiddle around with the symbols in this + * script. It is for example quite vital that all generated sections + * that are used are actually named here, otherwise the linker will + * put them at the end, where the init stuff is which is FREED after + * the kernel has booted. + */ + +#include +#include + +#ifdef CONFIG_ETRAX_VMEM_SIZE +#define __CONFIG_ETRAX_VMEM_SIZE CONFIG_ETRAX_VMEM_SIZE +#else +#define __CONFIG_ETRAX_VMEM_SIZE 0 +#endif + + +jiffies = jiffies_64; +SECTIONS +{ + . = DRAM_VIRTUAL_BASE; + dram_start = .; +#ifdef CONFIG_ETRAX_ARCH_V10 + ibr_start = .; +#else + ebp_start = .; + /* The boot section is only necessary until the VCS top */ + /* level testbench includes both flash and DRAM. */ + .boot : { *(.boot) } +#endif + + /* see head.S and pages reserved at the start */ + . = DRAM_VIRTUAL_BASE + 0x4000; + + _text = .; /* Text and read-only data. */ + text_start = .; /* Lots of aliases. */ + _stext = .; + __stext = .; + .text : { + TEXT_TEXT + SCHED_TEXT + LOCK_TEXT + *(.fixup) + *(.text.__*) + } + + _etext = . ; /* End of text section. */ + __etext = .; + + EXCEPTION_TABLE(4) + + _sdata = .; + RODATA + + . = ALIGN (4); + ___data_start = . ; + __Sdata = . ; + .data : { /* Data */ + CACHELINE_ALIGNED_DATA(32) + READ_MOSTLY_DATA(32) + DATA_DATA + } + __edata = . ; /* End of data section. */ + _edata = . ; + + INIT_TASK_DATA_SECTION(PAGE_SIZE) + + . = ALIGN(PAGE_SIZE); /* Init code and data. */ + __init_begin = .; + INIT_TEXT_SECTION(PAGE_SIZE) + .init.data : { INIT_DATA } + .init.setup : { INIT_SETUP(16) } + .initcall.init : { + INIT_CALLS + } + + .con_initcall.init : { + CON_INITCALL + } + SECURITY_INIT + + /* .exit.text is discarded at runtime, not link time, + * to deal with references from __bug_table + */ + .exit.text : { + EXIT_TEXT + } + .exit.data : { + EXIT_DATA + } + +#ifdef CONFIG_ETRAX_ARCH_V10 +#ifdef CONFIG_BLK_DEV_INITRD + .init.ramfs : { + __initramfs_start = .; + *(.init.ramfs) + __initramfs_end = .; + } +#endif +#endif + __vmlinux_end = .; /* Last address of the physical file. */ +#ifdef CONFIG_ETRAX_ARCH_V32 + PERCPU_SECTION(32) + + .init.ramfs : { + INIT_RAM_FS + } +#endif + + /* + * We fill to the next page, so we can discard all init + * pages without needing to consider what payload might be + * appended to the kernel image. + */ + . = ALIGN(PAGE_SIZE); + + __init_end = .; + + __data_end = . ; /* Move to _edata ? */ + BSS_SECTION(1, 1, 1) + + . = ALIGN (0x20); + _end = .; + __end = .; + + dram_end = dram_start + (CONFIG_ETRAX_DRAM_SIZE - __CONFIG_ETRAX_VMEM_SIZE)*1024*1024; + + DISCARDS +} diff --git a/kernel/arch/cris/mm/Makefile b/kernel/arch/cris/mm/Makefile new file mode 100644 index 000000000..d3ae08c90 --- /dev/null +++ b/kernel/arch/cris/mm/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the linux cris-specific parts of the memory manager. +# + +obj-y := init.o fault.o tlb.o ioremap.o + diff --git a/kernel/arch/cris/mm/fault.c b/kernel/arch/cris/mm/fault.c new file mode 100644 index 000000000..3066d40a6 --- /dev/null +++ b/kernel/arch/cris/mm/fault.c @@ -0,0 +1,388 @@ +/* + * arch/cris/mm/fault.c + * + * Copyright (C) 2000-2010 Axis Communications AB + */ + +#include +#include +#include +#include +#include +#include + +extern int find_fixup_code(struct pt_regs *); +extern void die_if_kernel(const char *, struct pt_regs *, long); +extern void show_registers(struct pt_regs *regs); + +/* debug of low-level TLB reload */ +#undef DEBUG + +#ifdef DEBUG +#define D(x) x +#else +#define D(x) +#endif + +/* debug of higher-level faults */ +#define DPG(x) + +/* current active page directory */ + +DEFINE_PER_CPU(pgd_t *, current_pgd); +unsigned long cris_signal_return_page; + +/* + * This routine handles page faults. It determines the address, + * and the problem, and then passes it off to one of the appropriate + * routines. + * + * Notice that the address we're given is aligned to the page the fault + * occurred in, since we only get the PFN in R_MMU_CAUSE not the complete + * address. + * + * error_code: + * bit 0 == 0 means no page found, 1 means protection fault + * bit 1 == 0 means read, 1 means write + * + * If this routine detects a bad access, it returns 1, otherwise it + * returns 0. + */ + +asmlinkage void +do_page_fault(unsigned long address, struct pt_regs *regs, + int protection, int writeaccess) +{ + struct task_struct *tsk; + struct mm_struct *mm; + struct vm_area_struct * vma; + siginfo_t info; + int fault; + unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; + + D(printk(KERN_DEBUG + "Page fault for %lX on %X at %lX, prot %d write %d\n", + address, smp_processor_id(), instruction_pointer(regs), + protection, writeaccess)); + + tsk = current; + + /* + * We fault-in kernel-space virtual memory on-demand. The + * 'reference' page table is init_mm.pgd. + * + * NOTE! We MUST NOT take any locks for this case. We may + * be in an interrupt or a critical region, and should + * only copy the information from the master page table, + * nothing more. + * + * NOTE2: This is done so that, when updating the vmalloc + * mappings we don't have to walk all processes pgdirs and + * add the high mappings all at once. Instead we do it as they + * are used. However vmalloc'ed page entries have the PAGE_GLOBAL + * bit set so sometimes the TLB can use a lingering entry. + * + * This verifies that the fault happens in kernel space + * and that the fault was not a protection error (error_code & 1). + */ + + if (address >= VMALLOC_START && + !protection && + !user_mode(regs)) + goto vmalloc_fault; + + /* When stack execution is not allowed we store the signal + * trampolines in the reserved cris_signal_return_page. + * Handle this in the exact same way as vmalloc (we know + * that the mapping is there and is valid so no need to + * call handle_mm_fault). + */ + if (cris_signal_return_page && + address == cris_signal_return_page && + !protection && user_mode(regs)) + goto vmalloc_fault; + + /* we can and should enable interrupts at this point */ + local_irq_enable(); + + mm = tsk->mm; + info.si_code = SEGV_MAPERR; + + /* + * If we're in an interrupt, have pagefaults disabled or have no + * user context, we must not take the fault. + */ + + if (faulthandler_disabled() || !mm) + goto no_context; + + if (user_mode(regs)) + flags |= FAULT_FLAG_USER; +retry: + down_read(&mm->mmap_sem); + vma = find_vma(mm, address); + if (!vma) + goto bad_area; + if (vma->vm_start <= address) + goto good_area; + if (!(vma->vm_flags & VM_GROWSDOWN)) + goto bad_area; + if (user_mode(regs)) { + /* + * accessing the stack below usp is always a bug. + * we get page-aligned addresses so we can only check + * if we're within a page from usp, but that might be + * enough to catch brutal errors at least. + */ + if (address + PAGE_SIZE < rdusp()) + goto bad_area; + } + if (expand_stack(vma, address)) + goto bad_area; + + /* + * Ok, we have a good vm_area for this memory access, so + * we can handle it.. + */ + + good_area: + info.si_code = SEGV_ACCERR; + + /* first do some preliminary protection checks */ + + if (writeaccess == 2){ + if (!(vma->vm_flags & VM_EXEC)) + goto bad_area; + } else if (writeaccess == 1) { + if (!(vma->vm_flags & VM_WRITE)) + goto bad_area; + flags |= FAULT_FLAG_WRITE; + } else { + if (!(vma->vm_flags & (VM_READ | VM_EXEC))) + goto bad_area; + } + + /* + * If for any reason at all we couldn't handle the fault, + * make sure we exit gracefully rather than endlessly redo + * the fault. + */ + + fault = handle_mm_fault(mm, vma, address, flags); + + if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) + return; + + if (unlikely(fault & VM_FAULT_ERROR)) { + if (fault & VM_FAULT_OOM) + goto out_of_memory; + else if (fault & VM_FAULT_SIGSEGV) + goto bad_area; + else if (fault & VM_FAULT_SIGBUS) + goto do_sigbus; + BUG(); + } + + if (flags & FAULT_FLAG_ALLOW_RETRY) { + if (fault & VM_FAULT_MAJOR) + tsk->maj_flt++; + else + tsk->min_flt++; + if (fault & VM_FAULT_RETRY) { + flags &= ~FAULT_FLAG_ALLOW_RETRY; + flags |= FAULT_FLAG_TRIED; + + /* + * No need to up_read(&mm->mmap_sem) as we would + * have already released it in __lock_page_or_retry + * in mm/filemap.c. + */ + + goto retry; + } + } + + up_read(&mm->mmap_sem); + return; + + /* + * Something tried to access memory that isn't in our memory map.. + * Fix it, but check if it's kernel or user first.. + */ + + bad_area: + up_read(&mm->mmap_sem); + + bad_area_nosemaphore: + DPG(show_registers(regs)); + + /* User mode accesses just cause a SIGSEGV */ + + if (user_mode(regs)) { +#ifdef CONFIG_NO_SEGFAULT_TERMINATION + DECLARE_WAIT_QUEUE_HEAD(wq); +#endif + printk(KERN_NOTICE "%s (pid %d) segfaults for page " + "address %08lx at pc %08lx\n", + tsk->comm, tsk->pid, + address, instruction_pointer(regs)); + + /* With DPG on, we've already dumped registers above. */ + DPG(if (0)) + show_registers(regs); + +#ifdef CONFIG_NO_SEGFAULT_TERMINATION + wait_event_interruptible(wq, 0 == 1); +#else + info.si_signo = SIGSEGV; + info.si_errno = 0; + /* info.si_code has been set above */ + info.si_addr = (void *)address; + force_sig_info(SIGSEGV, &info, tsk); +#endif + return; + } + + no_context: + + /* Are we prepared to handle this kernel fault? + * + * (The kernel has valid exception-points in the source + * when it accesses user-memory. When it fails in one + * of those points, we find it in a table and do a jump + * to some fixup code that loads an appropriate error + * code) + */ + + if (find_fixup_code(regs)) + return; + + /* + * Oops. The kernel tried to access some bad page. We'll have to + * terminate things with extreme prejudice. + */ + + if (!oops_in_progress) { + oops_in_progress = 1; + if ((unsigned long) (address) < PAGE_SIZE) + printk(KERN_ALERT "Unable to handle kernel NULL " + "pointer dereference"); + else + printk(KERN_ALERT "Unable to handle kernel access" + " at virtual address %08lx\n", address); + + die_if_kernel("Oops", regs, (writeaccess << 1) | protection); + oops_in_progress = 0; + } + + do_exit(SIGKILL); + + /* + * We ran out of memory, or some other thing happened to us that made + * us unable to handle the page fault gracefully. + */ + + out_of_memory: + up_read(&mm->mmap_sem); + if (!user_mode(regs)) + goto no_context; + pagefault_out_of_memory(); + return; + + do_sigbus: + up_read(&mm->mmap_sem); + + /* + * Send a sigbus, regardless of whether we were in kernel + * or user mode. + */ + info.si_signo = SIGBUS; + info.si_errno = 0; + info.si_code = BUS_ADRERR; + info.si_addr = (void *)address; + force_sig_info(SIGBUS, &info, tsk); + + /* Kernel mode? Handle exceptions or die */ + if (!user_mode(regs)) + goto no_context; + return; + +vmalloc_fault: + { + /* + * Synchronize this task's top level page-table + * with the 'reference' page table. + * + * Use current_pgd instead of tsk->active_mm->pgd + * since the latter might be unavailable if this + * code is executed in a misfortunately run irq + * (like inside schedule() between switch_mm and + * switch_to...). + */ + + int offset = pgd_index(address); + pgd_t *pgd, *pgd_k; + pud_t *pud, *pud_k; + pmd_t *pmd, *pmd_k; + pte_t *pte_k; + + pgd = (pgd_t *)per_cpu(current_pgd, smp_processor_id()) + offset; + pgd_k = init_mm.pgd + offset; + + /* Since we're two-level, we don't need to do both + * set_pgd and set_pmd (they do the same thing). If + * we go three-level at some point, do the right thing + * with pgd_present and set_pgd here. + * + * Also, since the vmalloc area is global, we don't + * need to copy individual PTE's, it is enough to + * copy the pgd pointer into the pte page of the + * root task. If that is there, we'll find our pte if + * it exists. + */ + + pud = pud_offset(pgd, address); + pud_k = pud_offset(pgd_k, address); + if (!pud_present(*pud_k)) + goto no_context; + + pmd = pmd_offset(pud, address); + pmd_k = pmd_offset(pud_k, address); + + if (!pmd_present(*pmd_k)) + goto bad_area_nosemaphore; + + set_pmd(pmd, *pmd_k); + + /* Make sure the actual PTE exists as well to + * catch kernel vmalloc-area accesses to non-mapped + * addresses. If we don't do this, this will just + * silently loop forever. + */ + + pte_k = pte_offset_kernel(pmd_k, address); + if (!pte_present(*pte_k)) + goto no_context; + + return; + } +} + +/* Find fixup code. */ +int +find_fixup_code(struct pt_regs *regs) +{ + const struct exception_table_entry *fixup; + /* in case of delay slot fault (v32) */ + unsigned long ip = (instruction_pointer(regs) & ~0x1); + + fixup = search_exception_tables(ip); + if (fixup != 0) { + /* Adjust the instruction pointer in the stackframe. */ + instruction_pointer(regs) = fixup->fixup; + arch_fixup(regs); + return 1; + } + + return 0; +} diff --git a/kernel/arch/cris/mm/init.c b/kernel/arch/cris/mm/init.c new file mode 100644 index 000000000..1e7fd45b6 --- /dev/null +++ b/kernel/arch/cris/mm/init.c @@ -0,0 +1,68 @@ +/* + * linux/arch/cris/mm/init.c + * + * Copyright (C) 1995 Linus Torvalds + * Copyright (C) 2000,2001 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include + +unsigned long empty_zero_page; +EXPORT_SYMBOL(empty_zero_page); + +void __init mem_init(void) +{ + BUG_ON(!mem_map); + + /* max/min_low_pfn was set by setup.c + * now we just copy it to some other necessary places... + * + * high_memory was also set in setup.c + */ + max_mapnr = max_low_pfn - min_low_pfn; + free_all_bootmem(); + mem_init_print_info(NULL); +} + +/* Free a range of init pages. Virtual addresses. */ + +void free_init_pages(const char *what, unsigned long begin, unsigned long end) +{ + unsigned long addr; + + for (addr = begin; addr < end; addr += PAGE_SIZE) { + ClearPageReserved(virt_to_page(addr)); + init_page_count(virt_to_page(addr)); + free_page(addr); + totalram_pages++; + } + + printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); +} + +/* Free the pages occupied by initialization code. */ + +void free_initmem(void) +{ + free_initmem_default(-1); +} + +/* Free the pages occupied by initrd code. */ + +#ifdef CONFIG_BLK_DEV_INITRD +void free_initrd_mem(unsigned long start, unsigned long end) +{ + free_init_pages("initrd memory", + start, + end); +} +#endif diff --git a/kernel/arch/cris/mm/ioremap.c b/kernel/arch/cris/mm/ioremap.c new file mode 100644 index 000000000..80fdb995a --- /dev/null +++ b/kernel/arch/cris/mm/ioremap.c @@ -0,0 +1,89 @@ +/* + * arch/cris/mm/ioremap.c + * + * Re-map IO memory to kernel address space so that we can access it. + * Needed for memory-mapped I/O devices mapped outside our normal DRAM + * window (that is, all memory-mapped I/O devices). + * + * (C) Copyright 1995 1996 Linus Torvalds + * CRIS-port by Axis Communications AB + */ + +#include +#include +#include +#include + +/* + * Generic mapping function (not visible outside): + */ + +/* + * Remap an arbitrary physical address space into the kernel virtual + * address space. Needed when the kernel wants to access high addresses + * directly. + * + * NOTE! We need to allow non-page-aligned mappings too: we will obviously + * have to convert them into an offset in a page-aligned mapping, but the + * caller shouldn't need to know that small detail. + */ +void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot) +{ + void __iomem * addr; + struct vm_struct * area; + unsigned long offset, last_addr; + + /* Don't allow wraparound or zero size */ + last_addr = phys_addr + size - 1; + if (!size || last_addr < phys_addr) + return NULL; + + /* + * Mappings have to be page-aligned + */ + offset = phys_addr & ~PAGE_MASK; + phys_addr &= PAGE_MASK; + size = PAGE_ALIGN(last_addr+1) - phys_addr; + + /* + * Ok, go for it.. + */ + area = get_vm_area(size, VM_IOREMAP); + if (!area) + return NULL; + addr = (void __iomem *)area->addr; + if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size, + phys_addr, prot)) { + vfree((void __force *)addr); + return NULL; + } + return (void __iomem *) (offset + (char __iomem *)addr); +} + +void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags) +{ + return __ioremap_prot(phys_addr, size, + __pgprot(_PAGE_PRESENT | __READABLE | + __WRITEABLE | _PAGE_GLOBAL | + _PAGE_KERNEL | flags)); +} + +/** + * ioremap_nocache - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * Must be freed with iounmap. + */ + +void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size) +{ + return __ioremap(phys_addr | MEM_NON_CACHEABLE, size, 0); +} +EXPORT_SYMBOL(ioremap_nocache); + +void iounmap(volatile void __iomem *addr) +{ + if (addr > high_memory) + return vfree((void *) (PAGE_MASK & (unsigned long) addr)); +} diff --git a/kernel/arch/cris/mm/tlb.c b/kernel/arch/cris/mm/tlb.c new file mode 100644 index 000000000..b7f8de576 --- /dev/null +++ b/kernel/arch/cris/mm/tlb.c @@ -0,0 +1,114 @@ +/* + * linux/arch/cris/mm/tlb.c + * + * Copyright (C) 2000, 2001 Axis Communications AB + * + * Authors: Bjorn Wesen (bjornw@axis.com) + * + */ + +#include +#include +#include + +#define D(x) + +/* The TLB can host up to 64 different mm contexts at the same time. + * The running context is R_MMU_CONTEXT, and each TLB entry contains a + * page_id that has to match to give a hit. In page_id_map, we keep track + * of which mm we have assigned to which page_id, so that we know when + * to invalidate TLB entries. + * + * The last page_id is never running - it is used as an invalid page_id + * so we can make TLB entries that will never match. + * + * Notice that we need to make the flushes atomic, otherwise an interrupt + * handler that uses vmalloced memory might cause a TLB load in the middle + * of a flush causing. + */ + +struct mm_struct *page_id_map[NUM_PAGEID]; +static int map_replace_ptr = 1; /* which page_id_map entry to replace next */ + +/* the following functions are similar to those used in the PPC port */ + +static inline void +alloc_context(struct mm_struct *mm) +{ + struct mm_struct *old_mm; + + D(printk("tlb: alloc context %d (%p)\n", map_replace_ptr, mm)); + + /* did we replace an mm ? */ + + old_mm = page_id_map[map_replace_ptr]; + + if(old_mm) { + /* throw out any TLB entries belonging to the mm we replace + * in the map + */ + flush_tlb_mm(old_mm); + + old_mm->context.page_id = NO_CONTEXT; + } + + /* insert it into the page_id_map */ + + mm->context.page_id = map_replace_ptr; + page_id_map[map_replace_ptr] = mm; + + map_replace_ptr++; + + if(map_replace_ptr == INVALID_PAGEID) + map_replace_ptr = 0; /* wrap around */ +} + +/* + * if needed, get a new MMU context for the mm. otherwise nothing is done. + */ + +void +get_mmu_context(struct mm_struct *mm) +{ + if(mm->context.page_id == NO_CONTEXT) + alloc_context(mm); +} + +/* called by __exit_mm to destroy the used MMU context if any before + * destroying the mm itself. this is only called when the last user of the mm + * drops it. + * + * the only thing we really need to do here is mark the used PID slot + * as empty. + */ + +void +destroy_context(struct mm_struct *mm) +{ + if(mm->context.page_id != NO_CONTEXT) { + D(printk("destroy_context %d (%p)\n", mm->context.page_id, mm)); + flush_tlb_mm(mm); /* TODO this might be redundant ? */ + page_id_map[mm->context.page_id] = NULL; + } +} + +/* called once during VM initialization, from init.c */ + +void __init +tlb_init(void) +{ + int i; + + /* clear the page_id map */ + + for (i = 1; i < ARRAY_SIZE(page_id_map); i++) + page_id_map[i] = NULL; + + /* invalidate the entire TLB */ + + flush_tlb_all(); + + /* the init_mm has context 0 from the boot */ + + page_id_map[0] = &init_mm; +} -- cgit 1.2.3-korg