From 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 Mon Sep 17 00:00:00 2001 From: Yunhong Jiang Date: Tue, 4 Aug 2015 12:17:53 -0700 Subject: Add the rt linux 4.1.3-rt3 as base Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang --- kernel/arch/blackfin/mach-bf561/coreb.c | 77 +++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 kernel/arch/blackfin/mach-bf561/coreb.c (limited to 'kernel/arch/blackfin/mach-bf561/coreb.c') diff --git a/kernel/arch/blackfin/mach-bf561/coreb.c b/kernel/arch/blackfin/mach-bf561/coreb.c new file mode 100644 index 000000000..78ecb50ba --- /dev/null +++ b/kernel/arch/blackfin/mach-bf561/coreb.c @@ -0,0 +1,77 @@ +/* Load firmware into Core B on a BF561 + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +/* The Core B reset func requires code in the application that is loaded into + * Core B. In order to reset, the application needs to install an interrupt + * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and + * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core + * B to stall when Supplemental Interrupt 0 is set, and will reset PC to + * 0xff600000 when COREB_SRAM_INIT is cleared. + */ + +#include +#include +#include +#include +#include + +#define CMD_COREB_START _IO('b', 0) +#define CMD_COREB_STOP _IO('b', 1) +#define CMD_COREB_RESET _IO('b', 2) + +static long +coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int ret = 0; + + switch (cmd) { + case CMD_COREB_START: + bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); + break; + case CMD_COREB_STOP: + bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020); + bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); + break; + case CMD_COREB_RESET: + bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); + break; + default: + ret = -EINVAL; + break; + } + + CSYNC(); + + return ret; +} + +static const struct file_operations coreb_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = coreb_ioctl, + .llseek = noop_llseek, +}; + +static struct miscdevice coreb_dev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "coreb", + .fops = &coreb_fops, +}; + +static int __init bf561_coreb_init(void) +{ + return misc_register(&coreb_dev); +} +module_init(bf561_coreb_init); + +static void __exit bf561_coreb_exit(void) +{ + misc_deregister(&coreb_dev); +} +module_exit(bf561_coreb_exit); + +MODULE_AUTHOR("Bas Vermeulen "); +MODULE_DESCRIPTION("BF561 Core B Support"); +MODULE_LICENSE("GPL"); -- cgit 1.2.3-korg