From 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 Mon Sep 17 00:00:00 2001 From: Yunhong Jiang Date: Tue, 4 Aug 2015 12:17:53 -0700 Subject: Add the rt linux 4.1.3-rt3 as base Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang --- kernel/arch/arm/mach-iop33x/irq.c | 118 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 kernel/arch/arm/mach-iop33x/irq.c (limited to 'kernel/arch/arm/mach-iop33x/irq.c') diff --git a/kernel/arch/arm/mach-iop33x/irq.c b/kernel/arch/arm/mach-iop33x/irq.c new file mode 100644 index 000000000..f7f5d3e45 --- /dev/null +++ b/kernel/arch/arm/mach-iop33x/irq.c @@ -0,0 +1,118 @@ +/* + * arch/arm/mach-iop33x/irq.c + * + * Generic IOP331 IRQ handling functionality + * + * Author: Dave Jiang + * Copyright (C) 2003 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +static u32 iop33x_mask0; +static u32 iop33x_mask1; + +static void intctl0_write(u32 val) +{ + asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); +} + +static void intctl1_write(u32 val) +{ + asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); +} + +static void intstr0_write(u32 val) +{ + asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); +} + +static void intstr1_write(u32 val) +{ + asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); +} + +static void intbase_write(u32 val) +{ + asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); +} + +static void intsize_write(u32 val) +{ + asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); +} + +static void +iop33x_irq_mask1 (struct irq_data *d) +{ + iop33x_mask0 &= ~(1 << d->irq); + intctl0_write(iop33x_mask0); +} + +static void +iop33x_irq_mask2 (struct irq_data *d) +{ + iop33x_mask1 &= ~(1 << (d->irq - 32)); + intctl1_write(iop33x_mask1); +} + +static void +iop33x_irq_unmask1(struct irq_data *d) +{ + iop33x_mask0 |= 1 << d->irq; + intctl0_write(iop33x_mask0); +} + +static void +iop33x_irq_unmask2(struct irq_data *d) +{ + iop33x_mask1 |= (1 << (d->irq - 32)); + intctl1_write(iop33x_mask1); +} + +struct irq_chip iop33x_irqchip1 = { + .name = "IOP33x-1", + .irq_ack = iop33x_irq_mask1, + .irq_mask = iop33x_irq_mask1, + .irq_unmask = iop33x_irq_unmask1, +}; + +struct irq_chip iop33x_irqchip2 = { + .name = "IOP33x-2", + .irq_ack = iop33x_irq_mask2, + .irq_mask = iop33x_irq_mask2, + .irq_unmask = iop33x_irq_unmask2, +}; + +void __init iop33x_init_irq(void) +{ + int i; + + iop_init_cp6_handler(); + + intctl0_write(0); + intctl1_write(0); + intstr0_write(0); + intstr1_write(0); + intbase_write(0); + intsize_write(1); + if (machine_is_iq80331()) + *IOP3XX_PCIIRSR = 0x0f; + + for (i = 0; i < NR_IRQS; i++) { + irq_set_chip_and_handler(i, + (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2, + handle_level_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } +} -- cgit 1.2.3-korg