From 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 Mon Sep 17 00:00:00 2001 From: Yunhong Jiang Date: Tue, 4 Aug 2015 12:17:53 -0700 Subject: Add the rt linux 4.1.3-rt3 as base Import the rt linux 4.1.3-rt3 as OPNFV kvm base. It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and the base is: commit 0917f823c59692d751951bf5ea699a2d1e2f26a2 Author: Sebastian Andrzej Siewior Date: Sat Jul 25 12:13:34 2015 +0200 Prepare v4.1.3-rt3 Signed-off-by: Sebastian Andrzej Siewior We lose all the git history this way and it's not good. We should apply another opnfv project repo in future. Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423 Signed-off-by: Yunhong Jiang --- kernel/arch/arm/mach-iop32x/include/mach/adma.h | 5 +++ .../arm/mach-iop32x/include/mach/entry-macro.S | 33 ++++++++++++++ .../arch/arm/mach-iop32x/include/mach/glantank.h | 13 ++++++ .../arch/arm/mach-iop32x/include/mach/hardware.h | 41 ++++++++++++++++++ kernel/arch/arm/mach-iop32x/include/mach/iop32x.h | 34 +++++++++++++++ kernel/arch/arm/mach-iop32x/include/mach/iq31244.h | 17 ++++++++ kernel/arch/arm/mach-iop32x/include/mach/iq80321.h | 17 ++++++++ kernel/arch/arm/mach-iop32x/include/mach/irqs.h | 50 ++++++++++++++++++++++ kernel/arch/arm/mach-iop32x/include/mach/n2100.h | 19 ++++++++ kernel/arch/arm/mach-iop32x/include/mach/time.h | 4 ++ .../arch/arm/mach-iop32x/include/mach/uncompress.h | 38 ++++++++++++++++ 11 files changed, 271 insertions(+) create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/adma.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/entry-macro.S create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/glantank.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/hardware.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/iop32x.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/iq31244.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/iq80321.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/irqs.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/n2100.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/time.h create mode 100644 kernel/arch/arm/mach-iop32x/include/mach/uncompress.h (limited to 'kernel/arch/arm/mach-iop32x/include/mach') diff --git a/kernel/arch/arm/mach-iop32x/include/mach/adma.h b/kernel/arch/arm/mach-iop32x/include/mach/adma.h new file mode 100644 index 000000000..5ed92037d --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/adma.h @@ -0,0 +1,5 @@ +#ifndef IOP32X_ADMA_H +#define IOP32X_ADMA_H +#include +#endif + diff --git a/kernel/arch/arm/mach-iop32x/include/mach/entry-macro.S b/kernel/arch/arm/mach-iop32x/include/mach/entry-macro.S new file mode 100644 index 000000000..ea13ae02d --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/entry-macro.S @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-iop32x/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for IOP32x-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include + + .macro get_irqnr_preamble, base, tmp + mrc p15, 0, \tmp, c15, c1, 0 + orr \tmp, \tmp, #(1 << 6) + mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access + mrc p15, 0, \tmp, c15, c1, 0 + mov \tmp, \tmp + sub pc, pc, #4 @ cp_wait + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC + cmp \irqstat, #0 + clzne \irqnr, \irqstat + rsbne \irqnr, \irqnr, #31 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + mrc p15, 0, \tmp1, c15, c1, 0 + ands \tmp2, \tmp1, #(1 << 6) + bicne \tmp1, \tmp1, #(1 << 6) + mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access + .endm diff --git a/kernel/arch/arm/mach-iop32x/include/mach/glantank.h b/kernel/arch/arm/mach-iop32x/include/mach/glantank.h new file mode 100644 index 000000000..958eb91c0 --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/glantank.h @@ -0,0 +1,13 @@ +/* + * arch/arm/mach-iop32x/include/mach/glantank.h + * + * IO-Data GLAN Tank board registers + */ + +#ifndef __GLANTANK_H +#define __GLANTANK_H + +#define GLANTANK_UART 0xfe800000 /* UART */ + + +#endif diff --git a/kernel/arch/arm/mach-iop32x/include/mach/hardware.h b/kernel/arch/arm/mach-iop32x/include/mach/hardware.h new file mode 100644 index 000000000..48cb1b20b --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/hardware.h @@ -0,0 +1,41 @@ +/* + * arch/arm/mach-iop32x/include/mach/hardware.h + */ + +#ifndef __HARDWARE_H +#define __HARDWARE_H + +#include + +/* + * Note about PCI IO space mappings + * + * To make IO space accesses efficient, we store virtual addresses in + * the IO resources. + * + * The PCI IO space is located at virtual 0xfe000000 from physical + * 0x90000000. The PCI BARs must be programmed with physical addresses, + * but when we read them, we convert them to virtual addresses. See + * arch/arm/plat-iop/pci.c. + */ + +#ifndef __ASSEMBLY__ +void iop32x_init_irq(void); +#endif + + +/* + * Generic chipset bits + */ +#include "iop32x.h" + +/* + * Board specific bits + */ +#include "glantank.h" +#include "iq80321.h" +#include "iq31244.h" +#include "n2100.h" + + +#endif diff --git a/kernel/arch/arm/mach-iop32x/include/mach/iop32x.h b/kernel/arch/arm/mach-iop32x/include/mach/iop32x.h new file mode 100644 index 000000000..56ec864ec --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/iop32x.h @@ -0,0 +1,34 @@ +/* + * arch/arm/mach-iop32x/include/mach/iop32x.h + * + * Intel IOP32X Chip definitions + * + * Author: Rory Bolt + * Copyright (C) 2002 Rory Bolt + * Copyright (C) 2004 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IOP32X_H +#define __IOP32X_H + +/* + * Peripherals that are shared between the iop32x and iop33x but + * located at different addresses. + */ +#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) + +#include + +/* ATU Parameters + * set up a 1:1 bus to physical ram relationship + * w/ physical ram on top of pci in the memory map + */ +#define IOP32X_MAX_RAM_SIZE 0x40000000UL +#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE +#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 + +#endif diff --git a/kernel/arch/arm/mach-iop32x/include/mach/iq31244.h b/kernel/arch/arm/mach-iop32x/include/mach/iq31244.h new file mode 100644 index 000000000..6b6b369e7 --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/iq31244.h @@ -0,0 +1,17 @@ +/* + * arch/arm/mach-iop32x/include/mach/iq31244.h + * + * Intel IQ31244 evaluation board registers + */ + +#ifndef __IQ31244_H +#define __IQ31244_H + +#define IQ31244_UART 0xfe800000 /* UART #1 */ +#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ +#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ +#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ +#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ + + +#endif diff --git a/kernel/arch/arm/mach-iop32x/include/mach/iq80321.h b/kernel/arch/arm/mach-iop32x/include/mach/iq80321.h new file mode 100644 index 000000000..498819b73 --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/iq80321.h @@ -0,0 +1,17 @@ +/* + * arch/arm/mach-iop32x/include/mach/iq80321.h + * + * Intel IQ80321 evaluation board registers + */ + +#ifndef __IQ80321_H +#define __IQ80321_H + +#define IQ80321_UART 0xfe800000 /* UART #1 */ +#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ +#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ +#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ +#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ + + +#endif diff --git a/kernel/arch/arm/mach-iop32x/include/mach/irqs.h b/kernel/arch/arm/mach-iop32x/include/mach/irqs.h new file mode 100644 index 000000000..33573e099 --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/irqs.h @@ -0,0 +1,50 @@ +/* + * arch/arm/mach-iop32x/include/mach/irqs.h + * + * Author: Rory Bolt + * Copyright: (C) 2002 Rory Bolt + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IRQS_H +#define __IRQS_H + +/* + * IOP80321 chipset interrupts + */ +#define IRQ_IOP32X_DMA0_EOT 0 +#define IRQ_IOP32X_DMA0_EOC 1 +#define IRQ_IOP32X_DMA1_EOT 2 +#define IRQ_IOP32X_DMA1_EOC 3 +#define IRQ_IOP32X_AA_EOT 6 +#define IRQ_IOP32X_AA_EOC 7 +#define IRQ_IOP32X_CORE_PMON 8 +#define IRQ_IOP32X_TIMER0 9 +#define IRQ_IOP32X_TIMER1 10 +#define IRQ_IOP32X_I2C_0 11 +#define IRQ_IOP32X_I2C_1 12 +#define IRQ_IOP32X_MESSAGING 13 +#define IRQ_IOP32X_ATU_BIST 14 +#define IRQ_IOP32X_PERFMON 15 +#define IRQ_IOP32X_CORE_PMU 16 +#define IRQ_IOP32X_BIU_ERR 17 +#define IRQ_IOP32X_ATU_ERR 18 +#define IRQ_IOP32X_MCU_ERR 19 +#define IRQ_IOP32X_DMA0_ERR 20 +#define IRQ_IOP32X_DMA1_ERR 21 +#define IRQ_IOP32X_AA_ERR 23 +#define IRQ_IOP32X_MSG_ERR 24 +#define IRQ_IOP32X_SSP 25 +#define IRQ_IOP32X_XINT0 27 +#define IRQ_IOP32X_XINT1 28 +#define IRQ_IOP32X_XINT2 29 +#define IRQ_IOP32X_XINT3 30 +#define IRQ_IOP32X_HPI 31 + +#define NR_IRQS 32 + + +#endif diff --git a/kernel/arch/arm/mach-iop32x/include/mach/n2100.h b/kernel/arch/arm/mach-iop32x/include/mach/n2100.h new file mode 100644 index 000000000..40b8a532b --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/n2100.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-iop32x/include/mach/n2100.h + * + * Thecus N2100 board registers + */ + +#ifndef __N2100_H +#define __N2100_H + +#define N2100_UART 0xfe800000 /* UART */ + +#define N2100_COPY_BUTTON IOP3XX_GPIO_LINE(0) +#define N2100_PCA9532_RESET IOP3XX_GPIO_LINE(2) +#define N2100_RESET_BUTTON IOP3XX_GPIO_LINE(3) +#define N2100_HARDWARE_RESET IOP3XX_GPIO_LINE(4) +#define N2100_POWER_BUTTON IOP3XX_GPIO_LINE(5) + + +#endif diff --git a/kernel/arch/arm/mach-iop32x/include/mach/time.h b/kernel/arch/arm/mach-iop32x/include/mach/time.h new file mode 100644 index 000000000..0f28c9949 --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/time.h @@ -0,0 +1,4 @@ +#ifndef _IOP32X_TIME_H_ +#define _IOP32X_TIME_H_ +#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0 +#endif diff --git a/kernel/arch/arm/mach-iop32x/include/mach/uncompress.h b/kernel/arch/arm/mach-iop32x/include/mach/uncompress.h new file mode 100644 index 000000000..b3d45fd36 --- /dev/null +++ b/kernel/arch/arm/mach-iop32x/include/mach/uncompress.h @@ -0,0 +1,38 @@ +/* + * arch/arm/mach-iop32x/include/mach/uncompress.h + */ + +#include +#include +#include +#include + +volatile u8 *uart_base; + +#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE) + +static inline void putc(char c) +{ + while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE) + barrier(); + uart_base[UART_TX] = c; +} + +static inline void flush(void) +{ +} + +static __inline__ void __arch_decomp_setup(unsigned long arch_id) +{ + if (machine_is_iq80321()) + uart_base = (volatile u8 *)IQ80321_UART; + else if (machine_is_iq31244() || machine_is_em7210()) + uart_base = (volatile u8 *)IQ31244_UART; + else + uart_base = (volatile u8 *)0xfe800000; +} + +/* + * nothing to do + */ +#define arch_decomp_setup() __arch_decomp_setup(arch_id) -- cgit 1.2.3-korg