From e09b41010ba33a20a87472ee821fa407a5b8da36 Mon Sep 17 00:00:00 2001 From: José Pekkarinen Date: Mon, 11 Apr 2016 10:41:07 +0300 Subject: These changes are the raw update to linux-4.4.6-rt14. Kernel sources are taken from kernel.org, and rt patch from the rt wiki download page. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit During the rebasing, the following patch collided: Force tick interrupt and get rid of softirq magic(I70131fb85). Collisions have been removed because its logic was found on the source already. Change-Id: I7f57a4081d9deaa0d9ccfc41a6c8daccdee3b769 Signed-off-by: José Pekkarinen --- .../devicetree/bindings/arm/mvebu-cpu-config.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 kernel/Documentation/devicetree/bindings/arm/mvebu-cpu-config.txt (limited to 'kernel/Documentation/devicetree/bindings/arm/mvebu-cpu-config.txt') diff --git a/kernel/Documentation/devicetree/bindings/arm/mvebu-cpu-config.txt b/kernel/Documentation/devicetree/bindings/arm/mvebu-cpu-config.txt new file mode 100644 index 000000000..2cdcd716d --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/arm/mvebu-cpu-config.txt @@ -0,0 +1,20 @@ +MVEBU CPU Config registers +-------------------------- + +MVEBU (Marvell SOCs: Armada 370/XP) + +Required properties: + +- compatible: one of: + - "marvell,armada-370-cpu-config" + - "marvell,armada-xp-cpu-config" + +- reg: Should contain CPU config registers location and length, in + their per-CPU variant + +Example: + + cpu-config@21000 { + compatible = "marvell,armada-xp-cpu-config"; + reg = <0x21000 0x8>; + }; -- cgit 1.2.3-korg