Add the rt linux 4.1.3-rt3 as base

Import the rt linux 4.1.3-rt3 as OPNFV kvm base.

It's from git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git linux-4.1.y-rt and
the base is:

commit 0917f823c59692d751951bf5ea699a2d1e2f26a2
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Sat Jul 25 12:13:34 2015 +0200

    Prepare v4.1.3-rt3

    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

We lose all the git history this way and it's not good. We
should apply another opnfv project repo in future.

Change-Id: I87543d81c9df70d99c5001fbdf646b202c19f423
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>

1 files changed, 71 insertions, 0 deletions

diff --git a/kernel/arch/mn10300/include/asm/intctl-regs.h b/kernel/arch/mn10300/include/asm/intctl-regs.h
new file mode 100644
index 000000000..d65bbeebe
--- /dev/null
+++ b/kernel/arch/mn10300/include/asm/intctl-regs.h
@@ -0,0 +1,71 @@
+/* MN10300 On-board interrupt controller registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_INTCTL_REGS_H
+#define _ASM_INTCTL_REGS_H
+
+#include <asm/cpu-regs.h>
+
+#ifdef __KERNEL__
+
+/*
+ * Interrupt controller registers
+ * - Registers 64-191 are at addresses offset from the main array
+ */
+#define GxICR(X)						\
+	__SYSREG(0xd4000000 + (X) * 4 +				\
+		 (((X) >= 64) && ((X) < 192)) * 0xf00, u16)
+
+#define GxICR_u8(X)							\
+	__SYSREG(0xd4000000 + (X) * 4 +					\
+		 (((X) >= 64) && ((X) < 192)) * 0xf00, u8)
+
+#include <proc/intctl-regs.h>
+
+#define XIRQ_TRIGGER_LOWLEVEL	0
+#define XIRQ_TRIGGER_HILEVEL	1
+#define XIRQ_TRIGGER_NEGEDGE	2
+#define XIRQ_TRIGGER_POSEDGE	3
+
+/* non-maskable interrupt control */
+#define NMIIRQ			0
+#define NMICR			GxICR(NMIIRQ)	/* NMI control register */
+#define NMICR_NMIF		0x0001		/* NMI pin interrupt flag */
+#define NMICR_WDIF		0x0002		/* watchdog timer overflow flag */
+#define NMICR_ABUSERR		0x0008		/* async bus error flag */
+
+/* maskable interrupt control */
+#define GxICR_DETECT		0x0001		/* interrupt detect flag */
+#define GxICR_REQUEST		0x0010		/* interrupt request flag */
+#define GxICR_ENABLE		0x0100		/* interrupt enable flag */
+#define GxICR_LEVEL		0x7000		/* interrupt priority level */
+#define GxICR_LEVEL_0		0x0000		/* - level 0 */
+#define GxICR_LEVEL_1		0x1000		/* - level 1 */
+#define GxICR_LEVEL_2		0x2000		/* - level 2 */
+#define GxICR_LEVEL_3		0x3000		/* - level 3 */
+#define GxICR_LEVEL_4		0x4000		/* - level 4 */
+#define GxICR_LEVEL_5		0x5000		/* - level 5 */
+#define GxICR_LEVEL_6		0x6000		/* - level 6 */
+#define GxICR_LEVEL_SHIFT	12
+#define GxICR_NMI		0x8000		/* nmi request flag */
+
+#define NUM2GxICR_LEVEL(num)	((num) << GxICR_LEVEL_SHIFT)
+
+#ifndef __ASSEMBLY__
+extern void set_intr_level(int irq, u16 level);
+extern void mn10300_set_lateack_irq_type(int irq);
+#endif
+
+/* external interrupts */
+#define XIRQxICR(X)		GxICR((X))	/* external interrupt control regs */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_INTCTL_REGS_H */