Freescale QUICC Engine Firmware Uploading
	   -----------------------------------------

(c) 2007 Timur Tabi <timur at freescale.com>,
    Freescale Semiconductor

Table of Contents
=================

  I - Software License for Firmware

  II - Microcode Availability

  III - Description and Terminology

  IV - Microcode Programming Details

  V - Firmware Structure Layout

  VI - Sample Code for Creating Firmware Files

Revision Information
====================

November 30, 2007: Rev 1.0 - Initial version

I - Software License for Firmware
=================================

Each firmware file comes with its own software license.  For information on
the particular license, please see the license text that is distributed with
the firmware.

II - Microcode Availability
===========================

Firmware files are distributed through various channels.  Some are available on
http://opensource.freescale.com.  For other firmware files, please contact
your Freescale representative or your operating system vendor.

III - Description and Terminology
================================

In this document, the term 'microcode' refers to the sequence of 32-bit
integers that compose the actual QE microcode.

The term 'firmware' refers to a binary blob that contains the microcode as
well as other data that

	1) describes the microcode's purpose
	2) describes how and where to upload the microcode
	3) specifies the values of various registers
	4) includes additional data for use by specific device drivers

Firmware files are binary files that contain only a firmware.

IV - Microcode Programming Details
===================================

The QE architecture allows for only one microcode present in I-RAM for each
RISC processor.  To replace any current microcode, a full QE reset (which
disables the microcode) must be performed first.

QE microcode is uploaded using the following procedure:

1) The microcode is placed into I-RAM at a specific location, using the
   IRAM.IADD and IRAM.IDATA registers.

2) The CERCR.CIR bit is set to 0 or 1, depending on whether the firmware
   needs split I-RAM.  Split I-RAM is only meaningful for SOCs that have
   QEs with multiple RISC processors, such as the 8360.  Splitting the I-RAM
   allows each processor to run a different microcode, effectively creating an
   asymmetric multiprocessing (AMP) system.

3) The TIBCR trap registers are loaded with the addresses of the trap handlers
   in the microcode.

4) The RSP.ECCR register is programmed with the value provided.

5) If necessary, device drivers that need the virtual traps and extended mode
   data will use them.

Virtual Microcode Traps

These virtual traps are conditional branches in the microcode.  These are
"soft" provisional introduced in the ROMcode in order to enable higher
flexibility and save h/w traps If new features are activated or an issue is
being fixed in the RAM package utilizing they should be activated.  This data
structure signals the microcode which of these virtual traps is active.

This structure contains 6 words that the application should copy to some
specific been defined.  This table describes the structure.

	---------------------------------------------------------------
	| Offset in |                  | Destination Offset | Size of |
	|   array   |     Protocol     |   within PRAM      | Operand |
	--------------------------------------------------------------|
	|     0     | Ethernet         |      0xF8          | 4 bytes |
	|           | interworking     |                    |         |
	---------------------------------------------------------------
	|     4     | ATM              |      0xF8          | 4 bytes |
	|           | interworking     |                    |         |
	---------------------------------------------------------------
	|     8     | PPP              |      0xF8          | 4 bytes |
	|           | interworking     |                    |         |
	---------------------------------------------------------------
	|     12    | Ethernet RX      |      0x22          | 1 byte  |
	|           | Distributor Page |                    |         |
	---------------------------------------------------------------
	|     16    | ATM Globtal      |      0x28          | 1 byte  |
	|           | Params Table     |                    |         |
	---------------------------------------------------------------
	|     20    | Insert Frame     |      0xF8          | 4 bytes |
	---------------------------------------------------------------


Extended Modes

This is a double word bit array (64 bits) that defines special functionality
which has an impact on the software drivers.  Each bit has its own impact
and has special instructions for the s/w associated with it.  This structure is
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