/* * ALSA SoC TLV320AIC31XX codec driver * * Copyright (C) 2014 Texas Instruments, Inc. * * Author: Jyri Sarha * * Based on ground work by: Ajit Kulkarni * * This package is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * THIS PACKAGE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. * * The TLV320AIC31xx series of audio codec is a low-power, highly integrated * high performance codec which provides a stereo DAC, a mono ADC, * and mono/stereo Class-D speaker driver. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "tlv320aic31xx.h" static const struct reg_default aic31xx_reg_defaults[] = { { AIC31XX_CLKMUX, 0x00 }, { AIC31XX_PLLPR, 0x11 }, { AIC31XX_PLLJ, 0x04 }, { AIC31XX_PLLDMSB, 0x00 }, { AIC31XX_PLLDLSB, 0x00 }, { AIC31XX_NDAC, 0x01 }, { AIC31XX_MDAC, 0x01 }, { AIC31XX_DOSRMSB, 0x00 }, { AIC31XX_DOSRLSB, 0x80 }, { AIC31XX_NADC, 0x01 }, { AIC31XX_MADC, 0x01 }, { AIC31XX_AOSR, 0x80 }, { AIC31XX_IFACE1, 0x00 }, { AIC31XX_DATA_OFFSET, 0x00 }, { AIC31XX_IFACE2, 0x00 }, { AIC31XX_BCLKN, 0x01 }, { AIC31XX_DACSETUP, 0x14 }, { AIC31XX_DACMUTE, 0x0c }, { AIC31XX_LDACVOL, 0x00 }, { AIC31XX_RDACVOL, 0x00 }, { AIC31XX_ADCSETUP, 0x00 }, { AIC31XX_ADCFGA, 0x80 }, { AIC31XX_ADCVOL, 0x00 }, { AIC31XX_HPDRIVER, 0x04 }, { AIC31XX_SPKAMP, 0x06 }, { AIC31XX_DACMIXERROUTE, 0x00 }, { AIC31XX_LANALOGHPL, 0x7f }, { AIC31XX_RANALOGHPR, 0x7f }, { AIC31XX_LANALOGSPL, 0x7f }, { AIC31XX_RANALOGSPR, 0x7f }, { AIC31XX_HPLGAIN, 0x02 }, { AIC31XX_HPRGAIN, 0x02 }, { AIC31XX_SPLGAIN, 0x00 }, { AIC31XX_SPRGAIN, 0x00 }, { AIC31XX_MICBIAS, 0x00 }, { AIC31XX_MICPGA, 0x80 }, { AIC31XX_MICPGAPI, 0x00 }, { AIC31XX_MICPGAMI, 0x00 }, }; static bool aic31xx_volatile(struct device *dev, unsigned int reg) { switch (reg) { case AIC31XX_PAGECTL: /* regmap implementation requires this */ case AIC31XX_RESET: /* always clears after write */ case AIC31XX_OT_FLAG: case AIC31XX_ADCFLAG: case AIC31XX_DACFLAG1: case AIC31XX_DACFLAG2: case AIC31XX_OFFLAG: /* Sticky interrupt flags */ case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ case AIC31XX_INTRDACFLAG2: case AIC31XX_INTRADCFLAG2: return true; } return false; } static bool aic31xx_writeable(struct device *dev, unsigned int reg) { switch (reg) { case AIC31XX_OT_FLAG: case AIC31XX_ADCFLAG: case AIC31XX_DACFLAG1: case AIC31XX_DACFLAG2: case AIC31XX_OFFLAG: /* Sticky interrupt flags */ case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ case AIC31XX_INTRDACFLAG2: case AIC31XX_INTRADCFLAG2: return false; } return true; } static const struct regmap_range_cfg aic31xx_ranges[] = { { .range_min = 0, .range_max = 12 * 128, .selector_reg = AIC31XX_PAGECTL, .selector_mask = 0xff, .selector_shift = 0, .window_start = 0, .window_len = 128, }, }; static const struct regmap_config aic31xx_i2c_regmap = { .reg_bits = 8, .val_bits = 8, .writeable_reg = aic31xx_writeable, .volatile_reg = aic31xx_volatile, .reg_defaults = aic31xx_reg_defaults, .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), .cache_type = REGCACHE_RBTREE, .ranges = aic31xx_ranges, .num_ranges = ARRAY_SIZE(aic31xx_ranges), .max_register = 12 * 128, }; #define AIC31XX_NUM_SUPPLIES 6 static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = { "HPVDD", "SPRVDD", "SPLVDD", "AVDD", "IOVDD", "DVDD", }; struct aic31xx_disable_nb { struct notifier_block nb; struct aic31xx_priv *aic31xx; }; struct aic31xx_priv { struct snd_soc_codec *codec; u8 i2c_regs_status; struct device *dev; struct regmap *regmap; struct aic31xx_pdata pdata; struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; unsigned int sysclk; u8 p_div; int rate_div_line; }; struct aic31xx_rate_divs { u32 mclk_p; u32 rate; u8 pll_j; u16 pll_d; u16 dosr; u8 ndac; u8 mdac; u8 aosr; u8 nadc; u8 madc; }; /* ADC dividers can be disabled by cofiguring them to 0 */ static const struct aic31xx_rate_divs aic31xx_divs[] = { /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */ /* 8k rate */ {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2}, {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3}, {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2}, /* 11.025k rate */ {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2}, {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3}, {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2}, /* 16k rate */ {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2}, {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3}, {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2}, /* 22.05k rate */ {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2}, {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3}, {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2}, /* 32k rate */ {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2}, {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3}, {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2}, /* 44.1k rate */ {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2}, {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3}, {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2}, /* 48k rate */ {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2}, {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4}, {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2}, /* 88.2k rate */ {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2}, {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3}, {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2}, /* 96k rate */ {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2}, {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4}, {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2}, /* 176.4k rate */ {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2}, {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3}, {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2}, /* 192k rate */ {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2}, {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4}, {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2}, }; static const char * const ldac_in_text[] = { "Off", "Left Data", "Right Data", "Mono" }; static const char * const rdac_in_text[] = { "Off", "Right Data", "Left Data", "Mono" }; static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); static const char * const mic_select_text[] = { "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" }; static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, mic_select_text); static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, mic_select_text); static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, mic_select_text); static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text); static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, mic_select_text); static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); /* * controls to be exported to the user space */ static const struct snd_kcontrol_new aic31xx_snd_controls[] = { SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, adc_fgain_tlv), SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 0, -24, 40, 6, 0, adc_cgain_tlv), SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 119, 0, mic_pga_tlv), SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, AIC31XX_HPRGAIN, 2, 1, 0), SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), }; static const struct snd_kcontrol_new aic311x_snd_controls[] = { SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, AIC31XX_SPRGAIN, 2, 1, 0), SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), }; static const struct snd_kcontrol_new aic310x_snd_controls[] = { SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 2, 1, 0), SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 3, 3, 0, class_D_drv_tlv), SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 0, 0x7F, 1, sp_vol_tlv), }; static const struct snd_kcontrol_new ldac_in_control = SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); static const struct snd_kcontrol_new rdac_in_control = SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, unsigned int mask, unsigned int wbits, int sleep, int count) { unsigned int bits; int counter = count; int ret = regmap_read(aic31xx->regmap, reg, &bits); while ((bits & mask) != wbits && counter && !ret) { usleep_range(sleep, sleep * 2); ret = regmap_read(aic31xx->regmap, reg, &bits); 
general:
    dir:
        home:               /home/opnfv
        repos:              /home/opnfv/repos
        dir_repo_rally:     /home/opnfv/repos/rally
        repo_tempest:       /src/tempest
        dir_repo_releng:    /home/opnfv/repos/releng
        repo_vims_test:     /src/vims-test
        repo_barometer:     /home/opnfv/repos/barometer
        repo_doctor:        /home/opnfv/repos/doctor
        repo_odl_test:      /src/odl_test
        repo_fds:           /src/fds
        repo_securityscan:  /home/opnfv/repos/securityscanning
        repo_vrouter:       /home/opnfv/repos/vnfs/vrouter
        functest:           /home/opnfv/functest
        results:            /home/opnfv/functest/results
        functest_conf:      /home/opnfv/functest/conf
        functest_data:      /home/opnfv/functest/data
        ims_data:           /home/opnfv/functest/data/ims/
        functest_images:    /home/opnfv/functest/images
        rally_inst:         /root/.rally

    openstack:
        creds: /home/opnfv/functest/conf/openstack.creds
        snapshot_file: /home/opnfv/functest/conf/openstack_snapshot.yaml

        image_name: Cirros-0.3.5
        image_name_alt: Cirros-0.3.5-1
        image_file_name:  cirros-0.3.5-x86_64-disk.img
        image_url: http://download.cirros-cloud.net/0.3.5/cirros-0.3.5-x86_64-disk.img
        image_user: cirros
        image_disk_format:  qcow2
        image_username:  cirros
        image_password:  cubswin:)

        flavor_name: opnfv_flavor
        flavor_name_alt: opnfv_flavor_1
        flavor_ram: 512
        flavor_disk: 1
        flavor_vcpus: 1

        # Private network for functest. Will be created by config_functest.py
        neutron_private_net_name: functest-net
        neutron_private_subnet_name: functest-subnet
        neutron_private_subnet_cidr: 192.168.120.0/24
        neutron_private_subnet_start: 192.168.120.2
        neutron_private_subnet_end: 192.168.120.254
        neutron_private_subnet_gateway: 192.168.120.254
        neutron_router_name: functest-router

snaps:
    use_keystone: True
    use_floating_ips: True
    images:
      glance_tests:
        disk_file: /home/opnfv/functest/images/cirros-0.3.5-x86_64-disk.img
      cirros:
        disk_file: /home/opnfv/functest/images/cirros-0.3.5-x86_64-disk.img
      ubuntu:
        disk_file: /home/opnfv/functest/images/ubuntu-14.04-server-cloudimg-amd64-disk1.img
      centos:
        disk_file: /home/opnfv/functest/images/CentOS-7-x86_64-GenericCloud.qcow2
      # All of these values are optional and will override the values retrieved
      # by the RC file
#    os_creds_override:
#      username: {user}
#      password: {password}
#      auth_url: {auth_url}
#      project_name: {project_name}
#      identity_api_version: {2|3}
#      network_api_version: {2}
#      compute_api_version: {2}
#      image_api_version: {1|2}
#      user_domain_id: {user_domain_id}
#      project_domain_id: {projects_domain_id}
#      interface: {interface}
#      cacert: {True|False}
#      proxy_settings:
#        host: {proxy_host}
#        port: {proxy_port}
#        ssh_proxy_cmd: {OpenSSH -o ProxyCommand value}

vping:
    ping_timeout:   200
    vm_flavor: m1.tiny # adapt to your environment
    vm_name_1: opnfv-vping-1
    vm_name_2: opnfv-vping-2
    image_name: functest-vping
    private_net_name: vping-net
    # network_type: vlan
    # physical_network: physnet2
    # segmentation_id: 2366
    private_subnet_name: vping-subnet
    private_subnet_cidr: 192.168.130.0/24
    router_name: vping-router
    sg_name: vPing-sg
    sg_desc: Security group for vPing test case
    keypair_name: vPing-keypair
    keypair_priv_file: /tmp/vPing-keypair
    keypair_pub_file: /tmp/vPing-keypair.pub
    vm_boot_timeout: 180
    vm_delete_timeout: 100
    vm_ssh_connect_timeout: 60
    cleanup_objects: True
    unique_names: True

odl_sfc:
    image_base_url: "http://artifacts.opnfv.org/sfc/images"
    image_name: sfc_nsh_danube
    image_file_name: sfc_nsh_danube.qcow2
    image_format: qcow2

tempest:
    deployment_name: opnfv-tempest
    identity:
        tenant_name: tempest
        tenant_description: Tenant for Tempest test suite
        user_name: tempest
        user_password: Tempest123!
    validation:
        ssh_timeout: 130
    object_storage:
        operator_role: SwiftOperator
    private_net_name: tempest-net
    private_subnet_name: tempest-subnet
    private_subnet_cidr: 192.168.150.0/24
    router_name: tempest-router
    use_custom_images: True
    use_custom_flavors: False
    volume_device_name: vdc

rally:
    deployment_name: opnfv-rally
    network_name: rally-net
    subnet_name: rally-subnet
    subnet_cidr: 192.168.140.0/24
    router_name: rally-router

vnf:
    juju_epc:
        tenant_name: epc
        tenant_description: OAI EPC deployed with Juju
        tenant_images: {}
    cloudify_ims:
        tenant_name: cloudify_ims
        tenant_description: vIMS
        config: cloudify_ims.yaml
    orchestra_openims:
        tenant_name: orchestra_openims
        tenant_description: OpenIMS deployed with Open Baton
        config: orchestra.yaml
    orchestra_clearwaterims:
        tenant_name: orchestra_clearwaterims
        tenant_description: Clearwater IMS deployed with Open Baton
        config: orchestra.yaml

promise:
    tenant_name: promise
    tenant_description: promise Functionality Testing
    user_name: promiser
    user_pwd: test
    image_name: promise-img
    flavor_name: promise-flavor
    flavor_vcpus: 1
    flavor_ram: 128
    flavor_disk: 0
    network_name: promise-net
    subnet_name: promise-subnet
    subnet_cidr: 192.168.121.0/24
    router_name: promise-router

example:
    vm_name: example-vm
    flavor: m1.small
    image_name: functest-example-vm
    private_net_name: example-net
    private_subnet_name: exampl