#ifndef _RRUNNER_H_ #define _RRUNNER_H_ #include #if ((BITS_PER_LONG != 32) && (BITS_PER_LONG != 64)) #error "BITS_PER_LONG not defined or not valid" #endif struct rr_regs { u32 pad0[16]; u32 HostCtrl; u32 LocalCtrl; u32 Pc; u32 BrkPt; /* Timer increments every 0.97 micro-seconds (unsigned int) */ u32 Timer_Hi; u32 Timer; u32 TimerRef; u32 PciState; u32 Event; u32 MbEvent; u32 WinBase; u32 WinData; u32 RX_state; u32 TX_state; u32 Overhead; u32 ExtIo; u32 DmaWriteHostHi; u32 DmaWriteHostLo; u32 pad1[2]; u32 DmaReadHostHi; u32 DmaReadHostLo; u32 pad2; u32 DmaReadLen; u32 DmaWriteState; u32 DmaWriteLcl; u32 DmaWriteIPchecksum; u32 DmaWriteLen; u32 DmaReadState; u32 DmaReadLcl; u32 DmaReadIPchecksum; u32 pad3; u32 RxBase; u32 RxPrd; u32 RxCon; u32 pad4; u32 TxBase; u32 TxPrd; u32 TxCon; u32 pad5; u32 RxIndPro; u32 RxIndCon; u32 RxIndRef; u32 pad6; u32 TxIndPro; u32 TxIndCon; u32 TxIndRef; u32 pad7[17]; u32 DrCmndPro; u32 DrCmndCon; u32 DrCmndRef; u32 pad8; u32 DwCmndPro; u32 DwCmndCon; u32 DwCmndRef; u32 AssistState; u32 DrDataPro; u32 DrDataCon; u32 DrDataRef; u32 pad9; u32 DwDataPro; u32 DwDataCon; u32 DwDataRef; u32 pad10[33]; u32 EvtCon; u32 pad11[5]; u32 TxPi; u32 IpRxPi; u32 pad11a[8]; u32 CmdRing[16]; /* The ULA is in two registers the high order two bytes of the first * word contain the RunCode features. * ula0 res res byte0 byte1 * ula1 byte2 byte3 byte4 byte5 */ u32 Ula0; u32 Ula1; u32 RxRingHi; u32 RxRingLo; u32 InfoPtrHi; u32 InfoPtrLo; u32 Mode; u32 ConRetry; u32 ConRetryTmr; u32 ConTmout; u32 CtatTmr; u32 MaxRxRng; u32 IntrTmr; u32 TxDataMvTimeout; u32 RxDataMvTimeout; u32 EvtPrd; u32 TraceIdx; u32 Fail1; u32 Fail2; u32 DrvPrm; u32 FilterLA; u32 FwRev; u32 FwRes1; u32 FwRes2; u32 FwRes3; u32 WriteDmaThresh; u32 ReadDmaThresh; u32 pad12[325]; u32 Window[512]; }; /* * Host control register bits. */ #define RR_INT 0x01 #define RR_CLEAR_INT 0x02 #define NO_SWAP 0x04000004 #define NO_SWAP1 0x00000004 #define PCI_RESET_NIC 0x08 #define HALT_NIC 0x10 #define SSTEP_NIC 0x20 #define MEM_READ_MULTI 0x40 #define NIC_HALTED 0x100 #define HALT_INST 0x200 #define PARITY_ERR 0x400 #define INVALID_INST_B 0x800 #define RR_REV_2 0x20000000 #define RR_REV_MASK 0xf0000000 /* * Local control register bits. */ #define INTA_STATE 0x01 #define CLEAR_INTA 0x02 #define FAST_EEPROM_ACCESS 0x08 #define ENABLE_EXTRA_SRAM 0x100 #define ENABLE_EXTRA_DESC 0x200 #define ENABLE_PARITY 0x400 #define FORCE_DMA_PARITY_ERROR 0x800 #define ENABLE_EEPROM_WRITE 0x1000 #define ENABLE_DATA_CACHE 0x2000 #define SRAM_LO_PARITY_ERR 0x4000 #define SRAM_HI_PARITY_ERR 0x8000 /* * PCI state bits. */ #define FORCE_PCI_RESET 0x01 #define PROVIDE_LENGTH 0x02 #define MASK_DMA_READ_MAX 0x1C #define RBURST_DISABLE 0x00 #define RBURST_4 0x04 #define RBURST_16 0x08 #define RBURST_32 0x0C #define RBURST_64 0x10 #define RBURST_128 0x14 #define RBURST_256 0x18 #define RBURST_1024 0x1C #define MASK_DMA_WRITE_MAX 0xE0 #define WBURST_DISABLE 0x00 #define WBURST_4 0x20 #define WBURST_16 0x40 #define WBURST_32 0x60 #define WBURST_64 0x80 #define WBURST_128 0xa0 #define WBURST_256 0xc0 #define WBURST_1024 0xe0 #define MASK_MIN_DMA 0xFF00 #define FIFO_RETRY_ENABLE 0x10000 /* * Event register */ #define DMA_WRITE_DONE 0x10000 #define DMA_READ_DONE 0x20000 #define DMA_WRITE_ERR 0x40000 #define DMA_READ_ERR 0x80000 /* * Receive state * * RoadRunner HIPPI Receive State Register controls and monitors the * HIPPI receive interface in the NIC. Look at err bits when a HIPPI * receive Error Event occurs. */ #define ENABLE_NEW_CON 0x01 #define RESET_RECV 0x02 #define RECV_ALL 0x00 #define RECV_1K 0x20 #define RECV_2K 0x40 #define RECV_4K 0x60 #define RECV_8K 0x80 #define RECV_16K 0xa0 #define RECV_32K 0xc0 #define RECV_64K 0xe0 /* * Transmit status. */ #define ENA_XMIT 0x01 #define PERM_CON 0x02 /* * DMA write state */ #define RESET_DMA 0x01 #define NO_SWAP_DMA 0x02 #define DMA_ACTIVE 0x04 #define THRESH_MASK 0x1F #define DMA_ERROR_MASK 0xff000000 /* * Gooddies stored in the ULA registers. */ #define TRACE_ON_WHAT_BIT 0x00020000 /* Traces on */ #define ONEM_BUF_WHAT_BIT 0x00040000 /* 1Meg vs 256K */ #define CHAR_API_WHAT_BIT 0x00080000 /* Char API vs network only */ #define CMD_EVT_WHAT_BIT 0x00200000 /* Command event */ #define LONG_TX_WHAT_BIT 0x00400000 #define LONG_RX_WHAT_BIT 0x00800000 #define WHAT_BIT_MASK 0xFFFD0000 /* Feature bit mask */ /* * Mode status */ #define EVENT_OVFL 0x80000000 #define FATAL_ERR 0x40000000 #define LOOP_BACK 0x01 #define MODE_PH 0x02 #define MODE_FP 0x00 #define PTR64BIT 0x04 #define PTR32BIT 0x00 #define PTR_WD_SWAP 0x08 #define PTR_WD_NOSWAP 0x00 #define POST_WARN_EVENT 0x10 #define ERR_TERM 0x20 #define DIRECT_CONN 0x40 #define NO_NIC_WATCHDOG 0x80 #define 
classes:
- service.neutron.gateway.single
parameters:
  neutron:
    gateway:
      dvr: ${_param:neutron_gateway_dvr}
      agent_mode: ${_param:neutron_gateway_agent_mode}
      backend:
        tenant_network_types: ${_param:neutron_tenant_network_types}"
      message_queue:
        members:
          - host: ${_param:openstack_message_queue_node01_address}
          - host: