/* * Status and system control registers for ARM RealView/Versatile boards. * * Copyright (c) 2006-2007 CodeSourcery. * Written by Paul Brook * * This code is licensed under the GPL. */ #include "hw/hw.h" #include "qemu/timer.h" #include "qemu/bitops.h" #include "hw/sysbus.h" #include "hw/arm/primecell.h" #include "sysemu/sysemu.h" #define LOCK_VALUE 0xa05f #define TYPE_ARM_SYSCTL "realview_sysctl" #define ARM_SYSCTL(obj) \ OBJECT_CHECK(arm_sysctl_state, (obj), TYPE_ARM_SYSCTL) typedef struct { SysBusDevice parent_obj; MemoryRegion iomem; qemu_irq pl110_mux_ctrl; uint32_t sys_id; uint32_t leds; uint16_t lockval; uint32_t cfgdata1; uint32_t cfgdata2; uint32_t flags; uint32_t nvflags; uint32_t resetlevel; uint32_t proc_id; uint32_t sys_mci; uint32_t sys_cfgdata; uint32_t sys_cfgctrl; uint32_t sys_cfgstat; uint32_t sys_clcd; uint32_t mb_clock[6]; uint32_t *db_clock; uint32_t db_num_vsensors; uint32_t *db_voltage; uint32_t db_num_clocks; uint32_t *db_clock_reset; } arm_sysctl_state; static const VMStateDescription vmstate_arm_sysctl = { .name = "realview_sysctl", .version_id = 4, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(leds, arm_sysctl_state), VMSTATE_UINT16(lockval, arm_sysctl_state), VMSTATE_UINT32(cfgdata1, arm_sysctl_state), VMSTATE_UINT32(cfgdata2, arm_sysctl_state), VMSTATE_UINT32(flags, arm_sysctl_state), VMSTATE_UINT32(nvflags, arm_sysctl_state), VMSTATE_UINT32(resetlevel, arm_sysctl_state), VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2), VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2), VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2), VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2), VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3), VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4), VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks, 4, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; /* The PB926 actually uses a different format for * its SYS_ID register. Fortunately the bits which are * board type on later boards are distinct. */ #define BOARD_ID_PB926 0x100 #define BOARD_ID_EB 0x140 #define BOARD_ID_PBA8 0x178 #define BOARD_ID_PBX 0x182 #define BOARD_ID_VEXPRESS 0x190 static int board_id(arm_sysctl_state *s) { /* Extract the board ID field from the SYS_ID register value */ return (s->sys_id >> 16) & 0xfff; } static void arm_sysctl_reset(DeviceState *d) { arm_sysctl_state *s = ARM_SYSCTL(d); int i; s->leds = 0; s->lockval = 0; s->cfgdata1 = 0; s->cfgdata2 = 0; s->flags = 0; s->resetlevel = 0; /* Motherboard oscillators (in Hz) */ s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */ s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */ s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */ s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */ s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */ s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */ /* Daughterboard oscillators: reset from property values */ for (i = 0; i < s->db_num_clocks; i++) { s->db_clock[i] = s->db_clock_reset[i]; } if (board_id(s) == BOARD_ID_VEXPRESS) { /* On VExpress this register will RAZ/WI */ s->sys_clcd = 0; } else { /* All others: CLCDID 0x1f, indicating VGA */ s->sys_clcd = 0x1f00; } } static uint64_t arm_sysctl_read(void *opaque, hwaddr offset, unsigned size) { arm_sysctl_state *s = (arm_sysctl_state *)opaque; switch (offset) { case 0x00: /* ID */ return s->sys_id; case 0x04: /* SW */ /* General purpose hardware switches. We don't have a useful way of exposing these to the user. */ return 0; case 0x08: /* LED */ return s->leds; case 0x20: /* LOCK */ return s->lockval; case 0x0c: /* OSC0 */ case 0x10: /* OSC1 */ case 0x14: /* OSC2 */ case 0x18: /* OSC3 */ case 0x1c: /* OSC4 */ case 0x24: /* 100HZ */ /* ??? Implement these. */ return 0; case 0x28: /* CFGDATA1 */ return s->cfgdata1; case 0x2c: /* CFGDATA2 */ return s->cfgdata2; case 0x30: /* FLAGS */ return s->flags; case 0x38: /* NVFLAGS */ return s->nvflags; case 0x40: /* RESETCTL */ if (board_id(s) == BOARD_ID_VEXPRESS) { /* reserved: RAZ/WI */ return 0; } return s->resetlevel; case 0x44: /* PCICTL */ return 1; case 0x48: /* 
##############################################################################
# Copyright (c) 2018 Mirantis Inc., Enea AB and others.
# All rights reserved. This program and the accompanying materials
# are made available under the terms of the Apache License, Version 2.0
# which accompanies this distribution, and is available at
# http://www.apache.org/licenses/LICENSE-2.0
##############################################################################
---
classes:
  - cluster.all-mcp-arch-common
  - cluster.mcp-ovn-ha.infra
  - cluster.mcp-ovn-ha.openstack
on = extract32(s->sys_cfgctrl, 20, 6); unsigned int site = extract32(s->sys_cfgctrl, 16, 2); unsigned int position = extract32(s->sys_cfgctrl, 12, 4); unsigned int device = extract32(s->sys_cfgctrl, 0, 12); s->sys_cfgstat = 1; /* complete */ if (s->sys_cfgctrl & (1 << 30)) { if (!vexpress_cfgctrl_write(s, dcc, function, site, position, device, s->sys_cfgdata)) { s->sys_cfgstat |= 2; /* error */ } } else { uint32_t val; if (!vexpress_cfgctrl_read(s, dcc, function, site, position, device, &val)) { s->sys_cfgstat |= 2; /* error */ } else { s->sys_cfgdata = val; } } } s->sys_cfgctrl &= ~(1 << 31); return; case 0xa8: /* SYS_CFGSTAT */ if (board_id(s) != BOARD_ID_VEXPRESS) { goto bad_reg; } s->sys_cfgstat = val & 3; return; default: bad_reg: qemu_log_mask(LOG_GUEST_ERROR, "arm_sysctl_write: Bad register offset 0x%x\n", (int)offset); return; } } static const MemoryRegionOps arm_sysctl_ops = { .read = arm_sysctl_read, .write = arm_sysctl_write, .endianness = DEVICE_NATIVE_ENDIAN, }; static void arm_sysctl_gpio_set(void *opaque, int line, int level) { arm_sysctl_state *s = (arm_sysctl_state *)opaque; switch (line) { case ARM_SYSCTL_GPIO_MMC_WPROT: { /* For PB926 and EB write-protect is bit 2 of SYS_MCI; * for all later boards it is bit 1. */ int bit = 2; if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) { bit = 4; } s->sys_mci &= ~bit; if (level) { s->sys_mci |= bit; } break; } case ARM_SYSCTL_GPIO_MMC_CARDIN: s->sys_mci &= ~1; if (level) { s->sys_mci |= 1; } break; } } static void arm_sysctl_init(Object *obj) { DeviceState *dev = DEVICE(obj); SysBusDevice *sd = SYS_BUS_DEVICE(obj); arm_sysctl_state *s = ARM_SYSCTL(obj); memory_region_init_io(&s->iomem, OBJECT(dev), &arm_sysctl_ops, s, "arm-sysctl", 0x1000); sysbus_init_mmio(sd, &s->iomem); qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2); qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1); } static void arm_sysctl_realize(DeviceState *d, Error **errp) { arm_sysctl_state *s = ARM_SYSCTL(d); s->db_clock = g_new0(uint32_t, s->db_num_clocks); } static void arm_sysctl_finalize(Object *obj) { arm_sysctl_state *s = ARM_SYSCTL(obj); g_free(s->db_voltage); g_free(s->db_clock); g_free(s->db_clock_reset); } static Property arm_sysctl_properties[] = { DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0), /* Daughterboard power supply voltages (as reported via SYS_CFG) */ DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors, db_voltage, qdev_prop_uint32, uint32_t), /* Daughterboard clock reset values (as reported via SYS_CFG) */ DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks, db_clock_reset, qdev_prop_uint32, uint32_t), DEFINE_PROP_END_OF_LIST(), }; static void arm_sysctl_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = arm_sysctl_realize; dc->reset = arm_sysctl_reset; dc->vmsd = &vmstate_arm_sysctl; dc->props = arm_sysctl_properties; } static const TypeInfo arm_sysctl_info = { .name = TYPE_ARM_SYSCTL, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(arm_sysctl_state), .instance_init = arm_sysctl_init, .instance_finalize = arm_sysctl_finalize, .class_init = arm_sysctl_class_init, }; static void arm_sysctl_register_types(void) { type_register_static(&arm_sysctl_info); } type_init(arm_sysctl_register_types)