/* * tegra30_ahub.h - Definitions for Tegra30 AHUB driver * * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef __TEGRA30_AHUB_H__ #define __TEGRA30_AHUB_H__ /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24 #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) /* Channel count minus 1 */ #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) /* Channel count minus 1 */ #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20 #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) /* Channel count minus 1 */ #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) /* Channel count minus 1 */ #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) #define TEGRA30_AUDIOCIF_BITS_4 0 #define TEGRA30_AUDIOCIF_BITS_8 1 #define TEGRA30_AUDIOCIF_BITS_12 2 #define TEGRA30_AUDIOCIF_BITS_16 3 #define TEGRA30_AUDIOCIF_BITS_20 4 #define TEGRA30_AUDIOCIF_BITS_24 5 #define TEGRA30_AUDIOCIF_BITS_28 6 #define TEGRA30_AUDIOCIF_BITS_32 7 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0 #define TEGRA30_AUDIOCIF_EXPAND_ONE 1 #define TEGRA30_AUDIOCIF_EXPAND_LF
##############################################################################
# Copyright (c) 2016 Mirantis, Inc. and others.
# mpolenchuk@mirantis.com
# All rights reserved. This program and the accompanying materials
# are made available under the terms of the Apache License, Version 2.0
# which accompanies this distribution, and is available at
# http://www.apache.org/licenses/LICENSE-2.0
##############################################################################

plugin-config-metadata:
  title: NFV KVM fuel Plugin configuration template
  version: 1.0.0
  created: 05.12.2016
  comment: None

fuel-plugin-kvm:
  metadata:
    #chosen_id: Assigned during installation
    class: plugin
    default: false
    enabled: true
    label: fuel-plugin-kvm
    toggleable: true
    versions:
    - metadata:
        always_editable: false
        #plugin_id: 1 Assigned during installation
        plugin_version: 1.0.0
      use_kvm:
        label: 'EXPERIMENTAL: KVM enhancements for NFV'
        type: checkbox
        value: true
        weight: 20
    weight: 70
ATUS_USER_TX_ENABLED (1 << 11) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1) #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0) /* TEGRA30_AHUB_I2S_INT_MASK */ #define TEGRA30_AHUB_I2S_INT_MASK 0xb0 /* TEGRA30_AHUB_DAM_INT_MASK */ #define TEGRA30_AHUB_DAM_INT_MASK 0xb4 /* TEGRA30_AHUB_SPDIF_INT_MASK */ #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc /* TEGRA30_AHUB_APBIF_INT_MASK */ #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0 /* TEGRA30_AHUB_I2S_INT_STATUS */ #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8 /* TEGRA30_AHUB_DAM_INT_STATUS */ #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc /* TEGRA30_AHUB_SPDIF_INT_STATUS */ #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4 /* TEGRA30_AHUB_APBIF_INT_STATUS */ #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8 /* TEGRA30_AHUB_I2S_INT_SOURCE */ #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0 /* TEGRA30_AHUB_DAM_INT_SOURCE */ #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4 /* TEGRA30_AHUB_SPDIF_INT_SOURCE */ #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec /* TEGRA30_AHUB_APBIF_INT_SOURCE */ #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0 /* TEGRA30_AHUB_I2S_INT_SET */ #define TEGRA30_AHUB_I2S_INT_SET 0xf8 /* TEGRA30_AHUB_DAM_INT_SET */ #define TEGRA30_AHUB_DAM_INT_SET 0xfc /* TEGRA30_AHUB_SPDIF_INT_SET */ #define TEGRA30_AHUB_SPDIF_INT_SET 0x100 /* TEGRA30_AHUB_APBIF_INT_SET */ #define TEGRA30_AHUB_APBIF_INT_SET 0x104 /* Registers within TEGRA30_AHUB_BASE */ #define TEGRA30_AHUB_AUDIO_RX 0x0 #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4 #define TEGRA30_AHUB_AUDIO_RX_COUNT 17 /* This register repeats once for each entry in enum tegra30_ahub_rxcif */ /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */ /* * Terminology: * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs, * I2S controllers, SPDIF controllers, and DAMs. * XBAR: The core cross-bar component of the AHUB. * CIF: Client Interface; the HW module connecting an audio device to the * XBAR. * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams, * possibly including sample-rate conversion. * * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio * transmitted by a particular TX CIF. * * This driver is currently very simplistic; many HW features are not * exposed; DAMs are not supported, only 16-bit stereo audio is supported, * etc. */ enum tegra30_ahub_txcif { TEGRA30_AHUB_TXCIF_APBIF_TX0, TEGRA30_AHUB_TXCIF_APBIF_TX1, TEGRA30_AHUB_TXCIF_APBIF_TX2, TEGRA30_AHUB_TXCIF_APBIF_TX3, TEGRA30_AHUB_TXCIF_I2S0_TX0, TEGRA30_AHUB_TXCIF_I2S1_TX0, TEGRA30_AHUB_TXCIF_I2S2_TX0, TEGRA30_AHUB_TXCIF_I2S3_TX0, TEGRA30_AHUB_TXCIF_I2S4_TX0, TEGRA30_AHUB_TXCIF_DAM0_TX0, TEGRA30_AHUB_TXCIF_DAM1_TX0, TEGRA30_AHUB_TXCIF_DAM2_TX0, TEGRA30_AHUB_TXCIF_SPDIF_TX0, TEGRA30_AHUB_TXCIF_SPDIF_TX1, }; enum tegra30_ahub_rxcif { TEGRA30_AHUB_RXCIF_APBIF_RX0, TEGRA30_AHUB_RXCIF_APBIF_RX1, TEGRA30_AHUB_RXcIF_APBIF_RX2, TEGRA30_AHUB_RXCIF_APBIF_RX3, TEGRA30_AHUB_RXCIF_I2S0_RX0, TEGRA30_AHUB_RXCIF_I2S1_RX0, TEGRA30_AHUB_RXCIF_I2S2_RX0, TEGRA30_AHUB_RXCIF_I2S3_RX0, TEGRA30_AHUB_RXCIF_I2S4_RX0, TEGRA30_AHUB_RXCIF_DAM0_RX0, TEGRA30_AHUB_RXCIF_DAM0_RX1, TEGRA30_AHUB_RXCIF_DAM1_RX0, TEGRA30_AHUB_RXCIF_DAM2_RX1, TEGRA30_AHUB_RXCIF_DAM3_RX0, TEGRA30_AHUB_RXCIF_DAM3_RX1, TEGRA30_AHUB_RXCIF_SPDIF_RX0, TEGRA30_AHUB_RXCIF_SPDIF_RX1, }; extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, char *dmachan, int dmachan_len, dma_addr_t *fiforeg); extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, char *dmachan, int dmachan_len, dma_addr_t *fiforeg); extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, enum tegra30_ahub_txcif txcif); extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif); struct tegra30_ahub_cif_conf { unsigned int threshold; unsigned int audio_channels; unsigned int client_channels; unsigned int audio_bits; unsigned int client_bits; unsigned int expand; unsigned int stereo_conv; unsigned int replicate; unsigned int direction; unsigned int truncate; unsigned int mono_conv; }; void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, struct tegra30_ahub_cif_conf *conf); void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, struct tegra30_ahub_cif_conf *conf); struct tegra30_ahub_soc_data { u32 mod_list_mask; void (*set_audio_cif)(struct regmap *regmap, unsigned int reg, struct tegra30_ahub_cif_conf *conf); /* * FIXME: There are many more differences in HW, such as: * - More APBIF channels. * - Extra separate chunks of register address space to represent * the extra APBIF channels. * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif * need expansion, coupled with there being more defined bits in * the AHUB routing registers. * However, the driver doesn't support those new features yet, so we * don't represent them here yet. */ }; struct tegra30_ahub { const struct tegra30_ahub_soc_data *soc_data; struct device *dev; struct clk *clk_d_audio; struct clk *clk_apbif; resource_size_t apbif_addr; struct regmap *regmap_apbif; struct regmap *regmap_ahub; DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); }; #endif