/* * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of the Open Source and Linux Lab nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "qemu/host-utils.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif static struct XtensaConfigList *xtensa_cores; static void xtensa_core_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); const XtensaConfig *config = data; xcc->config = config; /* Use num_core_regs to see only non-privileged registers in an unmodified * gdb. Use num_regs to see all registers. gdb modification is required * for that: reset bit 0 in the 'flags' field of the registers definitions * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. */ cc->gdb_num_core_regs = config->gdb_regmap.num_regs; } void xtensa_finalize_config(XtensaConfig *config) { unsigned i, n = 0; if (config->gdb_regmap.num_regs) { return; } for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) { n += (config->gdb_regmap.reg[i].type != 6); } config->gdb_regmap.num_regs = n; } void xtensa_register_core(XtensaConfigList *node) { TypeInfo type = { .parent = TYPE_XTENSA_CPU, .class_init = xtensa_core_class_init, .class_data = (void *)node->config, }; node->next = xtensa_cores; xtensa_cores = node; type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name); type_register(&type); g_free((gpointer)type.name); } static uint32_t check_hw_breakpoints(CPUXtensaState *env) { unsigned i; for (i = 0; i < env->config->ndbreak; ++i) { if (env->cpu_watchpoint[i] && env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT); } } return 0; } void xtensa_breakpoint_handler(CPUState *cs) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { uint32_t cause; cs->watchpoint_hit = NULL; cause = check_hw_breakpoints(env); if (cause) { debug_exception_env(env, cause); } cpu_resume_from_signal(cs, NULL); } } } XtensaCPU *cpu_xtensa_init(const char *cpu_model) { ObjectClass *oc; XtensaCPU *cpu; CPUXtensaState *env; oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model); if (oc == NULL) { return NULL; } cpu = XTENSA_CPU(object_new(object_class_get_name(oc))); env = &cpu->env; xtensa_irq_init(env); object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; } void xtensa_cpu_list(FILE *f, fprintf_f
#!/bin/bash
set -ex


export PATH=/usr/local/go/bin:$PATH
DIR="$(dirname `readlink -f $0`)"

apt-get update && apt-get install -y git wget gcc
wget -qO- https://storage.googleapis.com/golang/go1.8.3.linux-amd64.tar.gz | tar -C /usr/local/ -xz
rm -rf plugins
git clone https://github.com/containernetworking/plugins
cd plugins
git checkout 5544d9ced0d6e908fe26e9dbe529c7feb87d21f5
mkdir plugins/main/ovsdpdk
cp $DIR/ovsdpdk.go plugins/main/ovsdpdk
sed -i "s,PLUGINS=.*,PLUGINS=plugins/main/ovsdpdk," build.sh
./build.sh
mkdir -p /opt/cni/bin
cp bin/ovsdpdk /opt/cni/bin
cp $DIR/setup_ovsdpdk.sh $DIR/teardown_ovsdpdk.sh /opt/cni/bin
bool update_tlb, uint32_t vaddr, int is_write, int mmu_idx, uint32_t *paddr, uint32_t *page_size, unsigned *access, bool may_lookup_pt) { bool dtlb = is_write != 2; uint32_t wi; uint32_t ei; uint8_t ring; uint32_t vpn; uint32_t pte; const xtensa_tlb_entry *entry = NULL; xtensa_tlb_entry tmp_entry; int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && may_lookup_pt && get_pte(env, vaddr, &pte) == 0) { ring = (pte >> 4) & 0x3; wi = 0; split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); if (update_tlb) { wi = ++env->autorefill_idx & 0x3; xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); env->sregs[EXCVADDR] = vaddr; qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n", __func__, vaddr, vpn, pte); } else { xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); entry = &tmp_entry; } ret = 0; } if (ret != 0) { return ret; } if (entry == NULL) { entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); } if (ring < mmu_idx) { return dtlb ? LOAD_STORE_PRIVILEGE_CAUSE : INST_FETCH_PRIVILEGE_CAUSE; } *access = mmu_attr_to_access(entry->attr) & ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); if (!is_access_granted(*access, is_write)) { return dtlb ? (is_write ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE) : INST_FETCH_PROHIBITED_CAUSE; } *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; return 0; } static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) { CPUState *cs = CPU(xtensa_env_get_cpu(env)); uint32_t paddr; uint32_t page_size; unsigned access; uint32_t pt_vaddr = (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, &paddr, &page_size, &access, false); qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n", __func__, vaddr, ret ? ~0 : paddr); if (ret == 0) { *pte = ldl_phys(cs->as, paddr); } return ret; } static int get_physical_addr_region(CPUXtensaState *env, uint32_t vaddr, int is_write, int mmu_idx, uint32_t *paddr, uint32_t *page_size, unsigned *access) { bool dtlb = is_write != 2; uint32_t wi = 0; uint32_t ei = (vaddr >> 29) & 0x7; const xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); *access = region_attr_to_access(entry->attr); if (!is_access_granted(*access, is_write)) { return dtlb ? (is_write ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE) : INST_FETCH_PROHIBITED_CAUSE; } *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); *page_size = ~REGION_PAGE_MASK + 1; return 0; } /*! * Convert virtual address to physical addr. * MMU may issue pagewalk and change xtensa autorefill TLB way entry. * * \return 0 if ok, exception cause code otherwise */ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, uint32_t vaddr, int is_write, int mmu_idx, uint32_t *paddr, uint32_t *page_size, unsigned *access) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { return get_physical_addr_mmu(env, update_tlb, vaddr, is_write, mmu_idx, paddr, page_size, access, true); } else if (xtensa_option_bits_enabled(env->config, XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { return get_physical_addr_region(env, vaddr, is_write, mmu_idx, paddr, page_size, access); } else { *paddr = vaddr; *page_size = TARGET_PAGE_SIZE; *access = cacheattr_attr_to_access( env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27)); return 0; } } static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env, bool dtlb) { unsigned wi, ei; const xtensa_tlb *conf = dtlb ? &env->config->dtlb : &env->config->itlb; unsigned (*attr_to_access)(uint32_t) = xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? mmu_attr_to_access : region_attr_to_access; for (wi = 0; wi < conf->nways; ++wi) { uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; const char *sz_text; bool print_header = true; if (sz >= 0x100000) { sz >>= 20; sz_text = "MB"; } else { sz >>= 10; sz_text = "KB"; } for (ei = 0; ei < conf->way_size[wi]; ++ei) { const xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); if (entry->asid) { static const char * const cache_text[8] = { [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass", [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT", [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB", [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate", }; unsigned access = attr_to_access(entry->attr); unsigned cache_idx = (access & PAGE_CACHE_MASK) >> PAGE_CACHE_SHIFT; if (print_header) { print_header = false; cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text); cpu_fprintf(f, "\tVaddr Paddr ASID Attr RWX Cache\n" "\t---------- ---------- ---- ---- --- -------\n"); } cpu_fprintf(f, "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n", entry->vaddr, entry->paddr, entry->asid, entry->attr, (access & PAGE_READ) ? 'R' : '-', (access & PAGE_WRITE) ? 'W' : '-', (access & PAGE_EXEC) ? 'X' : '-', cache_text[cache_idx] ? cache_text[cache_idx] : "Invalid"); } } } } void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) { if (xtensa_option_bits_enabled(env->config, XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { cpu_fprintf(f, "ITLB:\n"); dump_tlb(f, cpu_fprintf, env, false); cpu_fprintf(f, "\nDTLB:\n"); dump_tlb(f, cpu_fprintf, env, true); } else { cpu_fprintf(f, "No TLB for this CPU core\n"); } }