/* * s3c24xx-i2s.c -- ALSA Soc Audio Layer * * (c) 2006 Wolfson Microelectronics PLC. * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com * * Copyright 2004-2005 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ #include #include #include #include #include #include #include #include #include #include #include "regs-iis.h" #include "dma.h" #include "s3c24xx-i2s.h" static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = { .channel = DMACH_I2S_OUT, .ch_name = "tx", .dma_size = 2, }; static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = { .channel = DMACH_I2S_IN, .ch_name = "rx", .dma_size = 2, }; struct s3c24xx_i2s_info { void __iomem *regs; struct clk *iis_clk; u32 iiscon; u32 iismod; u32 iisfcon; u32 iispsr; }; static struct s3c24xx_i2s_info s3c24xx_i2s; static void s3c24xx_snd_txctrl(int on) { u32 iisfcon; u32 iiscon; u32 iismod; pr_debug("Entered %s\n", __func__); iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); if (on) { iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE; iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN; iiscon &= ~S3C2410_IISCON_TXIDLE; iismod |= S3C2410_IISMOD_TXMODE; writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); } else { /* note, we have to disable the FIFOs otherwise bad things * seem to happen when the DMA stops. According to the * Samsung supplied kernel, this should allow the DMA * engine and FIFOs to reset. If this isn't allowed, the * DMA engine will simply freeze randomly. */ iisfcon &= ~S3C2410_IISFCON_TXENABLE; iisfcon &= ~S3C2410_IISFCON_TXDMA; iiscon |= S3C2410_IISCON_TXIDLE; iiscon &= ~S3C2410_IISCON_TXDMAEN; iismod &= ~S3C2410_IISMOD_TXMODE; writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); } pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); } static void s3c24xx_snd_rxctrl(int on) { u32 iisfcon; u32 iiscon; u32 iismod; pr_debug("Entered %s\n", __func__); iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); if (on) { iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE; iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN; iiscon &= ~S3C2410_IISCON_RXIDLE; iismod |= S3C2410_IISMOD_RXMODE; writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); } else { /* note, we have to disable the FIFOs otherwise bad things * seem to happen when the DMA stops. According to the * Samsung supplied kernel, this should allow the DMA * engine and FIFOs to reset. If this isn't allowed, the * DMA engine will simply freeze randomly. */ iisfcon &= ~S3C2410_IISFCON_RXENABLE; iisfcon &= ~S3C2410_IISFCON_RXDMA; iiscon |= S3C2410_IISCON_RXIDLE; iiscon &= ~S3C2410_IISCON_RXDMAEN; iismod &= ~S3C2410_IISMOD_RXMODE; writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); } pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); } /* * Wait for the LR signal to allow synchronisation to the L/R clock * from the codec. May only be needed for slave mode. */ static int s3c24xx_snd_lrsync(void) { u32 iiscon; int timeout = 50; /* 5ms */ pr_debug("Entered %s\n", __func__); while (1) { iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); if (iiscon & S3C2410_IISCON_LRINDEX) break; if (!timeout--) return -ETIMEDOUT; udelay(100); } return 0; } /* * Check whether CPU is the master or slave */ static inline int s3c24xx_snd_is_clkmaster(void) { pr_debug("Entered %s\n", __func__); return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1; } /* * Set S3C24xx I2S DAI format */ static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) { u32 iismod; pr_debug("Entered %s\n", __func__); iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); pr_debug("hw_params r: IISMOD: %x \n", iismod); switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBM_CFM: iismod |= S3C2410_IISMOD_SLAVE; break; case SND_SOC_DAIFMT_CBS_CFS: iismod &= ~S3C2410_IISMOD_SLAVE; break; default: return -EINVAL; } switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_LEFT_J: iismod |= S3C2410_IISMOD_MSB; break; case SND_SOC_DAIFMT_I2S: iismod &= ~S3C2410_IISMOD_MSB; break; default: return -EINVAL; } writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); pr_debug("hw_params w: IISMOD: %x \n", iismod); return 0; } static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_dmaengine_dai_dma_data *dma_data; u32 iismod; pr_debug("Entered %s\n", __func__); dma_data = snd_soc_dai_get_dma_data(dai, substream); /* Working copies of register */ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); pr_debug("hw_params r: IISMOD: %x\n", iismod); switch (params_width(params)) { case 8: iismod &= ~S3C2410_IISMOD_16BIT; dma_data->addr_width = 1; break; case 16: iismod |= S3C2410_IISMOD_16BIT; dma_data->addr_width = 2; break; default: return -EINVAL; } writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); pr_debug("hw_params w: IISMOD: %x\n", iismod); return 0; } static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { int ret = 0; pr_debug("Entered %s\n", __func__); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (!s3c24xx_snd_is_clkmaster()) { ret = s3c24xx_snd_lrsync(); if (ret) goto exit_err; } if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) s3c24xx_snd_rxctrl(1); else s3c24xx_snd_txctrl(1); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) s3c24xx_snd_rxctrl(0); else s3c24xx_snd_txctrl(0); break; default: ret = -EINVAL; break; } exit_err: return ret; } /* * Set S3C24xx Clock source */ static int s3c24xx_i2s_