/* * An RTC driver for the NVIDIA Tegra 200 series internal RTC. * * Copyright (c) 2010, NVIDIA Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #include #include #include #include #include #include #include #include #include #include /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */ #define TEGRA_RTC_REG_BUSY 0x004 #define TEGRA_RTC_REG_SECONDS 0x008 /* when msec is read, the seconds are buffered into shadow seconds. */ #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c #define TEGRA_RTC_REG_MILLI_SECONDS 0x010 #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014 #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c #define TEGRA_RTC_REG_INTR_MASK 0x028 /* write 1 bits to clear status bits */ #define TEGRA_RTC_REG_INTR_STATUS 0x02c /* bits in INTR_MASK */ #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4) #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3) #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2) #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1) #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0) /* bits in INTR_STATUS */ #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4) #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3) #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2) #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1) #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0) struct tegra_rtc_info { struct platform_device *pdev; struct rtc_device *rtc_dev; void __iomem *rtc_base; /* NULL if not initialized. */ int tegra_rtc_irq; /* alarm and periodic irq */ spinlock_t tegra_rtc_lock; }; /* RTC hardware is busy when it is updating its values over AHB once * every eight 32kHz clocks (~250uS). * outside of these updates the CPU is free to write. * CPU is always free to read. */ static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info) { return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1; } /* Wait for hardware to be ready for writing. * This function tries to maximize the amount of time before the next update. * It does this by waiting for the RTC to become busy with its periodic update, * then returning once the RTC first becomes not busy. * This periodic update (where the seconds and milliseconds are copied to the * AHB side) occurs every eight 32kHz clocks (~250uS). * The behavior of this function allows us to make some assumptions without * introducing a race, because 250uS is plenty of time to read/write a value. */ static int tegra_rtc_wait_while_busy(struct device *dev) { struct tegra_rtc_info *info = dev_get_drvdata(dev); int retries = 500; /* ~490 us is the worst case, ~250 us is best. */ /* first wait for the RTC to become busy. this is when it * posts its updated seconds+msec registers to AHB side. */ while (tegra_rtc_check_busy(info)) { if (!retries--) goto retry_failed; udelay(1); } /* now we have about 250 us to manipulate registers */ return 0; retry_failed: dev_err(dev, "write failed:retry count exceeded.\n"); return -ETIMEDOUT; } static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm) { struct tegra_rtc_info *info = dev_get_drvdata(dev); unsigned long sec, msec; unsigned long sl_irq_flags; /* RTC hardware copies seconds to shadow seconds when a read * of milliseconds occurs. use a lock to keep other threads out. */ spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS); sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS); spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); rtc_time_to_tm(sec, tm); dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n", sec, tm->tm_mon + 1, tm->tm_mday, tm->tm_year + 1900, tm->tm_hour, tm->tm_min, tm->tm_sec ); return 0; } static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm) { struct tegra_rtc_info *info = dev_get_drvdata