/* * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips * * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ * * This file is automatically generated from the AM33XX hardware databases. * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include "omap_hwmod.h" #include #include #include "omap_hwmod_common_data.h" #include "control.h" #include "cm33xx.h" #include "prm33xx.h" #include "prm-regbits-33xx.h" #include "i2c.h" #include "wd_timer.h" #include "omap_hwmod_33xx_43xx_common_data.h" /* * IP blocks */ /* * 'emif' class * instance(s): emif */ static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { .rev_offs = 0x0000, }; static struct omap_hwmod_class am33xx_emif_hwmod_class = { .name = "emif", .sysc = &am33xx_emif_sysc, }; /* emif */ static struct omap_hwmod am33xx_emif_hwmod = { .name = "emif", .class = &am33xx_emif_hwmod_class, .clkdm_name = "l3_clkdm", .flags = HWMOD_INIT_NO_IDLE, .main_clk = "dpll_ddr_m2_div2_ck", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, }; /* l4_hs */ static struct omap_hwmod am33xx_l4_hs_hwmod = { .name = "l4_hs", .class = &am33xx_l4_hwmod_class, .clkdm_name = "l4hs_clkdm", .flags = HWMOD_INIT_NO_IDLE, .main_clk = "l4hs_gclk", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, }; static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, }; /* wkup_m3 */ static struct omap_hwmod am33xx_wkup_m3_hwmod = { .name = "wkup_m3", .class = &am33xx_wkup_m3_hwmod_class, .clkdm_name = "l4_wkup_aon_clkdm", /* Keep hardreset asserted */ .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, .main_clk = "dpll_core_m4_div2_ck", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, .rst_lines = am33xx_wkup_m3_resets, .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), }; /* * 'adc/tsc' class * TouchScreen Controller (Anolog-To-Digital Converter) */ static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { .rev_offs = 0x00, .sysc_offs = 0x10, .sysc_flags = SYSC_HAS_SIDLEMODE, .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | SIDLE_SMART_WKUP), .sysc_fields = &omap_hwmod_sysc_type2, }; static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { .name = "adc_tsc", .sysc = &am33xx_adc_tsc_sysc, }; static struct omap_hwmod am33xx_adc_tsc_hwmod = { .name = "adc_tsc", .class = &am33xx_adc_tsc_hwmod_class, .clkdm_name = "l4_wkup_clkdm", .main_clk = "adc_tsc_fck", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, }; /* * Modules omap_hwmod structures * * The following IPs are excluded for the moment because: * - They do not need an explicit SW control using omap_hwmod API. * - They still need to be validated with the driver * properly adapted to omap_hwmod / omap_device * * - cEFUSE (doesn't fall under any ocp_if) * - clkdiv32k * - ocp watch point */ #if 0 /* * 'cefuse' class */ static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { .name = "cefuse", }; static struct omap_hwmod am33xx_cefuse_hwmod = { .name = "cefuse", .class = &am33xx_cefuse_hwmod_class, .clkdm_name = "l4_cefuse_clkdm", .main_clk = "cefuse_fck", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, }; /* * 'clkdiv32k' class */ static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { .name = "clkdiv32k", }; static struct omap_hwmod am33xx_clkdiv32k_hwmod = { .name = "clkdiv32k", .class = &am33xx_clkdiv32k_hwmod_class, .clkdm_name = "clk_24mhz_clkdm", .main_clk = "clkdiv32k_ick", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, }; /* ocpwp */ static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { .name = "ocpwp", }; static struct omap_hwmod am33xx_ocpwp_hwmod = { .name = "ocpwp", .class = &am33xx_ocpwp_hwmod_class, .clkdm_name = "l4ls_clkdm", .main_clk = "l4ls_gclk", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, }, }; #endif /* * 'debugss' class * debug sub system */ static struct omap_hwmod_opt_clk debugss_opt_clks[] = { { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" }, { .role = "dbg_clka", .clk = "dbg_clka_ck" }, }; static struct omap_hwmod_class am33xx_debugss_hwmod_class = { .name = "debugss", }; static struct omap_hwmod am33xx_debugss_hwmod = { .name = "debugss", .class = &am33xx_debugss_hwmod_class, .clkdm_name = "l3_aon_clkdm", .main
heat_template_version: ocata

description: >
  SNMP client configured with Puppet, to facilitate Ceilometer Hardware
  monitoring in the undercloud. This service is required to enable hardware
  monitoring.

parameters:
  ServiceNetMap:
    default: {}
    description: Mapping of service_name -> network name. Typically set
                 via parameter_defaults in the resource registry.  This
                 mapping overrides those in ServiceNetMapDefaults.
    type: json
  DefaultPasswords:
    default: {}
    type: json
  EndpointMap: