comment "Processor Type" # Select CPU types depending on the architecture selected. This selects # which CPUs we support in the kernel image, and the compiler instruction # optimiser behaviour. # ARM7TDMI config CPU_ARM7TDMI bool "Support ARM7TDMI processor" depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T select CPU_CACHE_V4 select CPU_PABRT_LEGACY help A 32-bit RISC microprocessor based on the ARM7 processor core which has no memory control unit and cache. Say Y if you want support for the ARM7TDMI processor. Otherwise, say N. # ARM720T config CPU_ARM720T bool "Support ARM720T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) select CPU_32v4T select CPU_ABRT_LV4T select CPU_CACHE_V4 select CPU_CACHE_VIVT select CPU_COPY_V4WT if MMU select CPU_CP15_MMU select CPU_PABRT_LEGACY select CPU_TLB_V4WT if MMU help A 32-bit RISC processor with 8kByte Cache, Write Buffer and MMU built around an ARM7TDMI core. Say Y if you want support for the ARM720T processor. Otherwise, say N. # ARM740T config CPU_ARM740T bool "Support ARM740T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T select CPU_CACHE_V4 select CPU_CP15_MPU select CPU_PABRT_LEGACY help A 32-bit RISC processor with 8KB cache or 4KB variants, write buffer and MPU(Protection Unit) built around an ARM7TDMI core. Say Y if you want support for the ARM740T processor. Otherwise, say N. # ARM9TDMI config CPU_ARM9TDMI bool "Support ARM9TDMI processor" depends on !MMU select CPU_32v4T select CPU_ABRT_NOMMU select CPU_CACHE_V4 select CPU_PABRT_LEGACY help A 32-bit RISC microprocessor based on the ARM9 processor core which has no memory control unit and cache. Say Y if you want support for the ARM9TDMI processor. Otherwise, say N. # ARM920T config CPU_ARM920T bool "Support ARM920T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) select CPU_32v4T select CPU_ABRT_EV4T select CPU_CACHE_V4WT select CPU_CACHE_VIVT select CPU_COPY_V4WB if MMU select CPU_CP15_MMU select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM920T is licensed to be produced by numerous vendors, and is used in the Cirrus EP93xx and the Samsung S3C2410. Say Y if you want support for the ARM920T processor. Otherwise, say N. # ARM922T config CPU_ARM922T bool "Support ARM922T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR) select CPU_32v4T select CPU_ABRT_EV4T select CPU_CACHE_V4WT select CPU_CACHE_VIVT select CPU_COPY_V4WB if MMU select CPU_CP15_MMU select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM922T is a version of the ARM920T, but with smaller instruction and data caches. It is used in Altera's Excalibur XA device family and Micrel's KS8695 Centaur. Say Y if you want support for the ARM922T processor. Otherwise, say N. # ARM925T config CPU_ARM925T bool "Support ARM925T processor" if ARCH_OMAP1 select CPU_32v4T select CPU_ABRT_EV4T select CPU_CACHE_V4WT select CPU_CACHE_VIVT select CPU_COPY_V4WB if MMU select CPU_CP15_MMU select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help The ARM925T is a mix between the ARM920T and ARM926T, but with different instruction and data caches. It is used in TI's OMAP device family. Say Y if you want support for the ARM925T processor. Otherwise, say N. # ARM926T config CPU_ARM926T bool "Support ARM926T processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V5) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB) select CPU_32v5 select CPU_ABRT_EV5TJ select CPU_CACHE_VIVT select CPU_COPY_V4WB if MMU select CPU_CP15_MMU select CPU_PABRT_LEGACY select CPU_TLB_V4WBI if MMU help This is a variant of the ARM920. It has slightly different instruction sequences for cache and TLB operations. Curiously, there is no documentation on it at the ARM corporate website. Say Y if you want support for the ARM926T processor. Otherwise, say N. # FA526 config CPU_FA526 bool select CPU_32v4 select CPU_ABRT_EV4 select CPU_CACHE_FA select CPU_CACHE_VIVT select CPU_COPY_FA if MMU select CPU_CP15_MMU select CPU_PABRT_LEGACY select CPU_TLB_FA if MMU help The FA526 is a version of the ARMv4 compatible processor with Branch Target Buffer, Unified TLB and cache line size 16. Say Y if you 
resource_registry:
  # Docker container with heat agents for containerized compute node.
  OS::TripleO::ComputePostDeployment: ../docker/compute-post.yaml
  OS::TripleO::NodeUserData: ../docker/firstboot/install_docker_agents.yaml

parameter_defaults:
  NovaImage: atomic-image

parameter_defaults:
  # Defaults to 'tripleoupstream'.  Specify a local docker registry
  # Example: 192.0.2.1:8787/tripleoupstream
  DockerNamespace: tripleoupstream
  # Enable local Docker registry
  DockerNamespaceIsRegistry: false
  # Compute Node Images
  DockerComputeImage: centos-binary-nova-compute:latest
  DockerAgentImage: heat-docker-agents:latest
  DockerComputeDataImage: centos-binary-data:latest
  DockerLibvirtImage: centos-binary-nova-libvirt:latest
  DockerOpenvswitchImage: centos-binary-neutron-openvswitch-agent:latest
  DockerOvsVswitchdImage: centos-binary-openvswitch-vswitchd:latest
  DockerOpenvswitchDBImage: centos-binary-openvswitch-db-server:latest
ARCH_SUPPORTS_BIG_ENDIAN help Say Y if you plan on running a kernel in big-endian mode. Note that your board must be properly built and your board port must properly enable any big-endian related features of your chipset/board/processor. config CPU_ENDIAN_BE8 bool depends on CPU_BIG_ENDIAN default CPU_V6 || CPU_V6K || CPU_V7 help Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. config CPU_ENDIAN_BE32 bool depends on CPU_BIG_ENDIAN default !CPU_ENDIAN_BE8 help Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. config CPU_HIGH_VECTOR depends on !MMU && CPU_CP15 && !CPU_ARM740T bool "Select the High exception vector" help Say Y here to select high exception vector(0xFFFF0000~). The exception vector can vary depending on the platform design in nommu mode. If your platform needs to select high exception vector, say Y. Otherwise or if you are unsure, say N, and the low exception vector (0x00000000~) will be used. config CPU_ICACHE_DISABLE bool "Disable I-Cache (I-bit)" depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) help Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_DISABLE bool "Disable D-Cache (C-bit)" depends on CPU_CP15 && !SMP help Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_SIZE hex depends on CPU_ARM740T || CPU_ARM946E default 0x00001000 if CPU_ARM740T default 0x00002000 # default size for ARM946E-S help Some cores are synthesizable to have various sized cache. For ARM946E-S case, it can vary from 0KB to 1MB. To support such cache operations, it is efficient to know the size before compile time. If your SoC is configured to have a different size, define the value here with proper conditions. config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you specifically require this or are unsure, say N. config CPU_CACHE_ROUND_ROBIN bool "Round robin I and D cache replacement algorithm" depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) help Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 help Say Y here to disable branch prediction. If unsure, say N. config TLS_REG_EMUL bool select NEED_KUSER_HELPERS help An SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to that required register must be emulated. config NEEDS_SYSCALL_FOR_CMPXCHG bool select NEED_KUSER_HELPERS help SMP on a pre-ARMv6 processor? Well OK then. Forget about fast user space cmpxchg support. It is just not possible. config NEED_KUSER_HELPERS bool config KUSER_HELPERS bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS depends on MMU default y help Warning: disabling this option may break user programs. Provide kuser helpers in the vector page. The kernel provides helper code to userspace in read only form at a fixed location in the high vector page to allow userspace to be independent of the CPU type fitted to the system. This permits binaries to be run on ARMv4 through to ARMv7 without modification. See Documentation/arm/kernel_user_helpers.txt for details. However, the fixed address nature of these helpers can be used by ROP (return orientated programming) authors when creating exploits. If all of the binaries and libraries which run on your platform are built specifically for your platform, and make no use of these helpers, then you can turn this option off to hinder such exploits. However, in that case, if a binary or library relying on those helpers is run, it will receive a SIGILL signal, which will terminate the program. Say N here only if you are absolutely certain that you do not need these helpers; otherwise, the safe option is to say Y. config VDSO bool "Enable VDSO for acceleration of some system calls" depends on AEABI && MMU && CPU_V7 default y if ARM_ARCH_TIMER select GENERIC_TIME_VSYSCALL help Place in the process address space an ELF shared object providing fast implementations of gettimeofday and clock_gettime. Systems that implement the ARM architected timer will receive maximum benefit. You must have glibc 2.22 or later for programs to seamlessly take advantage of this. config DMA_CACHE_RWFO bool "Enable read/write for ownership DMA cache maintenance" depends on CPU_V6K && SMP default y help The Snoop Control Unit on ARM11MPCore does not detect the cache maintenance operations and the dma_{map,unmap}_area() functions may leave stale cache entries on other CPUs. By enabling this option, Read or Write For Ownership in the ARMv6 DMA cache maintenance functions is performed. These LDR/STR instructions change the cache line state to shared or modified so that the cache operation has the desired effect. Note that the workaround is only valid on processors that do not perform speculative loads into the D-cache. For such processors, if cache maintenance operations are not broadcast in hardware, other workarounds are needed (e.g. cache maintenance broadcasting in software via FIQ). config OUTER_CACHE bool config OUTER_CACHE_SYNC bool help The outer cache has a outer_cache_fns.sync function pointer that can be used to drain the write buffer of the outer cache. config CACHE_FEROCEON_L2 bool "Enable the Feroceon L2 cache controller" depends on ARCH_MV78XX0 || ARCH_MVEBU default y select OUTER_CACHE help This option enables the Feroceon L2 cache controller. config CACHE_FEROCEON_L2_WRITETHROUGH bool "Force Feroceon L2 cache write through" depends on CACHE_FEROCEON_L2 help Say Y here to use the Feroceon L2 cache in writethrough mode. Unless you specifically require this, say N for writeback mode. config MIGHT_HAVE_CACHE_L2X0 bool help This option should be selected by machines which have a L2x0 or PL310 cache controller, but where its use is optional. The only effect of this option is to make CACHE_L2X0 and related options available to the user for configuration. Boards or SoCs which always require the cache controller support to be present should select CACHE_L2X0 directly instead of this option, thus preventing the user from inadvertently configuring a broken kernel. config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 default MIGHT_HAVE_CACHE_L2X0 select OUTER_CACHE select OUTER_CACHE_SYNC help This option enables the L2x0 PrimeCell. if CACHE_L2X0 config PL310_ERRATA_588369 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" help The PL310 L2 cache controller implements three types of Clean & Invalidate maintenance operations: by Physical Address (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). They are architecturally defined to behave as the execution of a clean operation followed immediately by an invalidate operation, both performing to the same memory location. This functionality is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0) as clean lines are not invalidated as a result of these operations. config PL310_ERRATA_727915 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" help PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. Revisions prior to r3p1 are affected by this errata (fixed in r3p1). config PL310_ERRATA_753970 bool "PL310 errata: cache sync operation may be faulty" help This option enables the workaround for the 753970 PL310 (r3p0) erratum. Under some condition the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. The workaround is to replace the normal offset of cache sync operation (0x730) by another offset targeting an unmapped PL310 register 0x740. This has the same effect as the cache sync operation: store buffer drain and waiting for all buffers empty. config PL310_ERRATA_769419 bool "PL310 errata: no automatic Store Buffer drain" help On revisions of the PL310 prior to r3p2, the Store Buffer does not automatically drain. This can cause normal, non-cacheable writes to be retained when the memory system is idle, leading to suboptimal I/O performance for drivers using coherent DMA. This option adds a write barrier to the cpu_idle loop so that, on systems with an outer cache, the store buffer is drained explicitly. endif config CACHE_TAUROS2 bool "Enable the Tauros2 L2 cache controller" depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) default y select OUTER_CACHE help This option enables the Tauros2 L2 cache controller (as found on PJ1/PJ4). config CACHE_XSC3L2 bool "Enable the L2 cache on XScale3" depends on CPU_XSC3 default y select OUTER_CACHE help This option enables the L2 cache on XScale3. config ARM_L1_CACHE_SHIFT_6 bool default y if CPU_V7 help Setting ARM L1 cache line size to 64 Bytes. config ARM_L1_CACHE_SHIFT int default 6 if ARM_L1_CACHE_SHIFT_6 default 5 config ARM_DMA_MEM_BUFFERABLE bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ MACH_REALVIEW_PB11MP) default y if CPU_V6 || CPU_V6K || CPU_V7 help Historically, the kernel has used strongly ordered mappings to provide DMA coherent memory. With the advent of ARMv7, mapping memory with differing types results in unpredictable behaviour, so on these CPUs, this option is forced on. Multiple mappings with differing attributes is also unpredictable on ARMv6 CPUs, but since they do not have aggressive speculative prefetch, no harm appears to occur. However, drivers may be missing the necessary barriers for ARMv6, and therefore turning this on may result in unpredictable driver behaviour. Therefore, we offer this as an option. You are recommended say 'Y' here and debug any affected drivers. config ARCH_HAS_BARRIERS bool help This option allows the use of custom mandatory barriers included via the mach/barriers.h file. config ARCH_SUPPORTS_BIG_ENDIAN bool help This option specifies the architecture can support big endian operation. config ARM_KERNMEM_PERMS bool "Restrict kernel memory permissions" depends on MMU help If this is set, kernel memory other than kernel text (and rodata) will be made non-executable. The tradeoff is that each region is padded to section-size (1MiB) boundaries (because their permissions are different and splitting the 1M pages into 4K ones causes TLB performance problems), wasting memory. config DEBUG_RODATA bool "Make kernel text and rodata read-only" depends on ARM_KERNMEM_PERMS default y help If this is set, kernel text and rodata will be made read-only. This is to help catch accidental or malicious attempts to change the kernel's executable code. Additionally splits rodata from kernel text so it can be made explicitly non-executable. This creates another section-size padded region, so it can waste more memory space while gaining the read-only protections.