/* * (C) Copyright 2011 * eInfochips Ltd. * Written-by: Ajay Bhargav * * (C) Copyright 2010 * Marvell Semiconductor * Contributor: Mahavir Jain * * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include #include #include #include #include #include #include #include #include "armada100_fec.h" #define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */ #ifdef DEBUG static int eth_dump_regs(struct eth_device *dev) { struct armdfec_device *darmdfec = to_darmdfec(dev); struct armdfec_reg *regs = darmdfec->regs; unsigned int i = 0; printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr)); printf("offset: smi, value: 0x%x\n", readl(®s->smi)); for (i = 0x400; i <= 0x4e4; i += 4) printf("offset: 0x%x, value: 0x%x\n", i, readl(ARMD1_FEC_BASE + i)); return 0; } #endif static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond) { u32 timeout = PHY_WAIT_ITERATIONS; u32 reg_val; while (--timeout) { reg_val = readl(reg); if (cond && (reg_val & flag)) break; else if (!cond && !(reg_val & flag)) break; udelay(PHY_WAIT_MICRO_SECONDS); } return !timeout; } static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, u16 *value) { struct eth_device *dev = eth_get_dev_by_name(devname); struct armdfec_device *darmdfec = to_darmdfec(dev); struct armdfec_reg *regs = darmdfec->regs; u32 val; if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { val = readl(®s->phyadr); *value = val & 0x1f; return 0; } /* check parameters */ if (phy_addr > PHY_MASK) { printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n", __func__, phy_addr); return -EINVAL; } if (phy_reg > PHY_MASK) { printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n", __func__, phy_reg); return -EINVAL; } /* wait for the SMI register to become available */ if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); return -1; } writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi); /* now wait for the data to be valid */ if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) { val = readl(®s->smi); printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n", __func__, val); return -1; } val = readl(®s->smi); *value = val & 0xffff; return 0; } static int smi_reg_write(const char *devname, u8 phy_addr, u8 phy_reg, u16 value) { struct eth_device *dev = eth_get_dev_by_name(devname); struct armdfec_device *darmdfec = to_darmdfec(dev); struct armdfec_reg *regs = darmdfec->regs; if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f); return 0; } /* check parameters */ if (phy_addr > PHY_MASK) { printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__); return -EINVAL; } if (phy_reg > PHY_MASK) { printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__); return -EINVAL; } /* wait for the SMI register to become available */ if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); return -1; } writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff), ®s->smi); return 0; } /* * Abort any transmit and receive operations and put DMA * in idle state. AT and AR bits are cleared upon entering * in IDLE state. So poll those bits to verify operation. */ static void abortdma(struct eth_device *dev) { struct armdfec_device *darmdfec = to_darmdfec(dev); struct armdfec_reg *regs = darmdfec->regs; int delay; int maxretries = 40; u32 tmp; while (--maxretries) { writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd); udelay(100); delay = 10; while (--delay) { tmp = readl(®s->sdma_cmd); if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT))) break; udelay(10); } if (delay) break; } if (!maxretries) printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__); } static inline u32 nibble_swapping_32_bit(u32 x) { return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4); } static inline u32 nibble_swapping_16_bit(u32 x) { return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4); } static inline u32 flip_4_bits(u32 x) { return ((x & 0x01) << 3) | ((x & 0x002) << 1) | ((x & 0x04) >> 1) | ((x & 0x008) >> 3); } /* * This function will calculate the hash function of the address. * depends on the hash mode and hash size. * Inputs * mach - the 2 most significant bytes of the MAC address. * macl - the 4 least significant bytes of the MAC address. * Outputs * return the calculated entry. */ static u32 hash_function(u32 mach, u32 macl) { u32 hashresult; u32 addrh; u32 addrl; u32 addr0; u32 addr1; u32 addr2; u32 addr3; u32 addrhswapped; u32 addrlswapped; addrh = nibble_swapping_16_bit(mach); addrl = nibble_swapping_32_bit(macl); addrhswapped = flip_4_bits(addrh & 0xf) + ((flip_4_bits((addrh >> 4) & 0xf)) << 4) + ((flip_4_bits((addrh >> 8) & 0xf)) << 8) + ((flip_4_bits((addrh >> 12) & 0xf)) << 12); addrlswapped = flip_4_bits(addrl & 0xf) + ((flip_4_bits((addrl >> 4) & 0xf)) << 4) + ((flip_4_bits((addrl >> 8) & 0xf)) << 8) + ((flip_4_bits((addrl >> 12) & 0xf)) << 12) + ((flip_4_bits((addrl >> 16) & 0xf)) << 16) + ((flip_4_bits((addrl >> 20) & 0xf)) << 20) + ((flip_4_bits((addrl >> 24) & 0xf)) << 24) + ((flip_4_bits((addrl >> 28) & 0xf)) << 28); addrh = addrhswapped; addrl = addrlswapped; addr0 = (addrl >> 2) & 0x03f; addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2); addr2 = (addrl >> 15) & 0x1ff; addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8); hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); hashresult = hashresult & 0x07ff; return hashresult; } /* * This function will add an entry to the address table. * depends on the hash mode and hash size that was initialized. * Inputs * mach - the 2 most significant bytes of the MAC address. * macl - the 4 least significant bytes of the MAC address. * skip - if 1, skip this address. * rd - the RD field in the address table. * Outputs * address table entry is added. * 0 if success. * -ENOSPC if table full */ static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach, u32 macl, u32 rd, u32 skip, int del) { struct addr_table_entry_t *entry, *start; u32 newhi; u32 newlo; u32 i; newlo = (((mach >> 4) & 0xf) << 15) | (((mach >> 0) & 0xf) << 11) | (((mach >> 12) & 0xf) << 7) | (((mach >> 8) & 0xf) << 3) | (((macl >> 20) & 0x1) << 31) | (((macl >> 16) & 0xf) << 27) | (((macl >> 28) & 0xf) << 23) | (((macl >> 24) & 0xf) << 19) | (skip << HTESKIP) | (rd << HTERDBIT) | HTEVALID; newhi = (((macl >> 4) & 0xf) << 15) | (((macl >> 0) & 0xf) << 11) | (((macl >> 12) & 0xf) << 7) | (((macl >> 8) & 0xf) << 3) | (((macl >> 21) & 0x7) << 0); /* * Pick the appropriate table, start scanning for free/reusable * entries at the index obtained by hashing the specified MAC address */ start = (struct addr_table_entry_t *)(darmdfec->htpr); entry = start + hash_function(mach, macl); for (i = 0; i < HOP_NUMBER; i++) { if (!(entry->lo & HTEVALID)) { break; } else { /* if same address put in same position */ if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8)) && (entry->hi == newhi)) break; } if (entry == start + 0x7ff) entry = start; else entry++; } if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) && (entry->hi != newhi) && del) return 0; if (i == HOP_NUMBER) { if (!del) { printf("ARMD100 FEC: (%s) table section is full\n", __func__); return -ENOSPC; } else { return 0; } } /* * Update the selected entry */ if (del) { entry->hi = 0; entry->lo = 0; } else { entry->hi = newhi; entry->lo = newlo; } return 0; } /* * Create an addressTable entry from MAC address info * found in the specifed net_device struct * * Input : pointer to ethernet interface network device structure
heat_template_version: pike

description: >
  OpenStack containerized Heat Engine service

parameters:
  DockerNamespace:
    description: namespace
    default: 'tripleoupstream'
    type: string
  DockerHeatEngineImage:
    description: image
    default: 'centos-binary-heat-engine:latest'
    type: string
  DockerHeatConfigImage:
    description: The container image to use for the heat config_volume
    default: 'ce